Ground fault detection circuit and power conversion device using same

Abstract

A ground fault detection circuit (6) comprises first to fourth resistance elements (31-34). Terminals on one side of the first to third resistance elements (31-33) are respectively connected to first to third AC lines (RL, SL, TL), and terminals on the other side of the first to third resistance elements (31-33) are all connected to a terminal on one side of a fourth resistance element (34). A terminal on the other side of the fourth resistance element (34) receives a ground voltage. The ground fault detection circuit (6) comprises a determination circuit (100) which, on the basis of the inter-terminal voltage of the fourth resistance element (34), determines whether a ground fault has occurred in a power conversion device. The determination circuit (100) includes: a first comparator (36) for comparing the inter-terminal voltage of the fourth resistance element (34) with a first reference voltage (VR); and a first on-delay timer (37) for receiving the output of the first comparator (36).

Description

Ground fault detection circuit and power conversion device using the same

[0001] The present disclosure relates to a ground fault detection circuit and a power conversion device using the same.

[0002] The thyristor starting device includes a converter that converts three-phase AC power of a commercial frequency into DC power, a DC reactor that smoothes the DC power, and an inverter that converts the DC power provided from the converter via the DC reactor into three-phase AC power of a desired frequency and provides the three-phase AC power to a synchronous motor via first to third AC lines. By controlling the three-phase AC power provided to the synchronous motor, the synchronous motor can be started from a stopped state and driven to rotate at a predetermined rotational speed (see, for example, Japanese Patent Laid-Open No. 2003-61380 (Patent Document 1)).

[0003] Furthermore, such a thyristor starting device is provided with a ground fault detection circuit that detects a ground fault. When the ground fault detection circuit detects a ground fault, the operation of the thyristor starting device is stopped.

[0004] Conventional ground fault detection circuits include those that connect a three-phase transformer to the first to third AC lines between the thyristor starting device and the synchronous motor, and detect the occurrence of a ground fault based on the output voltage of the three-phase transformer (see, for example, Japanese Patent Laid-Open No. 2009-131048 (Patent Document 2), Japanese Patent Laid-Open No. 2010-130704 (Patent Document 3), and Japanese Patent Laid-Open No. 2011-130634 (Patent Document 4)).

[0005] In addition, one terminal of each of the first and second resistance elements is connected to two input terminals of an inverter, and a third resistance element is connected between the other terminals of the first and second resistance elements and a ground voltage line, and the occurrence of a ground fault is detected based on the voltage between the terminals of the third resistance element (see, for example, "Thyristor Starting Device for Thermal Power Plants," Mitsubishi Electric Technical Report, Vol. 67, No. 5, 1993 (Non-Patent Document 1)).

[0006] JP 2003-61380 A JP 2009-131048 A JP 2010-130704 A JP 2011-130634 A

[0007] "Thyristor Starting Device for Thermal Power Plants," Mitsubishi Electric Technical Review, Vol. 67, No. 5, 1993

[0008] However, the ground fault detection circuits of Patent Documents 2 to 4 use a three-phase transformer, which results in a large and expensive circuit. Furthermore, the ground fault detection circuit of Non-Patent Document 1 has a problem of poor detection accuracy. Furthermore, in the initial stage of starting a motor from a stopped state, the neutral point potential fluctuates due to the residual magnetic flux of the motor, which can lead to false detection of a ground fault.

[0009] Therefore, an object of the present disclosure is to provide a highly accurate ground fault detection circuit and a power conversion device using the same.

[0010] The ground fault detection circuit disclosed herein detects a ground fault in a power conversion device that converts first three-phase AC power into DC power, converts the DC power into second three-phase AC power, and supplies the power to a load via first to third AC lines. The ground fault detection circuit includes first to fourth resistor elements. One terminal of each of the first to third resistor elements is connected to the first to third AC lines, respectively, and the other terminals of the first to third resistor elements are all connected to one terminal of a fourth resistor element, the other terminal of which receives a ground voltage. The ground fault detection circuit further includes a determination circuit that determines whether a ground fault has occurred in the power conversion device based on a voltage across the fourth resistor element. The determination circuit includes a first comparator that compares the voltage across the fourth resistor element with a first reference voltage, and a first on-delay timer that receives the output of the first comparator.

[0011] The ground fault detection circuit of the present disclosure includes the first on-delay timer, thereby enabling high-accuracy detection of a ground fault.

[0012] 1 is a diagram showing the configuration of a thyristor starting device of a first embodiment; 2 is a circuit diagram showing the configurations of a converter 3 and an inverter 5; 3 is a diagram showing the configuration of a ground fault detection circuit 6 of a first embodiment; 4 is a diagram showing the output voltage V35 of an amplifier 35, the output signal V36 (input signal of an on-delay timer 37) of a comparator 36, and the output signal V37 of an on-delay timer 37 in the first embodiment; 5 is a diagram showing the configuration of a ground fault detection circuit 6A of a second embodiment; 6 is a diagram showing the output voltage V35 of an amplifier 35, the output signal V36 (input signal of an on-delay timer 37) of a comparator 36, the output signal V37 of an on-delay timer 37, the output signal V38 of an on-delay timer 38, and the output signal V39 of an AND circuit 39 in the second embodiment; and 7 is a diagram showing the configuration of a ground fault detection circuit 6B of a third embodiment. 1 is a diagram showing the output voltage V35 of the amplifier 35, the output signal V36 of the comparator 36 (input signal of the on-delay timer 37), the output signal V37 of the on-delay timer 37, the output signal V40 of the comparator 40, and the output signal V41 of the AND circuit 41 in the third embodiment.

[0034] FIG. 1 is a diagram showing the configuration of a ground fault detection circuit 6C in the fourth embodiment.

[0035] FIG. 1 is a diagram showing the output voltage V35 of the amplifier 35, the output signal V36 of the comparator 36 (input signal of the on-delay timer 37), the output signal V37 of the on-delay timer 37, the output signal V42 of the comparator 42, and the output signal V43 of the AND circuit 43 in the fourth embodiment.

[0036] FIG. 1 is a diagram showing the configuration of a ground fault detection circuit 6D in the fifth embodiment.

[0037] FIG. 1 is a diagram showing the output voltage V35 of the amplifier 35, the output signal V36 of the comparator 36 (input signal of the on-delay timer 37D), the output signal V40 of the comparator 40, and the output signal V44 of the on-delay timer 37D in the fifth embodiment. 10 is a diagram showing the configuration of a ground fault detection circuit 6E according to a sixth embodiment, and is a diagram showing an output voltage V35 of an amplifier 35, an output signal V36 (an input signal to an on-delay timer 37E) of a comparator 36, an output signal V42 of a comparator 42, and an output signal V45 of an on-delay timer 37E according to the sixth embodiment.

[0013] Hereinafter, embodiments will be described with reference to the drawings. (First Embodiment) Fig. 1 is a diagram showing the configuration of a thyristor starter according to a first embodiment. The thyristor starter is a type of power conversion device. The thyristor starter is used, for example, in a power plant to start a stopped synchronous generator as a synchronous motor 8. With the synchronous generator running as the synchronous motor 8 at a predetermined rotational speed, the thyristor starter is disconnected from the synchronous motor 8, and the synchronous motor 8 is run by a gas turbine or the like to generate AC power.

[0014] The thyristor starting device receives three-phase AC power from an AC power source 1 and starts a synchronous motor 8, which is a load. The thyristor starting device includes a three-phase transformer 2, a converter 3, a DC reactor 4, an inverter 5, a ground fault detection circuit 6, and a control circuit 7.

[0015] Three-phase transformer 2 converts a commercial frequency three-phase AC voltage from AC power supply (power system) 1 into a predetermined three-phase AC voltage. The three-phase AC voltage generated by three-phase transformer 2 is applied to converter 3 via U-phase line UL, V-phase line VL, and W-phase line WL.

[0016] Converter 3 converts three-phase AC power from three-phase transformer 2 into DC power. DC reactor 4 is connected between high-voltage side output terminal 3a of converter 3 and high-voltage side input terminal 5a of inverter 5 and smoothes the DC power generated by converter 3. Low-voltage side output terminal 3b of converter 3 and low-voltage side input terminal 5b of inverter 5 are directly connected. DC reactor 4 may be connected between low-voltage side output terminal 3b of converter 3 and low-voltage side input terminal 5b of inverter 5. DC reactor 4 may be connected between high-voltage side output terminal 3a of converter 3 and high-voltage side input terminal 5a of inverter 5, and between low-voltage side output terminal 3b of converter 3 and low-voltage side input terminal 5b of inverter 5, respectively.

[0017] Inverter 5 converts the DC power provided from converter 3 via DC reactor 4 into three-phase AC power of a desired frequency, and provides the three-phase AC power to synchronous motor 8 via R-phase line RL, S-phase line SL, and T-phase line TL.

[0018] The synchronous motor 8 is driven to rotate by the three-phase AC power from the inverter 5. When the three-phase AC power is gradually increased, the rotation speed (revolutions per minute) of the synchronous motor 8 gradually increases. The control circuit 7 increases the switching frequency of the inverter 5 in accordance with the rotation speed of the synchronous motor 8. As a result, the rotation speed of the synchronous motor 8 gradually increases from 0 to a predetermined value, and the frequency of the three-phase AC power gradually increases from 0 to a predetermined value.

[0019] 2 is a circuit diagram showing the configurations of converter 3 and inverter 5. Converter 3 includes thyristors 11 to 16. The anodes of thyristors 11 to 13 are connected to U-phase line UL, V-phase line VL, and W-phase line WL, respectively, and the cathodes thereof are connected to high-voltage side output terminal 3a. The cathodes of thyristors 14 to 16 are connected to U-phase line UL, V-phase line VL, and W-phase line WL, respectively, and the anodes thereof are connected to low-voltage side output terminal 3b. Thyristors 11 to 16 are controlled by control circuit 7. Three-phase AC power can be converted to DC power by turning on thyristors 11 to 16 at predetermined timing.

[0020] Inverter 5 includes thyristors 21 to 26. The anodes of thyristors 21 to 23 are connected together to high-voltage side input terminal 5a, and the cathodes thereof are connected to R-phase line RL, S-phase line SL, and T-phase line TL, respectively. The anodes of thyristors 24 to 26 are connected together to R-phase line RL, S-phase line SL, and T-phase line TL, respectively, and the cathodes thereof are connected together to low-voltage side input terminal 5b. Thyristors 21 to 26 are controlled by control circuit 7. By turning on thyristors 21 to 26 at predetermined timings, DC power can be converted into three-phase AC power of a desired frequency.

[0021] The ground fault detection circuit 6 detects the occurrence of a ground fault in the thyristor starting device. Figure 3 shows the configuration of the ground fault detection circuit 6 of the first embodiment.

[0022] The ground fault detection circuit 6 includes resistance elements 31 to 34, an amplifier 35, and a determination circuit 100. The determination circuit 100 includes a comparator 36 and an on-delay timer 37.

[0023] Resistance elements 31 to 33 have one terminal connected to R-phase line RL, S-phase line SL, and T-phase line TL, respectively, and the other terminals connected to node N31 which is the neutral point. Resistance element 34 has one terminal connected to node N31, and the other terminal connected to the line of ground voltage GND.

[0024] The amplifier 35 amplifies the voltage V31 between the terminals of the resistance element 34. The comparator 36 compares the output voltage V35 of the amplifier 35 with a predetermined reference voltage VR and outputs a signal V36 at a level corresponding to the comparison result. If the output voltage V35 of the amplifier 35 is smaller than the reference voltage VR (V35<VR), the signal V36 is set to the "L" level. If the output voltage V35 of the amplifier 35 is equal to or greater than the reference voltage VR (VR≧V35), the signal V36 is set to the "H" level.

[0025] In the thyristor starting device, when no voltage fluctuation such as a ground fault occurs, the sum of the AC voltages of the R, S, and T phases is approximately 0 V, and the voltage V31 across the terminals of the resistance element 34 is approximately 0 V. In this case, V35<VR, and the signal V36 becomes the inactivation level "L".

[0026] In the case of a ground fault occurring in the thyristor starting device, the point where the ground fault occurred (for example, R-phase line RL) is connected to the other terminal of resistor element 34 (the line of ground voltage GND), creating a loop through which current flows and generating voltage V31 between the terminals of resistor element 34. In this case, VR<V35, and signal V36 goes to the "H" level, which is the activation level. In the case of a transient voltage fluctuation that is not a ground fault occurring, VR<V35 also occurs, and signal V36 goes to the "H" level, which is the activation level.

[0027] The on-delay timer 37 receives the signal V36 output from the comparator 36. The on-delay timer 37 is started when the signal V36 rises to the "H" level, and outputs the input signal V36 as the output signal V37 after a delay time TD1 has elapsed. The length of the delay time TD1 can be set using past data, etc.

[0028] FIG. 4 is a diagram showing the output voltage V35 of the amplifier 35, the output signal V36 of the comparator 36 (input signal of the on-delay timer 37), and the output signal V37 of the on-delay timer 37 in the first embodiment.

[0029] When a voltage fluctuation occurs after the start of startup of the thyristor starting device as shown in FIG. 4(1) or a transient voltage fluctuation occurs as shown in FIG. 4(2), the input signal V36 of the on-delay timer 37 becomes "H" level for a short time, but does not become "H" level for a time longer than the delay time TD1, so the output signal V37 of the on-delay timer 37 remains at "L" level.

[0030] 4(3), when a ground fault occurs, the input signal V36 of the on-delay timer 37 becomes "H" level for a time period equal to or longer than the delay time TD1. The output signal V37 of the on-delay timer 37 becomes "H" level after the delay time TD1 has elapsed since the occurrence of the ground fault.

[0031] If neither a ground fault nor a voltage fluctuation has occurred, the input signal V36 of the on-delay timer 37 remains at the "L" level, and the output signal V37 of the on-delay timer 37 therefore becomes the "L" level.

[0032] Control circuit 7 receives signals indicating the input current of converter 3, the output voltage of inverter 5, the rotational speed of synchronous motor 8, etc. from multiple sensors (not shown), and controls converter 3 and inverter 5 based on the received signals. When starting synchronous motor 8 that is in a stopped state, control circuit 7 gradually increases the frequency of the three-phase AC power output from inverter 5 from 0 to a predetermined value as the rotational speed of synchronous motor 8 gradually increases from 0 to a predetermined value. When output signal V37 of ground fault detection circuit 6 is set to an "H" level, control circuit 7 stops operation of converter 3 and inverter 5 and also opens multiple circuit breakers (not shown) to prevent damage to the thyristor starting device, synchronous motor 8, etc. due to a ground fault accident.

[0033] In this embodiment, the on-delay timer can prevent a transient potential fluctuation having a period shorter than the delay time TD1 that is not a ground fault from being detected as a ground fault.

[0034] Second Embodiment FIG. 5 is a diagram showing the configuration of a ground fault detection circuit 6A according to a second embodiment.

[0035] The difference between the discrimination circuit 100A of the ground fault detection circuit 6A of the second embodiment and the discrimination circuit 100 of the ground fault detection circuit 6 of the first embodiment is that the discrimination circuit 100A of the ground fault detection circuit 6A of the second embodiment further includes an on-delay timer 38 and an AND circuit 39.

[0036] The on-delay timer 38 receives a start-up signal ST for the thyristor starter from the control circuit 7. The on-delay timer 38 is started when the start-up signal ST rises to the "H" level, and outputs the start-up signal ST as an output signal V38 after a delay time TD2 has elapsed. The length of the delay time TD2 can be set to a value greater than the length of the delay time TD1. The length of the delay time TD2 can be set using past data, etc.

[0037] AND circuit 39 has an input terminal connected to the output of on-delay timer 37 and an input terminal connected to the output of on-delay timer 38. AND circuit 39 outputs signal V39 representing the logical AND of output signal V37 of on-delay timer 37 and output signal V38 of on-delay timer 38.

[0038] FIG. 6 is a diagram showing the output voltage V35 of amplifier 35, the output signal V36 of comparator 36 (input signal of on-delay timer 37), the output signal V37 of on-delay timer 37, the output signal V38 of on-delay timer 38, and the output signal V39 of AND circuit 39 in the second embodiment.

[0039] As shown in Figure 6 (1), if a voltage fluctuation occurs after the start of startup of the thyristor starting device, the output signal V37 of the on-delay timer 37 will become "H" level after the delay time TD1 has elapsed since the input signal V36 of the on-delay timer 37 went "H" level. However, the output signal V38 of the on-delay timer 38 remains "L" level. This is because the delay time TD2 has not yet elapsed since the start of startup of the thyristor starting device. Therefore, if a voltage fluctuation occurs after the start of startup of the thyristor starting device, the output signal V39 of the AND circuit 39 will be "L" level.

[0040] As shown in FIG. 6(2), after the delay time TD2 has elapsed since the start of activation of the thyristor starter, the output signal V38 of the on-delay timer 38 goes high.

[0041] As shown in (3) of Figure 6, when a transient voltage fluctuation occurs, the input signal V36 of the on-delay timer 37 becomes "H" level for a short time, but does not become "H" level for a time longer than the delay time TD1, so the output signal V37 of the on-delay timer 37 remains at "L" level.

[0042] 6 (4), when a ground fault occurs, the input signal V36 of the on-delay timer 37 becomes "H" level for a time period equal to or longer than the delay time TD1. The output signal V37 of the on-delay timer 37 becomes "H" level after the delay time TD1 has elapsed since the ground fault occurred. Therefore, the output signal V39 of the AND circuit 39 becomes "H" level after the delay time TD1 has elapsed since the ground fault occurred.

[0043] If no earth fault, transient voltage fluctuation, or voltage fluctuation after the start of startup of the thyristor starting device has occurred, the input signal V36 of the on-delay timer 37 remains at "L" level, and the output signal V39 of the AND circuit 39 becomes "L" level.

[0044] In this embodiment, the on-delay timer 38 can be used to prevent potential fluctuations after the start of startup of the thyristor starting device from being detected as a ground fault. This allows the on-delay timer 37 to be used to prevent detection of short-term potential fluctuations after the start of startup. As a result, the delay time TD1 of the on-delay timer 37 can be set short, allowing ground faults to be detected quickly.

[0045] Third Embodiment FIG. 7 is a diagram showing the configuration of a ground fault detection circuit 6B according to a third embodiment.

[0046] The difference between the discrimination circuit 100B of the ground fault detection circuit 6B of the third embodiment and the discrimination circuit 100 of the ground fault detection circuit 6 of the first embodiment is that the discrimination circuit 100B of the ground fault detection circuit 6B of the third embodiment further includes a comparator 40 and an AND circuit 41.

[0047] The control circuit 7 detects the rotation speed of the synchronous motor 8 using a rotation speed sensor or the like, and sends a signal representing the rotation speed FBNR of the synchronous motor 8 to the comparator 40. The control circuit 7 may calculate the angular frequency of the synchronous motor 8 based on the terminal voltage of the synchronous motor 8, the phase current of the synchronous motor 8, and the like, and calculate the rotation speed of the synchronous motor 8 from the angular frequency of the synchronous motor 8.

[0048] The comparator 40 compares the signal representing the rotation speed FBNR of the synchronous motor 8 sent from the control circuit 7 with a predetermined rotation speed NR, and outputs a signal V40 at a level corresponding to the comparison result. If the rotation speed FBNR of the synchronous motor 8 is smaller than the predetermined rotation speed NR (FBNR<NR), the signal V40 is set to "L" level. If the rotation speed FBNR of the synchronous motor 8 is equal to or greater than the predetermined rotation speed NR (FBNR≧NR), the signal V40 is set to "H" level.

[0049] AND circuit 41 has an input terminal connected to the output of on-delay timer 37 and an input terminal connected to the output of comparator 40. AND circuit 41 outputs signal V43 representing the logical AND of output signal V37 of on-delay timer 37 and output signal V40 of comparator 40.

[0050] FIG. 8 is a diagram showing the output voltage V35 of the amplifier 35, the output signal V36 (input signal of the on-delay timer 37) of the comparator 36, the output signal V37 of the on-delay timer 37, the output signal V40 of the comparator 40, and the output signal V41 of the AND circuit 41 in the third embodiment.

[0051] As shown in Figure 8 (1), if a voltage fluctuation occurs after the start of startup of the thyristor starting device, the output signal V37 of the on-delay timer 37 will become "H" level after the delay time TD1 has elapsed since the input signal V36 of the on-delay timer 37 went "H". However, the output signal V40 of the comparator 40 will remain "L" level. This is because the rotation speed FBNR of the synchronous motor 8 is smaller than the predetermined rotation speed NR until a certain amount of time has elapsed since the start of startup of the thyristor starting device. Therefore, if a voltage fluctuation occurs after the start of startup of the thyristor starting device, the output signal V41 of the AND circuit 41 will be "L" level.

[0052] As shown in (2) of Figure 8, after a certain amount of time has passed since the start of startup of the thyristor starting device, the rotation speed FBNR of the synchronous motor 8 becomes equal to or exceeds a predetermined rotation speed NR, and the output signal V40 of the comparator 40 becomes "H" level.

[0053] As shown in (3) of Figure 8, when a transient voltage fluctuation occurs, the input signal V36 of the on-delay timer 37 becomes "H" level for a short time, but does not become "H" level for a time longer than the delay time TD1, so the output signal V37 of the on-delay timer 37 remains at "L" level.

[0054] 8(4), when a ground fault occurs, the input signal V36 of the on-delay timer 37 becomes "H" level for a time period equal to or longer than the delay time TD1. The output signal V37 of the on-delay timer 37 becomes "H" level after the delay time TD1 has elapsed since the ground fault occurred. Therefore, the output signal V41 of the AND circuit 41 becomes "H" level after the delay time TD1 has elapsed since the ground fault occurred.

[0055] If no earth fault, transient voltage fluctuation, or voltage fluctuation after the start of startup of the thyristor starting device has occurred, the input signal V36 of the on-delay timer 37 remains at "L" level, and the output signal V41 of the AND circuit 41 becomes "L" level.

[0056] In this embodiment, the comparator 40 can be used to prevent potential fluctuations after the start of startup of the thyristor starting device from being detected as a ground fault. This allows the on-delay timer 37 to be used to prevent detection of short-term potential fluctuations after the start of startup. As a result, the delay time TD1 of the on-delay timer 37 can be set short, allowing ground faults to be detected quickly.

[0057] Fourth Embodiment FIG. 9 is a diagram showing the configuration of a ground fault detection circuit 6C according to a fourth embodiment.

[0058] The difference between the discrimination circuit 100C of the ground fault detection circuit 6C of the fourth embodiment and the discrimination circuit 100 of the ground fault detection circuit 6 of the first embodiment is that the discrimination circuit 100C of the ground fault detection circuit 6C of the fourth embodiment further includes a comparator 42 and an AND circuit 43.

[0059] The control circuit 7 acquires the voltage VR at the R-phase terminal, the voltage VS at the S-phase terminal, and the voltage VT at the T-phase terminal of the synchronous motor 8 using a voltage sensor or the like. The control circuit 7 determines either one of the absolute value DRS of the difference between VR and VS and the absolute value DTR of the difference between VT and VR, or the average value thereof, as the inter-terminal voltage FBV of the synchronous motor 8, and sends a signal representing the inter-terminal voltage FBV to the comparator 42.

[0060] The comparator 42 compares the signal representing the terminal voltage FBV of the synchronous motor 8 with a predetermined reference voltage VR2, and outputs a signal V42 at a level corresponding to the comparison result. When the terminal voltage FBV of the synchronous motor 8 is smaller than the predetermined reference voltage VR2 (FBV<VR2), the signal V42 is set to "L" level. When the terminal voltage FBV of the synchronous motor 8 is equal to or greater than the predetermined reference voltage VR2 (FBV≧VR2), the signal V42 is set to "H" level.

[0061] The AND circuit 43 has an input terminal connected to the output of the on-delay timer 37 and an input terminal connected to the output of the comparator 42. The AND circuit 43 outputs a signal V43 representing the logical AND of the output signal V37 of the on-delay timer 37 and the output signal V42 of the comparator 42.

[0062] FIG. 10 is a diagram showing the output voltage V35 of the amplifier 35, the output signal V36 (input signal of the on-delay timer 37) of the comparator 36, the output signal V37 of the on-delay timer 37, the output signal V42 of the comparator 42, and the output signal V43 of the AND circuit 43 in the fourth embodiment.

[0063] As shown in (1) of Figure 10, if a voltage fluctuation occurs after the start of startup of the thyristor starting device, the output signal V37 of the on-delay timer 37 will become "H" level after the delay time TD1 has elapsed since the input signal V36 of the on-delay timer 37 went "H". However, the output signal V42 of the comparator 42 will remain "L" level. This is because the voltage FBV across the terminals of the synchronous motor 8 is smaller than the predetermined voltage VR2 until a certain amount of time has elapsed since the start of startup of the thyristor starting device. Therefore, if a voltage fluctuation occurs after the start of startup of the thyristor starting device, the output signal V43 of the AND circuit 43 will be "L" level.

[0064] As shown in FIG. 10 (2), after a certain amount of time has passed since the start of startup of the thyristor starting device, the terminal voltage FBV of the synchronous motor 8 becomes equal to or higher than a predetermined voltage VR2, and the output signal V42 of the comparator 42 becomes “H” level.

[0065] As shown in (3) of Figure 10, when a transient voltage fluctuation occurs, the input signal V36 of the on-delay timer 37 becomes "H" level for a short time, but does not become "H" level for a time longer than the delay time TD1, so the output signal V37 of the on-delay timer 37 remains at "L" level.

[0066] 10 (4), when a ground fault occurs, the input signal V36 of the on-delay timer 37 becomes "H" level for a time period equal to or longer than the delay time TD1. The output signal V37 of the on-delay timer 37 becomes "H" level after the delay time TD1 has elapsed since the ground fault occurred. Therefore, the output signal V43 of the AND circuit 43 becomes "H" level after the delay time TD1 has elapsed since the ground fault occurred.

[0067] If no earth fault, transient voltage fluctuation, or voltage fluctuation after the start of startup of the thyristor starting device has occurred, the input signal V36 of the on-delay timer 37 remains at the "L" level, and the output signal V43 of the AND circuit 43 becomes the "L" level.

[0068] In this embodiment, the comparator 42 can prevent a transient potential fluctuation occurring after the start of startup of the thyristor starting device from being detected as a ground fault. This allows the on-delay timer 37 to be used to prevent detection of a short-term potential fluctuation occurring after the start of startup. As a result, the delay time TD1 of the on-delay timer 37 can be set short, allowing for rapid detection of a ground fault.

[0069] Fifth Embodiment FIG. 11 is a diagram showing the configuration of a ground fault detection circuit 6D according to a fifth embodiment.

[0070] The difference between the discrimination circuit 100D of the ground fault detection circuit 6D of the fifth embodiment and the discrimination circuit 100 of the ground fault detection circuit 6 of the first embodiment is that the discrimination circuit 100D of the ground fault detection circuit 6D of the fifth embodiment is that it has an on-delay timer 37D instead of the on-delay timer 37, and also has a comparator 40.

[0071] As in the third embodiment, the control circuit 7 sends a signal representing the rotation speed FBNR of the synchronous motor 8 to the comparator 40 .

[0072] As in the third embodiment, the comparator 40 compares a signal representing the rotation speed FBNR of the synchronous motor 8 with a predetermined rotation speed NR, and outputs a signal V40 at a level corresponding to the comparison result. If the rotation speed FBNR of the synchronous motor 8 is smaller than the predetermined rotation speed NR (FBNR<NR), the signal V40 is set to "L" level. If the rotation speed FBNR of the synchronous motor 8 is equal to or greater than the predetermined rotation speed NR (FBNR≧NR), the signal V40 is set to "H" level.

[0073] The on-delay timer 37D receives the signal V36 output from the comparator 36 and the signal V40 output from the comparator 40. The delay time of the on-delay timer 37D is set by the signal V40. The delay time of the on-delay timer 37D is set to TD2 when the signal V40 is at the "L" level (i.e., when the rotation speed FBNR of the synchronous motor 8 is smaller than the predetermined rotation speed NR), and is set to TD1 when the signal V40 is at the "H" level (i.e., when the rotation speed FBNR of the synchronous motor 8 is equal to or greater than the predetermined rotation speed NR). TD1<TD2.

[0074] FIG. 12 is a diagram showing the output voltage V35 of the amplifier 35, the output signal V36 of the comparator 36 (input signal of the on-delay timer 37D), the output signal V40 of the comparator 40, and the output signal V44 of the on-delay timer 37D in the fifth embodiment.

[0075] As shown in Figure 12 (1), if a voltage fluctuation occurs after the start of startup of the thyristor starting device, the output signal V40 of the comparator 40 remains at "L" level. This is because the rotation speed FBNR of the synchronous motor 8 is smaller than the predetermined rotation speed NR until a certain amount of time has passed since the start of startup of the thyristor starting device. Therefore, during this period, the delay time of the on-delay timer 37D is set to TD2. If a voltage fluctuation occurs after the start of startup of the thyristor starting device, the length of the period during which the input signal V36 of the on-delay timer 37D is at "H" level is shorter than TD2, so the output signal V44 of the on-delay timer 37D is at "L" level.

[0076] 12(2), after a certain time has passed since the start of the thyristor starting device, the rotational speed FBNR of the synchronous motor 8 becomes equal to or exceeds a predetermined rotational speed NR, and the output signal V40 of the comparator 40 becomes "H" level. As a result, the delay time of the on-delay timer 37D is set to TD1.

[0077] As shown in (3) of Figure 12, when a transient voltage fluctuation occurs, the input signal V36 of the on-delay timer 37D becomes "H" level for a short time, but does not become "H" level for a time longer than the delay time TD1, so the output signal V44 of the on-delay timer 37D remains at "L" level.

[0078] 12(4), when a ground fault occurs, the input signal V36 of the on-delay timer 37D becomes "H" level for a period of time equal to or longer than the delay time TD1. The output signal V44 of the on-delay timer 37D becomes "H" level after the delay time TD1 has elapsed since the occurrence of the ground fault.

[0079] If no earth fault, transient voltage fluctuation, or voltage fluctuation after the start of startup of the thyristor starting device has occurred, the input signal V36 of the on-delay timer 37D remains at the "L" level, and the output signal V44 of the on-delay timer 37D becomes the "L" level.

[0080] In this embodiment, the delay time TD2 of the on-delay timer 37D can be set to a long value so that a relatively long potential fluctuation after the start of startup of the thyristor starting device is not detected as a ground fault, and the delay time TD1 of the on-delay timer 37D can be set to a short value so that a relatively short transient potential fluctuation after the start of startup is not detected as a ground fault, thereby enabling ground faults to be detected quickly.

[0081] Sixth Embodiment FIG. 13 is a diagram showing the configuration of a ground fault detection circuit 6E according to a sixth embodiment.

[0082] The difference between the discrimination circuit 100E of the ground fault detection circuit 6E of the sixth embodiment and the discrimination circuit 100 of the ground fault detection circuit 6 of the first embodiment is that the discrimination circuit 100E of the ground fault detection circuit 6E of the sixth embodiment is that it has an on-delay timer 37E instead of the on-delay timer 37, and also has a comparator 42.

[0083] The control circuit 7 sends a signal representing the terminal voltage FBV of the synchronous motor 8 to the comparator 42, as in the fourth embodiment.

[0084] The comparator 42 compares the signal representing the terminal voltage FBV of the synchronous motor 8 with a predetermined reference voltage VR2, and outputs a signal V42 at a level corresponding to the comparison result. When the terminal voltage FBV of the synchronous motor 8 is smaller than the predetermined reference voltage VR2 (FBV<VR2), the signal V42 is set to "L" level. When the terminal voltage FBV of the synchronous motor 8 is equal to or greater than the predetermined reference voltage VR2 (FBV≧VR2), the signal V42 is set to "H" level.

[0085] The on-delay timer 37E receives the signal V36 output from the comparator 36 and the signal V42 output from the comparator 42. The delay time of the on-delay timer 37E is set by the signal V42. The delay time of the on-delay timer 37E is set to TD2 when the signal V42 is at the "L" level (i.e., when the voltage FBV between the terminals of the synchronous motor 8 is smaller than the predetermined reference voltage VR2), and is set to TD1 when the signal V42 is at the "H" level (i.e., when the voltage FBV between the terminals of the synchronous motor 8 is equal to or greater than the predetermined reference voltage VR2). TD1<TD2.

[0086] FIG. 14 is a diagram showing the output voltage V35 of the amplifier 35, the output signal V36 of the comparator 36 (input signal of the on-delay timer 37E), the output signal V42 of the comparator 42, and the output signal V45 of the on-delay timer 37E in the sixth embodiment.

[0087] As shown in (1) of Figure 14, if a voltage fluctuation occurs after the start of startup of the thyristor starting device, the output signal V42 of the comparator 42 remains at "L" level. This is because the voltage FBV across the terminals of the synchronous motor 8 is smaller than the predetermined reference voltage VR2 until a certain amount of time has passed since the start of startup of the thyristor starting device. Therefore, during this period, the delay time of the on-delay timer 37E is set to TD2. If a voltage fluctuation occurs after the start of startup of the thyristor starting device, the length of the period during which the input signal V36 of the on-delay timer 37E is at "H" level is shorter than TD2, so the output signal V45 of the on-delay timer 37E is at "L" level.

[0088] 14(2), after a certain time has passed since the start of startup of the thyristor starting device, the terminal voltage FBV of the synchronous motor 8 becomes equal to or higher than a predetermined reference voltage VR2, and the output signal V42 of the comparator 42 becomes "H" level. As a result, the delay time of the on-delay timer 37E is set to TD1.

[0089] As shown in (3) of Figure 14, when a transient voltage fluctuation occurs, the input signal V36 of the on-delay timer 37E becomes "H" level for a short time, but does not become "H" level for a time longer than the delay time TD1, so the output signal V45 of the on-delay timer 37E remains at "L" level.

[0090] 14(4), when a ground fault occurs, the input signal V36 of the on-delay timer 37E becomes "H" level for a time period equal to or longer than the delay time TD1. The output signal V45 of the on-delay timer 37E becomes "H" level after the delay time TD1 has elapsed since the occurrence of the ground fault.

[0091] If no earth fault, transient voltage fluctuation, or voltage fluctuation after the start of startup of the thyristor starting device has occurred, the input signal V36 of the on-delay timer 37E remains at the "L" level, and the output signal V45 of the on-delay timer 37E becomes the "L" level.

[0092] In this embodiment, the delay time TD2 of the on-delay timer 37E can be set to a long value so that a relatively long potential fluctuation after the start of startup of the thyristor starting device is not detected as a ground fault, and the delay time TD1 of the on-delay timer 37E can be set to a short value so that a relatively short transient potential fluctuation after the start of startup is not detected as a ground fault, thereby enabling ground faults to be detected quickly.

[0093] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0094] 1 AC power supply, 2 Three-phase transformer, 3 Converter, 3a High-voltage side output terminal, 3b Low-voltage side output terminal, 4 DC reactor, 5 Inverter, 5a High-voltage side input terminal, 5b Low-voltage side input terminal, 6, 6A, 6B, 6C, 6D, 6E Ground fault detection circuit, 7 Control circuit, 8 Synchronous motor, 11, 13, 14, 16, 21, 23, 24, 26 Thyristor, 31, 32, 33, 34 Resistive element, 35 Amplifier, 36, 40, 42 Comparator, 37, 37D, 37E, 38 On-delay timer, 39, 41, 43 AND circuit, 100, 100A, 100B, 100C, 100D, 100E Discrimination circuit.

Claims

1. A ground fault detection circuit for detecting a ground fault in a power conversion device that converts first three-phase AC power into DC power, converts the DC power into second three-phase AC power, and supplies it to a load via first to third AC lines, the ground fault detection circuit comprising first to fourth resistive elements, one terminal of each of the first to third resistive elements being connected to the first to third AC lines, the other terminal of each of the first to third resistive elements being connected to one terminal of a fourth resistive element, the other terminal of which receives a ground voltage, the ground fault detection circuit further comprising a determination circuit that determines whether or not the ground fault has occurred in the power conversion device based on a voltage across the fourth resistive element, the determination circuit including: a first comparator that compares the voltage across the fourth resistive element with a first reference voltage; and a first on-delay timer that receives the output of the first comparator.

2. The ground fault detection circuit according to claim 1, wherein said discrimination circuit further includes: a second on-delay timer that receives a signal indicating the start of startup of said power conversion device; and a logic circuit that receives the output of said first on-delay timer and the output of said second on-delay timer.

3. The ground fault detection circuit according to claim 1, wherein the frequency of the second three-phase AC power is variable, the load is a synchronous motor, and the power conversion device is a thyristor starting device that starts the synchronous motor.

4. A ground fault detection circuit according to claim 3, wherein said discrimination circuit further includes: a second comparator that compares the rotation speed of said synchronous motor with a predetermined rotation speed; and a logic circuit that receives the output of said first on-delay timer and the output of said second comparator.

5. The ground fault detection circuit according to claim 3, wherein said discrimination circuit further includes: a second comparator that compares the terminal voltage of said synchronous motor with a second reference voltage; and a logic circuit that receives the output of said first on-delay timer and the output of said second comparator.

6. A ground fault detection circuit according to claim 3, wherein the discrimination circuit further comprises a second comparator that compares the rotation speed of the synchronous motor with a predetermined rotation speed, and the delay time of the first on-delay timer is set by the output of the second comparator.

7. A ground fault detection circuit as claimed in claim 6, wherein when the rotation speed of the synchronous motor is lower than the predetermined rotation speed, the delay time of the first on-delay timer is set to a first time, and when the rotation speed of the synchronous motor is equal to or higher than the predetermined rotation speed, the delay time of the first on-delay timer is set to a second time shorter than the first time.

8. A ground fault detection circuit according to claim 3, wherein the discrimination circuit further comprises a second comparator that compares the terminal voltage of the synchronous motor with a second reference voltage, and the delay time of the first on-delay timer is set by the output of the second comparator.

9. A ground fault detection circuit as claimed in claim 8, wherein when the terminal voltage of the synchronous motor is smaller than the second reference voltage, the delay time of the first on-delay timer is set to a first time, and when the terminal voltage of the synchronous motor is equal to or greater than the second reference voltage, the delay time of the first on-delay timer is set to a second time shorter than the first time.

10. A power conversion device comprising: a converter that converts first three-phase AC power into DC power; a DC reactor that smoothes the DC power; an inverter that converts the DC power provided from the converter via the DC reactor into second three-phase AC power and supplies it to a load via first to third AC lines; a ground fault detection circuit according to any one of claims 1 to 9 that detects a ground fault in the power conversion device; and a control circuit that stops operation of the power conversion device when the ground fault is detected by the ground fault detection circuit.

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