Semiconductor device and electronic apparatus

Abstract

The purpose of the present invention is to improve the manufacturing yield of a semiconductor device. This semiconductor device is provided with a base member having one surface part, a semiconductor chip having an upper surface part and a side surface part and mounted on the one surface part side of the base member, an insulator provided on the one surface part side of the base member so as to cover the semiconductor chip, and a buffer part provided between the insulator and each of the upper surface part and the side surface part of the semiconductor chip.

Description

Semiconductor devices and electronic equipment

[0001] The present technology (technology related to the present disclosure) relates to semiconductor devices and electronic devices, and in particular to a technology that is effective when applied to a semiconductor device that includes a semiconductor chip mounted on a base member and an insulator that covers the semiconductor chip and is provided on the base member, and to an electronic device that includes the same.

[0002] Known semiconductor devices include photodetectors such as solid-state imaging devices and distance measuring devices, which employ a three-dimensional structure to achieve miniaturization and high pixel density.

[0003] Patent Document 1 discloses a three-dimensional structure in which a semiconductor chip is mounted on a base member such as a semiconductor wafer or semiconductor chip, and the mounted semiconductor chip is covered with an insulator.

[0004] JP 2024-42371 A

[0005] The insulator covering the semiconductor chip mounted on the base member is formed at a temperature higher than room temperature. Therefore, after the insulator is formed, different internal stresses are generated in the semiconductor chip and the insulator. This difference in internal stress between the semiconductor chip and the insulator causes stress distortion in the base member. This stress distortion causes variations (unevenness) in the photoelectric conversion characteristics of the photoelectric conversion unit provided on the base member, which reduces manufacturing yields and leaves room for improvement.

[0006] An object of the present technology is to provide a technology that can improve manufacturing yield.

[0007] (1) A semiconductor device according to one aspect of the present technology comprises: a base member having one surface; a semiconductor chip having an upper surface and a side surface and mounted on the one surface side of the base member; an insulator provided on the one surface side of the base member to cover the semiconductor chip; and buffer portions provided between the insulator and each of the upper surface and the side surface of the semiconductor chip. (2) A semiconductor device according to another aspect of the present technology comprises: a base member having one surface; a semiconductor chip mounted on the one surface of the base member; a support plate having a recess for accommodating the semiconductor chip and joined to the one surface of the base member with the semiconductor chip positioned in the recess; and a gap portion provided between the support plate and the semiconductor chip.

[0008] (3) An electronic device according to another aspect of the present technology includes: a semiconductor device according to (1) or (2) above; an optical lens that focuses image light from a subject on an imaging surface of the semiconductor device; and a signal processing circuit that processes a signal output from the semiconductor device.

[0009] 10A is a block diagram showing an example of a configuration of a photodetector according to a first embodiment of the present technology. FIG. 10B is an equivalent circuit diagram showing an example of a configuration of pixels and a readout circuit of the photodetector according to the first embodiment of the present technology. FIG. 10C is a plan layout diagram showing an example of a configuration of a photodetector according to the first embodiment of the present technology. FIG. 10D is a longitudinal sectional view showing an example of a longitudinal sectional structure taken along the a3-a3 cutting line of FIG. 3. FIG. 10E is a development view of FIG. 4. FIG. 10F is a bottom view showing the lower surface side of the photodetector of FIG. 3. FIG. 10G is a longitudinal sectional view showing an example of a longitudinal sectional structure taken along the a6-a6 cutting line of FIG. 6. FIG. 10H is a longitudinal sectional view showing an example of a longitudinal sectional structure taken along the b6-b6 cutting line of FIG. 6. FIG. 10I is a plan view showing an example of a configuration of a gap portion obtained by removing an insulator on an upper surface portion of a second semiconductor chip shown in FIG. 7. FIG. 10I is a plan view showing an example of a bonding surface portion of a first semiconductor chip. FIG. 10I is a plan view showing an example of a semiconductor wafer for explaining a manufacturing method of a second semiconductor chip included in a manufacturing method of a photodetector according to the first embodiment of the present technology. FIG. 10I is a diagram showing an example of a configuration of a chip formation region by enlarging region A of FIG. 12A 。 FIG. 13A is a plan view schematically showing a state in which a dicing step has been performed on a semiconductor wafer in a method for manufacturing a second semiconductor chip. FIG. 14A is a plan view schematically showing a wafer stack for explaining a manufacturing method of a first semiconductor chip included in a method for manufacturing a photodetector according to a first embodiment of the present technology. FIG. 15A is a longitudinal sectional view schematically showing a longitudinal sectional structure of the wafer stack of FIG. 12A. FIG. 15A is a diagram schematically showing an example of a configuration of a chip formation region by enlarging region B of FIG. 12A. FIG. 15B is a plan view schematically showing a process of a manufacturing method of a photodetector according to a first embodiment of the present technology. FIG. 15B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a13-a13 cutting line of FIG. 13A. FIG. 15C is a plan view schematically showing a process subsequent to FIG. 13A. FIG. 15D is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a14-a14 cutting line of FIG. 14A. FIG. 15D is a plan view schematically showing a process subsequent to FIG. 14A. 16A along the a16-a16 cutting line in Fig. 16. It is a plan view showing a process subsequent to Fig. 16A. It is a vertical cross-sectional view showing a vertical cross-sectional structure at the same position as the a17-a17 cutting line in Fig. 17A.17A. FIG. 18A is a diagram showing a process subsequent to FIG. 17, and is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the a17-a17 cutting line of FIG. 17A. FIG. 19A is a diagram showing a process subsequent to FIG. 19, and is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the a17-a17 cutting line of FIG. 17A. FIG. 19B is a plan view schematically showing a process subsequent to FIG. 19. FIG. 19C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a conventional photodetector. FIG. 19D is a diagram showing a modified example 1-1 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the b6-b6 cutting line of FIG. 6. FIG. 19E is a diagram showing a modified example 1-2 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the b6-b6 cutting line of FIG. 6. 27A . FIG. 28A is a diagram illustrating a modified example 1-3 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view illustrating a step of reducing the thickness of the second semiconductor chip. FIG. 29 is a diagram illustrating a modified example 1-4 according to the first embodiment of the present technology, and is a plan view schematically illustrating a plane pattern of a support portion of the insulator. FIG. 29 is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure taken along the b26-b26 cutting line of FIG. 26A. FIG. 30 is a diagram illustrating a modified example 1-5 according to the first embodiment of the present technology, and is a plan view schematically illustrating a plane pattern of a support portion of the insulator. FIG. 31 is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure taken along the b27-b27 cutting line of FIG. 32A. FIG. 32 is a diagram illustrating a modified example 1-6 according to the first embodiment of the present technology, and is a plan view schematically illustrating a plane pattern of a support portion of the insulator. FIG. 33 is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure taken along the a28-a28 cutting line of FIG. 34A. FIG. 34 is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure taken along the b28-b28 cutting line of FIG. 35A. Fig. 30A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b29-b29 cutting line in Fig. 29A. Fig. 30B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b27-b27 cutting line in Fig. 30A. Fig. 30C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b29-b29 cutting line in Fig. 29A. Fig. 30D is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b27-b27 cutting line in Fig. 30A.31A . FIG. 31B is a diagram illustrating a modified example 1-9 according to the first embodiment of the present technology, and is a plan view schematically showing a plane pattern of voids provided in an insulator. FIG. 31A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a31-a31 cutting line of FIG. 31A. FIG. 31B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b31-b31 cutting line of FIG. 31A. FIG. 31C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photodetector according to a second embodiment of the present technology. FIG. 32 is a longitudinal cross-sectional view enlarging a portion of FIG. 32. FIG. 32 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photodetector according to a third embodiment of the present technology. FIG. 34 is a development view of FIG. 34. FIG. 34 is a longitudinal cross-sectional view schematically showing a bonding state between the first semiconductor chip, the second semiconductor chip, and the support plate of FIG. 34. FIG. 37A is a plan view schematically showing a semiconductor wafer for explaining a manufacturing method of a support plate included in a manufacturing method of a photodetector according to a third embodiment of the present technology. FIG. 37A is an enlarged view of region C of FIG. 37A , and is a longitudinal cross-sectional view schematically showing a configuration example of a substrate formation region. FIG. 37B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a37-a37 cutting line of FIG. 38B . FIG. 39A is a longitudinal sectional view schematically showing a step of a method for manufacturing a photodetector according to a third embodiment of the present technology. FIG. 38B is a longitudinal sectional view schematically showing a step subsequent to the step of FIG. 38A . FIG. 38B is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photodetector according to a fourth embodiment of the present technology. FIG. 39A is a longitudinal sectional view schematically showing a bonding state between a first semiconductor chip, a second semiconductor chip, and a support plate. FIG. 39B is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photodetector according to a fifth embodiment of the present technology. FIG. 40A is a longitudinal sectional view schematically showing a bonding state between a first semiconductor chip, a second semiconductor chip, and a support plate. FIG. 40B is a longitudinal sectional view schematically showing a bonding state between a first semiconductor chip, a second semiconductor chip, and a support plate. 13 is a longitudinal sectional view showing a modification 8-1 of the eighth embodiment of the present technology, and is a schematic longitudinal sectional view showing a bonding state between a first semiconductor chip, a second semiconductor chip, and a support plate. FIG. 14 is a longitudinal sectional view showing a schematic longitudinal sectional structure of a photodetector according to a ninth embodiment of the present technology.46A is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photodetector according to a tenth embodiment of the present technology; FIG. 46B is a longitudinal sectional view schematically showing a bonding state between a first semiconductor chip and a second semiconductor chip and a support plate in FIG. 46A; and FIG. 46C is a diagram showing a schematic configuration of an electronic device according to an eleventh embodiment of the present technology.

[0010] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. Note that in the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0011] Furthermore, it goes without saying that the dimensional relationships and ratios may differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0012] Furthermore, the following embodiments exemplify devices and methods for embodying the technical idea of ​​the present technology, and do not limit the configuration to the following. In other words, the technical idea of ​​the present technology can be modified in various ways within the technical scope described in the claims.

[0013] Furthermore, the definitions of directions such as up and down in the following description are merely for the sake of convenience and do not limit the technical concept of the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0014] In the following embodiments, among the three mutually orthogonal directions in space, a first direction and a second direction that are mutually orthogonal in the same plane are referred to as the X direction and the Y direction, respectively, and a third direction that is orthogonal to each of the first and second directions is referred to as the Z direction. In the following embodiments, the stacking direction of a first semiconductor chip 20 and a second semiconductor chip 40 (described later) will be described as the Z direction.

[0015] In the following embodiments, a plan view refers to a semiconductor device viewed from the Z direction, and a cross-sectional view refers to a cross section along the Z direction viewed from a direction perpendicular to the cross section (Z direction).

[0016] First Embodiment In this first embodiment, an example in which the present technology is applied to a photodetector that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a semiconductor device will be described. Photodetectors include solid-state imaging devices and distance measuring devices. In addition, in this first embodiment, a case in which a gap portion is used as a specific example of a "buffer portion" of the present technology will be described.

[0017] <<Overall Configuration of Photodetector>> First, the overall configuration of the photodetector 1A will be described. As shown in FIGS. 3 to 6 , the photodetector 1A according to the first embodiment of the present technology includes a first semiconductor chip 20 having a bonding surface 20a as one surface, and a second semiconductor chip 40 having a bonding surface 40a and mounted on the bonding surface 20a side (one surface side) of the first semiconductor chip 20. The bonding surface 20a of the first semiconductor chip 20 and the bonding surface 40a of the second semiconductor chip 40 are bonded by direct bonding. The first semiconductor chip 20 and the second semiconductor chip 40 are stacked in the Z direction. In this first embodiment, the thickness direction of each of the first semiconductor chip 20 and the second semiconductor chip 40 corresponds to the Z direction.

[0018] In this first embodiment, although not limited thereto, two second semiconductor chips 40, 40 having a planar size smaller than that of the first semiconductor chip 20 are provided (see FIG. 6 ). The two second semiconductor chips 40 are spaced apart from each other in the X direction within the two-dimensional plane of the first semiconductor chip 20. Each of the first semiconductor chip 20 and the second semiconductor chip 40 has a rectangular two-dimensional planar shape in plan view. Surface activated bonding, for example, can be used to directly bond the second semiconductor chip 40. The direct bonding of the second semiconductor chip 40 is performed on the wafer stack 60 (see FIG. 12B ) before the process of dicing chip formation regions 65 (see FIG. 12C ) of the wafer stack 60 to form the first semiconductor chips 20, which will be described later.

[0019] Moreover, the photodetector 1A according to the first embodiment of the present technology further includes an insulator 51 provided on the bonding surface 20a side (one surface side) of the first semiconductor chip 20 to cover the second semiconductor chip 40. Moreover, the photodetector 1A according to the first embodiment of the present technology further includes a gap 55 as a buffer portion provided between the insulator 51 and the top surface 40b and the side surface 40c on the side opposite to the bonding surface 40a of the second semiconductor chip 40.

[0020] In the first embodiment, the first semiconductor chip 20 corresponds to a specific example of a "base member" of the present technology, the second semiconductor chip 40 corresponds to a specific example of a "semiconductor chip" of the present technology, and the bonding surface 20 a of the semiconductor chip 20 corresponds to a specific example of a "one surface portion of a base member" of the present technology. Also, in the first embodiment, the void portion 55 corresponds to a specific example of a "buffer portion" of the present technology.

[0021] As shown in Figure 34, the photodetector 1A (101) according to the first embodiment captures image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 focused on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs it as a pixel signal (image signal).

[0022] As shown in FIG. 3 , the first semiconductor chip 20 includes a rectangular pixel array section 2A provided in the center of a two-dimensional plane including mutually orthogonal X and Y directions, and a peripheral section 2B provided outside the pixel array section 2A so as to surround the pixel array section 2A. The first semiconductor chip 20 is formed by dicing the wafer stack 60 shown in FIG. 12C into chip formation regions 65 during the manufacturing process of the photodetector 1A. That is, the photodetector 1A described below has a substantially similar configuration even in the wafer state before the wafer stack is diced. Therefore, the present technology can be applied to both the chip state and the wafer state.

[0023] The pixel array section 2A is a light-receiving surface section that receives light collected by, for example, an optical lens (optical system) 102 shown in Fig. 34. In the pixel array section 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.

[0024] 3, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the first semiconductor chip 20. Each of the plurality of bonding pads 14 functions as an input / output terminal for electrical connection with an external device.

[0025] <Logic Circuit> The first semiconductor chip 20 includes a logic circuit 13 shown in Fig. 1. As shown in Fig. 1, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0026] The vertical drive circuit 4 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel array section 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion section (photoelectric conversion element) of each pixel 3 in accordance with the amount of received light to the column signal processing circuit 5 via vertical signal lines 11.

[0027] The column signal processing circuits 5 are arranged, for example, for each column of pixels 3, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to each pixel.

[0028] The horizontal drive circuit 6 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0029] The output circuit 7 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0030] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0031] <Pixels and Pixel Circuits> Each of the plurality of pixels 3 included in the pixel array unit 2A has a photoelectric conversion region 35 shown in Fig. 2. The photodetector 1A further has a pixel circuit (readout circuit) 16 shown in Fig. 2.

[0032] The photoelectric conversion region 35 includes, as common components, a photoelectric conversion unit 15 that photoelectrically converts light into signal charges, a floating diffusion region FD that serves as a charge storage unit that stores (accumulates) the signal charges photoelectrically converted by the photoelectric conversion unit 15, and a transfer transistor TR that transfers the signal charges photoelectrically converted by the photoelectric conversion unit 15 to the floating diffusion region FD. The photoelectric conversion region 35, which includes each of the photoelectric conversion unit 15, the floating diffusion region FD, and the transfer transistor TR, is provided in a semiconductor layer 32 (see FIGS. 4 and 5 ), which will be described later.

[0033] 2 is configured by, for example, a pn junction photodiode (PD) and generates a signal charge according to the amount of light received. The photoelectric conversion unit 15 has a cathode side electrically connected to the source region of the transfer transistor TR and an anode side electrically connected to a reference potential line (for example, ground).

[0034] 2 transfers signal charges photoelectrically converted by the photoelectric conversion unit 15 to the charge holding region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 15, and the drain region of the transfer transistor TR is electrically connected to the charge holding region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line among the pixel drive lines 10 shown in FIG.

[0035] The charge holding region FD shown in FIG. 2 temporarily holds (accumulates) the signal charge transferred from the photoelectric conversion unit 15 via the transfer transistor TR.

[0036] 2 has an input stage side electrically connected to the floating diffusion region FD of the photoelectric conversion region 35. In this first embodiment, as an example, a circuit configuration is used in which one pixel circuit 16 is assigned to one pixel 3. However, the assignment of the pixel circuits 16 is not limited to this first embodiment. For example, a circuit configuration may be used in which one pixel circuit 16 is assigned to one pixel block, each unit of which includes a plurality of pixels 3, or a circuit configuration may be used in which one pixel circuit 16 is assigned to multiple pixel blocks, each unit of which includes a plurality of pixels 3.

[0037] The pixel circuit 16 reads out the signal charges stored in the floating diffusion region FD and outputs a pixel signal based on the read signal charges. In other words, the pixel circuit 16 converts the signal charges photoelectrically converted by the photoelectric conversion unit 15 into a pixel signal based on the signal charges and outputs the pixel signal.

[0038] 2, the pixel circuit 16 includes, but is not limited to, pixel transistors, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG. These pixel transistors (AMP, SEL, RST, FDG) and the transfer transistor TR are insulated gate field effect transistors, and the gate insulating film is made of, for example, silicon oxide (SiO ２ These transistors are configured with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of a silicon nitride (Si) film. ３ N ４ Alternatively, a metal insulator semiconductor field effect transistor (MISFET) made of a laminated film of a silicon nitride film, a silicon oxide film, or the like may be used.

[0039] Of the pixel transistors included in the pixel circuit 16, the selection transistor SEL, reset transistor RST, and switching transistor FDG each function as a switching element, and the amplification transistor AMP functions as an amplification element. That is, the pixel circuit 16 includes field-effect transistors for different purposes. These pixel transistors (AMP, SEL, RST, FDG) are also provided in, for example, a semiconductor layer 32 described below.

[0040] 2, the amplifier transistor AMP has a source region electrically connected to the drain region of the select transistor SEL, a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST, and a gate electrode electrically connected to the floating diffusion region FD and the source region of the switching transistor FDG.

[0041] 2, the source of the selection transistor SEL is electrically connected to the vertical signal line 11 (VSL), the drain region is electrically connected to the source region of the amplification transistor AMP, and the gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line of the pixel drive lines 10 shown in FIG.

[0042] 2, the reset transistor RST has a source region electrically connected to the drain region of the switching transistor FDG, a drain region electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP, and a gate electrode electrically connected to the reset transistor drive line of the pixel drive line 10 shown in FIG.

[0043] 2, the switching transistor FDG has a source region electrically connected to the floating diffusion region FD and the gate electrode of the amplification transistor AMP, and a drain region electrically connected to the source region of the reset transistor RST. The gate electrode of the switching transistor FDG is electrically connected to a switching transistor drive line of the pixel drive line 10 shown in FIG.

[0044] The selection transistor SEL and the switching transistor FDG may be omitted as necessary. When the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL). When the switching transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode and floating diffusion region FD of the amplification transistor AMP.

[0045] When the transfer transistor TR shown in FIG. 2 is turned on, it transfers the signal charge generated in the photoelectric conversion unit 15 to the floating diffusion region FD.

[0046] 2, when the reset transistor RST is turned on, it resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd. The selection transistor SEL shown in FIG. 2 controls the output timing of a pixel signal from the pixel circuit 16.

[0047] 2 generates, as a pixel signal, a signal whose voltage corresponds to the level of the signal charge held in the floating diffusion region FD. The amplifying transistor AMP constitutes a source-follower amplifier, and outputs a pixel signal whose voltage corresponds to the level of the signal charge generated in the photoelectric conversion unit 15. When the selection transistor SEL is turned on, the amplifying transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0048] The switching transistor FDG shown in FIG. 2 controls charge retention by the floating diffusion region FD, and adjusts the multiplication factor of the voltage according to the potential amplified by the amplifier transistor AMP.

[0049] During operation of the photodetector 1A according to the first embodiment, signal charges generated in the photoelectric conversion unit 15 of each pixel 3 are held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the pixel 3. The signal charges held in the floating diffusion region FD are then read out by the pixel circuit 16 and applied to the gate electrode of the amplification transistor AMP of the pixel circuit 16. A horizontal line selection control signal is applied from the vertical shift register to the gate electrode of the selection transistor SEL of the pixel circuit 16. By setting the selection control signal to a high (H) level, the selection transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD, amplified by the amplification transistor AMP, flows through the vertical signal line 11. Furthermore, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 16 to a high (H) level, the reset transistor RST becomes conductive, resetting the signal charges accumulated in the floating diffusion region FD.

[0050] 1, the second semiconductor chip 40 has an internal circuit 17 electrically connected to the logic circuit 13 of the first semiconductor chip 20. Examples of the internal circuit 17 include a memory circuit such as a DRAM or a flash memory, and a high-performance circuit such as an artificial intelligence (AI).

[0051] <<Specific Configuration of Photodetector>> Next, a specific configuration of the photodetector 1A will be described. Note that FIGS. 7A and 7B are upside down compared to FIGS. 4 and 5. As shown in FIGS. 4 and 5, the photodetector 1A has a three-dimensional structure in which a second semiconductor chip 40 mounted on a first semiconductor chip 20 is covered with an insulator 51. The first semiconductor chip 20 and the second semiconductor chip 40 are stacked with their bonding surfaces facing each other. That is, the photodetector 1A includes a chip stack including the first semiconductor chip 20 and the second semiconductor chip 40.

[0052] <First Semiconductor Chip> As shown in Figures 3 and 6, the first semiconductor chip 20 has a rectangular planar shape in plan view, and in this first embodiment, it is, for example, rectangular. As shown in Figures 4 and 5, the first semiconductor chip 20 includes a first substrate portion 21 and a second substrate portion 31 stacked facing each other in their respective thickness directions (Z directions). The first substrate portion 21 includes the logic circuit 13 and other components. The second substrate portion 31 includes the pixel array portion 2A, the peripheral portion 2B, the pixel transistors included in the pixel circuits 15, and the bonding pads 14. The first substrate portion 21 and the second substrate portion 31 can also be expressed as semiconductor chips. Although not shown in detail, the first semiconductor chip 20 includes the bonding surface portion 20a, a light incident surface portion (rear surface portion) located opposite the bonding surface portion 20a, and four side surfaces (not shown) that form the outer periphery in plan view.

[0053] 4 and 5 , the second substrate unit 31 includes a semiconductor layer 32 having a first surface (element formation surface, main surface) and a second surface (light incident surface, back surface) located opposite each other in the thickness direction (Z), and a multilayer wiring layer 33 provided on the first surface side of the semiconductor layer 32. The second substrate unit 31 also includes a color filter layer 36 and a microlens 37 provided in this order from the semiconductor layer 32 side on the light incident surface side (second surface side) opposite the multilayer wiring layer 33 side (first surface side) of the semiconductor layer 32.

[0054] 4 and 5 , the semiconductor layer 32 spreads two-dimensionally across the pixel array section 2A and the peripheral section 2B, and overlaps the pixel array section 2A and the peripheral section 2B in a planar view. The semiconductor layer 32 may be a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In the first embodiment, the semiconductor layer 32 is made of, but is not limited to, silicon (Si) as a semiconductor material, single crystal as a crystallinity, and p-type as a conductivity type.

[0055] The semiconductor layer 32 is provided with the above-mentioned photoelectric conversion region 35 for each pixel 3. Although not shown in detail, the photoelectric conversion regions 35 are repeatedly arranged in, for example, the mutually orthogonal X and Y directions within a two-dimensional plane. Each photoelectric conversion region 35 is provided with the photoelectric conversion unit 15, transfer transistor TR, and floating diffusion region FD shown in FIG. 2. Each of these photoelectric conversion units 15, transfer transistor TR, and floating diffusion region FD is provided in a surface layer portion of the semiconductor layer 32 on the multilayer wiring layer 33 side. That is, the first semiconductor chip 20 serving as a base member includes the semiconductor layer 32 in which the photoelectric conversion unit 15 is provided.

[0056] (Multi-layer wiring layer) Although not shown in detail, referring to FIGS. 4 and 5, the multi-layer wiring layer 33 has a laminated structure in which insulating layers and wiring layers are alternately stacked in multiple stages. The multi-layer wiring layer 33 has wiring provided in each wiring layer and bonding metal pads 34. The insulating layer may be made of, for example, silicon oxide (SiO ２ The wiring layer and the bonding metal pads 34 may be made of a metal such as aluminum (Al) or copper (Cu), or an alloy mainly containing Al or Cu.

[0057] The wiring provided in the uppermost wiring layer of the multilayer wiring layer 33 is covered with the uppermost insulating layer. The bonding metal pad 34 is provided in the surface layer portion of the multilayer wiring layer 33 on the side opposite to the semiconductor layer 32, and is provided in the insulating layer with its surface exposed from the uppermost insulating layer. The bonding metal pad 34 is electrically connected to the wiring in a layer below the bonding metal pad 34. The lower wiring is then electrically connected to the floating diffusion region FD and the transfer transistor TR.

[0058] (Color Filter Layer and Microlens) The color filter layer 36 separates the color of incident light that is incident from the light incident surface side (back surface side) of the first semiconductor chip 20. The color filter layer 36 includes, for example, a first color filter of red (R), a second color filter of green (G), and a third color filter of blue (B).

[0059] The microlens 37 is provided for each photoelectric conversion region 35 (for each pixel 3) on the side (light incident surface side) opposite to the semiconductor layer 32 side of the color filter layer 36. The microlens 37 condenses the irradiated light and allows the condensed light to efficiently enter the photoelectric conversion unit 15.

[0060] <First substrate portion> As shown in Figures 4 and 5, the first substrate portion 21 comprises a semiconductor layer 22 having a first surface portion (element formation surface portion) and a second surface portion (back surface portion) located on opposite sides in the thickness direction (Z direction), a multilayer wiring layer 23 provided on the first surface portion side of the semiconductor layer 22, and a multilayer wiring layer 25 provided on the second surface portion side of the semiconductor layer 22.

[0061] (Semiconductor Layer) The semiconductor layer 22 spreads two-dimensionally across the pixel array section 2A and the peripheral section 2B, and overlaps the pixel array section 2A and the peripheral section 2B in a planar view. A Si substrate, a SiGe substrate, an InGaAs substrate, or the like can be used as the semiconductor layer 22. In the first embodiment, the semiconductor layer 22 is a semiconductor substrate that is made of, for example, silicon (Si) as a semiconductor material, has a crystallinity of, for example, single crystal, and has a conductivity type of, for example, p-type, although this is not limited thereto.

[0062] Although not shown in detail, a first surface (element-shaped surface) of the semiconductor layer 22 is provided with, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as a transistor element that constitutes the logic circuit 13 (see FIG. 2).

[0063] (Multi-layer Wiring Layer) Although not shown in detail, the multi-layer wiring layer 23 has a laminated structure in which insulating layers and wiring layers are alternately stacked in multiple stages. The multi-layer wiring layer 23 has wiring provided in each wiring layer and bonding metal pads 24. Examples of materials for the insulating layer include silicon oxide (SiO ２ The wiring layer and the bonding metal pads 24 may be made of a metal such as aluminum (Al) or copper (Cu), or an alloy mainly containing Al or Cu.

[0064] The wiring provided in the uppermost wiring layer of the multilayer wiring layer 23 is covered with the uppermost insulating layer. The bonding metal pad 24 is provided in the surface layer portion of the multilayer wiring layer 23 on the side opposite to the semiconductor layer 22, and the surface is exposed from the uppermost insulating layer. The bonding metal pad 24 is electrically connected to the wiring in the layer below the bonding metal pad 24.

[0065] (Multi-layer Wiring Layer) Although not shown in detail, the multi-layer wiring layer 25 has a laminated structure in which insulating layers and wiring layers are alternately stacked in multiple stages. The multi-layer wiring layer 25 has wiring provided in each wiring layer and bonding metal pads 27. The insulating layer may be made of, for example, silicon oxide (SiO ２ The wiring layer and the bonding metal pad 27 may be made of a metal such as aluminum (Al) or copper (Cu), or an alloy mainly containing Al or Cu.

[0066] The wiring provided in the uppermost wiring layer of the multilayer wiring layer 25 is covered with the uppermost insulating layer 26 (see FIGS. 7 and 8 ) of the multilayer wiring layer 25. The bonding metal pad 27 is provided in the surface layer portion of the multilayer wiring layer 25 on the side opposite to the semiconductor layer 22, and is provided in the insulating layer 26 with its surface exposed from the uppermost insulating layer 26. The bonding metal pad 27 is electrically connected to the wiring in a layer below the bonding metal pad 27.

[0067] 4 and 5, the wiring of the multilayer wiring layer 25 is electrically connected to the wiring of the multilayer wiring layer 23 via a contact electrode 28. The contact electrode 28 penetrates the semiconductor layer 22 in the thickness direction (Z direction) of the semiconductor layer 22, and extends across the multilayer wiring layer 23, the semiconductor layer 22, and the multilayer wiring layer 25. The contact electrode 28 may be made of a high-melting-point metal such as titanium (Ti) or tungsten (W).

[0068] 4 and 5, the bonding pad 14 is provided on the semiconductor layer 32 side of the multi-layer wiring layer 33. Specifically, the bonding pad 14 is provided in, for example, the first wiring layer of the multi-layer wiring layer 33.

[0069] 4 and 5 , the first semiconductor chip 20 is provided with bonding openings 38 that expose the surfaces of the bonding pads 14. The bonding openings 38 penetrate the semiconductor layer 32 in the thickness direction (Z direction) of the semiconductor layer 32 and extend across the semiconductor layer 32 and the multilayer wiring layer 33. Connection members such as bonding wires and bump electrodes are electrically and mechanically connected to the bonding pads 14 through the bonding openings 38.

[0070] 4 and 5, the first substrate portion 21 has a bonding metal pad 24 provided on a surface portion of the multilayer wiring layer 23 on the side opposite to the semiconductor layer 22. This bonding metal pad 24 is provided in the uppermost insulating layer of the multilayer wiring layer 23 with its bonding surface portion exposed.

[0071] As described above, the second substrate portion 31 has a bonding metal pad 34 provided on the surface layer portion of the multilayer wiring layer 33 on the side opposite to the semiconductor layer 32. This bonding metal pad 34 is provided in the uppermost insulating layer of the multilayer wiring layer 33 with its bonding surface portion exposed.

[0072] The bonding metal pads 24 of the first substrate portion 21 and the bonding metal pads 34 of the second substrate portion 31 are electrically and mechanically connected by intermetallic bonding with their respective bonding surfaces facing each other. The intermetallic bonding between the bonding metal pads 24 and 34 electrically connects the wiring of the multilayer wiring layer 23 of the first substrate portion 21 and the wiring of the multilayer wiring layer 33 of the second substrate portion 31.

[0073] The bonding metal pads 24 of the first substrate portion 21 and the bonding metal pads 34 of the second substrate portion 31 are bonded by direct bonding at their respective bonding surfaces. Also, the uppermost insulating layer of the multilayer wiring layer of the first substrate portion 21 and the uppermost insulating layer of the multilayer wiring layer of the second substrate portion 31 are bonded by direct bonding at their respective bonding surfaces. Surface activated bonding, for example, can be used as the direct bonding.

[0074] 4 and 5, the bonding surface 20a of the first semiconductor chip 20 is provided on the insulating layer 26 side of the multilayer wiring layer 25. Then, as shown in Figures 7A and 7B, the bonding surface 20a of the first semiconductor chip 20 includes the insulating layer 26 located in the uppermost layer of the multilayer wiring layer 25 of the first semiconductor chip 20, and further includes bonding metal pads 27 scattered on the insulating layer 26. Then, the bonding surface 20a is generally flat, with the difference in level between the bonding metal pads 27 and the insulating layer 26 being as small as possible.

[0075] 9, the bonding metal pads 27 are scattered in a chip mounting area Cm on the bonding surface 20a of the first semiconductor chip 20. The second semiconductor chip 40 is mounted in this chip mounting area Cm, and the bonding surface 40a of the second semiconductor chip 40 is directly bonded to the chip mounting area Cm.

[0076] 8, the second semiconductor chip 40 has a square planar shape, and in this first embodiment, the second semiconductor chip 40 has a rectangular planar shape, and the bonding surface 40a of the second semiconductor chip 40 also has a rectangular shape.

[0077] 4 and 5, each of the two semiconductor chips 40 includes a semiconductor layer 42 having a first surface portion (element forming surface portion, main surface portion) and a second surface portion (back surface portion) located on opposite sides in the thickness direction (Z), and a multilayer wiring layer 45 provided on the first surface portion side of this semiconductor layer 42. As shown in Fig. 5, each of the two semiconductor chips 40 includes the above-mentioned bonding surface portion 40a, a top surface portion 40b located on the opposite side to this bonding surface portion 40a, and four side surface portions 40c that form an outer periphery portion in a plan view.

[0078] (Semiconductor Layer) The semiconductor layer 42 may be made of a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In the first embodiment, the semiconductor layer 32 is made of, but is not limited to, silicon (Si), for example, a semiconductor substrate having a single crystal crystallinity and a p-type conductivity. The silicon semiconductor layer 42 has a surface roughness of 3.9×10 －６It has a thermal expansion coefficient of about 1 / K.

[0079] On the first surface (element forming surface) of the semiconductor layer 42, for example, a metal oxide semiconductor field effect transistor (MOSFET) is provided as a transistor that constitutes the internal circuit 17 (see FIG. 1).

[0080] (Multi-layer Wiring Layer) The multi-layer wiring layer 45 is not shown in detail, but will be described with reference to FIGS. 4 and 5. The multi-layer wiring layer 45 has a laminated structure in which insulating layers and wiring layers are alternately stacked in multiple stages. The multi-layer wiring layer 45 has wiring provided in each wiring layer and bonding metal pads 47. Examples of materials for the insulating layer include silicon oxide (SiO ２ The wiring layer and the bonding metal pad 47 may be made of a metal such as aluminum (Al) or copper (Cu), or an alloy mainly containing Al or Cu.

[0081] The wiring provided in the uppermost wiring layer of the multilayer wiring layer 45 is covered with the uppermost insulating layer 46 of the multilayer wiring layer 45 (see FIGS. 7A and 7B ). The bonding metal pad 47 is provided in the surface layer portion of the multilayer wiring layer 45 on the side opposite to the semiconductor layer 42, and its surface is exposed from the uppermost insulating layer 46 of the multilayer wiring layer 45. The bonding metal pad 47 is electrically connected to the wiring in a layer below the bonding metal pad 47. The lower wiring is then electrically connected to a transistor provided on the first surface side of the semiconductor layer 42.

[0082] 4 and 5, the bonding surface 40a of the second semiconductor chip 40 is provided on the insulating layer 46 side of the multilayer wiring layer 45. Then, as shown in Figures 7A and 7B, the bonding surface 40a of the second semiconductor chip 40 includes the insulating layer 46 located on the uppermost layer of the multilayer wiring layer 45 of the second semiconductor chip 40, and further includes bonding metal pads 47 scattered on the insulating layer 46. Then, the bonding surface 40a is generally flat, with the difference in level between the bonding metal pads 47 and the insulating layer 46 being as small as possible.

[0083] 7A and 7B , bonding metal pads 27 of first semiconductor chip 20 and bonding metal pads 47 of second semiconductor chip 40 are electrically and mechanically connected by intermetallic bonding with their respective bonding surfaces facing each other. The intermetallic bonding between bonding metal pads 27 and 47 electrically connects the wiring in multilayer wiring layer 25 of first semiconductor chip 20 to the wiring in multilayer wiring layer 45 of second semiconductor chip 40.

[0084] 7A and 7B , the bonding metal pads 27 of the first semiconductor chip 20 and the bonding metal pads 47 of the second semiconductor chip 40 are directly bonded together with their respective bonding surfaces facing each other. Also, the insulating layer 26 of the first semiconductor chip 20 and the insulating layer 46 of the second semiconductor chip 40 are directly bonded together with their respective bonding surfaces facing each other. That is, the bonding surface 20a including the insulating layer 26 and bonding metal pads 27 of the first semiconductor chip 20 and the bonding surface 48 including the insulating layer 46 and bonding metal pads 47 of the second semiconductor chip 40 are directly bonded together.

[0085] 7A and 7B , the insulator 51 is provided on the bonding surface 20a side of the first semiconductor chip 20 and covers the second semiconductor chip 40 mounted on the bonding surface 20a side of the first semiconductor chip 20. As shown in FIG. 6 , the insulator 51 has a rectangular planar shape when the photodetector 1A is viewed from the bottom side. In this first embodiment, the insulator 51 has a rectangular planar shape that is approximately the same as the first semiconductor chip 20. The insulator 51 fills in any step caused by the thickness of the second semiconductor chip 40 on the bonding surface 20a side of the first semiconductor chip 20, flattening the bonding surface 20a side of the first semiconductor chip 20 and protecting the bonding surface 20a side of the first semiconductor chip 20 and the second semiconductor chip 40.

[0086] The insulator 51 may be an organic or inorganic film, but is preferably an inorganic film from the viewpoint of degassing from the film and moisture absorption resistance. In this first embodiment, a silicon oxide film is used as the inorganic film. The silicon oxide film has a resistivity of, for example, 0.51 to 0.58×10 －６ It has a thermal expansion coefficient of about 1 / K.

[0087] The second semiconductor chip 40 is sealed with an insulator 51. Therefore, the insulator 51 can also be called a sealing body 51.

[0088] 7A , 7B , and 8 , a void 55 serving as a buffer is provided between the insulator 51 and the top surface 40 b and side surface 40 c of the second semiconductor chip 40. In the first embodiment, the void 55 is provided so as to cover the entire top surface 40 b of the semiconductor chip 40 and each of the four side surface portions 40 c of the semiconductor chip 40. In other words, the void 55 encompasses the entire top surface 40 b of the second semiconductor chip 40 and each of the four side surface portions 40 c of the second semiconductor chip 40. In further other words, the top surface 40 b and each of the four side surface portions 40 c of the second semiconductor chip 40 are entirely exposed to the void 55.

[0089] 14B due to the difference between the internal stress of the insulator 51 and the internal stress of the second semiconductor chip 40. The void 55 may be filled with a gas such as air or an inert gas, or may be in a vacuum state.

[0090] The void portion 55 can be formed by selectively removing (see Figure 18) a sacrificial film 55a (see Figure 16B) provided between the insulator 51 and the second semiconductor chip 40 during the manufacturing process of the photodetector 1A.

[0091] 6 and 7A , the insulator 51 on the top surface 40 a of the second semiconductor chip 40 has an opening 52 that penetrates the insulator 51 in the Z direction and connects the outside of the insulator 51 to the void 55. The opening 52 is closed by a cap film 53 that is provided on the opening 52, thereby blocking the connection between the outside of the insulator 51 and the void 55 and maintaining the airtightness of the void 55.

[0092] <<Method of Manufacturing Second Semiconductor Chip>> Next, a method of manufacturing the second semiconductor chip 40, which is included in the method of manufacturing the photodetector 1A described below, will be described with reference to Figs. 10A to 11. Fig. 10A is a plan view schematically showing an example of the configuration of a semiconductor wafer. Fig. 10B is an enlarged view of region A in Fig. 10A to schematically show an example of the configuration of a chip formation region. Fig. 11 is a process plan view schematically showing the state after the dicing process has been performed.

[0093] The second semiconductor chip 40 included in the photodetector 1A is fabricated in a chip formation region 75 of a semiconductor wafer 70 shown in Fig. 10B. The chip formation region 75 is partitioned by scribe lines 76 extending in both the X and Y directions, and a plurality of chip formation regions 75 are arranged in a matrix. Fig. 10B illustrates four chip formation regions 75 arranged around an intersection 76a where a scribe line 76 extending in the X direction intersects with a scribe line 76 extending in the Y direction.

[0094] Then, the second semiconductor chips 40 are formed by dividing the chip formation region 75 into individual small pieces along the scribe lines 76. The chip formation region 75 has a square shape in plan view, and in this first embodiment, a rectangular shape. Note that the scribe lines 76 are not physically formed.

[0095] 10A has already undergone pre-processing to form transistors and a multilayer wiring layer 45 (see FIG. 7) in the semiconductor layer 42 (see FIG. 7), and the semiconductor layer 42, multilayer wiring layer 45, and bonding surface portion 40a shown in FIGS. 7 and 8 are formed in the chip formation region 75 shown in FIG. 10B. The bonding surface portion 40a includes the insulating layer 46 of the multilayer wiring layer 45 and bonding metal pads 47. The steps after the pre-processing are described below.

[0096] 11, the semiconductor wafer 70 is diced along scribe lines 76, and the plurality of chip formation regions 75 of the semiconductor wafer 70 are individually diced to form second semiconductor chips 40. The dicing of the semiconductor wafer 70 is performed in a state where the semiconductor wafer 70 is adhesively fixed to a dicing tape 71.

[0097] Next, a surface modification process is performed to activate the bonding surface 40a of the second semiconductor chip 40, and then the second semiconductor chip 40 that has undergone the surface modification process is transported to the chip bonding process in the manufacturing process of the photodetector 1A described below.

[0098] <<Method of Manufacturing Photodetector>> Next, a method of manufacturing the photodetector 1A will be described with reference to FIGS. 12A to 21. FIG. 12A is a plan view schematically showing a wafer stack for describing a method of manufacturing a first semiconductor chip included in the method of manufacturing a photodetector according to the first embodiment of the present technology. FIG. 12B is a longitudinal sectional view schematically showing the longitudinal sectional structure of the wafer stack of FIG. 12A. FIG. 12C is a diagram schematically showing an example of a configuration of a chip formation region by enlarging region B of FIG. 12A. FIG. 13A is a plan view schematically showing a process of the method of manufacturing a photodetector according to the first embodiment of the present technology. FIG. 13B is a longitudinal sectional view schematically showing the longitudinal sectional structure along the a13-a13 cutting line of FIG. 13A. FIG. 14A is a plan view schematically showing a process subsequent to FIG. 13A. FIG. 14B is a longitudinal sectional view schematically showing the longitudinal sectional structure along the a14-a14 cutting line of FIG. 14A. FIG. 15A is a plan view schematically showing a process subsequent to FIG. 14A. 15B is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure taken along the a15-a15 cutting line in FIG. 15A. FIG. 16A is a plan view schematically showing a step subsequent to FIG. 15A. FIG. 16B is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure taken along the a16-a16 cutting line in FIG. 16A. FIG. 17A is a view showing a step subsequent to FIG. 16A. FIG. 17B is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure taken along the a17-a17 cutting line in FIG. 17A. FIG. 18 is a view showing a step subsequent to FIG. 17A, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure taken at the same position as the a16-a16 cutting line in FIG. 16A. FIG. 19 is a view showing a step subsequent to FIG. 18, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure taken at the same position as the a16-a16 cutting line in FIG. 16A. Fig. 20 is a diagram showing a step subsequent to Fig. 19, and is a longitudinal sectional view schematically showing a longitudinal sectional structure at the same position as the a16-a16 cutting line in Fig. 16A. Fig. 20 is upside down with respect to Fig. 19. Fig. 21 is a plan view schematically showing a step subsequent to Fig. 20.

[0099] Here, the first semiconductor chip 20 included in the photodetector 1A is fabricated in a chip formation region 65 of a wafer stack 60 shown in FIG. 12C. The chip formation regions 65 are partitioned by scribe lines 66 extending along the X and Y directions, and a plurality of chip formation regions 65 are arranged in a matrix. FIG. 12C illustrates nine chip formation regions 65 arranged in a matrix. The first semiconductor chip 20 is then formed by individually dicing these plurality of chip formation regions 65 along the scribe lines 66. The dicing of the chip formation regions 65 is performed after the manufacturing process described below has been performed. Note that the scribe lines 61 are not physically formed.

[0100] 12A and 12B , the wafer stack 60 includes two semiconductor wafers 61 and 62 stacked on top of each other in the Z direction. As shown in Fig. 12B , the semiconductor wafer 61 includes a semiconductor layer 22, a multilayer wiring layer 23 stacked on the element formation surface side of the semiconductor layer 22, and a multilayer wiring layer 25 stacked on the side of the semiconductor layer 22 opposite the multilayer wiring layer 23 side. As shown in Fig. 12B , the semiconductor wafer 62 includes a semiconductor layer 32 and a multilayer wiring layer 33 stacked on the element formation surface side of the semiconductor layer 32. The semiconductor wafers 61 and 62 are bonded together with the multilayer wiring layer 23 side of the semiconductor wafer 61 and the multilayer wiring layer 33 side of the semiconductor wafer 62 facing each other.

[0101] 13A to 20 show, as an example, one chip formation region 65 of the wafer stack 60. Also, Fig. 13A to 20 show the state of the wafer stack 60 formed by carrying out the wafer stacking step in the manufacturing process of the photodetector 1A.

[0102] 13B , the chip formation region 65 includes a multilayer wiring layer 25, a semiconductor layer 22, a multilayer wiring layer 23, a multilayer wiring layer 33, and a semiconductor layer 32. The bonding metal pad 24 of the multilayer wiring layer 23 is directly bonded to the bonding metal pad 34 of the multilayer wiring layer 33, thereby establishing electrical continuity between the multilayer wiring layer 23 and the multilayer wiring layer 33. The uppermost insulating layer 26 of the multilayer wiring layer 23 is directly bonded to the uppermost insulating layer of the multilayer wiring layer 23. The chip formation region 65 has a bonding surface 20a on the side of the multilayer wiring layer 25 opposite the semiconductor layer 22. The bonding surface 20a includes the uppermost insulating layer 26 of the multilayer wiring layer 25 and a bonding metal pad 27 provided in the insulating layer 26 with its surface (bonding surface) exposed from the insulating layer 26. 3, the logic circuit 13, the bonding pads (input / output terminals) 14, the pixel circuits 16, and the like shown in Figures 1 and 2 are already formed in the chip formation region 65. Hereinafter, steps after forming the wafer stack 60 (steps after the wafer stacking step) will be described.

[0103] In this first embodiment, the case where the photoelectric conversion region 35, the color filter layer 36, and the microlens 37 have already been formed will be described, but the photoelectric conversion region 35, the color filter layer 36, and the microlens 37 may also be formed after the insulator formation process described below.

[0104] 13A and 13B is formed, the second semiconductor chip 40 is mounted in the chip formation region 65 (chip mounting region Cm) of the wafer stack 60, as shown in Figures 14A and 14B. The second semiconductor chip 40 is mounted by directly bonding the bonding surface 40a of the second semiconductor chip 40 to the bonding surface 20a of the wafer stack 60.

[0105] Specifically, first, a surface improvement process is performed to activate the bonding surface 20a of the wafer stack 60. This surface improvement process involves, for example, irradiating the bonding surface 20a of the wafer stack 60 with plasma to remove oxides and adsorbates and create dangling atomic bonds. In the surface modification process for activating the bonding surface 40a of the second semiconductor chip 40 described above, dangling atomic bonds are also created by, for example, plasma irradiation.

[0106] In this process, the surface improvement treatment is performed on the surface portions of the insulating layer 26 and the bonding metal pads 27 included in the bonding surface 20a of the wafer stack 60. The surface improvement treatment is also performed on the surface portions of the insulating layer 46 and the bonding metal pads 47 included in the bonding surface 40a of the second semiconductor chip 40.

[0107] Next, the second semiconductor chip 40 is mounted in the chip formation area (chip mounting area) 65 of the wafer stack 60 with the bonding surface portion 20a and bonding metal pad 27 of the wafer stack 60, which has been subjected to surface improvement treatment, facing the bonding surface portion 40a and bonding metal pad 47 of the second semiconductor chip 40, which has also been subjected to surface improvement treatment.

[0108] Next, the bonding surface portion 40a of the second semiconductor chip 40 is pressed (press-welded) to the bonding surface portion 20a of the wafer stack 60 so that a bonding wave is generated from the center toward the periphery of the second semiconductor chip 40 in a two-dimensional plane.

[0109] In this process, unbonded portions of the bonding surface 20a of the wafer stack 60 and unbonded portions of the bonding surface 40a of the second semiconductor chip 40 are bonded, and the bonding surface 20a of the wafer stack 60 and the bonding surface 40a of the second semiconductor chip 40 are bonded by surface activated bonding. More specifically, the insulating layer 26 included in the bonding surface 20a of the wafer stack 60 and the insulating layer 46 included in the bonding surface 40a of the second semiconductor chip 40 are bonded by surface activated bonding, and the bonding metal pad 27 included in the bonding surface 20a of the wafer stack 60 and the bonding metal pad 47 included in the bonding surface 40a of the second semiconductor chip 40 are bonded by surface activated bonding.

[0110] Next, as shown in FIGS. 15A and 15B , a sacrificial film 55a covering the top surface 40b and side surface 40c of the second semiconductor chip 40 is formed on the bonding surface 20a side of the wafer stack 60. The sacrificial film 55a is selectively formed to individually encase each semiconductor chip 40. The sacrificial film 55a is used to provide a void 55 between the second semiconductor chip 40 and the insulator 51, which will be formed in a subsequent process. The void 55 can be formed by selectively removing the sacrificial film 55a by etching. Therefore, it is preferable to use a material for the sacrificial film 55a that can ensure a sufficient etching selectivity with respect to the insulating layer 26 of the wafer stack 60, the second semiconductor chip 40, and the insulator 51, which will be described later. In this first embodiment, for example, an amorphous silicon (a-Si) film is used as the sacrificial film 55a. The shape and thickness of the sacrificial film 55a determine the shape and thickness of the void 55.

[0111] Next, as shown in FIGS. 16A and 16B , an insulator 51 is formed on the bonding surface 20a of the wafer stack 60, covering the top surface 40b and side surface 40c of each of the two second semiconductor chips 40 and having a flattened surface layer on the side opposite the wafer stack 60. The insulator 51 can be formed, for example, by depositing an insulating film on the bonding surface 20a of the wafer stack 60 by chemical vapor deposition (CVD) or spin coating so as to cover the entire second semiconductor chip 40, and then flattening the surface of the insulating film by chemical mechanical polishing (CMP). While organic or inorganic films can be used as the insulator 51, inorganic films are preferred in terms of moisture absorption resistance. In this first embodiment, a silicon oxide film, for example, is used as the inorganic film. In this process, the insulator 51 is formed at a temperature higher than room temperature. After formation, the temperature of the insulator 51 returns to room temperature from the film-forming temperature. The temperatures of the wafer stack 60 and the second semiconductor chip 40 also return to room temperature from the deposition temperature of the insulator 51. In this process, contraction stress occurs as an internal stress in the second semiconductor chip 40, and expansion stress occurs as an internal stress in the insulator 51.

[0112] Next, as shown in FIGS. 17A and 17B , openings 52 are formed in the insulator 51 on the top surface 40 b of the second semiconductor chip 40, penetrating the insulator 51 in the Z direction. The openings 52 extend from the outside of the insulator 51 to the sacrificial film 55 a on the inside, exposing the sacrificial film 55 a through the openings 52. The openings 52 can be formed by selectively etching the insulator 51 using well-known photolithography and dry etching techniques. While FIGS. 17A and 17B illustrate an example in which two openings 52 are provided for one second semiconductor chip 40, the locations where the openings 52 are provided and the number of openings 52 are not limited to those illustrated in FIGS. 17A and 17B .

[0113] Next, the sacrificial film 55a shown in FIG. 17B is selectively removed to form the cavity 55 as shown in FIG. 18. The sacrificial film 55a is removed by, for example, wet etching. Specifically, an etching solution is supplied to the sacrificial film 55a through the opening 52 in the insulator 51, and the sacrificial film 55a is etched and removed with the supplied etching solution. The wet etching of the sacrificial film 55a is performed under conditions that ensure a sufficient selectivity with respect to the insulator 51 and the second semiconductor chip 40. In this process, the cavity 55 is formed with a shape and thickness that reflect the shape and thickness of the sacrificial film 55a.

[0114] 19 , a cap film 53 is formed to close the opening 52 of the insulator 51. In the first embodiment, the case where the opening 52 of the insulator 51 is selectively closed with the cap film 53 is illustrated, but the cap film 53 may be formed on the entire upper surface side of the insulator 51 so as to cover the opening 52, thereby closing the opening 52 with the cap film 53. It is preferable to use a film similar to that of the insulator 51 as the cap film 53.

[0115] Next, as shown in FIG. 20, a bonding opening 38 is formed which penetrates the semiconductor layer 32 in the Z direction and exposes the surface of the bonding pad 14 .

[0116] 21 , the plurality of chip formation regions 65 of the wafer stack 60 are individually diced along scribe lines 66 to form the first semiconductor chips 20. Then, the second semiconductor chip 40 is mounted on the bonding surface 20a side of the first semiconductor chip 20, and the photodetector 1A having a three-dimensional structure in which the second semiconductor chip 40 is covered with the insulator 51 is almost completed.

[0117] <<Main Effects of the First Embodiment>> Next, the main effects of the first embodiment will be described with reference to Fig. 16B and Fig. 22. Fig. 22 is a vertical cross-sectional view showing an insulator formation step in the manufacturing process of a photodetector as a reference example of the related art. Note that in Fig. 22, the same parts as those in the first embodiment are denoted by the same reference numerals.

[0118] 22 , in the manufacturing process of the photodetector 1A, the insulator 51 is formed on the bonding surface 20 a of the wafer stack 60 so as to cover the second semiconductor chip 40 mounted on the bonding surface 20 a of the wafer stack 60. In this process, the insulator 51 is formed at a film-forming temperature higher than room temperature. After the formation, the insulator 51 returns to room temperature from the film-forming temperature. The wafer stack 60 and the second semiconductor chip 40 also return to room temperature from the film-forming temperature of the insulator 51.

[0119] 22, after the insulator 51 is formed, a contraction stress (compression stress) Sc is generated as an internal stress in the second semiconductor chip 40, and an expansion stress (tensile stress) St is generated as an internal stress in the insulator 51. Due to the difference in the internal stress between the second semiconductor chip 40 and the insulator 51, a stress strain S is generated in the chip formation region 65 (second semiconductor chip 20) of the wafer stack 60, as shown in FIG. １ This stress-strain S １ This may cause variations in the photoelectric conversion characteristics of the photoelectric conversion section 35 provided in the chip formation region 65 (first semiconductor chip 20) of the wafer stack 60, which may result in a decrease in manufacturing yield.

[0120] In contrast, the photodetector 1A of the first embodiment has gaps 55 as buffers between the insulator 51 and each of the top surface 40b and side surface 4c of the second semiconductor chip 40. The gaps 55 suppress interference between the internal stress (contraction stress Sc) of the second semiconductor chip 40 and the internal stress (expansion stress St) of the insulator 51.

[0121] Therefore, in the manufacturing process of the photodetector 1A, the interference between the internal stress (contraction stress Sc) of the second semiconductor chip 40 and the internal stress (expansion stress St) of the insulator 51, which is generated by the formation of the insulator 51, can be suppressed by the void portion 55, and the stress strain S generated in the chip formation region 65 (first semiconductor chip 20) of the wafer stack 60 due to the difference between the internal stress of the second semiconductor chip 40 and the internal stress of the insulator 51 is reduced. １ This can reduce variations (unevenness) in the photoelectric conversion characteristics of the photoelectric conversion unit 35 due to the stress strain S1, thereby improving the manufacturing yield of the photodetector 1A. Also, color mixing between adjacent pixels 3 can be reduced.

[0122] In this first embodiment, the entire top surface 40b and each of the four side surfaces 40c of the second semiconductor chip 40 are exposed to the void 55 and are separated from the insulator 51, which provides a significant effect in alleviating stress distortion.

[0123] In the first embodiment, the first semiconductor chip 20 has been described as a specific example of the "base member" of the present technology, but the wafer stack 60 can also be considered as the "base member" of the present technology. Here, the photodetector 1A may be packaged in various types of packages and mounted on an electronic device, or may be mounted directly on an electronic device in a chip state. Furthermore, the photodetector 1A may be shipped as a product in a wafer state or in a chip state, and in either case, it is the photodetector 1A to which the present technology is applied.

[0124] <Modifications of First Embodiment> <Modification 1-1> FIG. 23 is a diagram illustrating Modification 1-1 according to the first embodiment of the present disclosure, and is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure taken at the same position as the b6-b6 cutting line in FIG. 6 . This Modification 1-1 is basically configured similarly to the first embodiment described above, with the following differences. That is, as shown in FIG. 23 , in Modification 1-1, the second semiconductor chip 40 mounted on the bonding surface 20a of the first semiconductor chip 20 is covered with a thin protective film 48. The protective film 48 is exposed to the void 55 while entirely covering the top surface 40a and each of the four side surfaces 40c of the second semiconductor chip 40. That is, the second semiconductor chip 40 is not exposed to the void 55.

[0125] The protective film 48 is intended to protect the second semiconductor chip 40 from the etching solution used when wet-etching the sacrificial film 55a shown in FIG. 16B to form the voids 55 in the manufacturing process of the first embodiment described above. Therefore, the protective film 48 is formed before forming the sacrificial film 55a shown in FIG. 15B of the first embodiment described above. It is preferable to use an insulating film with a sufficiently high etching selectivity relative to the sacrificial film 55a as the protective film 48. For example, since an amorphous silicon film is used as the sacrificial film 55a in the first embodiment described above, a silicon oxide film that has a high etching selectivity relative to the amorphous silicon film can be used as the protective film 48.

[0126] In this modified example 1-1, the same effects as those of the first embodiment can be obtained.

[0127] In addition, in this modification 1-1, the second semiconductor chip 40 mounted on the bonding surface portion 20a side of the first semiconductor chip 20 is covered with the protective film 48. This makes it possible to suppress damage to the second semiconductor chip 40 caused by the etching solution when the sacrificial film 55a is wet-etched to form the void portion 55, thereby further improving the manufacturing yield of the photodetector 1A.

[0128] <Modification 1-2> FIG. 24 is a diagram according to Modification 1-2 of the first embodiment, and is a vertical cross-sectional view schematically showing the vertical cross-sectional structure at the same position as the cutting line a6-a6 in FIG.

[0129] This modified example 1-2 basically has the same configuration as the first embodiment described above, but differs in the following configuration: That is, as shown in Figure 24, this modified example 1-2 further includes a support plate 80 provided on the side of the insulator 51 opposite to the first semiconductor chip 20 side.

[0130] In this modification 1-2, the same effects as those of the first embodiment can be obtained. Furthermore, in this modification 1-2, since the support plate 80 is provided on the side of the insulator 51 opposite to the first semiconductor chip 20 side, the mechanical strength of the photodetector 1A can be increased.

[0131] <Modification 1-3> FIG. 25 is a diagram showing Modification 1-3 according to the first embodiment of the present technology, and is a vertical cross-sectional view showing a step of reducing the thickness of the second semiconductor chip.

[0132] This modified example 1-3 basically has the same configuration as the first embodiment described above, but differs in the following configuration.

[0133] 25, in this modification 1-3, the thickness in the Z direction of the semiconductor layer 42 of the second semiconductor chip 40 is reduced, thereby thinning the second semiconductor chip 40. This thinning of the second semiconductor chip 40 can reduce the thickness of the photodetector 1A. The thickness in the Z direction of the semiconductor layer 42 can be reduced by grinding the surface layer portion of the semiconductor layer 42 on the side opposite to the multilayer wiring layer 45 side, for example, by CMP.

[0134] In this modification 1-3, similarly to the first embodiment described above, it is possible to improve the manufacturing yield of the photodetector 1A and also to reduce the thickness of the photodetector 1A.

[0135] 26A is a diagram illustrating a modification 1-4 according to the first embodiment of the present disclosure, and is a plan view schematically illustrating a planar pattern of a support portion of an insulator. Fig. 26B is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure taken along the b26-b26 cutting line in Fig. 26A.

[0136] This modified example 1-4 basically has the same configuration as the above-described first embodiment, but differs in the following configuration: That is, as shown in Figures 26A and 26B, this modified example 1-4 differs in the shape of the inner side (second semiconductor chip 40 side) of the insulator 51.

[0137] The insulator 51 of this modified example 1-4 is in partial contact with the top surface 40b opposite to the bonding surface 40a of the second semiconductor chip 40. Specifically, the insulator 51 of this modified example 1-4 includes a main body 51a that is spaced apart from the second semiconductor chip 40 across a gap 55 and covers the entire second semiconductor chip 40, and support pillars 51b that extend from the main body 51a on the top surface 40b of the second semiconductor chip 40 across the gap 55 in the thickness direction (Z direction) of the second semiconductor chip 40 and are in partial contact with the top surface 40b of the second semiconductor chip 40.

[0138] The support pillars 51b are configured, for example, in a cylindrical shape, but are not limited thereto. A plurality of support pillars 51b are provided. Although six support pillars 51b are illustrated in FIG. 26A, the number and size of the support pillars 51b are not limited to the number and size shown in FIG. 26A. Furthermore, although the support pillars 51b are configured in a cylindrical shape in this modified example 1-4, the support pillars 51b may also be configured in a prismatic shape. That is, the planar shape of the support pillars 51b may be circular or rectangular, or may be striped as described below.

[0139] In this way, by providing the support portion 51b in the insulator 51, which contacts the upper surface portion 40b of the second semiconductor chip 40, the mechanical strength of the insulator 51 can be maintained.

[0140] Here, there is a market demand for miniaturization of electronic devices incorporating image sensors (photodetectors) such as distance measuring devices and solid-state imaging devices, and the three-dimensional structure of the photodetector 1A is also being made thinner. As this thinning occurs, the thickness of the insulator 51 becomes thinner, and the mechanical strength of the insulator 51 decreases. In particular, the decrease in mechanical strength becomes more pronounced where the void portion 55 of the insulator 51 is provided. Therefore, in this modified example 1-4 in which the insulator 51 is configured to be in partial contact with the upper surface portion 40b of the second semiconductor chip 40, the stress strain S generated in the chip formation region 65 (second semiconductor chip 20) of the wafer stack 60 due to the difference in internal stress between the second semiconductor chip 40 and the insulator 51 is reduced. １ This is useful for ensuring the mechanical strength of the insulator 51 while mitigating the above-mentioned problems.

[0141] In this modification 1-4, even when the gap 55 is provided, the mechanical strength of the insulator 51 can be ensured, and the same effects as those of the first embodiment can be obtained.

[0142] The support pillars 51b can be rephrased as protrusions that protrude from the main body 51a toward the second semiconductor chip 40. The support pillars 51b of this modified example 1-1 can be easily formed by devising the patterning of the sacrificial film 55a in the manufacturing process of the photodetector 1A.

[0143] 27A is a diagram illustrating a modification 1-5 according to the first embodiment of the present disclosure, and is a plan view schematically illustrating a planar pattern of a support portion of an insulator. Fig. 27B is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure taken along the b27-b27 cutting line in Fig. 27A.

[0144] This modified example 1-5 basically has the same configuration as the above-described first embodiment, but differs in the following configuration: That is, as shown in Figures 27A and 27B, in this modified example 1-5, the shape of the support portion 51b of the insulator 51 is different.

[0145] 27A and 27B, the support pillars 51b of this modified example 1-5 are configured in a stripe shape extending in the X direction on the top surface 40b of the second semiconductor chip 40. The support pillars 51b of this modified example 1-5 are repeatedly arranged at predetermined intervals in the Y direction.

[0146] Like the support portion 51b of the above-mentioned modification 1-4, the support portion 51b of this modification 1-5 also extends from the main body portion 51a on the upper surface portion 40b of the second semiconductor chip 40 across the gap portion 55 in the thickness direction (Z direction) of the second semiconductor chip 40 and partially contacts the upper surface portion 40b of the second semiconductor chip 40.

[0147] In this variant 1-5, even when a void portion 55 is provided, the mechanical strength of the insulator 51 can be ensured, and the manufacturing yield of the photodetector 1A can be improved, as in the first embodiment described above.

[0148] 27A may be rotated by 90 degrees. In this case, the support columns 51b extend in the Y direction and are repeatedly arranged at predetermined intervals in the X direction. In this case, even when the gaps 55 are provided, the mechanical strength of the insulator 51 can be ensured, and the same effects as those of the first embodiment can be obtained.

[0149] Furthermore, the support column 51b of this modified example 1-5 can also be easily formed by devising the patterning of the sacrificial film 55a in the manufacturing process.

[0150] <Modification 1-6> Fig. 28A is a diagram showing Modification 1-6 according to the first embodiment of the present technology, and is a plan view schematically showing a planar pattern of a support portion of an insulator. Fig. 28B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a28-a28 cutting line in Fig. 28A. Fig. 28C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b28-b28 cutting line in Fig. 28A.

[0151] This modified example 1-6 basically has the same configuration as the above-described first embodiment, but differs in the following configuration: That is, as shown in Figures 28A and 28B, in this modified example 1-6, the shape of the support portion 51b of the insulator 51 is different.

[0152] As shown in Figures 28A and 28B, the support pillar 51b of this modified example 1-6 has a lattice-like planar shape on the top surface 40b of the second semiconductor chip 40. Specifically, the support pillar 51b of this modified example 1-6 includes a first support pillar portion 51bx extending in the X direction and a second support pillar portion 51by extending in the Y direction. The first support pillar portion 51bx and the second support pillar portion 51by are orthogonal to each other in the same plane. The first support pillar portions 51bx are repeatedly arranged at predetermined intervals in the Y direction. The second support pillar portions 51by are repeatedly arranged at predetermined intervals in the X direction. Like the support portion 51b of the above-mentioned modification 1-4, the support portion 51b of this modification 1-6 also extends from the main body portion 51a on the upper surface portion 40b of the second semiconductor chip 40 across the gap portion 55 in the thickness direction (Z direction) of the second semiconductor chip 40 and partially contacts the upper surface portion 40b of the second semiconductor chip 40.

[0153] In this variant 1-6, even when a void portion 55 is provided, the mechanical strength of the insulator 51 can be ensured, and the manufacturing yield of the photodetector 1A can be improved, as in the first embodiment described above.

[0154] The support column 51b of this modified example 1-6 can also be easily formed by devising the patterning of the sacrificial film 55a in the manufacturing process of the photodetector 1A.

[0155] 29A is a diagram illustrating a modification 1-7 according to the first embodiment of the present disclosure, and is a plan view schematically illustrating a planar pattern of a support portion of an insulator. Fig. 29B is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure taken along the b29-b29 cutting line in Fig. 29A.

[0156] This modified example 1-7 has a configuration basically similar to that of the above-described first embodiment, but differs in the following configuration: That is, as shown in Figures 29A and 29B, this modified example 1-7 has a different inner shape of the insulator 51.

[0157] As shown in FIGS. 29A and 29B, the insulator 51 of this modification 1-7 includes the main body portion 51a and the support portion 51b of the above-described modification 1-4, and further includes support portions 51b extending from the main body portion 51a above the gap 55 outside the side surface portion 40c of the second semiconductor chip 40 in the thickness direction (Z direction) of the second semiconductor chip 40 across the gap 55 and in contact with the first semiconductor chip 20. １ In this modified example 1-7, the planar size of the gap 55 is larger than the planar size of the gap 55 shown in the above modified example 1-4.

[0158] Support portion 51b １ For example, the support pillar 51b is configured in a cylindrical shape similar to the support pillar 51b on the first semiconductor chip 40. １ 29A, a plurality of support pillars 51b are provided on the outer side of second semiconductor chip 40 so as to surround second semiconductor chip 40 in a plan view. １ In the example shown, the support portions 51b are arranged in a single row. １ The arrangement and number of are not limited to those shown in FIG. 29A.

[0159] Support portion 51b １ The length of the insulator 51 along the thickness direction (Z direction) is longer than the support column 51b on the second semiconductor chip 40. In this modification 1-7, the length of the support column 51b is longer than the length of the support column 51b by the thickness of the second semiconductor chip 40. １ The length of is longer.

[0160] In this modification 1-7, the support column 51b located on the top surface 40b of the first semiconductor chip 40 corresponds to a specific example of the "first support column" of the present technology, and the support column 51b located outside the side surface 40c of the first semiconductor chip 40 corresponds to a specific example of the "first support column" of the present technology. １ corresponds to a specific example of a “second support portion” of the present technology.

[0161] In this modification 1-7, support posts 51b are provided on the outer side of second semiconductor chip 40.１ , the stress strain S generated in the chip formation region 65 (second semiconductor chip 20) of the wafer stack 60 due to the difference between the internal stress of the second semiconductor chip 40 and the internal stress of the insulator 51 is reduced. １ Even if the planar size of the void 55 is made larger than that of the above-described modification 1-4 in order to further suppress relaxation of the stress, it is possible to ensure the mechanical strength of the insulator 51. Therefore, according to this modification 1-7, it is possible to ensure the mechanical strength of the insulator 51 and also to improve the manufacturing yield of the photodetector 1A, as in the above-described first embodiment.

[0162] In addition, the support column 51b and the support column 51b １ This can also be easily formed by devising the patterning of the sacrificial film 55a in the manufacturing process of the photodetector 1A.

[0163] <Modification 1-8> FIG. 30A is a diagram illustrating Modification 1-8 according to the first embodiment of the present technology, and is a plan view schematically illustrating an arrangement pattern of connecting voids and separating voids provided in an insulator.

[0164] FIG. 30B is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure taken along the b30-b30 cutting line in FIG. 30A.

[0165] This modified example 1-8 has a configuration basically similar to that of the above-described first embodiment, but differs in the configuration of the insulator 51. That is, as shown in Figures 30A and 30B, the insulator 51 of this modified example 1-8 includes a connecting void portion 56a connected to the void portion 55 and a separating void portion 56b provided at a distance from the void portion 55.

[0166] The connecting voids 56a are configured in a stripe shape that extends in the X direction from the inside to the outside of the second semiconductor chip 40 in a plan view and crosses the voids 55. The separating voids 56b are configured in a stripe shape that extends in the X direction outside the second semiconductor chip 40 in a plan view. Like the voids 55, the connecting voids 56a and the separating voids 56b each relieve (suppress) distortion that occurs in the chip formation region 65 (first semiconductor chip 20) of the wafer stack 60 due to the difference in internal stress between the insulator 51 and the second semiconductor chip 40.

[0167] Figures 30A and 30B illustrate three connecting voids 56a arranged repeatedly at a predetermined interval in the Y direction in a plan view, but the number of connecting voids 56a is not limited to the example shown in Figures 30A and 30B.

[0168] Furthermore, Figures 30A and 30B illustrate an example in which one spaced gap 56b is provided on the outside of each of two side portions 40c located on opposite sides of the second semiconductor chip 40 in the Y direction, but the number of spaced gaps 56b is not limited to the example shown in Figures 30A and 30B.

[0169] In this modification 1-8, the connecting gap 56a corresponds to a specific example of "connecting buffer portion" in the present technology, and the separating gap 56b corresponds to a specific example of "separating gap portion" in the present technology.

[0170] The insulator 51 of this modified example 1-8 includes the connecting void portion 56a and the separating void portion 56b, and therefore the substantial volume can be reduced without changing the outer size of the insulator 51. As a result, the stress strain S generated in the chip formation region 65 (second semiconductor chip 20) of the wafer stack 60 due to the difference in internal stress between the second semiconductor chip 40 and the insulator 51 during the manufacturing process of the photodetector 1A is reduced. １ can be further alleviated compared to the first embodiment described above, and the manufacturing yield of the photodetector 1A can be improved as in the first embodiment described above.

[0171] In this modified example 1-8, the case where both the connecting voids 56a and the separating voids 56b are provided in the insulator 51 has been described, but a configuration in which either the connecting voids 56a or the separating voids 56b are provided in the insulator may also be used. Even in this case, the stress strain S generated in the chip formation region 65 (second semiconductor chip 20) of the wafer stack 60 due to the difference in internal stress between the second semiconductor chip 40 and the insulator 51 during the manufacturing process of the photodetector 1A may be increased. １ can be further alleviated compared to the first embodiment.

[0172] Furthermore, even when the connecting gap 56a and the separating gap 56b are each extended in the Y direction, the same effect as in Modification 1-8 can be obtained.

[0173] The connecting gap 56a and the separating gap 56b can be rephrased as a connecting recess 56a and a separating recess 56b, respectively.

[0174] <Modification 1-9> Fig. 31A is a diagram showing Modification 1-9 according to the first embodiment of the present technology, and is a plan view schematically showing a planar pattern of voids provided in an insulator. Fig. 31B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a31-a31 cutting line in Fig. 31A. Fig. 31C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b31-b31 cutting line in Fig. 31A.

[0175] This modified example 1-9 has a configuration basically similar to that of the above-described first embodiment, but differs in the configuration of the insulator 51. That is, as shown in Figures 31A to 31C, the insulator 51 of this modified example 1-9 includes void portions 57 that have a lattice-like planar shape in plan view.

[0176] The cavity 57 extends in the X direction across the second semiconductor chip 40 and the cavity 55, and is connected to the cavity 55 by a first connecting cavity portion 57x. １ and a first spaced gap portion 57x that is spaced from the second semiconductor chip 40 and the gap portion 55 in a plan view and extends in the X direction. ２The insulator 51 of the modified example 1-9 also includes a second connecting void portion 57y that extends in the Y direction across the second semiconductor chip 40 and the void portion 55 in a plan view and is connected to the void portion 55. １ and a second spaced gap portion 57y extending in the Y direction and spaced from the second semiconductor chip 40 and the gap portion 55 in a plan view. ２ and,

[0177] As shown in FIGS. 31A and 31C, the first connecting gap portion 57x １ and the first spaced gap portion 57x ２ are arranged at predetermined intervals in the Y direction. In FIGS. 31A and 31C, three first connecting gap portions 57x １ and two first spaced apart gap portions 57x ２ The first connecting gap portion 57x is shown as an example. １ and the first spaced gap portion 57x ２ The number of each of the above is not limited to the example shown in FIG. 31A.

[0178] As shown in FIGS. 31A and 31B, the second connecting gap portion 57y １ and the second spaced gap portion 57y ２ are arranged at predetermined intervals in the X direction. In FIGS. 31A and 31B, one second connecting gap portion 57y １ and two second spaced apart gap portions 57y ２ The second connecting gap portion 57y is shown as an example. １ and the second spaced gap portion 57y ２ The number of each of the above is not limited to the example shown in FIG. 31A.

[0179] As shown in FIG. 31A, the first connecting gap portion 57x １ and the first spaced gap portion 57x ２ is the second connecting gap portion 57y １ and the second spaced gap portion 57y ２ The first connecting gap portion 57x is in the same plane and is perpendicular to the first connecting gap portion 57x. １ and the second connecting gap portion 57y １The depth of each of the portions along the thickness direction (Z direction) of the second semiconductor chip 40 differs between the portion overlapping with the second semiconductor chip 40 in a planar view and the portion located outside the second semiconductor chip 40, and the depth of the portion located outside the second semiconductor chip 40 is deeper than the depth of the portion overlapping with the second semiconductor chip 40.

[0180] The insulator 51 of this modified example 1-9 includes lattice-shaped voids 57 in a planar shape, and therefore, similar to the modified example 1-8 described above, the substantial volume can be reduced without changing the external size of the insulator 51. As a result, the stress strain S generated in the chip formation region 65 (second semiconductor chip 20) of the wafer stack 60 due to the difference in internal stress between the second semiconductor chip 40 and the insulator 51 during the manufacturing process of the photodetector 1A can be reduced. １ can be further alleviated compared to the first embodiment described above, and the manufacturing yield of the photodetector 1A can be improved as in the first embodiment described above.

[0181] The void 57 can be rephrased as a recess 57. The first connecting void portion 57x included in the void 57 １ , first spaced gap portion 57x ２ , second connection gap portion 57y １ and the second spaced gap portion 57y ２ are the first recessed portions 57x １ , first spaced apart concave portion 57x ２ , second connecting concave portion 57y １ , second spaced concave portion 57y ２ This can be rephrased as follows.

[0182] [Second Embodiment] In this second embodiment, a case where a buffer film is used as a specific example of the "buffer section" of the present technology will be described. Fig. 32 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photodetector according to a second embodiment of the present technology. Fig. 33 is a longitudinal sectional view enlarging a part of Fig. 32. Note that Fig. 33 is upside down compared to Fig. 32.

[0183] 32 and 33 , the photodetector 1B according to the second embodiment of the present technology has a configuration basically similar to that of the photodetector 1A according to the first embodiment described above, but differs in the following configuration. That is, as shown in FIGS. 32 and 33 , the photodetector 1B according to the second embodiment of the present technology includes a buffer film 59 instead of the void portion 55 shown in FIG. 7A of the first embodiment described above. The buffer film 59 has a thermal expansion coefficient that is smaller than that of the second semiconductor chip 40 and larger than that of the insulator 51 (thermal expansion coefficient of the second semiconductor chip 40 > thermal expansion coefficient of the buffer film 59 > thermal expansion coefficient of the insulator 51). In this third embodiment, the buffer film 59 corresponds to a specific example of a "buffer portion" according to the present technology.

[0184] 32 and 33 , the buffer film 59 serving as a buffer is provided between the insulator 51 and the top surface 40b and side surface 40c of the second semiconductor chip 40, as in the first embodiment described above. Also in this second embodiment, the buffer film 59 is provided so as to cover the entire top surface 40b of the semiconductor chip 40 and each of the four side surface portions 40c of the semiconductor chip 40. In other words, the buffer film 59 encompasses the entire top surface 40b of the semiconductor chip 40 and each of the four side surface portions 40c of the semiconductor chip 40. In yet other words, the top surface 40b and each of the four side surface portions 40c of the second semiconductor chip 40 are in contact with the buffer film 59.

[0185] In this buffer film 59, as in the case of the void portion 55 of the first embodiment described above, the stress strain S 100 occurs in the chip formation region 65 (first semiconductor chip 20) of the wafer stack 60 due to the difference between the internal stress of the insulator 51 and the internal stress of the second semiconductor chip 40 during the manufacturing process of the photodetector 1B. １The buffer film 59 can be formed in the manufacturing process of the photodetector 1B by forming a buffer film on the bonding surface 20a side of the wafer stack 60 so as to cover the second semiconductor chip 40 mounted on the bonding surface 20a of the wafer stack 60, and then patterning the buffer film into a predetermined shape. For example, a silicon nitride film can be used as the buffer film 59. The thermal expansion coefficient of the silicon nitride film can be controlled by changing the conditions (reactive gas, pressure, temperature, high-frequency power, etc.) during film formation.

[0186] Since the second semiconductor chip 40 includes the semiconductor layer 42 and the multi-layer wiring layer 45, the thermal expansion coefficient of the second semiconductor chip 40 differs depending on the material of the semiconductor layer 42, the number of layers in the multi-layer wiring layer 45, and the like.

[0187] In the photodetector 1B according to the second embodiment, too, the buffer film 59 can suppress interference between the internal stress (contraction stress Sc) of the second semiconductor chip 40 and the internal stress (expansion stress St) of the insulator 51, which occurs during the manufacturing process of the photodetector 1BC. The difference between the internal stress of the second semiconductor chip 40 and the internal stress of the insulator 51 reduces the stress strain S generated in the chip formation region 65 (second semiconductor chip 20) of the wafer stack 60. １ This can reduce variations (unevenness) in the photoelectric conversion characteristics of the photoelectric conversion unit 35 due to the stress strain S1, thereby improving the manufacturing yield of the photodetector 1B. Also, color mixing between adjacent pixels 3 can be reduced.

[0188] In the second embodiment, the entire top surface portion 40b and the four side surface portions 40c of the second semiconductor chip 40 are in contact with the buffer film 59 and are separated from the insulator 51, so that the stress strain S １ The mitigation effect is large.

[0189] Modification of Second Embodiment The buffer film 59 is not limited to that of the second embodiment. For example, the buffer film 59 can be used as a buffer portion instead of the gap 55 shown in Modification 1-1 ( FIG. 23 ). In this case, the buffer film 59 is present in the gap 55 in FIG. 23 , and the buffer film 59 is present between the insulator 51 and the protective film 48.

[0190] Also, when the support plate 80 shown in the above-described modified example 1-2 (FIG. 24) is provided, the buffer film 59 can be used as the buffer portion instead of the gap portion 55 .

[0191] Furthermore, in the manufacturing process of the photodetector, even when the chip thinning step shown in the above-described modified example 1-3 (FIG. 25) is carried out, the buffer film 59 can be used as the buffer portion instead of the gap portion 55 .

[0192] Furthermore, as the buffer portion, a buffer film 59 can be applied instead of the gap portion 55 shown in each of the above-described modified examples 1-4 (FIGS. 26A and 26B), 1-5 (FIGS. 27A and 76B), 1-6 (FIGS. 28A and 28B), 1-7 (FIGS. 29A, 29B, and 29C), and 1-8. In this case, the buffer film 59 is present in the gap portion 55, and the support portions 51b, 51b of the insulator 51 are １ is surrounded by the buffer film 59.

[0193] Furthermore, as the buffer portion, a buffer film 59 can be applied in place of each of the gap portion 55, the connecting gap portion 56a, and the separating gap portion 56b shown in the above-described modified example 1-8 (FIGS. 30A and 30B). In this case, the buffer film 59 is present in each of the gap portion 55, the connecting gap portion 56a, and the separating gap portion 56b.

[0194] Furthermore, as the buffer portion, a buffer film 59 can be applied in place of each of the gaps 55 and 57 shown in the above-described modified example 1-9 (FIGS. 31A, 31B, and 31C). １ and the first spaced gap portion 57x ２ and the second connecting gap portion 57y １ and the second spaced gap portion 57y ２In this case, the buffer film 59 is present in each of the gaps 55 and 57.

[0195] These modifications also provide the same effects as the modifications of the first embodiment described above.

[0196] [Third Embodiment] In this third embodiment, a photodetector (semiconductor device) using a support plate instead of an insulator will be described. Fig. 34 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photodetector according to a third embodiment of the present technology. Fig. 35 is a development view of Fig. 34. Fig. 36 is a longitudinal sectional view schematically showing a bonding state between a first semiconductor chip, a second semiconductor chip, and the support plate of Fig. 34.

[0197] <Overall Configuration of Photodetector> As shown in Fig. 34 and Fig. 35 , a photodetector 1C according to the third embodiment of the present technology has a configuration basically similar to that of the photodetector 1A according to the above-described first embodiment, but differs in the following configuration: That is, as shown in Fig. 34 and Fig. 35 , the photodetector 1C according to the third embodiment of the present technology includes a support plate 81 and a gap 83 instead of the insulator 51 and the gap 55 according to the above-described first embodiment shown in Fig. 4 and Fig. 5 .

[0198] <Support Plate> As shown in Figures 34 and 35, the support plate 81 is provided on the bonding surface portion 20a side of the first semiconductor chip 20, and covers the second semiconductor chip 40 mounted on the bonding surface portion 20a side of the first semiconductor chip 20.

[0199] The support plate 81 has a bonding surface portion 81a and an upper surface portion (rear surface portion) 81b located on opposite sides in the thickness direction (Z direction) of the support plate 81, and a recess 82 recessed from the bonding surface portion 81a toward the upper surface portion 81b and accommodating the second semiconductor chip 40 mounted on the bonding surface portion 20a side of the first semiconductor chip 20. The bonding surface portion 81a of the support plate 81 is bonded to the bonding surface portion 20a of the first semiconductor chip 20 with the second semiconductor chip 40 located inside the recess 82. That is, the photodetector 1C according to the third embodiment has the recess 82 for accommodating the second semiconductor chip 40 and includes the support plate 81 bonded to the bonding surface portion 20a of the first semiconductor chip 20 with the second semiconductor chip 40 located inside the recess 82.

[0200] Although not shown in detail, the support plate 81 has a square planar shape in plan view, similar to the insulator 51 of the first embodiment described above, and in this third embodiment, has a rectangular planar shape similar to that of the first semiconductor chip 20. The planar size of the support plate 81 is approximately the same as that of the first semiconductor chip 20. In the thickness direction (Z direction) of the photodetector 1C, side surface portions 81c of the outer periphery of the support plate 81 and side surface portions 20c of the outer periphery of the first semiconductor chip 20 are flush with each other, as shown in FIGS.

[0201] The support plate 81 fills in any step on the bonding surface 20a side of the first semiconductor chip 20 caused by the thickness of the second semiconductor chip 40, flattening the bonding surface 20a side of the first semiconductor chip 20, and protecting the bonding surface 20a side of the first semiconductor chip 20 and the second semiconductor chip 40. The support plate 81 also increases the mechanical strength of the photodetector 1C.

[0202] Although a semiconductor substrate can be used as the support plate 81, it is preferable to use an intrinsic semiconductor substrate having an insulating function in order to ensure insulation from the second semiconductor chip 40. In the third embodiment, an intrinsic Si semiconductor substrate made of, for example, single-crystal silicon (Si) is used as the support plate 81. The bonding surface 81a of the support plate 81 includes silicon of the intrinsic Si semiconductor substrate.

[0203] 34 and 35 is not shown in detail, the recess 82 of the support plate 81 has a rectangular planar shape in plan view similar to the planar shape of the second semiconductor chip 40. The recess 82 has a planar size in plan view and a depth in cross-sectional view that are slightly larger than the planar size and thickness of the second semiconductor chip 40.

[0204] 34 and 35 , a recess 82 is provided for each second semiconductor chip 40. Since the photodetector 1C of the third embodiment includes two second semiconductor chips 40, two recesses 82 are provided in the support plate 81.

[0205] <Bonding of First Semiconductor Chip and Support Plate> As explained in the first embodiment above, as shown in Figure 36, the bonding surface 20a of the first semiconductor chip 20 includes an insulating layer 26 located on the top layer of the multilayer wiring layer 25 of the first semiconductor chip 20. The insulating layer 26 in this third embodiment is made of, for example, a silicon oxide film. On the other hand, the bonding surface 81a of the support plate 81 includes silicon as described above.

[0206] 36 , the bonding surface 20a of the first semiconductor chip 20 and the bonding surface 81a of the support plate 81 are bonded by direct bonding. In this third embodiment, the bonding surface 20a of the first semiconductor chip 20 includes a silicon oxide film, and the bonding surface 81a of the support plate 81 includes silicon. Therefore, in this third embodiment, the bonding surface 20a of the first semiconductor chip 20 and the bonding surface 81a of the support plate 81 are bonded by direct bonding between the oxide film on the bonding surface 21a side of the first semiconductor chip 20 and the silicon on the bonding surface 81a side of the support plate 81.

[0207] 36 , the void 83 is provided between the support plate 81 and the second semiconductor chip 40. The void 83 is provided at least between the side surface 40 c of the second semiconductor chip 40 and the recess 82 of the support plate 81. In the third embodiment, the void 83 is provided between each of the side surface 40 c and the top surface 40 b of the second semiconductor chip 40 and the recess 82 of the support plate 81. In other words, the void 83 encompasses the entire top surface 40 b of the second semiconductor chip 40 and each of the entire four side surface portions 40 c of the second semiconductor chip 40. In further other words, the top surface 40 b and each of the entire four side surface portions 40 c of the second semiconductor chip 40 are exposed to the void 83. The void 83 can be selectively provided on the side surface 40 c side and the top surface 40 b side of the second semiconductor chip 40 by changing the planar size and depth of the recess 82 .

[0208] 37D of the wafer stack 90 due to the difference in internal stress between the support plate 81 and the second semiconductor chip 40. The void 83 may be filled with a gas such as air or an inert gas, or may be in a vacuum state.

[0209] <<Method of Manufacturing Photodetector>> Next, a method of manufacturing a photodetector 1C according to the third embodiment of the present technology will be described with reference to FIGS. 37A to 38C. FIG. 37A is a plan view schematically showing a semiconductor wafer for describing a method of manufacturing a support plate included in the method of manufacturing a photodetector according to the third embodiment of the present technology. FIG. 37B is a diagram schematically showing an example of a configuration of a substrate formation region by enlarging region C of FIG. 37A. FIG. 37C is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along cutting line a37-a37 of FIG. 37B. FIG. 38A is a longitudinal sectional view schematically showing a step of the method of manufacturing a photodetector according to the third embodiment of the present technology. FIG. 38B is a longitudinal sectional view schematically showing a step subsequent to the step of FIG. 38A. FIG. 38C is a longitudinal sectional view schematically showing a step subsequent to the step of FIG. 38B.

[0210] The method for manufacturing a photodetector 1C according to the third embodiment uses a semiconductor wafer 90 shown in Figures 37A to 37C and the wafer stack 60 of the first embodiment shown in Figures 12A to 13B. The wafer stack 60 of the third embodiment has a configuration generally similar to that of the wafer stack 60 of the first embodiment, and therefore a description of the wafer stack 60 will be omitted in this third embodiment. Note that Figures 37A and 37B are plan views viewed from the bonding surface side of the semiconductor wafer.

[0211] The support plate 81 included in the photodetector 1C is formed in a support plate forming region 95 of a semiconductor wafer 90 shown in Fig. 37B. The support plate forming regions 95 are partitioned by scribe lines 96 extending in both the X and Y directions, and a plurality of support plate forming regions 95 are arranged in a matrix. Fig. 37B illustrates nine support plate forming regions 95 arranged in a matrix.

[0212] The support plate forming region 95 is then divided into individual small pieces along scribe lines 96 to form the support plate 81. The support plate forming region 95 has a square planar shape in plan view, and in this first embodiment, is rectangular. Note that the scribe lines 96 are not physically formed.

[0213] 37A to 37C , the semiconductor wafer 90 has a bonding surface portion (main surface portion) 81 a and an upper surface portion (rear surface portion) 81 b located on opposite sides, and recesses 82 recessed from the bonding surface portion 81 a toward the upper surface portion 81 b in the support plate forming region 95 and for accommodating the second semiconductor chip 40. In this third embodiment, two recesses 82 are provided for each support plate forming region 95.

[0214] Although not shown in detail, the recess 82 can be formed by selectively etching the bonding surface 81a of the semiconductor wafer 90 toward the upper surface 81b. The planar size and depth of the recess 82 are formed to be slightly larger than the planar size and thickness of the second semiconductor chip 40 to be housed therein. The semiconductor wafer 90 can be, for example, an intrinsic Si semiconductor substrate.

[0215] The support plate forming region 95 of the semiconductor wafer 90 shown in Figure 37B and the chip forming region 65 of the wafer stack 60 shown in Figure 12C of the first embodiment described above are configured to have approximately the same planar size. As shown in Figure 38B, when the semiconductor wafer 90 and the wafer stack 60 are stacked in their respective thickness directions (Z direction), the support plate forming region 95 of the semiconductor wafer 90 is positioned so as to overlap the chip forming region 65 of the wafer stack 60 in a planar view. Furthermore, when the wafer stack 60 and the semiconductor wafer 90 are stacked, the recess 82 of the support plate forming region 95 is also positioned so as to overlap the chip mounting region Cm (see Figure 9) of the chip forming region 95 in a planar view. Here, the bonding surface 20a of the wafer stack 60 becomes the bonding surface 20a of the first semiconductor chip 20.

[0216] First, a semiconductor wafer 90 shown in Figures 37A to 37C and a wafer stack 60 shown in Figures 12A to 13B are prepared. A recess 82 has already been formed in a support plate formation region 95 of the semiconductor wafer 90. Then, the chip formation region 65 of the wafer stack 60 has already been provided with the configuration of the first semiconductor chip 20 shown in Figures 34 and 35.

[0217] 38A , the second semiconductor chip 40 is mounted in the chip formation region 65 (chip mounting region Cm) of the wafer stack 60. The second semiconductor chip 40 is mounted by directly bonding the bonding surface 40 a of the second semiconductor chip 40 to the bonding surface 20 a of the wafer stack 60 using a method similar to that of the first embodiment described above.

[0218] Next, as shown in FIG. 39B, the bonding surface 20a of the wafer stack 60 and the bonding surface 81a of the semiconductor wafer 90 are bonded by direct bonding.

[0219] Specifically, first, a surface improvement process is performed to activate each of the bonding surface 20a of the wafer stack 60 and the bonding surface 81a of the semiconductor wafer 90. The surface improvement process for the bonding surface 20a of the wafer stack 60 involves, for example, irradiating the bonding surface 20a of the wafer stack 60 with plasma to remove oxides and adsorbates and create dangling atomic bonds. In the surface improvement process for activating the bonding surface 81a of the semiconductor wafer 90, similar dangling atomic bonds are created by plasma irradiation.

[0220] Next, the semiconductor wafer 90 is stacked on the wafer stack 60 in a state in which the bonding surface portion 20a of the wafer stack 60, which has been subjected to the surface improvement treatment, and the bonding surface portion 81a of the semiconductor wafer 90, which has also been subjected to the surface improvement treatment, face each other, and the second semiconductor chip 40 mounted on the bonding surface portion 20a of the wafer stack 60 is positioned inside the recess 82 of the semiconductor wafer 90.

[0221] Next, the bonding surface 81a of the semiconductor wafer 90 is pressed (press-welded) to the bonding surface 20a of the wafer stack 60 so that a bonding wave is generated from the center to the periphery of the semiconductor wafer 90 in a two-dimensional plane.

[0222] In this process, the unbonded portions of the bonding surface 20 a of the wafer stack 60 and the unbonded portions of the bonding surface 81 a of the semiconductor wafer 90 are bonded, and the bonding surface 20 a of the wafer stack 60 and the bonding surface 81 a of the semiconductor wafer 90 are bonded by surface activated bonding. More specifically, the insulating layer 26 included in the bonding surface 20 a of the wafer stack 60 and the semiconductor included in the bonding surface 81 a of the semiconductor wafer 90 are bonded by surface activated bonding. In this third embodiment, the insulating layer 26 of the wafer stack 60 is made of a silicon oxide film, and the semiconductor wafer 90 is made of an intrinsic Si semiconductor substrate made of single-crystal silicon (Si), so bonding is achieved by direct bonding between the oxide film on the bonding surface 21 a side of the wafer stack 60 and the silicon on the bonding surface 81 a side of the support plate 81.

[0223] In this process, the recess 82 is configured so that its planar size in a plan view and its depth in a cross-sectional view are slightly larger than the planar size and thickness of the second semiconductor chip 40, and therefore, voids 83 are formed between each of the side surface portions 40c and top surface portion 40b of the second semi-semiconductor chip 40 and the recess 82 of the semiconductor wafer 90. Although not shown in detail, the voids 83 are formed so as to continuously surround the four side surface portions 40c of the second semiconductor chip 40.

[0224] 34 are formed, the wafer stack 60 and the semiconductor wafer 90 are then diced along their respective scribe lines 66, 96 to separate the chip formation region 65 of the wafer stack 60 and the support plate formation region 95 of the semiconductor wafer 90 into small pieces. This process forms the first semiconductor chip 20 and the support plate 81. Then, with the second semiconductor chip 40 positioned inside the recess 82, the three-dimensional photodetector 1C is nearly completed, in which the bonding surface 81a of the support plate 81 is bonded to the bonding surface 20a of the first semiconductor chip 20.

[0225] <<Main Effects of the Third Embodiment>> Next, the main effects of the third embodiment will be described. The photodetector 1C according to the third embodiment includes a recess 82 for accommodating the second semiconductor chip 40 mounted on the bonding surface 20a of the first semiconductor chip 20, a support plate 81 bonded to the bonding surface 20a of the first semiconductor chip 20 with the second semiconductor chip 40 positioned inside the recess 82, and a void 83 provided between the support plate 81 and the second semiconductor chip 40. The void 83 suppresses interference between the internal stress (contraction stress) of the second semiconductor chip 40 and the internal stress (expansion stress) of the support plate 81. Therefore, referring to FIG. 22 used in the first embodiment, similar to the first embodiment, the stress strain S1 generated in the chip formation region 65 (first semiconductor chip 20) of the wafer stack 60 can be alleviated due to the difference between the internal stress (contraction stress Sc) of the second semiconductor chip 40 and the internal stress (expansion stress St) of the support plate 81. This makes it possible to suppress variations (unevenness) in the photoelectric conversion characteristics of the photoelectric conversion unit 35 caused by the stress strain S1, thereby improving the manufacturing yield of the photodetector 1C. Also, it is possible to suppress color mixing between adjacent pixels 3.

[0226] Furthermore, the photodetector 1C according to the third embodiment uses an intrinsic Si semiconductor substrate as the support plate 81, thereby improving heat dissipation compared to the case where the insulator 51 according to the first embodiment is used. Furthermore, the photodetector 1C according to the third embodiment uses the support plate 81, which increases the mechanical strength of the photodetector 1C, to fill in any steps on the bonding surface 20a side of the first semiconductor chip 20 caused by the thickness of the second semiconductor chip 40, and flatten the bonding surface 20a side of the first semiconductor chip 20. Therefore, compared to the case of the above-described modified example 1-2, the insulator 51 can be omitted, thereby improving productivity.

[0227] In the third embodiment, an intrinsic Si semiconductor substrate is used as the support plate 81, but the support plate 81 is not limited to an intrinsic semiconductor substrate. For example, an impurity-doped Si semiconductor substrate may also be used as the support plate 81. In this case, however, it is preferable to cover the inner wall surface of the recess 82 with an insulating film in order to maintain insulation between the support plate 81 and the second semiconductor chip 40.

[0228] 39A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photodetector according to a fourth embodiment of the present disclosure, and FIG. 39B is a longitudinal cross-sectional view schematically showing a bonding state between a first semiconductor chip, a second semiconductor chip, and a support plate shown in FIG.

[0229] As shown in Figures 39A and 39B, the photodetector 1D according to the fourth embodiment of the present technology has a configuration basically similar to that of the photodetector 1C according to the third embodiment described above, but differs in the following respects. That is, as shown in Figures 39A and 39B, the photodetector 1D according to the fourth embodiment of the present technology has a junction insulating film 84 provided on the bonding surface 81a side of the support plate 81. The junction insulating film 84 may be, for example, an oxide film such as a silicon oxide (SiO) film, a silicon oxynitride (SiON) film, or a silicon oxycarbide (SiOC) film. Therefore, the bonding surface 81a of the support plate 81 according to the fourth embodiment includes an oxide film. Furthermore, in the fourth embodiment, the bonding surface 20a of the first semiconductor chip 20 and the bonding surface 81a of the support plate 81 are directly bonded to each other by the oxide film on the bonding surface 20a side of the first semiconductor chip 20 and the oxide film on the bonding surface 81a side of the support plate 81.

[0230] The present technology can also be applied to the photodetector 1D according to the fourth embodiment, and the same effects as those of the photodetector 1C according to the third embodiment described above can be obtained.

[0231] The bonding insulating film 84 may be, for example, a nitride film such as a silicon nitride (SiN) film, a silicon oxynitride (SiON) film, or a silicon carbonitride (SiOC) film. In this case, the bonding surface 81a of the support plate 81 includes a nitride film. In this case, the bonding surface 20a of the first semiconductor chip 20 and the bonding surface 81a of the support plate 81 are bonded by direct bonding between the oxide film on the bonding surface 20a side of the first semiconductor chip 20 and the nitride film on the bonding surface 81a side of the support plate 81.

[0232] The junction insulating film 84 may also be provided on the bonding surface 20a side of the first semiconductor chip 20. In this case, the bonding surface 20a of the first semiconductor chip 20 includes the junction insulating film 84. Also in this case, the bonding surface 20a of the first semiconductor chip 20 and the bonding surface 81a of the support plate 81 can be bonded by direct bonding between an oxide film and silicon, direct bonding between an oxide film and an oxide film, or direct bonding between an oxide film and a nitride film.

[0233] Fifth Embodiment FIG. 40 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photodetector according to a fifth embodiment of the present technology.

[0234] 40 , a photodetector 1E according to a fifth embodiment of the present technology has a configuration basically similar to that of the photodetector 1C according to the above-described third embodiment, but differs in the configuration of the support plate. That is, as shown in FIG. 40 , a support plate 81 according to the fifth embodiment has a wiring layer 85 on the bonding surface portion 81 a side.

[0235] The present technology can also be applied to the photodetector 1E according to the fifth embodiment, and the same effects as those of the photodetector 1C according to the third embodiment described above can be obtained.

[0236] Furthermore, in this fifth embodiment, a wiring layer 85 is provided on the bonding surface portion 81a side of the support plate 81, so that the stress strain S1 generated in the chip formation region 65 (first semiconductor chip 20) of the wafer stack 60 due to the difference between the internal stress (contraction stress Sc) of the second semiconductor chip 40 and the internal stress (expansion stress St) of the support plate 81 can be more mitigated compared to the third embodiment.

[0237] Sixth Embodiment FIG. 41 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photodetector according to a sixth embodiment of the present technology.

[0238] 41 , a photodetector 1F according to the sixth embodiment of the present technology has a configuration basically similar to that of the photodetector 1C according to the above-described third embodiment, but differs in the following configuration. That is, as shown in Fig. 41 , the photodetector 1F according to the sixth embodiment of the present technology houses a plurality of second semiconductor chips 40 inside one recess 82 of a support plate 81. In this sixth embodiment, two second semiconductor chips 40 are arranged inside one recess 82.

[0239] The present technology can also be applied to the photodetector 1F according to the sixth embodiment, and the same effects as those of the photodetector 1C according to the third embodiment described above can be obtained.

[0240] 42A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photodetector according to a seventh embodiment of the present disclosure, and FIG. 42B is a longitudinal cross-sectional view schematically showing a bonding state between a first semiconductor chip, a second semiconductor chip, and a support plate shown in FIG.

[0241] 42A and 42B , a photodetector 1G according to the seventh embodiment of the present technology has a configuration basically similar to that of the photodetector 1C according to the third embodiment described above, but differs in the following configuration. That is, as shown in Fig. 42A and 42B , in the photodetector 1G according to the seventh embodiment of the present technology, the top surface 40b of the second semiconductor chip 40 is in slidable contact with the bottom surface 82b of the recess 82 of the support plate 81. The gap 83 in this seventh embodiment is provided between the side surface 40c of the second semiconductor chip 40 and the support plate 81.

[0242] The present technology can also be applied to the photodetector 1G according to the seventh embodiment, and the same effects as those of the photodetector 1C according to the third embodiment described above can be obtained.

[0243] Furthermore, in the photodetector 1G according to the seventh embodiment, the top surface 40b of the second semiconductor chip 40 is in slidable contact with the bottom surface 82b of the recess 82 of the support plate 81. This makes it easier to transfer heat generated in the second semiconductor chip 40 to the support plate 81 compared to the photodetector 1C according to the third embodiment described above, thereby improving heat dissipation.

[0244] A gel-like thermally conductive material with good thermal conductivity may be interposed between the top surface 40 b of the second semiconductor chip 40 and the bottom surface 82 b of the recess 82 of the support plate 81 .

[0245] 43A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photodetector according to an eighth embodiment of the present disclosure. Fig. 43B is a longitudinal cross-sectional view schematically showing a bonding state between a first semiconductor chip, a second semiconductor chip, and a support plate shown in Fig. 43A.

[0246] 43A and 43B , a photodetector 1H according to an eighth embodiment of the present technology has a configuration basically similar to that of the photodetector 1C according to the above-described third embodiment, with the following difference: That is, as shown in Fig. 43A and 43B , the photodetector 1H according to the eighth embodiment of the present technology has a metallization layer 86 provided on the top surface portion 40b of the second semiconductor chip 40. The metallization layer 86 is in slidable contact with the bottom surface portion 82b of the recess 82 of the support plate 81.

[0247] The present technology can also be applied to the photodetector 1H according to the eighth embodiment, and the same effects as those of the photodetector 1C according to the third embodiment described above can be obtained.

[0248] Furthermore, in the photodetector 1H according to the eighth embodiment, the metallized layer 85 provided on the upper surface 40b of the second semiconductor chip 40 is in slidable contact with the bottom surface 82b of the recess 82 of the support plate 81. This makes it easier to transfer heat generated in the second semiconductor chip 40 to the support plate 81 compared to the photodetector 1C according to the third embodiment described above, thereby improving heat dissipation.

[0249] In addition, in the photodetector device 1H according to the eighth embodiment, a gel-like thermally conductive material with good thermal conductivity may be interposed between the metallized layer 86 on the upper surface 40b of the second semiconductor chip 40 and the bottom surface 82b of the recess 82 of the support plate 81.

[0250] <<Variation of Eighth Embodiment>> FIG. 44 is a diagram showing a variation 8-1 according to the eighth embodiment of the present technology, and is a vertical cross-sectional view schematically showing the bonding state between the first semiconductor chip, the second semiconductor chip, and the support plate.

[0251] In the above-described eighth embodiment, the metallized layer 86 is provided on the top surface 40b side of the second semiconductor chip 40. In contrast, as shown in Fig. 44, in this modification 8-1, the metallized layer 86 is provided on the bottom surface 82b of the recess 82 of the support plate 81. The metallized layer 86 is in slidable contact with the top surface 40b of the second semiconductor chip 40.

[0252] The present technology can also be applied to this modification 8-1, and the same effects as those of the photodetector 1C according to the third embodiment described above can be obtained.

[0253] Ninth Embodiment FIG. 45 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photodetector according to a ninth embodiment of the present technology.

[0254] As shown in FIG. 45 , the photodetector 1I according to the ninth embodiment of the present technology has a configuration basically similar to that of the photodetector 1C according to the third embodiment described above, but differs in the following configuration. That is, as shown in FIG. 45 , the photodetector 1I according to the ninth embodiment of the present technology includes, as the second semiconductor chip 40, second semiconductor chips 40L and 40M having different thicknesses. The support plate 81 has, as the recess 82, a recess 82L for accommodating the second semiconductor chip 40L and a recess 82M for accommodating the second semiconductor chip 40M. The recess 82L has a planar size in a plan view and a depth in a cross-sectional view that are slightly larger than the planar size and thickness of the second semiconductor chip 40L. The recess 82M has a planar size in a plan view and a depth in a cross-sectional view that are slightly larger than the planar size and thickness of the second semiconductor chip 40M. In this ninth embodiment, the second semiconductor chip 40M is thicker than the second semiconductor chip 40L, so the recess 82M that houses the second semiconductor chip 40M has a greater depth dimension than the recess 82L that houses the second semiconductor chip 40L.

[0255] The photodetector 1I according to the ninth embodiment also provides the same effects as the photodetector 1C according to the third embodiment. Furthermore, by changing the depth of the recess 82, second semiconductor chips 40 of different thicknesses can be easily accommodated. Furthermore, by changing the planar size of the recess 82, second semiconductor chips 40 of different planar sizes can be accommodated.

[0256] 46A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photodetector according to a tenth embodiment of the present disclosure. Fig. 46B is a longitudinal cross-sectional view schematically showing a bonding state between a first semiconductor chip, a second semiconductor chip, and a support plate shown in Fig. 46A.

[0257] 46A and 46B , the photodetector 1J according to the tenth embodiment of the present technology has a configuration basically similar to that of the photodetector 1C according to the third embodiment described above, but differs in the following configuration. That is, as shown in Fig. 46A and 46B , the photodetector 1J according to the tenth embodiment of the present technology further includes an insulating film 87 that covers the second semiconductor chip 40 and is included in the bonding surface portion 20a of the first semiconductor chip 20. The insulating film 87 can be an oxide film or a nitride film.

[0258] When the insulating film 87 is an oxide film, the bonding surface 20a of the first semiconductor chip 20 and the bonding surface 81a of the support plate 81 are bonded by direct bonding between the oxide film on the bonding surface 20a side of the first semiconductor chip 20 and the silicon on the bonding surface 81a side of the support plate 81. On the other hand, when the insulating film 87 is a nitride film, the bonding surface 20a of the first semiconductor chip 20 and the bonding surface 81a of the support plate 81 are bonded by direct bonding between the nitride film on the bonding surface 20a side of the first semiconductor chip 20 and the silicon on the bonding surface 81a side of the support plate 81.

[0259] The photodetector 1J according to the tenth embodiment also provides the same effects as the photodetector 1C according to the third embodiment.

[0260] Eleventh Embodiment Example of Application to Electronic Devices The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0261] FIG. 47 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to an eleventh embodiment of the present technology.

[0262] 47 , the electronic device 100 includes a photodetector 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 illustrates an embodiment in which the photodetectors 1A to 1J according to the first to tenth embodiments of the present technology and the photodetectors according to the modified examples of the respective embodiments are used in an electronic device (for example, a camera) as the photodetector 101.

[0263] The optical lens 102 focuses image light (incident light 106) from the subject onto the imaging surface of the photodetector 101. This causes signal charge to accumulate in the photodetector 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period of the photodetector 101. The drive circuit 104 supplies a drive signal that controls the transfer operation of the photodetector 101 and the shutter operation of the shutter device 103. The drive signal (timing signal) supplied from the drive circuit 104 causes charge transfer in the photodetector 101. The signal processing circuit 105 performs various signal processing on the signal (pixel signal (image signal)) output from the photodetector 101. The processed video signal is stored in a storage medium such as a memory or output to a monitor.

[0264] With this configuration, color mixing between adjacent pixels 3 in the photodetector 101 can be suppressed, and the image quality performance of the electronic device 100 of the third embodiment can be improved.

[0265] The electronic device 100 to which the photodetector of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the photodetector may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0266] Furthermore, the present technology can be applied to photodetectors in general, including distance measurement sensors called Time of Flight (ToF) sensors that measure distance, as well as photodetectors as described above. A distance measurement sensor emits light toward an object, detects the light reflected by the surface of the object, and calculates the distance to the object based on the time of flight between when the light is emitted and when the reflected light is received. The pixel transistors described above can also be used in such distance measurement sensors.

[0267] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0268] The present technology may be configured as follows: (1) A semiconductor device comprising: a base member having one surface; a semiconductor chip having a top surface and a side surface and mounted on the one surface side of the base member; an insulator provided on the one surface side of the base member to cover the semiconductor chip; and a buffer portion provided between the insulator and each of the top surface and the side surface of the semiconductor chip. (2) The semiconductor device according to (1) above, in which the buffer portion relieves stress distortion caused in the base member due to a difference in internal stress between the insulator and the semiconductor chip. (3) The semiconductor device according to (1) or (2) above, in which the buffer portion is a void portion. (4) The semiconductor device according to (1) or (2) above, in which the buffer portion is a buffer film having a thermal expansion coefficient smaller than that of the second semiconductor chip and larger than that of the insulator (thermal expansion coefficient of second semiconductor chip > thermal expansion coefficient of buffer film > thermal expansion coefficient of insulator). (5) The semiconductor device according to any one of (1) to (4) above, wherein the insulator includes a support pillar that crosses the buffer section in the thickness direction of the semiconductor chip and contacts the top surface of the semiconductor chip. (6) The semiconductor device according to (5) above, wherein the support pillar has a circular, rectangular, or striped planar shape. (7) The semiconductor device according to (5) or (6) above, wherein the support pillar is a first support pillar, and the insulator includes a second support pillar that crosses the buffer section in the thickness direction of the semiconductor chip on the outside of the semiconductor chip and contacts the base member. (8) The semiconductor device according to any one of (1) to (7) above, wherein the insulator includes a connecting buffer section that is connected to the buffer section. (9) The semiconductor device according to (8) above, wherein the connecting buffer section is a void section or a buffer film. (10) The semiconductor device according to any one of (1) to (9) above, wherein the insulator includes a separating buffer section that is provided at a distance from the buffer section. (11) The semiconductor device according to (10), wherein the separation buffer portion is a gap portion or a buffer film. (12) The semiconductor device according to any one of (1) to (11), wherein the base member includes a semiconductor layer provided with a photoelectric conversion portion.(13) The semiconductor device according to any one of (1) to (12) above, wherein the base member is a first semiconductor chip, and the semiconductor chip is a second semiconductor chip. (14) The semiconductor device according to any one of (1) to (12) above, wherein the base member is a wafer stack. (15) A semiconductor device comprising: a base member having one surface; a semiconductor chip mounted on the one surface of the base member; a support plate having a recess for accommodating the semiconductor chip and joined to the one surface of the base member with the semiconductor chip positioned in the recess; and a gap provided between the support plate and the semiconductor chip. (16) The semiconductor device according to (15) above, wherein the support plate is an intrinsic semiconductor substrate. (17) The semiconductor device according to (15) or (16) above, wherein the semiconductor chip includes a side portion, a bonding surface portion bonded to the one surface portion of the base member, and an upper surface portion located opposite the bonding surface portion, and the gap portion is provided at least between the side portion of the semiconductor chip and the recess of the support plate. (18) The semiconductor device according to any of (15) to (17) above, wherein the semiconductor chip includes a bonding surface portion bonded to the one surface portion of the base member and an upper surface portion located opposite the bonding surface portion, and the upper surface portion of the semiconductor chip is in contact with the chip bonding surface portion of the support plate inside the recess. (19) The semiconductor device according to (18) above, wherein at least one of the chip bonding surface portion of the support plate and the upper surface portion of the semiconductor chip includes a metallized layer. (20) The semiconductor device according to any one of (15) to (19) above, wherein the support plate is bonded to the one surface portion of the base member by direct bonding. (21) The semiconductor device according to any one of (15) to (19) above, wherein the base member and the support plate are bonded by direct bonding between an oxide film and silicon, or between an oxide film and an oxide film, or between an oxide film and a nitride film. (22) The semiconductor device according to any one of (15) to (21) above, wherein the support substrate has a wiring layer 85 on the bonding surface side bonded to the one surface portion of the base substrate.(23) The semiconductor device according to any one of (15) to (22) above, wherein a plurality of the semiconductor chips are arranged in the recess of the support substrate. (24) The semiconductor device according to any one of (15) to (23) above, wherein the support substrate has two recesses, and wherein the semiconductor chips having different thicknesses are individually arranged in each of the two recesses. (25) The semiconductor device according to any one of (15) to (24) above, further comprising an oxide film or a nitride film covering the semiconductor chip and included on the one surface portion of the base member. (26) The semiconductor device according to any one of (15) to (24) above, wherein the base member is a first semiconductor chip, and the semiconductor chip is a second semiconductor chip. (27) An electronic device comprising: the semiconductor device according to any one of (1) to (25) above; an optical lens that focuses image light from a subject on an imaging surface of the semiconductor device; and a signal processing circuit that performs signal processing on a signal output from the semiconductor device.

[0269] 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J Photodetector 2A Pixel array section 2B Peripheral section 3 Pixel 4 Vertical drive circuit 5 Column signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control circuit 10 Pixel drive line 11 Vertical signal line 13 Logic circuit 14 Bonding pad 15 Photoelectric conversion section 16 Pixel circuit (readout circuit) 20 First semiconductor chip (base member) 20a Bonding surface section (one surface section) 21 First substrate section 22 Semiconductor layer 23 Multilayer wiring layer 24 Bonding metal pad 25 Multilayer wiring layer 26 Insulating layer (first insulating layer) 27 Bonding metal pad (first bonding metal pad) 28 Contact electrode 31 Second substrate section 32 Semiconductor layer 33 Multilayer wiring layer 34 Bonding metal pad 35 Photoelectric conversion region 36 Color filter layer 37 Microlens 38 Bonding opening 40, 40L, 40M Second semiconductor chip 40a Bonding surface 40a １ , 40a ２ , 40a ３ , 40a ４ Side 40b １, 40b ２ , 40b ３ , 40b ４ Corner portion 42 Semiconductor layer 45 Multilayer wiring layer 46 Insulating layer (second insulating layer) 47 Bonding metal pad 48 Protective film 51 Insulator 51a Main body portion 51b Support portion (first support portion) 51b １ Support portion (second support portion) 51bx First support portion 51by Second support portion 52 Opening 53 Cap film 55 Void portion (buffer portion) 55a Sacrificial film 56a Connecting void portion (connecting buffer portion) 56b Separating void portion (separating buffer portion) 57 Void portion (buffer portion) 57x １ 1st connection gap part 57x ２ First separation gap portion 57y １ 2nd connection gap part 57y ２ Second separating gap portion 59 Buffer film (buffer portion) 60 Wafer stack (base member) 61, 62 Semiconductor wafer 65 Chip forming area 66 Scribe line 70 Semiconductor wafer 75 Chip forming area 76 Scribe line 80 Support plate 81 Support plate 81a Bonding surface portion 81b Upper surface portion 82, 82L, 82M Recessed portion 82b Bottom surface portion 83 Gap portion 84 Bonding insulating film 85 Wiring layer 86 Metallized layer 87 Insulating film 100 Electronic device 101 Photodetector 102 Optical lens 103 Shutter device 104 Drive circuit 105 Signal processing circuit 106 Incident light AMP Amplifying transistor FD Charge holding region FDG Switching transistor PD Photodiode RST Reset transistor SEL Select transistor TR Transfer transistor

Claims

1. A semiconductor device comprising: a base member having one surface; a semiconductor chip having a top surface and a side surface and mounted on the one surface side of the base member; an insulator provided on the one surface side of the base member to cover the semiconductor chip; and a buffer portion provided between the insulator and each of the top surface and side surface of the semiconductor chip.

2. The semiconductor device according to claim 1, wherein said buffer portion relieves stress distortion caused in said base member due to a difference in internal stress between said insulator and said semiconductor chip.

3. The semiconductor device according to claim 1, wherein the buffer portion is a void portion.

4. The semiconductor device according to claim 1, wherein the buffer portion is a buffer film having a thermal expansion coefficient smaller than that of the second semiconductor chip 40 and larger than that of the insulator.

5. The semiconductor device according to claim 1, wherein said insulator includes a support pillar portion that crosses said buffer portion in the thickness direction of said semiconductor chip and is in partial contact with the top surface portion of said semiconductor chip.

6. The semiconductor device according to claim 5, wherein the first support pillar has a planar shape of a circle, a square, or a stripe.

7. The semiconductor device according to claim 5, wherein the support portion is a first support portion, and the insulator includes a second support portion that crosses the buffer portion in the thickness direction of the semiconductor chip on the outside of the semiconductor chip and contacts the base member.

8. The semiconductor device of claim 1, wherein the insulator includes a connecting buffer portion connected to the buffer portion.

9. The semiconductor device according to claim 8, wherein the connecting buffer portion is a gap portion or a buffer film.

10. The semiconductor device of claim 1, wherein the insulator includes a spaced apart buffer portion spaced apart from the buffer portion.

11. The semiconductor device according to claim 9, wherein the spacing buffer is a gap or a buffer film.

12. The semiconductor device according to claim 1, wherein the base member includes a semiconductor layer provided with a photoelectric conversion portion.

13. The semiconductor device according to claim 1, wherein the base member is a first semiconductor chip, and the semiconductor chip is a second semiconductor chip.

14. The semiconductor device of claim 1, wherein the base member is a wafer stack.

15. A semiconductor device comprising: a base member having one surface; a semiconductor chip mounted on the one surface of the base member; a support plate having a recess for accommodating the semiconductor chip and joined to the one surface of the base member with the semiconductor chip positioned in the recess; and a gap provided between the support plate and the semiconductor chip.

16. The semiconductor device of claim 15, wherein the support plate is an intrinsic semiconductor substrate.

17. The semiconductor device according to claim 15, wherein the semiconductor chip includes a side portion, a bonding surface portion bonded to the one surface portion of the base member, and an upper surface portion located opposite the bonding surface portion, and the gap portion is provided at least between the side portion of the semiconductor chip and the recessed portion of the support plate.

18. The semiconductor device according to claim 15, wherein the semiconductor chip includes a bonding surface portion bonded to the one surface portion of the base member and an upper surface portion located opposite the bonding surface portion, and the upper surface portion of the semiconductor chip is in contact with the chip bonding surface portion of the support plate inside the recess.

19. The semiconductor device according to claim 18, wherein at least one of the chip bonding surface of the support plate and the top surface of the semiconductor chip includes a metallization layer.

20. The semiconductor device according to claim 15, wherein the support plate is joined to the one surface of the base member by direct bonding.

21. The semiconductor device according to claim 15, wherein the base member and the support plate are bonded together by direct bonding between an oxide film and silicon, or direct bonding between an oxide film and an oxide film, or direct bonding between an oxide film and a nitride film.

22. The semiconductor device according to claim 15, wherein the support substrate has a wiring layer on the bonding surface side bonded to the one surface of the base substrate.

23. The semiconductor device according to claim 15, wherein a plurality of the semiconductor chips are disposed in the recess of the support substrate.

24. The semiconductor device according to claim 15, wherein the support substrate has two recesses, and the semiconductor chips having different thicknesses are individually disposed in each of the two recesses.

25. The semiconductor device of claim 15, further comprising an oxide or nitride film covering the semiconductor chip and included on the one surface of the base member.

26. The semiconductor device of claim 15, wherein the base member is a first semiconductor chip, and the semiconductor chip is a second semiconductor chip.

27. An electronic device comprising: a semiconductor device; an optical lens that focuses image light from a subject on an imaging surface of the semiconductor device; and a signal processing circuit that performs signal processing on a signal output from the semiconductor device, wherein the semiconductor device comprises: a base member having a first surface portion and a second surface portion located opposite each other; a semiconductor chip mounted on the first surface portion of the base member; an insulator provided on the first surface portion of the base member to cover the semiconductor chip; and a buffer portion provided between the insulator and the top surface portion and side surface portion of the semiconductor chip.

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