Semiconductor device and method for driving gate of semiconductor device

Abstract

The present invention provides a highly reliable semiconductor device that incorporates a plurality of built-in semiconductor elements connected in series-parallel, and can continue to operate even if any of a gate–source (emitter) connection, a drain (collector)–source (emitter) connection, or a drain (collector)–gate connection of a semiconductor element is short-circuited. The present invention is characterized by having a plurality of semiconductor elements in a multistage connection whereby the drain of a semiconductor element in a preceding stage is connected in series with the source of a semiconductor element in a subsequent stage. The present invention comprises a plurality of power switch sections in which a drive signal is inputted into the gate of a semiconductor element in a first stage, a first gate drive circuit that inputs the drive signal into the gate of the semiconductor element in the first stage to drive the semiconductor element in the first stage, and a plurality of gate-series drive circuits that control the gate of a semiconductor element in a subsequent stage according to a signal outputted by a semiconductor element in a preceding stage. The plurality of power switch sections include a first power switch section and second power switch section connected to each other in parallel. The source of the semiconductor element in the first stage of the first power switch section is connected to the source of the semiconductor element in the first stage of the second power switch section. The drain of a semiconductor element in a final stage of the first power switch section is connected to the drain of a semiconductor element in a final stage of the second power switch section. The gate of the semiconductor element in the first stage of the first power switch section and the gate of the semiconductor element in the first stage of the second power switch section are electrically isolated, or are electrically isolated under a certain condition.

Description

Semiconductor device and gate driving method for semiconductor device

[0001] The present invention relates to a semiconductor device configuration and a driving method thereof, and more particularly to a technique that is effective when applied to a power semiconductor module incorporating a plurality of semiconductor elements connected in series and parallel.

[0002] Power conversion devices used to control electric motors for railways and large industrial equipment, and power conversion devices used for large-capacity frequency conversion in power systems, etc., use large-capacity power semiconductor elements to control high-voltage, large-current power. Many of these power conversion devices are configured using power semiconductor modules that incorporate multiple power semiconductor elements connected in parallel.

[0003] In such equipment, if, for example, one of the gates of a power semiconductor element connected in parallel fails during operation, causing a short circuit between the gate and source (or between the gate and emitter in the case of an IGBT), the power semiconductor element cannot be controlled by applying a voltage to the gate. For example, an enhancement-type MOSFET cannot be turned on. In this case, since the gates of the power semiconductor elements connected in parallel are electrically connected to each other, a failure of one gate causes a gate-source short circuit in all of the gates connected in parallel, preventing the power conversion device from continuing to operate.

[0004] Furthermore, if a short circuit occurs between the drain and source (or between the collector and emitter in the case of IGBTs) of some of the parallel-connected power semiconductor elements, an excessive short-circuit current will flow through the power semiconductor module, potentially damaging the system or causing an unplanned system shutdown, resulting in significant economic losses.When the protection function installed to deal with this type of failure mode detects a short-circuit current, the power conversion device will shut down, reducing the risk of abnormal heat generation or damage to the equipment connected to the power conversion device.

[0005] However, as long as the short-circuited power semiconductor element remains in the power semiconductor module, the power conversion device cannot be restarted.

[0006] Background art in this technical field includes, for example, technology such as that disclosed in Patent Document 1. Patent Document 1 discloses technology that aims to enable the continued operation of a power conversion device even when a short circuit fault occurs between the gate and source of a part of a semiconductor element.

[0007] Furthermore, Patent Document 2 discloses a technique that aims to enable the power conversion device to continue operating even when a short circuit fault occurs between the drain and source of a part of a semiconductor element.

[0008] Furthermore, Patent Document 3 discloses a technology in which series-connected semiconductor elements are operated as a single semiconductor element, and even if a short circuit occurs between the drain and source of one of the series-connected semiconductor elements, operation can be continued by using the voltage cut-off function of the other series-connected semiconductor elements.

[0009] JP 2015-225990 A JP 2018-148164 A JP 2023-166747 A

[0010] Incidentally, the breakdown modes of a power semiconductor module can be broadly classified into short circuits between the three terminals of the gate, source, and drain, i.e., short circuits between the gate and source (emitter), between the drain (collector) and source (emitter), and between the drain (collector) and gate.

[0011] To improve the reliability of power conversion equipment for social infrastructure such as railways, large industrial equipment, and power grids, redundancy that can handle all of these failure modes is required.

[0012] The technology of Patent Document 1 can deal with short circuits between the gate and source (emitter), and the technologies of Patent Documents 2 and 3 can deal with short circuits between the drain (collector) and source (emitter), but no technology is known that can deal with short circuits between the drain (collector) and gate.

[0013] When a short circuit occurs between the drain (collector) and gate, the high voltage of the drain (collector) is applied directly to the gate, resulting in gate overvoltage, which induces a gate-source (emitter) failure.

[0014] Furthermore, since a high voltage is applied to the gate drive circuit via the gate, it can cause a breakdown in the gate drive circuit. Secondary breakdown due to high voltage occurs in a short period of time, making it difficult to prevent secondary breakdown using a fuse.

[0015] Therefore, an object of the present invention is to provide a highly reliable semiconductor device that incorporates a plurality of semiconductor elements connected in series and parallel, and that can continue to operate even if a short circuit occurs between the gate and source (emitter), between the drain (collector) and source (emitter), or between the drain (collector) and gate of the semiconductor elements, and a gate driving method for the same.

[0016] In order to solve the above problems, the present invention provides a power supply circuit having a plurality of semiconductor elements connected in multiple stages, with the drain of a semiconductor element in a preceding stage and the source of a semiconductor element in a succeeding stage connected in series, the power supply circuit comprising: a plurality of power switch sections to which a drive signal is inputted to the gate of a first stage semiconductor element; a first gate drive circuit that inputs a drive signal to the gate of the first stage semiconductor element to drive the first stage semiconductor element; and a plurality of gate series drive circuits that control the gate of a succeeding stage semiconductor element by a signal outputted from the semiconductor element in the preceding stage, the plurality of power switch sections being connected in parallel with each other; the source of the first-stage semiconductor element of the first power switch section is connected to the source of the first-stage semiconductor element of the second power switch section, the drain of the final-stage semiconductor element of the first power switch section is connected to the drain of the final-stage semiconductor element of the second power switch section, and the gate of the first-stage semiconductor element of the first power switch section is electrically insulated from the gate of the first-stage semiconductor element of the second power switch section, or is electrically insulated under predetermined conditions.

[0017] The present invention also provides a gate driving method for a semiconductor device that drives a semiconductor device having the above-described characteristics, characterized in that the gates of the first-stage semiconductor elements are independently controlled for the plurality of power switch sections by the respective first gate driving circuits.

[0018] According to the present invention, in a semiconductor device incorporating a plurality of semiconductor elements connected in series and parallel, it is possible to realize a highly reliable semiconductor device and a gate driving method thereof that can continue to operate even if a short circuit occurs between the gate and source (emitter), between the drain (collector) and source (emitter), or between the drain (collector) and gate of the semiconductor elements.

[0019] This will contribute to improving the reliability of power conversion equipment for social infrastructure such as railways, large industrial equipment, and power systems.

[0020] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments.

[0021] FIG. 6 is a circuit diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 7 is a circuit diagram showing a modified example of the semiconductor device of FIG. 1. FIG. 8 is a circuit diagram showing a modified example of the semiconductor device of FIG. 1. FIG. 9 is a circuit diagram showing a schematic configuration of a semiconductor device according to a second embodiment of the present invention. FIG. 10 is a diagram showing an example of a gate current waveform flowing through a gate switch during normal operation of the semiconductor device of FIG. 4. FIG. 11 is a diagram showing an example of a gate current waveform flowing through a gate switch when a gate-source or drain-gate short-circuit fault occurs in the semiconductor device of FIG. 4. FIG. 12 is a circuit diagram showing a schematic configuration of a semiconductor device according to a third embodiment of the present invention. FIG. 13 is a circuit diagram showing a modified example of the semiconductor device of FIG.

[0022] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted.

[0023] In the following description, the term "gate-source voltage" refers to the gate voltage with the source potential as the reference.

[0024] A semiconductor device and a gate driving method thereof according to a first embodiment of the present invention will be described with reference to FIGS.

[0025] Fig. 1 is a circuit diagram showing a schematic configuration of a semiconductor device according to this embodiment, while Figs. 2 and 3 are circuit diagrams showing modifications of the semiconductor device shown in Fig. 1.

[0026] The semiconductor device of this embodiment shown in FIG. 1 constitutes, for example, one arm of a three-phase inverter that drives a motor, and a source terminal 1 and a drain terminal 2 are connected to the positive power supply, negative power supply, or load (motor) of the inverter.

[0027] In order to control the speed or torque of the motor using the three-phase inverter, a PWM signal is output from the gate control unit 3, and the signal is amplified by gate drive circuits 4 and 5 connected in parallel to each other, and drives the gates of first-stage N-type MOSFETs 7 and 11 of power switch units 6 and 10, which are made up of series-connected N-type MOSFETs 7, 8, and 9 and N-type MOSFETs 11, 12, and 13, respectively.

[0028] In this embodiment, as an example, each of the power switch sections 6 and 10 is made up of three N-type MOSFETs connected in series, but it goes without saying that the number of series can be changed arbitrarily.

[0029] The N-type MOSFETs 7, 8, 9 and the N-type MOSFETs 11, 12, 13 are all enhancement type MOSFETs.

[0030] In this embodiment, as an example, when the power switch units 6 and 10 are controlled to be in the ON state, the gate voltage is controlled to 15V, and when the power switch units 6 and 10 are controlled to be in the OFF state, the gate voltage is controlled to 0V.

[0031] The signals output from the gate drive circuits 4 and 5 are also input to the gates of the P-type MOSFETs 16 and 22 and the drains of the P-type MOSFETs 15 and 21 that constitute the gate series drive circuits 14 and 20 .

[0032] The P-type MOSFETs 15, 16, 18, 19, 21, 22, 24, and 25 are all enhancement type MOSFETs.

[0033] Furthermore, the absolute values ​​of the gate threshold voltages of the N-type MOSFETs 8 or 9 and the N-type MOSFETs 12 or 13 are greater than the gate threshold voltages of the P-type MOSFETs 15 or 18 and the P-type MOSFETs 21 or 24 .

[0034] First, the operation when the gate control unit 3 outputs an ON command will be described.

[0035] The 15V signals output from the gate drive circuits 4 and 5 turn on the N-type MOSFETs 7 and 11, and the drain voltages of the first-stage N-type MOSFETs 7 and 11 (i.e., the source voltages of the second-stage N-type MOSFETs 8 and 12) drop.

[0036] Furthermore, the 15V signals output by the gate drive circuits 4 and 5 are applied to the gates of the N-type MOSFETs 8 and 12 via the P-type MOSFETs 15 and 21 .

[0037] The source voltages of the N-type MOSFETs 8 and 12 decrease, the gate-source voltages of the N-type MOSFETs 8 and 12 increase to about 15 V, the N-type MOSFETs 8 and 12 enter the on state, and the drain voltages of the second-stage N-type MOSFETs 8 and 12 (i.e., the source voltages of the third-stage N-type MOSFETs 9 and 13) decrease.

[0038] At this time, the P-type MOSFETs 15 and 21 are in the ON state, and the P-type MOSFETs 16 and 22 are in the OFF state.

[0039] By a similar operation, the N-type MOSFETs 9 and 13 are also turned on, and the power switch sections 6 and 10 are turned on completely.

[0040] Next, the operation when the gate control unit 3 outputs an OFF command will be described.

[0041] The 0V signals output by the gate drive circuits 4 and 5 turn the N-type MOSFETs 7 and 11 off, and the drain voltages of the first-stage N-type MOSFETs 7 and 11 (i.e., the source voltages of the second-stage N-type MOSFETs 8 and 12 and the gate voltages of the P-type MOSFETs 15 and 21) rise.

[0042] Since the gate voltages of the P-type MOSFETs 15 and 21 increase, the P-type MOSFETs 15 and 21 are turned off, and the source-drain voltages of the P-type MOSFETs 15 and 21 (i.e., the source-gate voltages of the P-type MOSFETs 16 and 22) increase, turning the P-type MOSFETs 16 and 22 on.

[0043] As a result, the gate-source voltages of the N-type MOSFETs 8 and 12 become 0 V, the N-type MOSFETs 8 and 12 transition to the OFF state, and the drain voltages of the second-stage N-type MOSFETs 8 and 12 (i.e., the source voltages of the third-stage N-type MOSFETs 9 and 13 and the gate voltages of the P-type MOSFETs 18 and 24) rise.

[0044] By a similar operation, the N-type MOSFETs 9 and 13 are also turned off, and the power switch sections 6 and 10 are turned completely off.

[0045] By the on / off operation described above, the semiconductor device of this embodiment is capable of switching large power based on commands from the gate control unit 3.

[0046] <Drain-Source Short-Circuit Fault> Next, an operation when a short-circuit fault occurs between the drain and source of a part of the power switch units 6 and 10, for example, the N-type MOSFET 7, will be described.

[0047] The short circuit between the drain and source of the N-type MOSFET 7 does not affect the operation when the gate control unit 3 is outputting an ON command, and therefore the ON operation can be performed as normal.

[0048] Next, the operation when the gate control unit 3 outputs an OFF command will be described.

[0049] The power switch unit 10 is not broken and can operate normally.

[0050] In the power switch unit 6, since the drain and source of the N-type MOSFET 7 are short-circuited, the drain voltage of the N-type MOSFET 7 (i.e., the gate voltage of the P-type MOSFET 15) and the gate voltage of the N-type MOSFET 7 (i.e., the drain voltage of the P-type MOSFET 15) are at approximately the same potential.

[0051] Then, the charge accumulated in the source of the P-type MOSFET 15 (that is, the gate of the N-type MOSFET 8) is discharged until the source-gate voltage of the P-type MOSFET 15 reaches the gate threshold voltage of the P-type MOSFET 15.

[0052] Since the absolute value of the gate threshold voltage of the N-type MOSFET 8 is greater than the absolute value of the gate threshold voltage of the P-type MOSFET 15, the gate-source voltage of the N-type MOSFET 8 becomes lower than the gate threshold voltage of the N-type MOSFET 8, the N-type MOSFET 8 is turned off, and the drain voltage of the N-type MOSFET 8 increases.

[0053] Since the N-type MOSFET 8 is turned off, the N-type MOSFET 9 on the upper side is turned off as in normal operation.

[0054] As explained above, even if a short circuit occurs between the drain and source of N-type MOSFET 7, N-type MOSFETs 8 and 9 will operate in the off state, and therefore the withstand voltage of power switch unit 6 can be maintained by N-type MOSFETs 8 and 9, allowing the power switch unit 6 to continue operating in the off state.

[0055] <Gate-Source Short-Circuit Fault> Next, an operation when a short-circuit fault occurs between the gate and source of a part of the power switch units 6 and 10, for example, the N-type MOSFET 7, will be described.

[0056] A short circuit between the gate and source of the N-type MOSFET 7 does not affect the operation when the gate control unit 3 is outputting an OFF command, and therefore the OFF operation can be performed as normal.

[0057] Next, the operation when the gate control unit 3 outputs an ON command will be described.

[0058] In the power switch unit 6, the gate and source of the N-type MOSFET 7 are short-circuited, and the gate voltages of the N-type MOSFETs 7, 8, and 9 do not rise sufficiently, so the N-type MOSFETs 7, 8, and 9 are in the OFF state. In other words, the power switch unit 6 cannot be turned ON.

[0059] On the other hand, in the power switch section 10, the gates of the N-type MOSFETs 11, 12, and 13 are electrically insulated from the gate of the N-type MOSFET 7, so they are turned on as in normal operation.

[0060] As explained above, even if a short circuit occurs between the gate and source of the N-type MOSFET 7, the power switch section 10 can continue to operate in an on state.

[0061] <Drain-Gate Short-Circuit Fault> Next, an operation when a short-circuit fault occurs between the drain and gate of a part of the power switch units 6 and 10, for example, the N-type MOSFET 7, will be described.

[0062] The operation when the gate control unit 3 outputs an ON command will be described.

[0063] In the power switch unit 6, the drain and gate of the N-type MOSFET 7 are short-circuited, and the gate voltages of the N-type MOSFETs 8 and 9 do not rise sufficiently, so the N-type MOSFETs 8 and 9 are in the OFF state. In other words, the power switch unit 6 cannot be turned ON.

[0064] On the other hand, in the power switch section 10, the gates of the N-type MOSFETs 11, 12, and 13 are electrically insulated from the gate of the N-type MOSFET 7, so they are turned on as in normal operation.

[0065] As explained above, even if a short circuit occurs between the drain and gate of the N-type MOSFET 7, the power switch section 10 can continue to operate in an on state.

[0066] Next, the operation when the gate control unit 3 outputs an OFF command will be described.

[0067] The power switch unit 10 is not broken and can operate normally.

[0068] In the power switch unit 6, since the gate and drain of the N-type MOSFET 7 are short-circuited, the drain voltage of the N-type MOSFET 7 (i.e., the gate voltage of the P-type MOSFET 15) and the gate voltage of the N-type MOSFET 7 (i.e., the drain voltage of the P-type MOSFET 15) are at approximately the same potential.

[0069] Then, the charge accumulated in the source of the P-type MOSFET 15 (that is, the gate of the N-type MOSFET 8) is discharged until the source-gate voltage of the P-type MOSFET 15 reaches the gate threshold voltage of the P-type MOSFET 15.

[0070] Since the absolute value of the gate threshold voltage of the N-type MOSFET 8 is greater than the absolute value of the gate threshold voltage of the P-type MOSFET 15, the gate-source voltage of the N-type MOSFET 8 becomes lower than the gate threshold voltage of the N-type MOSFET 8, the N-type MOSFET 8 is turned off, and the drain voltage of the N-type MOSFET 8 increases.

[0071] Since the N-type MOSFET 8 is turned off, the N-type MOSFET 9 on the upper side is turned off as in normal operation.

[0072] As explained above, even if a short circuit occurs between the drain and gate of N-type MOSFET 7, N-type MOSFETs 8 and 9 operate in the off state, and therefore the withstand voltage of power switch unit 6 can be maintained by N-type MOSFETs 8 and 9, allowing the power switch unit 6 to continue operating in the off state.

[0073] As described above, the semiconductor device of this embodiment shown in FIG. 1 can continue power switching operation even if a short circuit occurs between the drain and source, between the gate and source, or between the drain and gate of some of the semiconductor elements that make up the power switch units 6 and 10.

[0074] As a modification of FIG. 1, FIG. 2 shows an example in which the power switch section 6 is configured with a P-type MOSFET.

[0075] The gate of the first-stage P-type MOSFET 26 of the power switch section 6 , which is made up of P-type MOSFETs 26 , 27 , and 28 connected in series, is controlled by a gate drive circuit 4 .

[0076] In this modified example, as an example, when the power switch unit 6 is controlled to be in the on state, the gate-source voltage is controlled to -15V, and when the power switch unit 6 is controlled to be in the off state, the gate-source voltage is controlled to 0V.

[0077] The signal output from the gate drive circuit 4 is also input to the drain of an N-type MOSFET 29 and the gate of an N-type MOSFET 30 that constitute the gate series drive circuit 14 .

[0078] As in the example of FIG. 1, when the gate drive circuit 4 outputs an ON signal (-15V), the P-type MOSFETs 26, 27, and 28 are turned ON, and the power switch section 6 is turned ON.

[0079] Furthermore, when the gate drive circuit 4 outputs an OFF signal (0 V), the N-type MOSFETs 30 and 32 are turned ON, the N-type MOSFETs 29 and 31 are turned OFF, the P-type MOSFETs 26, 27 and 28 are turned OFF, and the power switch unit 6 is turned OFF.

[0080] As another modification of FIG. 1, FIG. 3 shows an example in which the power switch section 6 is configured with a high-voltage N-type MOSFET.

[0081] In the configuration shown in FIG. 1 , for example, when the power switch unit 6 is in the off state, the drain-source voltage of the N-type MOSFET 7 is equal to the voltage applied between the gate of the N-type MOSFET 7 and the gate of the N-type MOSFET 8 and the source-gate voltage of the P-type MOSFET 16. Therefore, even if the drain-source withstand voltage of the N-type MOSFET 7 is improved, the withstand voltage of the circuit configuration as a whole is limited to the source-gate withstand voltage of the P-type MOSFET 16.

[0082] In the modification shown in FIG. 3, the power switch unit 6 is composed of high-voltage N-type MOSFETs 33, 34, and 35, with a high-voltage P-type MOSFET 36 provided between the gate of the high-voltage N-type MOSFET 33 and the drain of the P-type MOSFET 15, and a high-voltage P-type MOSFET 37 provided between the gate of the high-voltage N-type MOSFET 34 and the drain of the P-type MOSFET 18.

[0083] When the gate control unit 3 outputs an ON command, the high voltage P-type MOSFETs 36 and 37 are turned on, and therefore the high voltage N-type MOSFETs 33, 34, and 35 are turned on.

[0084] Furthermore, when the gate control unit 3 is outputting an OFF command, the high voltage P-type MOSFETs 36 and 37 are in the OFF state, and the high voltage N-type MOSFETs 33, 34, and 35 are in the OFF state.

[0085] The operations of the P-type MOSFETs 15, 16, 18, and 19 are the same as those in FIG.

[0086] In this modification, when the power switch unit 6 is in the off state, the drain-source voltage of the high-voltage N-type MOSFET 33 is equal to the voltage between the gate of the high-voltage N-type MOSFET 33 and the gate of the high-voltage N-type MOSFET 34, that is, the sum of the source-drain voltage of the high-voltage P-type MOSFET 36 and the source-gate voltage of the P-type MOSFET 16.

[0087] The addition of the high-voltage P-type MOSFET 36 has the effect of reducing the voltage applied between the source and gate of the P-type MOSFET 16, so that in this modification, the voltage resistance performance per semiconductor element stage can be improved.

[0088] As described above, the semiconductor device of this embodiment has a plurality of semiconductor elements (N-type MOSFETs 7, 8, 9, 11, 12, 13) connected in multiple stages in which the drain of a semiconductor element (e.g., N-type MOSFET 7) in a preceding stage is connected in series with the source of a semiconductor element (e.g., N-type MOSFET 8) in a succeeding stage, and includes a plurality of power switch units 6, 10 to which drive signals are input to the gates of the first-stage semiconductor elements (N-type MOSFETs 7, 11), first gate drive circuits 4, 5 to which drive signals are input to the gates of the first-stage semiconductor elements (N-type MOSFETs 7, 11) to drive the first-stage semiconductor elements (N-type MOSFETs 7, 11), and a plurality of gate series drive circuits 14, 17, 20, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91 23, and the plurality of power switch sections 6, 10 have a first power switch section 6 and a second power switch section 10 connected in parallel to each other, the source of the first-stage semiconductor element (N-type MOSFET 7) of the first power switch section 6 is connected to the source of the first-stage semiconductor element (N-type MOSFET 11) of the second power switch section 10, the drain of the final-stage semiconductor element (N-type MOSFET 9) of the first power switch section 6 is connected to the drain of the final-stage semiconductor element (N-type MOSFET 13) of the second power switch section 10, and the gate of the first-stage semiconductor element (N-type MOSFET 7) of the first power switch section 6 is electrically insulated from the gate of the first-stage semiconductor element (N-type MOSFET 11) of the second power switch section 10, or is electrically insulated under predetermined conditions.

[0089] Each of the plurality of power switch sections 6, 10 is composed of a plurality of semiconductor elements of a first conductivity type (N-type MOSFETs), and each of the plurality of gate series drive circuits 14, 17, 20, 23 is composed of two semiconductor elements of a second conductivity type (for example, P-type MOSFETs 15, 16), and a first terminal to which the sources of the two semiconductor elements of the second conductivity type (P-type MOSFETs 15, 16) are connected is connected to the gate of one semiconductor element of the second conductivity type (P-type MOSFET 15) and the drain of the other semiconductor element of the second conductivity type (P-type MOSFET 16). The power switching element has a second terminal and a third terminal connected to each other, the first terminal being electrically connected to the gate of the next-stage semiconductor element (e.g., N-type MOSFET 8) of each of the plurality of power switch sections 6, 10, the second terminal being electrically connected to the source of the next-stage semiconductor element (e.g., N-type MOSFET 8) of each of the plurality of power switch sections 6, 10 or the drain of the previous-stage semiconductor element (e.g., N-type MOSFET 7), and the third terminal being connected directly or indirectly to the gate of the previous-stage semiconductor element (e.g., N-type MOSFET 7) of each of the plurality of power switch sections 6, 10.

[0090] Furthermore, the gate of the first-stage semiconductor element (N-type MOSFET 7) of the first power switch section 6 is electrically insulated from the gate of the first-stage semiconductor element (N-type MOSFET 11) of the second power switch section 10, and first gate drive circuits 4 and 5 are provided for the first power switch section 6 and the second power switch section 10, respectively, and each of the first gate drive circuits 4 and 5 is controlled by the same control signal (signal from the gate control section 3).

[0091] Furthermore, in the gate drive method for the semiconductor device of this embodiment, the gates of the first-stage semiconductor elements (N-type MOSFETs 7, 11) of the plurality of power switch units 6, 10 are independently controlled by the respective first gate drive circuits 4, 5.

[0092] Second Embodiment A semiconductor device and a gate driving method thereof according to a second embodiment of the present invention will be described with reference to FIGS. 4 to 5B.

[0093] Fig. 4 is a circuit diagram showing a schematic configuration of a semiconductor device of this embodiment. Fig. 5A is a diagram showing an example of a gate current waveform flowing through a gate switch during normal operation of the semiconductor device of Fig. 4. Fig. 5B is a diagram showing an example of a gate current waveform flowing through a gate switch during a gate-source or drain-gate short-circuit fault of the semiconductor device of Fig. 4.

[0094] The difference from the first embodiment is that in this embodiment, the gate drive circuit 4 drives the gates of the N-type MOSFETs 7 and 11 of the power switch sections 6 and 10 via gate switches 38 and 39 .

[0095] The configuration of this embodiment shown in Fig. 4 has the advantage that there is no concern about mismatch in drive timing due to variations in performance of the components of the gate drive circuit, compared to the case of embodiment 1 (Fig. 1) in which the power switch units 6 and 10 are driven by different gate drive circuits 4 and 5. In addition, there is the advantage that the number of gate drive circuits can be reduced, thereby reducing the number of components.

[0096] FIG. 5A is a schematic diagram of the gate current waveform flowing through the gate switch 38 during normal operation, and FIG. 5B is a schematic diagram of the gate current waveform when, for example, a short circuit occurs between the gate and source or between the drain and gate of the N-type MOSFET 7.

[0097] The gate switches 38 and 39 are on (conductive) during normal operation, but are controlled to be off (non-conductive) if the gate current value during period 40 (see FIG. 5A) is equal to or greater than a predetermined value, for example, while the gate control unit 3 is outputting an on command.

[0098] Furthermore, as shown in FIG. 5B, if there is a short circuit between the gate and source or between the drain and gate, a DC gate current flows during the on period after turning on, and therefore, by sensing the gate current during period 40, it is possible to detect a short circuit between the gate and source or between the drain and gate.

[0099] The gate switches 38 and 39 may be semiconductor switches such as MOSFETs, but fuses, capacitors, etc. may also be used as autonomous cutoff means.

[0100] As described above, in the semiconductor device of this embodiment, the gates of the first-stage semiconductor elements (N-type MOSFETs 7, 11) of each of the plurality of power switch units 6, 10 are connected to the same first gate drive circuit 4 via the gate switches 38, 39.

[0101] Furthermore, during a predetermined period 40, if the amount of current flowing through a gate switch 38 arranged between the first gate drive circuit 4 and the gate of the first-stage semiconductor element (N-type MOSFET 7) of the first power switch section 6 is greater than a predetermined value, the gate switch 38 is turned off, and the first gate drive circuit 4 and the gate of the first-stage semiconductor element (N-type MOSFET 7) of the first power switch section 6 are electrically isolated from each other.

[0102] Third Embodiment A semiconductor device and a gate driving method thereof according to a third embodiment of the present invention will be described with reference to FIGS.

[0103] Fig. 6 is a circuit diagram showing a schematic configuration of a semiconductor device according to this embodiment, and Fig. 7 is a circuit diagram showing a modification of the semiconductor device shown in Fig. 6.

[0104] The difference from the first embodiment is that in this embodiment, the gate drive circuits 4 and 5 are electrically separated from the gate series drive circuits 14 and 20, and the signals are amplified by the gate drive circuits 42 and 43 based on a command output from a gate control unit 41 to drive the gate series drive circuits 14 and 20.

[0105] The gate control unit 41 issues an ON command at least while the arm is ON and during the dead time when the opposite arm is turned OFF. For example, it may output an ON command at all times while the system is operating.

[0106] In the semiconductor device of the first embodiment ( FIG. 1 ), when the paired arm performs a turn-off operation and a reflux current flows in its own arm, the N-type MOSFETs 7, 8, 9, 11, 12, and 13 are in an off state, and therefore the current flows through the diodes parasitic to the respective MOSFETs. However, there is a problem in that the reverse conduction loss increases due to the built-in potential of the diodes.

[0107] According to the configuration of this embodiment (FIG. 6), the N-type MOSFETs 8, 9, 12, and 13 are in the on state when the device switches to freewheeling operation, and current flows through the MOSFETs, thereby reducing reverse conduction loss due to the built-in potential of the diodes.

[0108] Although the above description has been given based on the configuration of the first embodiment (FIG. 1), it may be combined with the configuration of the second embodiment (FIG. 4) as shown in FIG.

[0109] As described above, in the semiconductor device of this embodiment, the gate of the first-stage semiconductor element (e.g., N-type MOSFET 7) in each of the plurality of power switch sections 6, 10 is electrically isolated from the third terminal of the first-stage gate series drive circuit (e.g., gate series drive circuit 14), and the semiconductor device is provided with a second gate drive circuit (e.g., gate drive circuit 42) that is electrically connected directly or indirectly to the third terminal of the first-stage gate series drive circuit (e.g., gate series drive circuit 14) and drives the first-stage gate series drive circuit (e.g., gate series drive circuit 14).

[0110] Furthermore, the gate of the first-stage semiconductor element (N-type MOSFET 7) of the first power switch section 6 is electrically insulated from the gate of the first-stage semiconductor element (N-type MOSFET 11) of the second power switch section 10, the third terminal of the first-stage gate series drive circuit 14 connected to the first power switch section 6 is electrically insulated from the third terminal of the first-stage gate series drive circuit 20 connected to the second power switch section 10, and first gate drive circuits 4, 5 and second gate drive circuits 42, 43 are provided for the first power switch section 6 and the second power switch section 10, respectively, and the plurality of first gate drive circuits 4, 5 and the plurality of second gate drive circuits 42, 43 are each controlled by the same control signal (signal from the gate control sections 3, 41).

[0111] Furthermore, the gates of the first-stage semiconductor elements (N-type MOSFETs 7, 11) of each of the plurality of power switch units 6, 10 are connected to the same first gate drive circuit 4 via gate switches 38, 39, and the third terminals of the first-stage gate series drive circuits 14, 20 of the plurality of gate series drive circuits 14, 17, 20, 23 are connected to the same second gate drive circuit 42 via gate switches 44, 45.

[0112] Furthermore, during a predetermined period 40, if the amount of current flowing through a first switch (gate switch 38) arranged between the first gate drive circuit 4 and the gate of the first-stage semiconductor element (N-type MOSFET 7) of the first power switch section 6 is greater than a predetermined value, the first switch (gate switch 38) is turned off, and the first gate drive circuit 4 and the gate of the first-stage semiconductor element (N-type MOSFET 7) of the first power switch section 6 are electrically isolated from each other, and during the predetermined period 40, if the amount of current flowing through a second switch (gate switch 44) arranged between the second gate drive circuit 42 and the third terminal of the first-stage gate series drive circuit 14 connected to the first power switch section 6 is greater than a predetermined value, the second switch (gate switch 44) is turned off, and the second gate drive circuit 42 and the third terminal of the first-stage gate series drive circuit 14 connected to the first power switch section 6 are electrically isolated from each other.

[0113] The present invention is not limited to the above-described embodiments, but includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0114] 1...Source terminal, 2...Drain terminal, 3, 41...Gate control unit, 4, 5, 42, 43...Gate drive circuit, 6, 10...Power switch unit, 7, 8, 9, 11, 12, 13, 29, 30, 31, 32...N-type MOSFET, 14, 17, 20, 23...Gate series drive circuit, 15, 16, 18, 19, 21, 22, 24, 25, 26, 27, 28...P-type MOSFET, 33, 34, 35...High-voltage N-type MOSFET, 36, 37...High-voltage P-type MOSFET, 38, 39, 44, 45...Gate switch, 40...Current detection period.

Claims

1. A power supply circuit having a plurality of semiconductor elements connected in multiple stages, with the drain of a semiconductor element in a preceding stage and the source of a semiconductor element in a succeeding stage connected in series, and comprising: a plurality of power switch sections to which a drive signal is input to the gate of a first-stage semiconductor element; a first gate drive circuit that inputs a drive signal to the gate of the first-stage semiconductor element to drive the first-stage semiconductor element; and a plurality of gate series drive circuits that control the gate of a next-stage semiconductor element by a signal output from a preceding-stage semiconductor element, wherein the plurality of power switch sections have a first power switch section and a second power switch section that are connected in parallel to each other; the source of the first-stage semiconductor element of the first power switch section is connected to the source of the first-stage semiconductor element of the second power switch section; and the drain of a final-stage semiconductor element of the first power switch section is connected to the drain of a final-stage semiconductor element of the second power switch section; a gate of a first-stage semiconductor element of the first power switch section and a gate of a first-stage semiconductor element of the second power switch section are electrically insulated from each other, or are electrically insulated from each other under predetermined conditions.

2. A semiconductor device according to claim 1, wherein each of the plurality of power switch sections is composed of a plurality of semiconductor elements of a first conductivity type, and each of the plurality of gate series drive circuits is composed of two semiconductor elements of a second conductivity type and has a first terminal to which the sources of the two semiconductor elements of the second conductivity type are connected, and a second terminal and a third terminal to which the gate of one semiconductor element of the second conductivity type is connected to the drain of the other semiconductor element of the second conductivity type, respectively, the first terminal is electrically connected to the gate of the semiconductor element in the next stage of each of the plurality of power switch sections, the second terminal is electrically connected to the source of the semiconductor element in the next stage of each of the plurality of power switch sections or the drain of the semiconductor element in the previous stage, and the third terminal is connected directly or indirectly to the gate of the semiconductor element in the previous stage of each of the plurality of power switch sections.

3. A semiconductor device according to claim 2, wherein the gate of the first-stage semiconductor element of each of said plurality of power switch sections is electrically isolated from the third terminal of said first-stage gate series drive circuit, and further comprising a second gate drive circuit that is electrically connected directly or indirectly to the third terminal of said first-stage gate series drive circuit and drives said first-stage gate series drive circuit.

4. A semiconductor device according to claim 1, wherein the gate of the first stage semiconductor element of the first power switch section and the gate of the first stage semiconductor element of the second power switch section are electrically insulated, the first power switch section and the second power switch section are provided with respective first gate drive circuits, and each of the first gate drive circuits is controlled by the same control signal.

5. A semiconductor device according to claim 1, wherein the gates of the first-stage semiconductor elements of each of the plurality of power switch sections are connected to one and the same first gate drive circuit via a switch.

6. A semiconductor device according to claim 5, characterized in that when the amount of current flowing through the switch arranged between the first gate drive circuit and the gate of the first stage semiconductor element of the first power switch section during a predetermined period is greater than a predetermined value, the switch is turned off, and the first gate drive circuit and the gate of the first stage semiconductor element of the first power switch section are electrically isolated.

7. A semiconductor device according to claim 3, wherein the gate of the first stage semiconductor element of the first power switch section is electrically insulated from the gate of the first stage semiconductor element of the second power switch section, the third terminal of the first stage gate series drive circuit connected to the first power switch section is electrically insulated from the third terminal of the first stage gate series drive circuit connected to the second power switch section, and the semiconductor device is provided with a first gate drive circuit and a second gate drive circuit for the first power switch section and the second power switch section, respectively, and the plurality of first gate drive circuits and the plurality of second gate drive circuits are each controlled by the same control signal.

8. A semiconductor device according to claim 3, wherein the gates of the first-stage semiconductor elements of each of the plurality of power switch sections are connected to one and the same first gate drive circuit via a switch, and the third terminals of each of the first-stage gate series drive circuits of the plurality of gate series drive circuits are connected to one and the same second gate drive circuit via a switch.

9. A semiconductor device according to claim 8, wherein, when the amount of current flowing through a first switch arranged between said first gate drive circuit and the gate of the first stage semiconductor element of said first power switch section is greater than a predetermined value during a predetermined period, said first switch is turned off, thereby electrically isolating said first gate drive circuit from the gate of the first stage semiconductor element of said first power switch section; and when the amount of current flowing through a second switch arranged between said second gate drive circuit and a third terminal of said first stage gate series drive circuit connected to said first power switch section is greater than a predetermined value during a predetermined period, said second switch is turned off, thereby electrically isolating said second gate drive circuit from the third terminal of said first stage gate series drive circuit connected to said first power switch section.

10. A gate driving method for a semiconductor device for driving the semiconductor device described in claim 1, characterized in that the gates of the first stage semiconductor elements are independently controlled for the plurality of power switch sections by the respective first gate driving circuits.

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