Semiconductor device, and semiconductor device manufacturing method

Abstract

A semiconductor device comprising: an interlayer insulating film having a multilayer structure obtained by repeatedly layering a first insulating film and a second insulating film that makes it possible to etch the first insulating film at a high selectivity; a lower layer conductive pattern and an upper layer conductive pattern arranged above and below the interlayer insulating film; and a capacitor having a configuration in which a lower electrode layer, an insulating layer, and an upper electrode layer are layered in this order continuously from the upper surface of the interlayer insulating film and along the inner wall of a recess provided in the interlayer insulating film, wherein the side peripheral wall of the recess has a recessed / protruding shape including the inner walls of lateral grooves formed in the second insulating films, and the capacitor is disposed on the side peripheral wall of the recess so as to follow the recessed / protruding shape.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] One technology related to a semiconductor device equipped with a capacitor is described in Patent Document 1 below. Patent Document 1 states that "metal-insulator-metal (MIM) capacitors are disposed along the sidewall and bottom surfaces of each of a plurality of trenches present in the upper part of a second dielectric layer, and on the uppermost surface of the portion of the second dielectric layer that defines the plurality of trenches," and claims that this makes it possible to increase the capacitance of the capacitor without increasing the size of the chip.

[0003] U.S. Pat. No. 1,004,3863

[0004] However, in semiconductor devices, there is a demand for further increases in capacitor capacitance without increasing the chip size or the area occupied by the capacitor.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device and a method for manufacturing the semiconductor device that can increase the capacitance of the capacitor without increasing the chip size and the area occupied by the capacitor.

[0006] In order to solve the above-mentioned problems, for example, the configuration described in the claims is adopted. The present application includes a plurality of means for solving the above-mentioned problems, and one example thereof is a semiconductor device including: an interlayer insulating film having a multilayer structure in which a first insulating film and a second insulating film that can be etched with a high selectivity relative to the first insulating film are repeatedly stacked; a lower-layer conductive pattern and an upper-layer conductive pattern arranged above and below the interlayer insulating film; and a capacitor configured in which a lower electrode layer, an insulating layer, and an upper electrode layer are continuously stacked in this order from an upper surface of the interlayer insulating film along an inner wall of a recess provided in the interlayer insulating film, the side walls of the recess having an uneven shape including an inner wall of a lateral groove formed in the second insulating film, and the capacitor is arranged on the side walls of the recess along the uneven shape.

[0007] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device that can increase the capacitance of the capacitor without increasing the chip size and the area occupied by the capacitor.

[0008] FIG. 1 is a cross-sectional view of a main portion of a semiconductor device according to a first embodiment; FIG. 2 is a plan view of a capacitor of the semiconductor device according to the first embodiment; FIG. 3 is a plan view showing another example of a capacitor of the semiconductor device according to the first embodiment; FIG. 4 is a process diagram (part 1) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 5 is a process diagram (part 6) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 6 is a process diagram (part 7) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 8 is a process diagram (part 9) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 10 is a process diagram (part 10) showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 11 is a plan view for explaining a capacitor area of ​​a conventional structure compared with the first embodiment; FIG. 12 is a plan view for explaining a capacitor area of ​​a first example to which the first embodiment is applied; FIG. 13 is a plan view for explaining a capacitor area of ​​a second example to which the first embodiment is applied; and FIG. 14 is a plan view for explaining a capacitor area of ​​another conventional structure to compare with the semiconductor device of the first embodiment. FIG. 1 is a plan view for explaining a capacitor area of ​​a third example to which the first embodiment is applied. FIG. 2 is a plan view for explaining a capacitor area of ​​a fourth example to which the first embodiment is applied. FIG. 3 is a plan view for explaining a capacitor area of ​​a fifth example to which the first embodiment is applied. FIG. 4 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment. FIG. 5 is a plan view of a capacitor of a semiconductor device according to a second embodiment. FIG. 6 is a plan view showing another example of a capacitor of a semiconductor device according to the second embodiment. FIG. 7 is a process diagram (part 1) showing a method for manufacturing a semiconductor device according to a second embodiment. FIG. 8 is a process diagram (part 2) showing a method for manufacturing a semiconductor device according to a second embodiment. FIG. 9 is a process diagram (part 3) showing a method for manufacturing a semiconductor device according to a second embodiment. FIG. 10 is a process diagram (part 4) showing a method for manufacturing a semiconductor device according to a second embodiment. FIG. 11 is a process diagram (part 5) showing a method for manufacturing a semiconductor device according to a second embodiment. FIG. 12 is a process diagram (part 6) showing a method for manufacturing a semiconductor device according to a second embodiment.7A to 7C are process diagrams (part 7) illustrating the method for manufacturing a semiconductor device according to the second embodiment.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the embodiments described below, the same components are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0010] 1 is a cross-sectional view of a main portion of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 shown in FIG. 1 has a configuration in which a capacitor 30 having a fin-shaped portion is provided in an interlayer insulating film 20 that is arranged between a lower conductive layer in which a lower-layer conductive pattern 10 is arranged and an upper conductive layer in which an upper-layer conductive pattern 50 is arranged.

[0011] The interlayer insulating film 20 is a via layer insulating film in which vias 40 that connect the lower layer conductive pattern 10 and the upper layer conductive pattern 50 are arranged, and is an insulating film sandwiched between a lower conductive layer and an upper conductive layer immediately above it. This interlayer insulating film 20 has a multilayer structure in which first insulating films 201 and second insulating films 202 that can be etched with a high selectivity relative to the first insulating film 201 are alternately stacked. In other words, it is a multilayer structure in which the first insulating films 201 and the second insulating films 202 that have a lower film density than the first insulating film 202 are alternately stacked.

[0012] Such an interlayer insulating film 20 has a recess 20a penetrating at least two second insulating films 202. In the illustrated example, the interlayer insulating film 20 has a stacked structure in which a second insulating film 202 is sandwiched between four first insulating films 201, and includes a recess 20a with the bottom surface of the lowest first insulating film 201. The side walls of such a recess 20a have an uneven shape with multiple lateral grooves 20b formed in the second insulating film 202. More specifically, the side walls of the recess 20a have an uneven shape with multiple lateral grooves 20b formed by receding each second insulating film 202 with respect to the first insulating film 201. In the illustrated example, the lateral grooves 20b are formed with a width [W1] in the surface direction of the second insulating film 202.

[0013] The capacitor 30 is a metal-insulator-metal capacitor (MIM capacitor) formed by laminating a thin-film lower electrode layer 301, an insulating layer 302, and an upper electrode layer 303 in this order. The capacitor 30 is disposed continuously from the top surface of the interlayer insulating film 20 along the side walls and bottom surface of a recess 20a formed in the interlayer insulating film 20. On the side walls of the recess 20a, the capacitor 30 is disposed along the inner walls of lateral grooves 20b formed by recession of the second insulating film 202, and the portions along the side walls of the lateral grooves 20b form a fin shape.

[0014] 2 is a plan view of a capacitor 30 of the semiconductor device according to the first embodiment. As shown in FIG. 2, the recess 20a may be trench-shaped. In this case, a lateral groove 20b extends outward from the entire periphery of the trench-shaped recess 20a formed in the interlayer insulating film 20, and the capacitor 30 is provided so as to cover the inner wall thereof. Note that FIG. 1 shown above corresponds to the A-A cross section of FIG. 2 as an example.

[0015] 3 is a plan view showing another example of the capacitor 30 of the semiconductor device according to the first embodiment. As shown in FIG. 3, the recess 20a may be hole-shaped. Even in this case, a lateral groove 20b is provided extending outward from the entire periphery of the hole-shaped recess 20a formed in the interlayer insulating film 20, and the capacitor 30 is provided so as to cover the inner wall of the lateral groove 20b.

[0016] 4 to 13 are process diagrams (parts 1) to (part 10) showing a method for manufacturing the semiconductor device 1 according to the first embodiment. The detailed configuration of the semiconductor device 1 described above will be described below in accordance with the manufacturing process sequence shown in FIGS.

[0017] 4, an interlayer insulating film 20 is formed by alternately depositing first insulating films 201 and second insulating films 202 on an underlying insulating film 100 that exposes an underlying conductive pattern 10. As an example, the underlying conductive pattern 10 is a wiring containing copper (Cu), but may also be made of Ru, Mo, Co, etc. The underlying insulating film 100 is made of a hydrogenated silicon dioxide carbon material (hereinafter referred to as SiCOH) containing Si, C, O, and H, but may also be SiCNH or SiNCOH.

[0018] Here, four layers of first insulating films 201 and three layers of second insulating films 202 are alternately formed so that the bottom and top layers of the interlayer insulating film 20 are the first insulating films 201. In this case, for example, a silicon carbonitride (hereinafter, SiCN) film is formed as the first insulating film 201. Furthermore, a SiCOH film is formed as the second insulating film 202, which enables etching with a high selectivity relative to the first insulating film 201. The first insulating film 201 is not limited to SiCN, and may be AlO, AlN, or SiC.

[0019] Next, as shown in FIG. 5 , a resist pattern 61 is formed on the interlayer insulating film 20 by lithography. Thereafter, the interlayer insulating film 20 is etched using the resist pattern 61 as a mask to form trench-shaped or hole-shaped recesses 20a. This etching is performed until the first insulating film 201 constituting the bottom layer of the interlayer insulating film 20 is exposed, thereby forming the recesses 20a with the first insulating film 201 exposed at the bottom. This etching is anisotropic etching using fluorine gas. This anisotropic etching forms a damaged layer 20d in which carbon C is removed from the etched sidewalls of the second insulating film 202 made of SiCOH.

[0020] 6, the resist pattern 61 (see FIG. 5) is completely removed by ashing using oxygen plasma. This ashing process also removes carbon from the second insulating film 202 exposed on the side walls of the recess 20a, expanding the damaged layer 20d in the width direction (the surface direction of the second insulating film 202). At this time, the ashing process is performed under conditions adjusted so that the expanded range of the damaged layer 20d corresponds to the width [W1] of the lateral groove 20b shown in FIG.

[0021] 7, the damaged layer 20d is selectively etched away from the first insulating film 201 and the second insulating film 202, thereby forming a lateral groove 20b on the side wall of the recess 20a. At this time, the damaged layer 20d is isotropically etched away by, for example, a DHF (diluted hydrogen fluoride) process using diluted hydrofluoric acid.

[0022] 8, a thin-film lower electrode layer 301 is formed continuously over the entire exposed surface of the interlayer insulating film 20, including the inner walls of the recesses 20a, from the upper surface of the interlayer insulating film 20 along the inner walls of the recesses 20a formed in the interlayer insulating film 20. At this time, the lower electrode layer 301 made of titanium nitride (TiN) is formed by, for example, atomic layer deposition (ALD).

[0023] 9, a resist pattern 62 is formed on the lower electrode layer 301 by lithography so as to fill the recess 20a. Thereafter, the lower electrode layer 301 is etched using the resist pattern 62 as a mask, and the lower electrode layer 301 is patterned so as to leave at least the portion along the inner wall of the recess 20a. At this time, reactive ion etching (RIE) using halogen gas is performed to pattern the lower electrode layer 301 made of titanium nitride (TiN).

[0024] Thereafter, the resist pattern 62 is completely removed by an ashing process using oxygen plasma and a cleaning process using wet etching.

[0025] 10 , a thin-film insulating layer 302 and an upper electrode layer 303 are formed in this order on the entire exposed surface of the interlayer insulating film 20, including the inner walls of the recesses 20a, via the lower electrode layer 301. In this process, a high-dielectric-constant (high-k) film such as hafnium oxide (HfOx) is formed as the insulating layer 302, for example, by ALD, and then the upper electrode layer 303 made of TiN is formed. Note that the insulating layer 302 is not limited to HfOx as long as it is a high-dielectric-constant (high-k) film. For example, aluminum oxide (AlOx) or zirconium oxide (ZrOx) may be used, or a mixed film such as HZO (HfZrO) may be used. Furthermore, a film obtained by stacking these films, such as HAH (HfO / AlO / HfO), HZH (HfO / AlO / HfO), or ZAZ (ZrO / AlO / ZrO), may also be used.

[0026] Next, as shown in FIG. 11 , a resist pattern 63 is formed on the upper electrode layer 303 by lithography so as to fill the recess 20a. The upper electrode layer 303 is then etched using the resist pattern 63 as a mask, leaving at least the portion along the inner wall of the recess 20a and patterning the upper electrode layer 303 so that the upper portion of the lower electrode layer 301 is partially removed. At this time, the upper electrode layer 303 made of titanium nitride (TiN) is patterned by RIE using halogen gas. This forms a capacitor 30 with an MIM structure in which the lower electrode layer 301, insulating layer 302, and upper electrode layer 303 are stacked in this order. This capacitor 30 is arranged along the uneven shape on the side walls of the recess 20a.

[0027] Thereafter, the resist pattern 63 is completely removed by an ashing process using oxygen plasma and a cleaning process using wet etching.

[0028] 12, a buried insulating film 41 is formed on the entire surface of the interlayer insulating film 20 via the capacitor 30, and the recess 20a and the lateral groove 20b are filled with the buried insulating film 41. At this time, silicon oxide (SiO ２In forming the buried insulating film 41, voids and seams may remain in the recess 20a and the lateral groove 20b, but it is sufficient that the opening of the recess 20a is closed with the buried insulating film 41, and the recess 20a and the lateral groove 20b do not have to be completely filled with the buried insulating film 41.

[0029] 13, a planarization insulating film 42 and an insulating mask layer 43 are formed on the buried insulating film 41. The planarization insulating film 42 may be formed as a film made of, for example, SiCOH, and may be subjected to chemical mechanical polishing (CMP) for planarization after the film formation. The insulating mask layer 43 is a layer used as a hard mask in the subsequent etching, and may be formed of, for example, SiO ２ The film is formed as a film consisting of the above.

[0030] 1, vias 40 connected to the lower-layer conductive pattern 10 are formed in the interlayer insulating film 20, and upper-layer conductive patterns 50 connected to the vias 40 are formed in the buried insulating film 41 and the planarizing insulating film 42. The vias 40 include a first via 401 connected to the lower electrode layer 301 and the lower-layer conductive pattern 10, and a second via 402 connected to the upper electrode layer 303 and the lower-layer conductive pattern 10. Here, the vias 40 and the upper-layer conductive pattern 50 are formed by, for example, the following dual damascene method.

[0031] First, by etching using a resist pattern (not shown) as a mask, via holes are formed in the insulating mask layer 43 (see FIG. 13), the planarizing insulating film 42, the buried insulating film 41, the upper electrode layer 303, the insulating layer 302, and the lower electrode layer 301 that constitute the capacitor 30, and further in the interlayer insulating film 20. The etching is stopped at the first insulating film 201, which is the lowest layer in the interlayer insulating film 20.

[0032] Next, a wiring groove pattern communicating with the via hole is formed in the insulating mask layer 43 (see FIG. 13 ) and the planarizing insulating film 42 by etching using a multilayer photoresist pattern as a mask. The first insulating film 201 remaining at the bottom of the via pattern is then etched away, exposing the lower-layer conductive pattern 10 at the bottom of the via hole. A copper seed layer is then formed on the entire exposed surface, including the groove pattern and the inner wall of the via hole, and the groove pattern and the via hole are filled with a copper plating film using this as a base. The copper film on the insulating mask layer 43 (see FIG. 13 ) is then removed by CMP, and the planarizing insulating film 42 is then removed, thereby forming the via 40 connected to the lower-layer conductive pattern 10 and the upper-layer conductive pattern 50 above it by the dual damascene method. At this time, for example, at least one upper-layer conductive pattern 51 of the multiple upper-layer conductive patterns 50 is connected to the lower electrode layer 301 of the capacitor 30, and the other upper-layer conductive pattern 52 is connected to the upper electrode layer 303 of the capacitor 30.

[0033] In this manner, the semiconductor device 1 according to the first embodiment described above is obtained.

[0034] Effects of the First Embodiment According to the first embodiment described above, by providing the MIM-structure capacitor 30 along the recess 20a having uneven side walls, it is possible to increase only the area of ​​the capacitor 30 without increasing the area occupied by the capacitor 30. Moreover, because the recess 20a in which the capacitor 30 is disposed is formed in the interlayer insulating film 20 between the lower conductive layer in which the lower-layer conductive pattern 10 is disposed and the upper conductive layer immediately above it, the expansion of the area of ​​the capacitor 30 does not affect the arrangement of the conductive pattern. As a result, it is possible to increase the capacitance of the capacitor without increasing the chip size or the area occupied by the capacitor.

[0035] A comparison of the area between a capacitor with a conventional configuration and a capacitor with a configuration to which the first embodiment is applied will be described below.

[0036] FIG. 14 is a plan view illustrating the capacitor area of ​​a conventional structure compared with the first embodiment. In FIG. 14 , we assume that a capacitor is disposed within a planar area of ​​an insulating film having a width of H = 13 × a height of V = 13, in which six trenches (length C = 11, aspect ratio = 2) are formed with a line-and-space ratio of 1:1. The trenches 20aa correspond to the recesses 20a ( FIG. 1 ) in the first embodiment. In this configuration, if MIM-structure capacitors are disposed continuously along the entire top surface of the insulating film and the inner walls of each trench 20aa, the total capacitor area [Tc1] is expressed as the sum of (1) the planar area and (2) the trench side wall area. In this case, the total capacitor area [Tc1] is 457. Note that (1) the planar area is the area of ​​the insulating film surface above the trenches 20aa, and includes the area of ​​the bottom of the trenches 20aa, as will be seen hereinafter.

[0037] 15 is a plan view illustrating the capacitor area of ​​a first example to which the first embodiment is applied, in which lateral grooves 20b are formed on the side walls of trenches 20aa in the configuration shown in FIG. The width [W1] of lateral grooves 20b is set to 0.3. In this case, the total capacitor area [T1] is expressed as the sum of (1) the area of ​​the flat surface, (2) the area of ​​the trench side walls, and (4) the additional area per lateral groove.

[0038] The total capacitor area [T1] in this case is as shown in Figure 15. When the number of lateral grooves is three, the conventional ratio is 1.60 and the planar ratio is 4.31. It can be seen that the ratio increases as the number of lateral grooves increases, and the effect of increasing the total capacitor area [T1] is significant. The conventional ratio is the total capacitor area [T1] relative to the total capacitor area [Tc1] in the conventional structure shown in Figure 14. The planar ratio is the total capacitor area [T1] relative to the case where the capacitor is formed flat (i.e., the planar area (1)), and the same applies hereinafter. In addition, since the side wall area in the structure of the first embodiment is expanded at the position of the lateral grooves, the capacitor area becomes even larger, and this also applies hereinafter.

[0039] 16 is a plan view illustrating the capacitor area of ​​a second example to which the first embodiment is applied. In this example, three trenches (length C=11, aspect ratio=2) are formed in a line-and-space ratio of 1:3 within a plane area of ​​width H=13×length V=13 in an insulating film, and lateral grooves 20b are formed on the side walls of trenches 20aa. The width [W1] of lateral grooves 20b is 1.

[0040] In this case, the total capacitor area [T2] is as shown in FIG. 16. When the number of lateral grooves is three, the conventional ratio is 1.79 and the planar ratio is 4.83. It can be seen that the ratio increases as the number of lateral grooves increases, and the effect of expanding the total capacitor area [T2] is significant.

[0041] FIG. 17 is a plan view illustrating the capacitor area of ​​another conventional structure for comparison with the semiconductor device of the first embodiment. In FIG. 17 , we assume a configuration in which 6×6 holes (aspect ratio 2) with a diameter d=1 are formed in an insulating film with a hole-and-space ratio of 1:1 within a plane area of ​​width H=13×length V=13, and capacitors are arranged in the insulating film. Holes 20ab correspond to recesses 20a ( FIG. 1 ) in the first embodiment. In this configuration, if MIM-structure capacitors are arranged continuously along the entire top surface of the insulating film and the inner walls of each hole 20ab, the total capacitor area [Tc2] is expressed as the sum of (1) the planar area and (2) the hole-side peripheral wall area. In this case, the total capacitor area [Tc2] is 395. Note that (1) the planar area is the area of ​​the insulating film surface above holes 20ab, and includes the area of ​​the bottom of holes 20ab, as will be seen hereinafter.

[0042] 18 is a plan view illustrating the capacitor area of ​​a third example to which the first embodiment is applied, in which lateral grooves 20b are formed on the side walls of holes 20ab in the configuration shown in FIG. The width [W1] of lateral grooves 20b is 0.3. In this case, the total capacitor area [T3] is expressed as the sum of (1) the area of ​​the flat portion, (2) the area of ​​the hole-side periphery wall, and (4) the additional area per lateral groove, as will be the case hereinafter.

[0043] In this case, the total capacitor area [T3] is as shown in Figure 18. When the number of lateral grooves is three, the conventional ratio is 1.67 and the planar ratio is 3.91. It can be seen that the ratio increases as the number of lateral grooves increases, and the effect of increasing the total capacitor area [T3] is significant. Note that the conventional ratio is the total capacitor area [T3] relative to the total capacitor area [Tc2] in the conventional structure shown in Figure 17. The planar ratio is the total capacitor area [T3] relative to the case where the capacitor is formed flat (i.e., the planar area (1)), and the same applies hereinafter.

[0044] 19 is a plan view illustrating the capacitor area of ​​a fourth example to which the first embodiment is applied. In this example, 3 × 3 holes (aspect ratio = 3) with a diameter d = 1 and a hole-and-space ratio of 1:3 are formed in a plane area of ​​an insulating film with a width H = 13 × a height V = 13, and horizontal grooves 20 b are formed on the side walls of holes 20 ab. The width [W1] of horizontal groove 20 b is 1.

[0045] The total capacitor area [T4] in this case is as shown in Figure 19. When the number of lateral grooves is three, the conventional ratio is 1.5 and the planar ratio is 3.51. It can be seen that the ratio increases as the number of lateral grooves increases, and the effect of expanding the total capacitor area [T4] is significant.

[0046] 20 is a plan view illustrating the capacitor area of ​​a fifth example to which the first embodiment is applied. In this example, 6 × 6 holes (aspect ratio = 3) with a diameter d = 1 are formed in a plane area of ​​an insulating film with a width H = 13 × height V = 13, with a hole-and-space ratio of 1:1. Lateral grooves 20 b are formed on the side walls of holes 20 ab. The width [W1] of the lateral grooves 20 b is 1.

[0047] In this case, the total capacitor area [T5] is as shown in Fig. 20. When the number of lateral grooves is three, the conventional ratio is 1.52 and the planar ratio is 4.57. It can be seen that the ratio increases as the number of lateral grooves increases, and the effect of enlarging the total capacitor area [T5] is high. Here, the conventional ratio refers to the total capacitor area [T5] relative to the total capacitor area when the aspect ratio of the hole 20ab in the conventional structure shown in Fig. 17 is 3.

[0048] Second Embodiment Configuration of Semiconductor Device of Second Embodiment Fig. 21 is a cross-sectional view of a main portion of a semiconductor device 2 according to a second embodiment. The semiconductor device 2 shown in Fig. 21 differs from the semiconductor device 1 of the first embodiment described with reference to Fig. 1 in that a stopper groove 20a' is provided in the interlayer insulating film 20. Since the other configuration is the same as that of the semiconductor device 1 of the first embodiment, only the configuration of the stopper groove 20a' will be described here, and a description of the other configuration will be omitted.

[0049] Stopper groove 20a' is formed in interlayer insulating film 20 so as to surround lateral groove 20b formed by receding the side wall of recess 20a. The inner wall of stopper groove 20a' is covered with insulating film 201'. In lateral groove 20b formed in the side wall of recess 20a, second insulating film 202 is removed to expose insulating film 201', and lower electrode layer 301 of capacitor 30 arranged along lateral groove 20b is arranged in contact with insulating film 201'.

[0050] In this configuration, the capacitor 30 is disposed continuously from the upper surface of the interlayer insulating film 20 through the insulating film 201' along the inner wall of the stopper groove 20a'.

[0051] The stopper groove 20a' may be provided integrally between adjacent recesses 20a, which allows the arrangement density of the capacitors 30 to be improved.

[0052] FIG. 22 is a plan view of a capacitor 30 of a semiconductor device according to the second embodiment. As shown in FIG. 22 , when the recess 20 a is trench-shaped, a stopper groove 20 a ′ is provided around the outer periphery of a lateral groove 20 b extending outward from the entire periphery of the trench-shaped recess 20 a, surrounding the entire periphery of the lateral groove 20 b. As shown in the figure, the stopper groove 20 a ′ may be shared between adjacent recesses 20 a. The capacitor 30 is provided to cover the upper surface of the interlayer insulating film 20, the inner wall of the trench-shaped recess 20 a including the lateral groove 20 b, and the inner wall of the stopper groove 20 a ′. Note that FIG. 21 corresponds to the A-A cross section of FIG. 22 , as an example.

[0053] 23 is a plan view showing another example of a capacitor 30 of a semiconductor device according to the second embodiment. As shown in FIG. 23 , even when the recess 20a is hole-shaped, a stopper groove 20a' is provided on the outer periphery of a lateral groove 20b extending outward from the entire periphery of the hole-shaped recess 20a, so as to surround the entire periphery of the lateral groove 20b. The stopper groove 20a' may be shared between adjacent recesses 20a. The capacitor 30 is provided so as to cover the upper surface of the interlayer insulating film 20, the inner wall of the hole-shaped recess 20a including the lateral groove 20b, and the inner wall of the stopper groove 20a'.

[0054] 24 to 30 are process diagrams (parts 1) to (part 7) illustrating a method for manufacturing the semiconductor device 2 according to the second embodiment. The detailed configuration of the semiconductor device 2 described above will be described below in accordance with the manufacturing process sequence shown in FIGS.

[0055] 24, an interlayer insulating film 20 is formed by alternately depositing first insulating films 201 and second insulating films 202 that enable etching with a high selectivity relative to the first insulating film 201 on an underlying insulating film 100 that exposes the underlying conductive pattern 10 on its surface. As an example, the underlying conductive pattern 10 is, for example, a copper (Cu) wiring, and the underlying insulating film 100 is, for example, made of SiCOH.

[0056] Here, four layers of first insulating films 201 and three layers of second insulating films 202 are alternately formed so that the bottom and top layers of the interlayer insulating film 20 are the first insulating films 201. In this case, for example, a SiCN film is formed as the first insulating film 201. Also, a SiO ２ Form a film.

[0057] 25, a resist pattern 71 is formed on the interlayer insulating film 20 by lithography. Thereafter, the interlayer insulating film 20 is etched using the resist pattern 71 as a mask to form a stopper groove 20a' that surrounds the entire periphery of a region where a recess 20a (see FIG. 21) having uneven side walls is to be formed. This etching is carried out until the first insulating film 201 that constitutes the bottom layer of the interlayer insulating film 20 is exposed, thereby forming the stopper groove 20a' with the first insulating film 201 exposed at the bottom. This etching is carried out by anisotropic etching using, for example, fluorine gas.

[0058] Thereafter, the resist pattern 71 is completely removed by an ashing process using oxygen plasma and a cleaning process using wet etching.

[0059] 26, a thin insulating film 201' is formed on the entire exposed surface of the interlayer insulating film 20, including the inner wall of the stopper groove 20a'. This insulating film 201' may be made of the same material as the first insulating film 201 that forms the uppermost layer of the interlayer insulating film 20, such as a SiCN film.

[0060] 27, a resist pattern 72 is formed on the interlayer insulating film 20 via the insulating film 201' by lithography. Thereafter, the insulating film 201' and the interlayer insulating film 20 are etched using the resist pattern 72 as a mask to form a trench-shaped or hole-shaped recess 20a in the center of the stopper groove 20a'. This etching is performed until the first insulating film 201, which constitutes the bottom layer of the interlayer insulating film 20, is exposed, forming the recess 20a with the first insulating film 201 exposed at the bottom. This etching is performed by anisotropic etching using, for example, fluorine gas. As a result, the side walls of the stopper groove 20a' are covered with the insulating film 201', while the side walls of the recess 20a are exposed from the interlayer insulating film 20.

[0061] Thereafter, the resist pattern 72 is completely removed by an ashing process using oxygen plasma and a cleaning process using wet etching.

[0062] 28, the second insulating film 202 is selectively etched away from the insulating film 201' and the first insulating film 201, thereby forming a lateral groove 20b on the side wall of the recess 20a. At this time, the insulating film 201' and the first insulating film 201 made of SiCN are used as an etching stopper, and the SiO ２ The second insulating film 202 made of a film is selectively etched away. As a result, the width [W1] of the lateral groove 20b in the surface direction of the interlayer insulating film 20 is not affected by the etching conditions of the second insulating film 202.

[0063] 29, a capacitor 30 having an MIM structure is formed along the inner wall of the recess 20a, including the uneven sidewalls formed by the lateral groove 20b, and along the exposed surfaces of the insulating film 201' and interlayer insulating film 20, including the inner wall of the stopper groove 20a'. The procedure for forming the capacitor 30 may be the same as that described in the first embodiment with reference to FIGS. 8 to 11. In this manner, the capacitor 30 is formed in which a lower electrode layer 301 made of a TiN film, an insulating layer 302 made of a high-dielectric-constant (High-k) film such as hafnium oxide (HfOx), and an upper electrode layer 303 made of TiN are stacked in this order.

[0064] 30, a buried insulating film 41 is formed on the entire surface of the insulating film 201′ via the capacitor 30, and the recess 20a, the lateral groove 20b, and the stopper groove 20a′ are filled with the buried insulating film 41. At this time, silicon oxide (SiO ２ The procedure for forming the buried insulating film 41 made of SiO 2 is the same as that described with reference to FIG. 12 in the first embodiment.

[0065] Thereafter, the same procedures as those described in the first embodiment with reference to FIGS. 13 and 1 are carried out to obtain the semiconductor device 2 according to the second embodiment shown in FIG.

[0066] Effect of the Second Embodiment In the second embodiment described above, by providing the MIM-structure capacitor 30 along the recess 20a having the uneven side walls, it is possible to increase the capacitor capacitance without increasing the chip size and the capacitor's occupied area, as in the first embodiment. Furthermore, by covering the inner wall of the stopper groove 20a' surrounding the entire periphery of the recess 20a with the insulating film 201' and exposing the insulating film 201' on the inner wall of the lateral groove 20b of the recess 20a, it is not necessary to provide a margin for the width [W1] of the lateral groove 20b. Moreover, since the capacitor 30 is also disposed on the inner wall of the stopper groove 20a', it is possible to increase the capacitor capacitance while preventing an increase in the occupied area even more than in the first embodiment.

[0067] The present invention is not limited to the above-described embodiments and modifications, and includes various other modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0068] REFERENCE SIGNS LIST 1, 2...Semiconductor device 10...Lower layer conductive pattern 20...Interlayer insulating film 20a...Recess 20a'...Stopper groove 20b...Horizontal groove 30...Capacitor 40...Via 41...Buried insulating film 50...Upper layer conductive pattern 51...Upper layer conductive pattern 52...Upper layer conductive pattern 201...First insulating film 201'...Insulating film 202...Second insulating film 301...Lower electrode layer 302...Insulating layer 303...Upper electrode layer

Claims

1. A semiconductor device comprising: an interlayer insulating film having a multilayer structure in which a first insulating film and a second insulating film that enables etching with a high selectivity relative to the first insulating film are repeatedly stacked; a lower layer conductive pattern and an upper layer conductive pattern arranged above and below the interlayer insulating film; and a capacitor configured by continuously stacking a lower electrode layer, an insulating layer, and an upper electrode layer in this order from the upper surface of the interlayer insulating film along the inner wall of a recess provided in the interlayer insulating film, wherein the side walls of the recess have an uneven shape including the inner wall of a lateral groove formed in the second insulating film, and the capacitor is arranged on the side walls of the recess along the uneven shape.

2. The semiconductor device according to claim 1, wherein a first via and a second via that connect the lower conductive pattern and the upper conductive pattern are provided through the interlayer insulating film, the first via being connected to the lower electrode layer, and the second via being connected to the upper electrode layer.

3. The semiconductor device according to claim 1, wherein a buried insulating film is provided on the entire surface of said interlayer insulating film, closing the opening of said recess with said capacitor interposed therebetween.

4. The semiconductor device according to claim 1, further comprising: a stopper groove formed in the interlayer insulating film on the outer periphery of the concave portion having the uneven shape in which the capacitor is formed; and an insulating film covering the inner wall of the stopper groove; and in a lateral groove provided on the side wall of the concave portion, the second insulating film is removed to expose the insulating film.

5. The semiconductor device according to claim 4, wherein the capacitor is disposed continuously from the upper surface of the interlayer insulating film along the inner wall of the stopper groove.

6. The semiconductor device according to claim 5, wherein a plurality of said recesses are arranged in said interlayer insulating film, and said stopper grooves are integrated between adjacent said recesses.

7. A method for manufacturing a semiconductor device, comprising the steps of: forming an interlayer insulating film having a multilayer structure in which first insulating films and second insulating films are repeatedly stacked on a layer having a lower conductive pattern; forming a recess in the interlayer insulating film; forming a lateral groove in the side wall of the recess by setting the second insulating film back relative to the first insulating film, thereby making the side wall of the recess uneven; forming a capacitor having a configuration in which a lower electrode layer, an insulating layer, and an upper electrode layer are stacked in this order from the top surface of the interlayer insulating film along an inner wall including the uneven side wall and bottom surface of the recess; and forming an upper conductive pattern above the interlayer insulating film.

8. A method for manufacturing a semiconductor device according to claim 7, further comprising the step of forming a buried insulating film over the entire surface of the interlayer insulating film to close the recess via the capacitor after the step of forming the capacitor, and in the step of forming the upper layer conductive pattern, the upper layer conductive pattern is formed above the interlayer insulating film via the buried insulating film.

9. A method of manufacturing a semiconductor device according to claim 7, comprising the steps of: before the step of forming the recess, forming a stopper groove in the interlayer insulating film so as to surround the entire periphery of an area where the recess is to be formed, the stopper groove having the uneven side walls; and forming an insulating film on the inner walls of the stopper groove and the entire surface of the interlayer insulating film, wherein in the step of forming the recess, the recess is formed in the insulating film and the interlayer insulating film; and in the step of making the side walls of the recess uneven, a lateral groove is formed by receding the second insulating film with respect to the first insulating film by etching using the insulating film as a stopper.

10. The method for manufacturing a semiconductor device according to claim 7, wherein in the step of forming the capacitor, the lower electrode layer, the insulating layer, and the upper electrode layer are formed by atomic layer deposition.

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