Semiconductor device

Abstract

Provided is a semiconductor device that comprises a semiconductor substrate, a plurality of trench portions, a plurality of mesa portions, an emitter electrode, and an interlayer insulating film in which a contact hole is formed. The plurality of mesa portions include: a channel mesa portion having a first conductivity-type emitter region provided on an upper surface of the semiconductor substrate and a second conductivity-type base region provided between the emitter region and a drift region, and connected to the emitter electrode by the contact hole; and a floating mesa portion in which the contact hole is not provided above or the length of the contact hole above is shorter than the length of the contact hole above the channel mesa portion. A second trench bottom region of a second conductivity type having a concentration higher than that of the base region is provided at a lower end of at least one of the trench portions sandwiching the channel mesa portion.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Conventionally, semiconductor devices provided with transistors such as insulated gate bipolar transistors (IGBTs) have been known (see, for example, Patent Documents 1 and 2). [Prior art documents] [Patent Documents] [Patent Document 1] International Publication No. 2015 / 022989 [Patent Document 2] Japanese Patent Laid-Open No. 2019-91892 General disclosure

[0003] (Problem to be Solved) In a semiconductor device, it is preferable to reduce turn-on loss. (Means for Solving the Problem)

[0004] In order to solve the above problem, one aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and including a first conductivity type drift region, a plurality of trenches extending from the upper surface toward the interior of the semiconductor substrate in an extension direction, a plurality of mesa regions sandwiched between two of the trenches, an emitter electrode provided above the upper surface of the semiconductor substrate, and an interlayer insulating film provided between the upper surface of the semiconductor substrate and the emitter electrode, with a contact hole formed therein. In any of the above semiconductor devices, the plurality of mesa regions may include a channel mesa portion having an emitter region of the first conductivity type provided on the upper surface of the semiconductor substrate and a base region of a second conductivity type provided between the emitter region and the drift region, and connected to the emitter electrode by the contact hole. In any of the semiconductor devices described above, the plurality of mesa portions may include floating mesa portions that do not have the contact hole provided thereover or that have a length of the contact hole provided thereover in the extension direction that is shorter than a length of the contact hole provided thereover in the channel mesa portion. In any of the semiconductor devices described above, a second trench bottom region of the second conductivity type having a higher concentration than the base region may be provided at a lower end of at least one of the trench portions sandwiching the channel mesa portion.

[0005] In any of the above semiconductor devices, the second trench bottom region may not be provided in at least some of the floating mesa portions.

[0006] In any of the above semiconductor devices, the second trench bottom region may be provided across the entire width of at least a portion of the channel mesa portion.

[0007] In any of the above semiconductor devices, the trench portion may have a gate trench portion and a dummy trench portion. In any of the above semiconductor devices, the plurality of mesa portions may include a second mesa portion sandwiched between the gate trench portion and the dummy trench portion. In any of the above semiconductor devices, at least a portion of the second mesa portion may be a channel mesa portion.

[0008] In any of the above semiconductor devices, the second trench bottom region may be provided at a lower end of the dummy trench portion.

[0009] In any of the above semiconductor devices, the trench portion may have a plurality of the dummy trench portions. In any of the above semiconductor devices, the plurality of mesa portions may include a third mesa portion sandwiched between two of the dummy trench portions. In any of the above semiconductor devices, at least a portion of the third mesa portion may be the floating mesa portion.

[0010] In any of the above semiconductor devices, the trench portion may have a plurality of gate trench portions. In any of the above semiconductor devices, the plurality of mesa portions may include a first mesa portion sandwiched between two of the gate trench portions. In any of the above semiconductor devices, at least a portion of the first mesa portion may be the floating mesa portion.

[0011] In any of the above semiconductor devices, the trench portion may have a plurality of gate trench portions. In any of the above semiconductor devices, the plurality of mesa portions may include a first mesa portion sandwiched between two of the gate trench portions. In any of the above semiconductor devices, at least a portion of the first mesa portion may be the channel mesa portion.

[0012] In any of the above semiconductor devices, the trench portion may have a dummy trench portion. In any of the above semiconductor devices, the plurality of mesa portions may include a second mesa portion sandwiched between the gate trench portion and the dummy trench portion. In any of the above semiconductor devices, at least a portion of the second mesa portion may be the floating mesa portion.

[0013] In any of the above semiconductor devices, the trench portion may have a plurality of the dummy trench portions. In any of the above semiconductor devices, the plurality of mesa portions may include a third mesa portion sandwiched between two of the dummy trench portions. In any of the above semiconductor devices, at least a portion of the third mesa portion may be the floating mesa portion.

[0014] In any of the above semiconductor devices, the second trench bottom region may be provided in the floating mesa portion located adjacent to the channel mesa portion.

[0015] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions.

[0016] 3A to 3C are diagrams showing turn-on waveforms of the semiconductor device 100 according to the example and the semiconductor device 200 according to the comparative example; 3B is a diagram showing Eon-dV / dt characteristics of the semiconductor device 100 shown in FIGS. 3A to 3C and the semiconductor device 200 according to the comparative example; 3C is a diagram showing Eoff-Vce(sat) characteristics of the semiconductor device 100 shown in FIGS. 3A to 3C and the semiconductor device 200 according to the comparative example; 3D is a diagram showing Eon-dV / dt characteristics of the semiconductor device 100 shown in FIGS. 3A to 3C and the semiconductor device 200 according to the comparative example; 3D is a diagram showing Eoff-Vce(sat) ... 7A is a top view showing an example of the active portion 120 of the semiconductor device 100 of FIG. 7A. FIG. 7A is a top view showing an example of the termination portion 122 of the semiconductor device 100 of FIG. 7A. FIG. 8A is a cross-sectional view showing another example of the semiconductor device 100 according to an embodiment of the present invention. FIG. 8A is a top view showing an example of the active portion 120 of the semiconductor device 100 of FIG. 8A. FIG. 8A is a top view showing an example of the termination portion 122 of the semiconductor device 100 of FIG. 8A. FIG. 8A is a diagram showing turn-on waveforms of the semiconductor device 100 of the example and the semiconductor device 200 of the comparative example ... Eon-dV / dt characteristics of the semiconductor device 100 shown in FIGS. 8A to 8C and the semiconductor device 200 according to the comparative example. FIG. 11A is a cross-sectional view showing another example of the semiconductor device 100 according to an embodiment of the present invention. FIG. 11A is a top view showing an example of the active portion 120 of the semiconductor device 100 of FIG. 11A. FIG. 11A is a top view showing an example of the termination portion 122 of the semiconductor device 100 of FIG. 11B is a diagram showing Eon-dV / dt characteristics of the semiconductor device 100 shown in FIGS. 11A to 11C and the semiconductor device 200 according to the comparative example. FIG.

[0017] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0018] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0019] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0020] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0021] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0022] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0023] In this specification, the conductivity type of a doped region doped with impurities is described as p-type or n-type. Sometimes, n-type conductivity is referred to as the first conductivity type and p-type conductivity is referred to as the second conductivity type, but the corresponding conductivity types may be reversed. In this specification, impurities may particularly refer to either n-type donors or p-type acceptors, and may be referred to as dopants. In this specification, doping refers to introducing donors or acceptors into a semiconductor substrate to form a semiconductor exhibiting n-type conductivity or a semiconductor exhibiting p-type conductivity.

[0024] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N Ｄ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0025] In this specification, when p+ type or n+ type is described, it means that the doping concentration is higher than that of p type or n type, and when p- type or n- type is described, it means that the doping concentration is lower than that of p type or n type. Furthermore, when p++ type or n++ type is described in this specification, it means that the doping concentration is higher than that of p+ type or n+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0026] 1A is a cross-sectional view showing an example of a semiconductor device 100 according to an embodiment of the present invention. In this specification, an example will be described in which the semiconductor device 100 is provided with an IGBT (Insulated Gate Bipolar Transistor) as a transistor element. However, the semiconductor device 100 may also be provided with a MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor). In FIG. 1A, only some components of the semiconductor device 100 are shown, and other components are omitted.

[0027] The semiconductor device 100 includes a semiconductor substrate 10, an interlayer insulating film 38, and an emitter electrode 52. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an upper surface 21. FIG. 1A shows the configuration of the upper surface 21 side of the semiconductor substrate 10, and does not show the lower surface side.

[0028] The interlayer insulating film 38 is provided between the upper surface 21 of the semiconductor substrate 10 and the emitter electrode 52. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. A contact hole 54 is formed in the interlayer insulating film 38. The contact hole 54 is a through-hole that penetrates the interlayer insulating film 38.

[0029] The emitter electrode 52 is provided above the upper surface 21 of the semiconductor substrate 10. In this example, the emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is connected to the upper surface 21 of the semiconductor substrate 10 via a contact hole 54. The emitter electrode 52 is, for example, an aluminum-silicon alloy.

[0030] An n-type drift region 18 is provided in the semiconductor substrate 10. The drift region 18 may be a region that remains without doping the semiconductor substrate 10. Although not shown, a collector region of a second conductivity type is provided on the lower surface side of the semiconductor substrate 10 in contact with the lower surface. A collector electrode is also provided in contact with the collector region. A field stop layer (FS layer) of a first conductivity type having a higher impurity concentration than the drift region 18 may be provided between the drift region 18 and the collector region.

[0031] The semiconductor substrate 10 has a plurality of trenches extending from the upper surface 21 of the semiconductor substrate 10 toward the interior thereof. The trenches may include gate trenches 40 and dummy trenches 30. The gate trenches 40 are trenches to which a gate voltage is applied. The dummy trenches 30 are connected to an emitter electrode 52 in other cross sections. In FIG. 1A and subsequent figures, the gate trenches are indicated as G and the dummy trenches are indicated as E. In FIG. 1A, the trenches are hatched.

[0032] The trench portion in this example has a plurality of gate trench portions 40 and a plurality of dummy trench portions 30. The trench portions are arranged in an arrangement direction (X-axis direction) and extend in an extension direction (Y-axis direction). In FIG. 1A, three gate trench portions 40 and four dummy trench portions are arranged periodically.

[0033] A mesa portion 60 is provided between each trench portion in the arrangement direction. The mesa portion 60 refers to a region inside the semiconductor substrate 10 that is sandwiched between two trench portions. As an example, the upper end of the mesa portion 60 is the upper surface 21 of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion 60 is provided on the upper surface 21 of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench portion.

[0034] The semiconductor substrate 10 of this example is provided with a plurality of mesas 60. The plurality of mesas 60 include a channel mesa 60-1, a floating mesa 60-2, and a hole-punching mesa 60-3.

[0035] The channel mesa portion 60-1 has an n+ type emitter region 12 and a p-type base region 14. The emitter region 12 and the base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. The channel mesa portion 60 may also be provided with an n+ type accumulation region 16. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0036] The emitter region 12 is a first conductivity type region provided on the upper surface 21 of the semiconductor substrate 10. The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the channel mesa portion 60-1. The emitter region 12 has a higher doping concentration than the drift region 18.

[0037] The base region 14 is a region of the second conductivity type provided between the emitter region 12 and the drift region 18. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the channel mesa portion 60-1.

[0038] The accumulation region 16 is a first conductivity type region provided between the base region 14 and the drift region 18. The accumulation region 16 is an n+ type region with a higher doping concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the collector-emitter saturation voltage Vce(sat) can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in the channel mesa portion 60.

[0039] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0040] The gate trench portion 40 may be provided to be longer in the depth direction than the base region 14. The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40. As a result, a main current flows between the emitter electrode 52 and the collector electrode (not shown).

[0041] The dummy trench portion 30 may have a structure similar to that of the gate trench portion 40 in the cross section. That is, the dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52 in another cross section. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0042] In this example, the gate trench 40 and the dummy trench 30 are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench 30 and the gate trench 40 may have a downwardly convex curved shape (a curved shape in cross section). In this specification, the depth position of the lower end 46 of the gate trench 40 is designated Zt. The depth position of the lower end 46 of the gate trench 40 may be the same as the depth position of the lower end 36 of the dummy trench 30.

[0043] The channel mesa portion 60-1 is connected to the emitter electrode 52 via a contact hole 54. The channel mesa portion 60-1 may be a mesa portion 60 that is connected to the emitter electrode 52, has an emitter region 12 provided therein, and at least one of the trench portions sandwiching the mesa portion 60 is a gate trench portion 40. The channel mesa portion 60-1 may be sandwiched between two gate trench portions 40.

[0044] The floating mesa portion 60-2 has a base region 14 and an accumulation region 16. The floating mesa portion 60-2 may or may not have an emitter region 12. In this example, two floating mesa portions 60-2 are provided consecutively adjacent to the channel mesa portion 60-1.

[0045] The floating mesa portion 60-2 does not have a contact hole 54 above it, or the length of the contact hole 54 above it in the extension direction (Y-axis direction) is shorter than the length of the contact hole 54 above the channel mesa portion 60-1. In the cross section shown in Figure 1A, no contact hole 54 is provided above the floating mesa portion 60-2. By providing the floating mesa portion 60-2, the IE effect can be promoted and Vce(sat) can be reduced.

[0046] The hole extraction mesa portion 60-3 has a base region 14 and an accumulation region 16. The hole extraction mesa portion 60-3 may or may not have an emitter region 12. The hole extraction mesa portion 60-3 of this example is provided next to the floating mesa portion 60-2.

[0047] The hole extraction mesa portion 60-3 is a mesa portion 60 in which no channel is formed and which is connected to the emitter electrode 52 via a contact hole 54. The hole extraction mesa portion 60-3 extracts holes injected from the lower surface side when the semiconductor device 100 is turned on. The hole extraction mesa portion 60-3 may be a mesa portion 60 which is connected to the emitter electrode 52 and which does not have an emitter region 12. The hole extraction mesa portion 60-3 may be a mesa portion which is connected to the emitter electrode 52 and which is sandwiched between dummy trench portions 30.

[0048] The multiple mesas 60 may include at least one of a channel mesa 60-1, a floating mesa 60-2, and a hole-punching mesa 60-3, or may include any two of them. The semiconductor device 100 of this example has one channel mesa 60-1, two floating mesa 60-2, and one hole-punching mesa 60-3 periodically arranged.

[0049] The semiconductor device 100 of this example includes a second trench bottom region 204 of a second conductivity type provided at the lower end of the trench portion. The second trench bottom region 204 is a p-type region with a higher concentration than the base region 14. The second trench bottom region 204 may be provided at the lower end of at least one of the trench portions that sandwich the channel mesa portion 60-1. In FIG. 1A , the second trench bottom region 204 is provided at the lower end 46 of one of the gate trench portions 40 that sandwich the channel mesa portion 60-1. Specifically, the second trench bottom region 204 is provided at the lower end 46 of the gate trench portion 40 that is located at the boundary between the channel mesa portion 60-1 and the floating mesa portion 60-2.

[0050] The lower end 46 of the gate trench portion 40 refers to the portion of the gate trench portion 40 that is farthest from the upper surface 21 of the semiconductor substrate 10. In the example of FIG. 1A , the lower end 46 of the gate trench portion 40 is disposed at the center of the gate trench portion 40 in the X-axis direction. Furthermore, the lower end 36 of the dummy trench portion 30 refers to the portion of the dummy trench portion 30 that is farthest from the upper surface 21 of the semiconductor substrate 10. In the example of FIG. 1A , the lower end 36 of the dummy trench portion 30 is disposed at the center of the dummy trench portion 30 in the X-axis direction.

[0051] The provision of the second trench bottom region 204 increases the gate-collector capacitance Cgc. As a result, the time change (dVce / dt) of the collector-emitter voltage Vce at turn-on is gradual, which reduces the gate resistance Rg when the magnitude of dVce / dt is made uniform, thereby reducing turn-on loss. Furthermore, the provision of the second trench bottom region 204 can alleviate the electric field at the bottom end 46 of the gate trench portion 40.

[0052] At least a portion of the second trench bottom region 204 may be located at a position overlapping the lower end of the trench portion in a top view and may be located below the lower end in the Z-axis direction. The second trench bottom region 204 may include a portion that does not overlap with the lower end in a top view. The second trench bottom region 204 may include a portion that is located above the lower end. The second trench bottom region 204 is in contact with the lower end. In the example of FIG. 1A , the second trench bottom region 204 is in contact with the entire curved portion of the gate trench portion 40, including the lower end 46.

[0053] The second trench bottom region 204 may be formed by implanting a p-type dopant near the bottom end of the trench structure after forming the trench structure and before forming the conductive portion. However, among the three gate trench portions 40 arranged in succession, the bottom end 46 of the central gate trench portion 40 does not need to be implanted with a p-type dopant.

[0054] The second trench bottom region 204 is electrically floating with respect to electrodes such as the emitter electrode 52, the gate conductive portion 44, and the collector electrode. At least one of an n-type region and an insulating film is disposed between the second trench bottom region 204 and the electrode. In other words, the second trench bottom region 204 and the electrode are not connected only by a p-type region and a conductive material. The doping concentration of the second trench bottom region 204 is, for example, 1×10 １５ cm －３ That's it, 1 x 10 １７ cm －３ The following is the result.

[0055] The second trench bottom region 204 may be located apart from the base region 14 and the accumulation region 16. In this example, the drift region 18 is provided between the second trench bottom region 204 and the accumulation region 16 in the depth direction.

[0056] The semiconductor device 100 has one or more second trench bottom regions 204. The semiconductor device 100 may have multiple second trench bottom regions 204. In the semiconductor device 100 of this example, the second trench bottom regions 204 are provided at the lower ends 46 of the two outer gate trench portions 40 that sandwich two adjacent channel mesa portions 60-1. The multiple second trench bottom regions 204 do not need to be in contact with each other.

[0057] The second trench bottom region 204 may be provided in at least one trench portion of the semiconductor device 100, or in 10% or more of the trench portions, or in 20% or more of the trench portions. The second trench bottom region 204 may be provided in 50% or less of the trench portions of the semiconductor device 100.

[0058] If a trench portion having a second trench bottom region 204 at its lower end is defined as a corresponding trench portion, each second trench bottom region 204 may or may not extend to below the lower end of the trench portion (in this example, the gate trench portion 40 and the dummy trench portion 30) arranged adjacent to the corresponding trench portion. Each second trench bottom region 204 may or may not contact the adjacent trench portion.

[0059] The second trench bottom region 204 may be provided in at least a portion of the channel mesa portions 60-1. The second trench bottom region 204 may be provided over the entire width direction (X-axis direction) of at least a portion of the channel mesa portions 60-1. The second trench bottom region 204 may be provided in at least a portion of the floating mesa portions 60-2. The second trench bottom region 204 may be provided over the entire width direction (X-axis direction) of at least a portion of the floating mesa portions 60-2.

[0060] However, at least some of the floating mesas 60-2 may not be provided with the second trench bottom region 204. At least some of the channel mesas 60-1 may not be provided with the second trench bottom region 204. At least some of the hole-punched mesas 60-3 may not be provided with the second trench bottom region 204.

[0061] The mesa portion 60 adjacent to the channel mesa portion 60-1 across the gate trench portion 40 may be a floating mesa portion 60-2. The floating mesa portion 60-2 may be sandwiched between the gate trench portion 40 and the dummy trench portion 30 (GE-floating in the figure). This reduces the gate-emitter capacitance Cge and increases the gate-collector capacitance Cgc. As a result, as with the above, dVce / dt becomes gentler, reducing the gate resistance Rg when the magnitude of dVce / dt is uniform, thereby reducing turn-on loss. Furthermore, since dI / dt at turn-on increases, the drop in Vce due to L (circuit inductance)·dI / dt increases. This also reduces turn-on loss. A second trench bottom region 204 may be provided in the floating mesa portion 60-2.

[0062] The mesa 60 adjacent to the floating mesa 60-2 and provided on the opposite side to the channel mesa 60-1 may be the floating mesa 60-2. The floating mesa 60-2 may be sandwiched between two dummy trenches (EE floating in the figure). This enhances the IE effect and reduces Vce(sat).

[0063] The semiconductor device 100 may include a first trench bottom region 202 of a first conductivity type provided at the lower end of the trench portion. The first trench bottom region 202 is an n-type region with a higher concentration than the drift region 18. The first trench bottom region 202 may be provided at the lower end of at least one of the trench portions sandwiching the hole extraction mesa portion 60-3. In FIG. 1A , the first trench bottom region 202 is provided at the lower end 36 of each of the two dummy trench portions 30 that sandwich the hole extraction mesa portion 60-3. Specifically, the first trench bottom region 202 is provided at the lower end 36 of the dummy trench portion 30 located at the boundary between the floating mesa portion 60-2 and the hole extraction mesa portion 60-3.

[0064] When the semiconductor device 100 is turned on, holes flow from the lower surface toward the upper surface 21. Because the channel mesa portion 60-1 is subjected to the gate voltage of the gate trench portion 40, holes are less likely to flow toward the channel mesa portion 60-1 and more likely to flow toward the hole extraction mesa portion 60-3. By providing the first trench bottom region 202 in the hole extraction mesa portion 60-3, holes are less likely to escape from the hole extraction mesa portion 60-3 and are more likely to accumulate. The accumulated holes generate a displacement current, which increases the gate voltage (self-charging), thereby making it possible to speed up the dI / dt at turn-on. As a result, the loss that occurs at turn-on can be reduced.

[0065] Similar to the second trench bottom region 204, the first trench bottom region 202 may be formed by implanting an n-type dopant near the bottom end of the trench structure after forming the trench structure and before forming the conductive portion. The doping concentration of the second trench bottom region 204 and the doping concentration of the first trench bottom region 202 may be the same. However, the first trench bottom region 202 does not necessarily have to be provided.

[0066] In this specification, the mesa portion 60 sandwiched between two gate trench portions 40 is referred to as a first mesa portion. Similarly, the mesa portion 60 sandwiched between the gate trench portion 40 and the dummy trench portion 30 is referred to as a second mesa portion, and the mesa portion 60 sandwiched between two dummy trench portions 30 is referred to as a third mesa portion. In other words, the multiple mesa portions 60 include a first mesa portion, a second mesa portion, and a third mesa portion.

[0067] At least a portion of the first mesa portion may be the channel mesa portion 60-1. A second trench bottom region 204 may be provided at the lower end of at least one of the trench portions sandwiching the channel mesa portion 60-1. All of the first mesa portions may be the channel mesa portion 60-1. The second trench bottom region 204 may be provided in at least a portion of the first mesa portions, and may be provided across the entire width direction (X-axis direction) of at least a portion of the first mesa portions. However, the first mesa portion does not have to be provided. In this case, at least a portion of the second mesa portion becomes the channel mesa portion 60-1.

[0068] At least a portion of the second mesa portion may be a floating mesa portion 60-2. When at least a portion of the above-described first mesa portion is a channel mesa portion 60-1, at least a portion of the second mesa portion may be a floating mesa portion 60-2. The second mesa portion provided adjacent to the first mesa portion may be a floating mesa portion 60-2 (GE floating). This makes it possible to reduce turn-on loss, as described above. All of the second mesa portions may be floating mesa portions 60-2. The second trench bottom region 204 may be provided in at least a portion of the second mesa portions, and may be provided across the entire width direction (X-axis direction) of at least a portion of the second mesa portions.

[0069] At least a portion of the third mesa portion may be a floating mesa portion 60-2. When at least a portion of the first mesa portion described above is a channel mesa portion 60-1 and at least a portion of the second mesa portion is a floating mesa portion 60-2, at least a portion of the third mesa portion may be a floating mesa portion 60-2. The third mesa portion provided adjacent to the second mesa portion may be a floating mesa portion 60-2 (EE floating). This enhances the IE effect and reduces Vce(sat). All of the third mesa portions may be floating mesa portions 60-2. However, the other third mesa portions may be in contact with the emitter electrode 52 via the contact hole 54. A portion of the third mesa portion may be a hole-punched mesa portion 60-3.

[0070] The floating mesa portion 60-2 located adjacent to the channel mesa portion 60-1 may be provided with the second trench bottom region 204. In any of the cases where at least a portion of the first mesa portion described above is the channel mesa portion 60-1, where at least a portion of the second mesa portion is the floating mesa portion 60-2, or where at least a portion of the third mesa portion is the floating mesa portion 60-2, or any combination of these cases, the floating mesa portion 60-2 located adjacent to the channel mesa portion 60-1 may be provided with the second trench bottom region 204.

[0071] 1B is a top view showing an example of an active portion 120 of the semiconductor device 100 according to the embodiment. The active portion 120 may be a region in the semiconductor device 100 through which a main current flows, and may be a portion located inside an emitter region 12 provided at the outermost position of a channel mesa portion 60-1 in the extension direction (Y-axis direction) of a trench portion (described later). FIG. 1B shows a portion of the active portion 120. The emitter electrode 52 and the interlayer insulating film 38 are also omitted.

[0072] The gate trench portion 40 and the dummy trench portion 30 extend in the extension direction. In addition to the emitter region 12, the channel mesa portion 60-1 is provided with a contact region 15. The contact region 15 is a p+ type region with a higher doping concentration than the base region 14. In this example, the emitter region 12 and the contact region 15 are provided alternately in the extension direction of the gate trench portion 40.

[0073] A contact hole 54 is provided above the channel mesa portion 60-1. In FIG. 1B, the position where the contact hole 54 is provided is hatched. The contact hole 54 above the channel mesa portion 60-1 may be provided so as to cross the active portion 120 in the extension direction. In this specification, the contact hole 54 above the channel mesa portion 60-1 may be referred to as a contact hole 54-1.

[0074] The base region 14 is exposed on the upper surface of the floating mesa portion 60-2. In the active portion 120, no contact hole 54 is provided above the floating mesa portion 60-2 in this example. The base region 14 is exposed on the upper surface of the hole-opening mesa portion 60-3. A contact hole 54 is provided above the hole-opening mesa portion 60-3. The contact hole 54 above the hole-opening mesa portion 60-3 may also be provided so as to cross the active portion 120 in the extension direction. In this specification, the contact hole 54 above the hole-opening mesa portion 60-3 may be referred to as a contact hole 54-3. Neither a contact region 15 nor an emitter region 12 is provided in the hole-opening mesa portion 60-3. The contact region 15 and the emitter region 12 may be provided in the hole-opening mesa portion 60-3.

[0075] 1C is a top view showing another example of the active portion 120 of the semiconductor device 100 according to the embodiment. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in FIG. 1B in the configurations of the floating mesa portion 60-2 and the hole-removing mesa portion 60-3. The hole-removing mesa portion 60-3 of this example is provided with a contact region 15.

[0076] In this example, a contact hole 54 is provided above the floating mesa portion 60-2. In this specification, the contact hole 54 above the floating mesa portion 60-2 may be referred to as a contact hole 54-2. The contact hole 54-2 is provided inside the emitter region 12 provided at the outermost position of the channel mesa portion 60-1 in the extension direction described below. In other words, the contact hole 54-2 is provided in the active portion 120. If the contact hole 54-2 is not provided above the floating mesa portion 60-2, the dI / dt may become too large. By providing the contact hole 54-2 above the floating mesa portion 60-2, the magnitude of dI / dt can be adjusted.

[0077] The length d1 of the contact hole 54-2 may be shorter than the length d2 of the contact hole 54-3. The floating mesa 60-2 in which the contact hole 54-2 is provided may be the second mesa or the third mesa.

[0078] At least a portion of the third mesa portion not adjacent to the second mesa portion may be provided with a contact hole 54 longer than the second mesa portion. In this example, the third mesa portion is the hole-opening mesa portion 60-3. The third mesa portion does not have to be the floating mesa portion 60-2. The length d2 of the contact hole 54-3 in the hole-opening mesa portion 60-3, which is the third mesa portion, may be longer than the length d1 of the contact hole 54-2 in the floating mesa portion 60-2, which is the second mesa portion. The phrase "length d2 being longer than length d1" may include the case where length d1 is zero (i.e., no contact hole 54-2 is provided). The same applies to the following length relationships. Length d1 may be half or less of length d2, or may be 10% or less, or may be 5% or less.

[0079] The length d1 may be shorter than the length d3 of the contact hole 54-1. The length d1 may be half or less of the length d3, 10% or less, or 5% or less. The lengths d2 and d3 may be equal. The contact holes 54-1 and 54-3 may extend further in the Y-axis direction than the active section 120 shown in FIGS. 1B and 1C. In this case, the ends of the lengths d2 and d3 are also located outside the active section 120 shown in FIGS. 1B and 1C.

[0080] At least one of the floating mesa portions 60-2 may be provided with a contact hole 54-2, while the other floating mesas 60-2 may not be provided with a contact hole 54-2. Furthermore, a plurality of contact holes 54-2 may be provided in the extension direction of the same floating mesa portion 60-2. In this case, the length d1 may be the sum of the lengths of the plurality of contact holes 54-2. The configuration in which the contact hole 54-2 is provided in the floating mesa portion 60-2 of the active portion 120 shown in FIG. 1C may also be applied to other embodiments.

[0081] 1D is a top view showing an example of a termination portion 122 of the semiconductor device 100 according to the embodiment. The termination portion 122 is a portion located outside the emitter region 12 provided at the outermost position of the channel mesa portion 60-1 in the extension direction (Y-axis direction). The emitter region 12 is shown in the channel mesa portion 60-1 in FIG. 1D.

[0082] 1D shows the area where the emitter electrode 52 is provided and the area where the gate wiring 131 is provided. The gate wiring 131 is a wiring that transmits a gate voltage to the gate conductive portion 44. In the terminal portion 122, the dummy trench portion 30 and the emitter electrode 52 are connected via a contact hole 54. In the terminal portion 122, the gate trench portion 40 and the gate wiring 131 are connected via a contact hole 54. However, the dummy trench portion 30 may be connected to the emitter electrode 52 via the contact hole 54 in the active portion 120. In a plan view, the contact hole 54 connected to the dummy trench portion 30 is not adjacent to the contact hole 54 connected to the gate trench portion 40. In other words, the contact hole 54 connected to the dummy trench portion 30 and the contact hole 54 connected to the gate trench portion 40 are located at different positions in the extension direction.

[0083] The gate trench portion 40 includes two extension portions 41 extending in the extension direction and a connection portion 43 connecting the ends of the two extension portions 41 in a top view. Similarly, the dummy trench portion 30 includes two extension portions 31 extending in the extension direction and a connection portion 33 connecting the ends of the two extension portions 31 in a top view. By providing the connection portions 43 and 33, the mesa portion 60 can be made floating. In this example, the termination portion 122 is provided with a base region 14, and the base region 14 is connected to an emitter electrode in another region, for example, and is at emitter potential. However, by providing the connection portions 43 and 33, the mesa portion 60 can be made floating. In other words, the base region 14 surrounded by the connection portions and extension portions is separated from the base region 14 outside the termination portion 122 by the connection portions and extension portions.

[0084] The connection portion 43 and the connection portion 33 may be provided in the termination portion 122. The extension portion 41 and the extension portion 31 extend from the active portion 120 to the termination portion 122. The ends of the two trench portions (extension portions) that sandwich the floating mesa portion 60-2 may be connected by a connection portion, or may be connected to different connection portions.

[0085] The ends of the two trench portions (extension portions) sandwiching the hole extraction mesa portion 60-3 may be connected by a connection portion. That is, the base region 14 of the hole extraction mesa portion 60-3 may be separated from the base region 14 of the floating mesa portion 60-2. Since the base region 14 of the hole extraction mesa portion 60-3 is connected to the emitter electrode 52, separating it from the base region 14 of the floating mesa portion 60-2 allows the floating mesa portion 60-2 to be floating.

[0086] In this example, the dummy trench portion 30 is provided in a region surrounded by the two extension portions 41 and the connection portion 43. Both the extension portion 31 and the connection portion 33 of the dummy trench portion 30 may be provided in the region surrounded by the two extension portions 41 and the connection portion 43. A plurality of dummy trench portions 30 may be provided in the region surrounded by the two extension portions 41 and the connection portion 43. Furthermore, another dummy trench portion 30 may be provided in the region surrounded by the two extension portions 31 and the connection portion 33 of the dummy trench portion 30, or both the extension portion 31 and the connection portion 33 of another dummy trench portion 30 may be provided, or a plurality of dummy trench portions 30 may be provided.

[0087] The trench portion may have a gate trench portion 40 that is provided between an extension portion that connects to one connection portion and an extension portion that connects to another connection portion, and that is not connected to the connection portion 43. In this example, the gate trench portion 40 located in the center in the X-axis direction of FIG. 1D is a gate trench portion 40 that is provided between an extension portion 41 that connects to one connection portion 43 and an extension portion 41 that connects to the other connection portion 43, and that is not connected to the connection portion 43. The gate trench portion 40 may be a gate trench portion 40 that sandwiches the channel mesa portion 60-1.

[0088] FIG. 1E is a top view showing another example of the termination portion 122 of the semiconductor device 100 according to the embodiment. The semiconductor device 100 shown in FIG. 1E is a top view of the semiconductor device 100 shown in FIG. 1C. In the floating mesa portion 60-2 of the semiconductor device 100 of this example, a contact hole 54-2 is provided outside the outermost emitter region 12 of the channel mesa portion 60-1 in the extension direction. That is, in the termination portion 122, the contact hole 54-2 is provided above the floating mesa portion 60-2. This allows the magnitude of dI / dt to be adjusted. In the top view of FIG. 1E, the contact hole 54-1 provided in the channel mesa portion 60-1 and the contact hole 54-2 provided in the floating mesa portion 60-2 are arranged so as not to be adjacent to the contact holes 54 connecting to the dummy trench portion 30 and the gate trench portion 40. In other words, the contact holes 54-1 and 54-2 are provided at positions different from the contact holes 54 provided in the dummy trench portion 30 and the gate trench portion 40 in the trench extension direction.

[0089] The length d1 of the contact hole 54-2 in the terminal portion 122 may be shorter than the length d2 of the contact hole 54-3 and the length d3 of the contact hole 54-1. The contact hole 54-2 in the terminal portion 122 does not have to extend to the active portion 120. Note that although only one terminal portion 122 in the extension direction is shown in Figures 1D and 1E, the other terminal portion may have the same length.

[0090] The contact hole 54-2 may be provided in both the termination portion 122 and the active portion 120. When the contact hole 54-2 is provided in the same floating mesa portion 60-2, the length d1 of the contact hole 54-2 may be the sum of the lengths of the contact hole 54-2 in the termination portion 122 and the contact hole 54-2 in the active portion 120. The configuration in which the contact hole 54-2 is provided in the floating mesa portion 60-2 of the termination portion 122 shown in FIG. 1E may also be applied to other embodiments.

[0091] 2 is a cross-sectional view showing a semiconductor device 200 according to a comparative example. The semiconductor device 200 of this example does not have a second trench bottom region 204. Therefore, the effect of the second trench bottom region 204 described above is not achieved, resulting in a larger turn-on loss compared to the semiconductor device 100 shown in FIG. 1A and other figures. Furthermore, the semiconductor device 200 of this example does not have a floating mesa portion 60-2. Therefore, Vce(sat) is larger compared to the semiconductor device 100.

[0092] 3A is a cross-sectional view showing another example of a semiconductor device 100 according to an embodiment of the present invention. In FIG. 3A, the underside of the semiconductor substrate 10 is also omitted. Further, descriptions of the same configuration as in FIG. 1A will be omitted as appropriate. The semiconductor device 100 of this example also has three gate trench portions 40 and four dummy trench portions 30 periodically arranged.

[0093] The semiconductor device 100 of this example has two channel mesa portions 60-1 and five floating mesa portions 60-2 arranged periodically. The semiconductor device 100 of this example does not have a hole-removing mesa portion 60-3. The semiconductor device 100 of this example has a floating mesa portion 60-2 instead of the hole-removing mesa portion 60-3 of the semiconductor device 100 of FIG. 1A. Furthermore, like the semiconductor device 100 of FIG. 1A, it has a GE floating and EE floating configuration. Therefore, holes injected from the underside flow into the channel mesa portion 60-1. In FIG. 3A, the flow of holes is indicated by a thick dashed line.

[0094] In the semiconductor device 100 of this example, a second trench bottom region 204 is also provided at the lower end of at least one of the trench portions sandwiching the channel mesa portion 60-1. In FIG. 3A, the second trench bottom region 204 is provided at the lower end 46 of the gate trench portion 40 on the floating mesa portion 60-2 side of the trench portions sandwiching the channel mesa portion 60-1. In this example, at least a portion of the first mesa portion is the channel mesa portion 60-1. Of the multiple mesa portions 60, all mesa portions 60 other than the channel mesa portion 60-1 may be floating mesa portions 60-2.

[0095] As a result, holes are discharged to the upper surface 21 in the second trench bottom region 204. At this time, a displacement current is generated, raising the gate-emitter voltage Vge. As a result, dI / dt increases, Vce decreases during turn-on, and turn-on loss can be reduced. In addition, the IE effect is enhanced by the floating between the electrodes, allowing Vce(sat) to be reduced.

[0096] The hole discharge amount can be adjusted by adjusting the doping concentration of the second trench bottom region 204. The higher the doping concentration of the second trench bottom region 204, the easier it is to discharge holes. The doping concentration of the second trench bottom region 204 may be at least two times, at least five times, at least ten times, at least 100 times, or at most 1000 times the doping concentration of the base region 14. The doping concentration of the second trench bottom region 204 may be lower than the doping concentration of the accumulation region 16.

[0097] In the semiconductor device 100 of this example, as in FIG. 1A , at least a portion of the second mesa portion may be a floating mesa portion 60-2. When at least a portion of the first mesa portion described above is a channel mesa portion 60-1, at least a portion of the second mesa portion may be a floating mesa portion 60-2. The second mesa portion provided adjacent to the first mesa portion may be a floating mesa portion 60-2 (GE floating). This makes it possible to reduce turn-on loss, as described above. All of the second mesa portions may be floating mesa portions 60-2. The second trench bottom region 204 may be provided in at least a portion of the second mesa portions, and may be provided across the entire width direction (X-axis direction) of at least a portion of the second mesa portions.

[0098] At least a portion of the third mesa portion may be a floating mesa portion 60-2. When at least a portion of the first mesa portion described above is a channel mesa portion 60-1 and at least a portion of the second mesa portion is a floating mesa portion 60-2, at least a portion of the third mesa portion may be a floating mesa portion 60-2. The third mesa portion provided adjacent to the second mesa portion may be a floating mesa portion 60-2 (EE floating). This enhances the IE effect and can reduce Vce(sat). All of the third mesa portions may be floating mesa portions 60-2.

[0099] The floating mesa portion 60-2 located adjacent to the channel mesa portion 60-1 may be provided with the second trench bottom region 204. In any of the cases where at least a portion of the first mesa portion is the channel mesa portion 60-1, where at least a portion of the second mesa portion is the floating mesa portion 60-2, or where at least a portion of the third mesa portion is the floating mesa portion 60-2, or in any combination thereof, the floating mesa portion 60-2 located adjacent to the channel mesa portion 60-1 may be provided with the second trench bottom region 204.

[0100] 3B is a top view showing an example of the active portion 120 of the semiconductor device 100 of FIG. 3A. Description of the same configuration as in the top view shown in FIG. 1B will be omitted as appropriate. The emitter region 12 and contact region 15 are exposed on the top surface of the channel mesa portion 60-1, and a contact hole 54-1 is provided. The base region 14 is exposed on the top surface of the floating mesa portion 60-2.

[0101] In this example, the floating mesa 60-2 does not have a contact hole 54-2. However, as described in Figure 1C, the floating mesa 60-2 may have a contact hole 54-2. In this case, the relationship between the length of the contact hole 54-2 and the length of the contact hole 54-1 may be the same as in Figure 1C.

[0102] 3C is a top view showing an example of the termination portion 122 of the semiconductor device 100 of FIG. 1D. The description of the same configuration as that shown in the top view of FIG. 1D will be omitted as appropriate. The gate trench portion 40 of this example has an extension portion 41 and a connection portion 43, and a plurality of dummy trench portions 30 are provided in the area surrounded by the extension portion 41 and the connection portion 43.

[0103] The dummy trench portion 30 of this example has an extension portion 31 but does not have a connection portion 33. The floating mesa portion 60-2 of this example is electrically isolated from the base region 14 of the termination portion 122 by the extension portion 41 of the gate trench portion 40 and the connection portion 43. Furthermore, since the semiconductor device 100 of this example does not have a hole extraction mesa portion 60-3, it does not have a connection portion 33 for separating the hole extraction mesa portion 60-3 and the floating mesa portion 60-2. However, the dummy trench portion 30 of this example may have a connection portion 33. In this case, the configuration of the connection portion 33 may be the same as that of FIG. 1D .

[0104] In this example, the floating mesa 60-2 does not have a contact hole 54-2 in the termination 122. However, as described in Fig. 1E, the floating mesa 60-2 may have a contact hole 54-2 in the termination 122. In this case, the relationship between the length of the contact hole 54-2 and the length of the contact hole 54-1 may be the same as in Fig. 1E.

[0105] 4 is a diagram showing turn-on waveforms of the semiconductor device 100 according to the example and the semiconductor device 200 according to the comparative example. The vertical axis in the diagram represents Vce and collector current Ic, and the horizontal axis represents time. The solid line in the diagram represents the waveform of the semiconductor device 100 according to the example, and the dotted line represents the waveform of the comparative example.

[0106] As described above, in the semiconductor device 100 of the embodiment, the displacement current generated by the second trench bottom region 204 increases the gate-emitter voltage Vge, increasing dI / dt. This increases the drop in Vce due to L (circuit inductance) × dI / dt. As a result, Vce decreases during turn-on, reducing turn-on loss. The above effect was confirmed in both the semiconductor device 100 shown in FIGS. 1A to 1C and the semiconductor device 100 shown in FIGS. 3A to 3C.

[0107] FIG. 5 is a graph showing the Eon-dV / dt characteristics of the semiconductor device 100 shown in FIGS. 3A to 3C and the semiconductor device 200 according to the comparative example. The vertical axis of FIG. 5 represents turn-on loss Eon, and the horizontal axis represents the rate of change of Vce during turn-on. As described above, in the semiconductor device 100, the gate-emitter voltage Vge rises due to the displacement current, resulting in a large dI / dt. Accordingly, the drop in Vce also increases. As a result, the turn-on loss is significantly reduced compared to the semiconductor device 200, which has the same magnitude of dV / dt. In other words, the Eon-dV / dt characteristics are improved. A similar trend was confirmed in the semiconductor device 100 shown in FIGS. 1A to 1C.

[0108] FIG. 6 is a graph showing the Eoff-Vce(sat) characteristics of the semiconductor device 100 shown in FIGS. 3A to 3C and the semiconductor device 200 according to the comparative example. The vertical axis of FIG. 6 represents the turn-off loss Eoff, and the horizontal axis represents Vce(sat). As described above, the semiconductor device 100 has a floating mesa portion 60-2 (EE floating) as the third mesa portion, thereby enhancing the IE effect and reducing Vce(sat). Therefore, in FIG. 6, Vce(sat) is significantly reduced compared to the semiconductor device 200, which has the same magnitude of turn-off loss. In other words, the Eoff-Vce(sat) characteristics are improved. A similar trend was confirmed in the semiconductor device 100 shown in FIGS. 1A to 1C and other examples having an EE floating configuration, which will be described later.

[0109] 7A is a cross-sectional view showing another example of a semiconductor device 100 according to an embodiment of the present invention. In FIG. 7A, the underside of the semiconductor substrate 10 is also omitted. Furthermore, descriptions of the same configuration as in FIG. 1A will be omitted as appropriate. The semiconductor device 100 of this example has one gate trench portion 40 and two dummy trench portions 30 periodically arranged.

[0110] The semiconductor device 100 of this example also has a second trench bottom region 204 at the bottom end of at least one of the trenches sandwiching the channel mesa portion 60-1. In the semiconductor device 100 of this example, at least a portion of the second mesa portion may be the channel mesa portion 60-1. In the semiconductor device 100 of this example, two channel mesas 60-1 and one floating mesa portion 60-2 are periodically arranged. The trench portion provided between the two channel mesas 60-1 is the gate trench portion 40, and the other trench portions sandwiching the two channel mesas 60-1 are dummy trench portions 30. In the semiconductor device 100 of this example, the second trench bottom region 204 is provided at the bottom end 46 of the gate trench portion 40. The semiconductor device 100 of this example also does not have a hole extraction mesa portion 60-3. Even with this configuration, the same effects as those in FIG. 1A or FIG. 3A can be obtained.

[0111] In the semiconductor device 100, at least a portion of the third mesa portion may be a floating mesa portion 60-2. That is, the semiconductor device 100 of this example may also have an E-E floating. When at least a portion of the second mesa portion described above is a channel mesa portion 60-1, at least a portion of the third mesa portion may be a floating mesa portion 60-2. This enhances the IE effect and reduces Vce(sat). The floating mesa portion 60-2 may not be provided with a second trench bottom region 204.

[0112] 7B is a top view showing an example of the active portion 120 of the semiconductor device 100 of FIG. 7A. Description of the same configuration as in the top view shown in FIG. 1B will be omitted as appropriate. The emitter region 12 and contact region 15 are also exposed on the top surface of the channel mesa portion 60-1 of this example, and a contact hole 54-1 is provided. The base region 14 is exposed on the top surface of the floating mesa portion 60-2.

[0113] The floating mesa 60-2 in this example also does not have a contact hole 54-2. However, as described in Figure 1C, the floating mesa 60-2 may have a contact hole 54-2. In that case, the relationship between the length of the contact hole 54-2 and the length of the contact hole 54-1 may be the same as that in Figure 1C.

[0114] 7C is a top view showing an example of the termination portion 122 of the semiconductor device 100 of FIG. 7A. Description of the same configuration as that shown in the top view of FIG. 1D will be omitted as appropriate. The semiconductor device 100 of this example also has an extension portion 41 of the gate trench portion 40 and a connection portion 43. A dummy trench portion 30 is provided in the region surrounded by the extension portion 41 and the connection portion 43.

[0115] The other dummy trench portions 30 in this example are provided outside the region surrounded by the extension portion 41 and the connection portion 43. However, since the dummy trench portions 30 have the connection portion 33, the mesa portion 60 sandwiched between the dummy trench portions 30 becomes a floating mesa portion 60-2. In the channel mesa portion 60-1, the base region 14 is provided continuously from the termination portion 122 to the active portion 120.

[0116] In this example, the floating mesa portion 60-2 does not have a contact hole 54-2 in the termination portion 122. However, as described in Fig. 1E, a contact hole 54-2 may be provided in the floating mesa portion 60-2 of the termination portion 122. In this case, the relationship between the length of the contact hole 54-2 and the length of the contact hole 54-1 may be the same as in Fig. 1E.

[0117] 8A is a cross-sectional view showing another example of a semiconductor device 100 according to an embodiment of the present invention. In FIG. 8A , the underside of the semiconductor substrate 10 is also omitted. Furthermore, descriptions of the same configuration as in FIG. 1A will be omitted as appropriate. In the semiconductor device 100 of this example, two gate trench portions 40 and four dummy trench portions 30 are periodically arranged.

[0118] In the semiconductor device 100 of this example, a second trench bottom region 204 is provided at the bottom end of at least one of the trench portions sandwiching the channel mesa portion 60-1. In the semiconductor device 100 of this example, at least a portion of the second mesa portion is the channel mesa portion 60-1. In the semiconductor device 100 of this example, one floating mesa portion 60-2, one channel mesa portion 60-1, three hole-punching mesa portions 60-3, and one channel mesa portion 60-1 are periodically arranged in this order. With this configuration, the same effect as in FIG. 1A can be obtained.

[0119] A second trench bottom region 204 may be provided at the lower end 36 of the dummy trench portion 30. In this example, the second trench bottom region 204 is provided at the lower end 36 of one of the dummy trench portions 30 that sandwich the channel mesa portion 60-1. Specifically, the second trench bottom region 204 is provided at the lower end 36 of the dummy trench portion 30 that is located at the boundary between the channel mesa portion 60-1 and the floating mesa portion 60-3. By forming the second trench bottom region 204 from the lower end 36 of the dummy trench portion 30, oscillation of the gate voltage can be reduced compared to when the second trench bottom region 204 is formed from the lower end 46 of the gate trench portion 40.

[0120] A second trench bottom region 204 may be provided in the channel mesa portion 60-1, which is the second mesa portion. The second trench bottom region 204 may be provided across the entire width direction (X-axis direction) of the channel mesa portion 60-1. The second trench bottom region 204 may be in contact with the adjacent gate trench portion 40.

[0121] At least a portion of the first mesa portion may be the floating mesa portion 60-2 (inter-G-G floating). In the semiconductor device 100 of this example, the first mesa portion sandwiched between the channel mesa portions 60-1 is the floating mesa portion 60-2. This increases Cgc, further improving turn-on loss. The increase in Cgc due to inter-G-G floating is caused by a different mechanism from the increase in Cgc due to the second trench bottom region 204 described above, so by applying them simultaneously, the Eon-dV / dt characteristics can be significantly improved.

[0122] 8B is a top view showing an example of the active portion 120 of the semiconductor device 100 of FIG. 8A. Descriptions of the same configuration as in the top view shown in FIG. 1B will be omitted where appropriate. The emitter region 12 and contact region 15 are exposed on the top surface of the channel mesa portion 60-1 of this example, and a contact hole 54-1 is provided. The base region 14 is exposed on the top surface of the floating mesa portion 60-2. The base region 14 is exposed on the top surface of the hole-punched mesa portion 60-3 of this example, and a contact hole 54-3 is provided.

[0123] In this example, the floating mesa 60-2 also does not have a contact hole 54-2. However, as described in FIG. 1C, the floating mesa 60-2 may have a contact hole 54-2. In this case, the relationship between the length of the contact hole 54-2 and the length of the contact hole 54-1 or the contact hole 54-3 may be the same as in FIG. 1C.

[0124] 8C is a top view showing an example of the termination portion 122 of the semiconductor device 100 of FIG. 8A. Description of the same configuration as in the top view shown in FIG. 1D will be omitted as appropriate. The semiconductor device 100 of this example also has an extension portion 41 and a connection portion 43 of the gate trench portion 40, and a floating mesa portion 60-2 is formed in the region surrounded by the extension portion 41 and the connection portion 43. In other words, the floating mesa portion 60-2 is electrically isolated from the base region 14 of the termination portion 122.

[0125] The dummy trench portion 30 in this example has an extension portion 31 and a connection portion 33, and a hole-removing mesa portion 60-3 is formed in the region surrounded by the extension portion 31 and the connection portion 33. In other words, the hole-removing mesa portion 60-3 is electrically isolated from the base region 14 of the termination portion 122. However, other hole-removing mesa portions 60-3 are not surrounded by the extension portion and the connection portion, and are at the same potential as the base region 14 of the termination portion 122. As another example, as shown in FIG. 7C , other extension portions 31 and connection portions 33 may be provided in the region surrounded by the extension portion 31 and the connection portion 33. Alternatively, the connection portion 33 may not be provided.

[0126] In this example, the floating mesa portion 60-2 does not have a contact hole 54-2 in the termination portion 122. However, as described in Fig. 1E, a contact hole 54-2 may be provided in the floating mesa portion 60-2 of the termination portion 122. In this case, the relationship between the length of the contact hole 54-2 and the lengths of the contact holes 54-1 and 54-3 may be the same as in Fig. 1E.

[0127] 9A and 9B are diagrams showing turn-on waveforms of the semiconductor device 100 of the example and the semiconductor device 200 of the comparative example. The vertical axis in the diagrams represents Vce and collector current Ic, and the horizontal axis represents time. The solid line in the diagrams represents the waveform of the semiconductor device 100 of the example, and the dotted line represents the waveform of the comparative example.

[0128] 9A , the values ​​of the gate resistance Rg are the same for the semiconductor device 100 and the semiconductor device 200. In this case, as described above, Cgc increases in the semiconductor device 100, and therefore the change over time (dV / dt) of the collector-emitter voltage Vce at turn-on is gentler than in the semiconductor device 200.

[0129] FIG. 9B shows the turn-on waveform when the magnitude of dV / dt is made uniform by adjusting the gate resistance Rg. When the magnitude of dV / dt is the same, the value of the gate resistance Rg of the semiconductor device 100 is smaller than the value of the gate resistance Rg of the semiconductor device 200. As a result, the switching operation is faster and turn-on loss can be reduced. The above effect was also confirmed in all other semiconductor devices 100. Note that in order to explain the magnitude of dV / dt, the Vce drop described in FIG. 4 is not shown in FIGS. 9A and 9B, but in reality, the Vce drop may also appear.

[0130] FIG. 10 shows the Eon-dV / dt characteristics of the semiconductor device 100 shown in FIGS. 8A to 8C and the semiconductor device 200 according to the comparative example. The vertical axis of FIG. 10 represents turn-on loss Eon, and the horizontal axis represents the rate of change of Vce during turn-on. As described above, the semiconductor device 100 increases dI / dt because the gate-emitter voltage Vge increases due to the displacement current. Furthermore, when the magnitude of dV / dt is the same, the value of gate resistance Rg can be reduced. As a result, turn-on loss is significantly reduced compared to the semiconductor device 200 with the same magnitude of dV / dt. For example, when comparing at a certain value of dV / dt, turn-on loss is reduced by as much as 51%.

[0131] 11A is a cross-sectional view showing another example of a semiconductor device 100 according to an embodiment of the present invention. In FIG. 11A , the underside of the semiconductor substrate 10 is also omitted. Further, descriptions of the same configuration as in FIG. 1A will be omitted as appropriate. In the semiconductor device 100 of this example, three gate trench portions 40 and four dummy trench portions 30 are periodically arranged.

[0132] In the semiconductor device 100 of this example, a second trench bottom region 204 is provided at the lower end of at least one of the trench portions sandwiching the channel mesa portion 60-1. In the semiconductor device 100 of this example, at least a portion of the second mesa portion is the channel mesa portion 60-1. In the semiconductor device 100 of this example, one channel mesa portion 60-1, two floating mesa portions 60-2, one channel mesa portion 60-1, and three floating mesa portions 60-2 are periodically arranged in this order. In addition, the second trench bottom region 204 is provided at the lower end 46 of one of the gate trench portions 40 sandwiching the channel mesa portion 60-1. Specifically, the second trench bottom region 204 is provided at the lower end 46 of the gate trench portion 40 located at the boundary between the channel mesa portion 60-1 and the floating mesa portion 60-2. With this configuration, the same effect as in FIG. 1A can be obtained. The semiconductor device 100 of this example does not have a hole-removing mesa portion 60-3.

[0133] At least a part of the third mesa portion may be the floating mesa portion 60-2 (EE floating). In this example, the three third mesas located between the channel mesa portion 60-1, which is the second mesa portion, are the floating mesa portions 60-2. This allows carriers to accumulate on the upper surface 21 side, thereby reducing Vce(sat).

[0134] At least a part of the first mesa portion may be the floating mesa portion 60-2 (inter-G-G floating). In the semiconductor device 100 of this example, the two first mesas sandwiched between the channel mesa portion 60-1 are the floating mesa portions 60-2. As described above, this increases Cgc, further improving turn-on loss.

[0135] 11B is a top view showing an example of the active portion 120 of the semiconductor device 100 of FIG. 11A. Description of the same configuration as in the top view shown in FIG. 1B will be omitted as appropriate. In this example, the emitter region 12 and the contact region 15 are exposed on the top surface of the channel mesa portion 60-1, and a contact hole 54-1 is provided. The base region 14 is exposed on the top surface of the floating mesa portion 60-2.

[0136] In this example, the floating mesa 60-2 also does not have a contact hole 54-2. However, as described in FIG. 1C, the floating mesa 60-2 may have a contact hole 54-2. In this case, the relationship between the length of the contact hole 54-2 and the length of the contact hole 54-1 or the contact hole 54-3 may be the same as in FIG. 1C.

[0137] 11C is a top view showing an example of the termination portion 122 of the semiconductor device 100 of FIG. 11A. Description of the same configuration as in the top view shown in FIG. 1D will be omitted as appropriate. The semiconductor device 100 of this example also has an extension portion 41 and a connection portion 43 of the gate trench portion 40, and two floating mesas 60-2 and the gate trench portion 40 are formed in the area surrounded by the extension portion 41 and the connection portion 43. In other words, the two floating mesas 60-2 are electrically isolated from the base region 14 of the termination portion 122.

[0138] In this example, the dummy trench portion 30 has an extension portion 31 and a connection portion 33, and three floating mesa portions 60-2 and the dummy trench portion 30 are formed in the area surrounded by the extension portion 31 and the connection portion 33. In other words, the three floating mesa portions 60-2 are electrically isolated from the base region 14 of the termination portion 122. The dummy trench portion 30 also has two extension portions 31 and a connection portion 33. However, the extension portions 31 do not have to be connected by the connection portions 33 as shown in FIG. 3C .

[0139] In this example, the floating mesa portion 60-2 does not have a contact hole 54-2 in the termination portion 122. However, as described in Fig. 1E, a contact hole 54-2 may be provided in the floating mesa portion 60-2 of the termination portion 122. In this case, the relationship between the length of the contact hole 54-2 and the length of the contact hole 54-1 may be the same as in Fig. 1E.

[0140] FIG. 12 shows the Eon-dV / dt characteristics of the semiconductor device 100 shown in FIGS. 11A to 11C and the semiconductor device 200 according to the comparative example. The vertical axis of FIG. 12 represents turn-on loss Eon, and the horizontal axis represents the rate of change of Vce during turn-on. As described above, the semiconductor device 100 increases dI / dt because the gate-emitter voltage Vge increases due to the displacement current. Furthermore, when the magnitude of dV / dt is the same, the value of gate resistance Rg can be reduced. As a result, turn-on loss is significantly reduced compared to the semiconductor device 200 with the same magnitude of dV / dt. For example, when comparing at a certain value of dV / dt, turn-on loss is reduced by as much as 42%.

[0141] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. For example, if the gate potential trench does not contact the emitter region 12, it can be considered a dummy trench portion 30. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0142] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 18...Drift region, 21...Upper surface, 30...Dummy trench portion, 31...Extension portion, 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 36...Lower end, 38...Interlayer insulating film, 40...Gate trench portion, 41...Extension portion, 42...Gate insulating film, 43...Connection portion, 44...Gate conductive portion, 46...Lower end, 52...Emitter electrode, 54...Contact hole, 60...Mesa portion, 60-1...Channel mesa portion, 60-2...Floating mesa portion, 60-3...Hole-punched mesa portion, 100...Semiconductor device, 120...Active portion, 122...Termination portion, 131...Gate wiring, 200...Semiconductor device, 202...First trench bottom region, 204...Second trench bottom region

Claims

1. A semiconductor substrate having an upper surface and provided with a first conductivity type drift region; a plurality of trenches extending from the upper surface of the semiconductor substrate toward the interior and in an extension direction; a plurality of mesa regions sandwiched between two of the trenches; an emitter electrode provided above the upper surface of the semiconductor substrate; and an interlayer insulating film provided between the upper surface of the semiconductor substrate and the emitter electrode and having a contact hole formed therein, wherein the plurality of mesa regions include: a channel mesa region having a first conductivity type emitter region provided on the upper surface of the semiconductor substrate and a second conductivity type base region provided between the emitter region and the drift region, the channel mesa region being connected to the emitter electrode by the contact hole; and a floating mesa region above which the contact hole is not provided or the length of the contact hole above in the extension direction is shorter than the length of the contact hole above the channel mesa region, a second trench bottom region of a second conductivity type having a higher impurity concentration than the base region is provided at a lower end of at least one of the trench portions sandwiching the channel mesa portion.

2. The semiconductor device according to claim 1, wherein the second trench bottom region is not provided in at least a portion of the floating mesa portion.

3. The semiconductor device according to claim 1, wherein the second trench bottom region is provided across the entire width of at least a portion of the channel mesa portion.

4. The semiconductor device according to any one of claims 1 to 3, wherein the trench portion has a gate trench portion and a dummy trench portion, the plurality of mesa portions include a second mesa portion sandwiched between the gate trench portion and the dummy trench portion, and at least a portion of the second mesa portion is a channel mesa portion.

5. The semiconductor device according to claim 4, wherein the second trench bottom region is provided at the lower end of the dummy trench portion.

6. The semiconductor device according to claim 4, wherein the trench portion has a plurality of the dummy trench portions, the plurality of mesa portions includes a third mesa portion sandwiched between two of the dummy trench portions, and at least a portion of the third mesa portion is the floating mesa portion.

7. The semiconductor device according to any one of claims 1 to 3, wherein the trench portion has a plurality of gate trench portions, the plurality of mesa portions include a first mesa portion sandwiched between two of the gate trench portions, and at least a portion of the first mesa portion is the floating mesa portion.

8. The semiconductor device according to any one of claims 1 to 3, wherein the trench portion has a plurality of gate trench portions, the plurality of mesa portions include a first mesa portion sandwiched between two of the gate trench portions, and at least a portion of the first mesa portion is the channel mesa portion.

9. The semiconductor device according to claim 8, wherein the trench portion has a dummy trench portion, the plurality of mesa portions include a second mesa portion sandwiched between the gate trench portion and the dummy trench portion, and at least a portion of the second mesa portion is the floating mesa portion.

10. The semiconductor device according to claim 9, wherein the trench portion has a plurality of the dummy trench portions, the plurality of mesa portions includes a third mesa portion sandwiched between two of the dummy trench portions, and at least a portion of the third mesa portion is the floating mesa portion.

11. The semiconductor device according to claim 9, wherein the second trench bottom region is provided in the floating mesa portion located adjacent to the channel mesa portion.

Images