Semiconductor device, electric circuit, and electronic apparatus

Abstract

A semiconductor device according to an embodiment of the present disclosure comprises: a substrate; a channel layer that is provided on one surface side of the substrate; a buffer layer that is provided between the substrate and the channel layer and includes impurities; and a first barrier layer that is provided between the buffer layer and the channel layer, includes impurities, and has a band gap larger than that of the channel layer. The buffer layer includes a first region that is on the substrate side and that has a first impurity concentration, and a second region that is on the channel layer side and that has a second impurity concentration. The first barrier layer has a third impurity concentration. The impurity concentrations of the first region, the second region, and the first barrier layer have the relationship of the first impurity concentration < the third impurity concentration < the second impurity concentration.

Description

Semiconductor devices, electric circuits and electronic devices

[0001] The present disclosure relates to semiconductor devices, electric circuits, and electronic devices.

[0002] For example, Patent Document 1 discloses a semiconductor device in which a high-resistivity layer is provided between a buffer layer containing carbon and a channel layer, the high-resistivity layer having, from the buffer layer side, a first region having a lower carbon concentration than the buffer layer and a second region having a higher carbon concentration than the first region.

[0003] Japanese Patent Application Laid-Open No. 2015-207624

[0004] In HEMTs, low buffer leakage, low gate leakage, and low current collapse are desired, which have a trade-off relationship.

[0005] Therefore, it is desirable to provide a semiconductor device, an electric circuit, and an electronic device that can simultaneously achieve low buffer leakage, low gate leakage, and low current collapse.

[0006] A semiconductor device according to an embodiment of the present disclosure includes a substrate, a channel layer provided on one surface of the substrate, a buffer layer provided between the substrate and the channel layer and containing an impurity, and a first barrier layer provided between the buffer layer and the channel layer, containing an impurity and having a larger band gap than the channel layer, wherein the buffer layer has a first region on the substrate side having a first impurity concentration and a second region on the channel layer side having a second impurity concentration, the first barrier layer has a third impurity concentration, and the impurity concentrations of the first region, the second region, and the first barrier layer satisfy the following relationship: first impurity concentration<third impurity concentration<second impurity concentration (1).

[0007] An electric circuit according to an embodiment of the present disclosure includes the semiconductor device according to the embodiment of the present disclosure.

[0008] An electronic device according to an embodiment of the present disclosure includes an electric circuit having the semiconductor device according to the embodiment of the present disclosure.

[0009] In a semiconductor device, an electric circuit, and an electronic device according to an embodiment of the present disclosure, a buffer layer and a first barrier layer, each containing an impurity, are provided in this order between a substrate and a channel layer. The buffer layer has a first region with a first impurity concentration on the substrate side and a second region with a second impurity concentration on the channel layer side, and the first barrier layer has a third impurity concentration, the impurity concentrations being related by the above-mentioned mathematical formula (1). This improves the crystallinity of the buffer layer and suppresses an increase in crystal defects and trap sources caused by doping with impurities, while improving voltage resistance. Furthermore, the first barrier layer prevents electrons from leaking from the channel layer to the buffer layer side.

[0010] FIG. 1 is a cross-sectional view schematically illustrating an example of a configuration of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a plan view schematically illustrating an example of a configuration of the semiconductor device illustrated in FIG. 1. FIG. 3 illustrates an example of a carbon concentration profile of the buffer layer and the back barrier layer illustrated in FIG. 1. FIG. 4 illustrates another example of a carbon concentration profile of the buffer layer and the back barrier layer illustrated in FIG. 1. FIG. 5 illustrates another example of a carbon concentration profile of the buffer layer and the back barrier layer illustrated in FIG. 1. FIG. 6 illustrates another example of a carbon concentration profile of the buffer layer and the back barrier layer illustrated in FIG. 1. FIG. 7 is a characteristic diagram illustrating the relationship between drain voltage and buffer leakage in a typical semiconductor device. FIG. 8 illustrates a carbon concentration profile of the buffer layer in a typical semiconductor device. FIG. 9 is a characteristic diagram illustrating the relationship between drain voltage and buffer leakage in the semiconductor device illustrated in FIG. 1. FIG. 10 is a diagram illustrating gate leakage currents of a typical semiconductor device and the semiconductor device illustrated in FIG. 1. FIG. 11 is a diagram illustrating current collapse of a typical semiconductor device and the semiconductor device illustrated in FIG. 1. FIG. 12 is a cross-sectional view schematically illustrating an example of a configuration of a semiconductor device according to a modified example of the present disclosure. Fig. 13 shows an example of carbon concentration profiles of the buffer layer and the back barrier layer shown in Fig. 12. Fig. 14 is a perspective view showing an example of the configuration of a wireless communication device. Fig. 15 is a block diagram showing an example of the configuration of a wireless communication device.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The following description is one specific example of the present disclosure, and the present disclosure is not limited to the following embodiment. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of each component shown in each drawing.

[0012] The description will be given in the following order: 1. Embodiment (example of a semiconductor device having three regions with different carbon concentrations between a substrate and a channel layer) 2. Modification (another example of a semiconductor device) 3. Application example

[0013] 1. Embodiment Fig. 1 is a schematic diagram illustrating an example of a cross-sectional configuration of a semiconductor device (semiconductor device 1) according to an embodiment of the present disclosure. Fig. 2 is a schematic diagram illustrating an example of a planar configuration of the semiconductor device 1 illustrated in Fig. 1.

[0014] The semiconductor device 1 has a structure in which a buffer layer 12 and a back barrier layer 13 are stacked in this order between a substrate 11 and a channel layer 14. The buffer layer 12 and the back barrier layer 13 each contain an impurity. The buffer layer 12 has, from the substrate 11 side, a first buffer layer 121, a second buffer layer 122, and a third buffer layer 123. The back barrier layer 13 has a larger band gap than the channel layer 14. The first buffer layer 121 has a first impurity concentration, the third buffer layer 123 has a second impurity concentration, and the back barrier layer 13 has a third impurity concentration, and the impurity concentrations have a relationship of first impurity concentration < third impurity concentration < second impurity concentration.

[0015] Here, the substrate 11 corresponds to a specific example of a "substrate" according to an embodiment of the present disclosure. The channel layer 14 corresponds to a specific example of a "channel layer" according to an embodiment of the present disclosure. The buffer layer 12 corresponds to a specific example of a "buffer layer" according to an embodiment of the present disclosure. The first buffer layer 121 corresponds to a specific example of a "first region" according to an embodiment of the present disclosure, and the third buffer layer 123 corresponds to a specific example of a "second region" according to an embodiment of the present disclosure. The back barrier layer 13 corresponds to a specific example of a "first barrier layer" according to an embodiment of the present disclosure.

[0016] [Configuration of Semiconductor Device] The semiconductor device 1 has a layered structure in which a substrate 11, a buffer layer 12, a back barrier layer 13, a channel layer 14, a spacer layer 15, a barrier layer 16, and a cap layer 17 are layered in this order. The semiconductor device 1 further has a gate electrode G provided on the cap layer 17, a pair of contact layers 18 arranged opposite each other in the in-plane direction (XY plane direction) of the substrate 11 with the gate electrode G interposed therebetween, and a source electrode S and a drain electrode D provided on each of the pair of contact layers 18. An insulating film 19 is provided between the source electrode S and the drain electrode D. The gate electrode G has, for example, a Schottky gate structure, and a gate length Lg is defined by an opening 19H provided in the insulating film 19.

[0017] The semiconductor device 1 according to this embodiment is a high electron mobility transistor (HEMT) having a two-dimensional electron gas layer 2DEG as a channel. The two-dimensional electron gas layer 2DEG is generated due to the difference in the magnitude of polarization between the channel layer 14 and the barrier layer 16. The two-dimensional electron gas layer 2DEG is generated in the channel layer 14, for example, near the interface between the channel layer 14 and the spacer layer 15.

[0018] The substrate 11 is a support for the semiconductor device 1. The substrate 11 is, for example, a compound semiconductor substrate, and is made of, for example, a speckled insulating single-crystal gallium nitride (GaN), which is a III-V group compound semiconductor. The buffer layer 12 alleviates lattice constant mismatch, allowing the substrate 11 to have a different lattice constant from the channel layer 14. Examples of substrates having a different lattice constant from the channel layer 14 include a silicon (Si) substrate, a silicon carbide (SiC) substrate, and a sapphire substrate. A suitable Si substrate is, for example, a single-crystal Si(111) substrate having a (111) plane as its main surface.

[0019] It should be noted that the substrate 11 made of the above-mentioned materials can achieve the effects of the semiconductor device of the present disclosure described below. The semiconductor device 1 using a substrate made of SiC or a substrate made of GaN can obtain a GaN-based crystal growth layer with fewer defects than when a substrate made of Si(111) is used, and therefore, further reduction in off-leak current and higher breakdown voltage can be expected. Therefore, the substrate 11 can be constructed by selecting an appropriate material depending on the application, etc.

[0020] The buffer layer 12 is made of an epitaxially grown compound semiconductor. ｘ１ Ga （１－ｘ１） In ｙ１ The buffer layer 12 is made of a nitride semiconductor containing N (0≦x1≦1, 0≦y1<1, 0<x1+y1≦1). The buffer layer 12 contains, for example, carbon atoms (C) or iron atoms (Fe) as impurities. As described above, the buffer layer 12 has a first buffer layer 121, a second buffer layer 122, and a third buffer layer 123 stacked in this order from the substrate 11 side.

[0021] The first buffer layer 121 is intended to alleviate the lattice mismatch between the substrate 11 and the channel layer 14 and to improve the crystallinity of the layers above the first buffer layer 121. When the lattice constants of the substrate 11 and the channel layer 14 are different, controlling the lattice constant of the first buffer layer 121 can improve the crystalline state of the channel layer 14, suppress crystal defects, and suppress warpage of the substrate 11. The impurity concentration of the first buffer layer 121 is, for example, 1e17 cm －３ The thickness (hereinafter simply referred to as thickness) of the first buffer layer 121 in the stacking direction (Z-axis direction) is, for example, 200 nm or more and 400 nm or less. When the substrate 11 is made of single-crystal Si and the channel layer 14 is made of gallium nitride (GaN), the first buffer layer 121 is made of, for example, aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), aluminum indium gallium nitride (AlInGaN), or the like.

[0022] The second buffer layer 122 corresponds to a specific example of a "third region" according to an embodiment of the present disclosure. The second buffer layer 122 is made of, for example, epitaxially grown gallium nitride (GaN). The impurity concentration of the second buffer layer 122 is, for example, 1e17 cm －３ Larger 5e18cm －３ The thickness of the second buffer layer 122 is, for example, not less than 400 nm and not more than 1500 nm.

[0023] The third buffer layer 123 is intended to suppress buffer leakage and has the highest resistance among the first buffer layer 121, the second buffer layer 122, and the third buffer layer 123. The third buffer layer 123 is made of, for example, epitaxially grown gallium nitride (GaN). The impurity concentration of the third buffer layer 123 is, for example, 5e18 cm －３ Larger than 1e20cm －３ The thickness of the third buffer layer 123 is, for example, not less than 50 nm and not more than 300 nm.

[0024] The first buffer layer 121, the second buffer layer 122, and the third buffer layer 123 are each formed by epitaxially growing gallium nitride (GaN) to a predetermined thickness at a temperature of about 900° C. to 1100° C. The impurities (e.g., C) contained in the first buffer layer 121, the second buffer layer 122, and the third buffer layer 123 are supplied from methyl groups contained in trimethylgallium (TMG) used as a material. ３ The predetermined impurity concentration is set by adjusting the supply ratio of V to III, i.e., the V / III ratio. The impurity (e.g., C) may be added during the formation of the first buffer layer 121, the second buffer layer 122, and the third buffer layer 123, or may be added after the formation of the layers by ion implantation or diffusion.

[0025] The back barrier layer 13 is intended to prevent electrons from leaking from the channel layer 14 to the buffer layer 12. The back barrier layer 13 is made of an epitaxially grown nitride semiconductor having a band gap larger than that of the channel layer 14. For example, when the channel layer 14 is made of gallium nitride (GaN), the back barrier layer 13 is made of Al ｘ２ Ga （１－ｘ２） In ｙ２ N (0≦x2≦1, 0≦y2<1, 0<x2+y2≦1). The back barrier layer 13, like the buffer layer 12, contains carbon atoms (C) or iron atoms (Fe) as impurities. The impurity concentration of the back barrier layer 13 is, for example, 1e17 cm －３ 5e18cm or more －３ The following is the result.

[0026] The back barrier layer 13 is formed by epitaxially growing aluminum gallium nitride (AlGaN) at approximately 900°C to 1100°C to a thickness of 400 nm to 1500 nm. The impurities (e.g., C) contained in the back barrier layer 13 are supplied from the materials trimethylgallium (TMG) and trimethylaluminum (TMA). The impurity concentration is set by adjusting the supply ratio of trimethylgallium (TMG) to trimethylaluminum (TMA), the so-called V / III ratio. The impurities (e.g., C) may be added during the formation of the back barrier layer 13 or may be added after the formation of the layer using ion implantation or diffusion.

[0027] 3 shows an example of carbon concentration profiles of the first buffer layer 121, the second buffer layer 122, the third buffer layer 123, and the back barrier layer 13. In the semiconductor device 1, the buffer layer 12 has three regions with different carbon concentrations. The carbon concentrations of the three regions increase sequentially in the crystal growth direction. These three regions correspond to the first buffer layer 121, the second buffer layer 122, and the third buffer layer 123 described above. The back barrier layer 13 is provided on the third buffer layer 123. When the carbon concentration of the first buffer layer 121 is defined as a first impurity concentration, the carbon concentration of the third buffer layer 123 is defined as a second impurity concentration, and the impurity concentration of the back barrier layer 13 is defined as a third impurity concentration, the carbon concentration of the back barrier layer 13 is greater than the carbon concentration of the first buffer layer 121 and less than the carbon concentration of the third buffer layer 123, as shown in the following equation (1): Furthermore, when the second buffer layer 122 is added and the impurity concentration of the second buffer layer 122 is a fourth impurity concentration, the carbon concentration of the back barrier layer 13 is greater than the carbon concentration of the first buffer layer 121, less than the carbon concentration of the third buffer layer 123, and equal to or less than the carbon concentration of the second buffer layer 122, as shown in the following mathematical formula (2): (Math 1) First impurity concentration<Third impurity concentration<Second impurity concentration (1) (Math 2) First impurity concentration<Third impurity concentration≦Fourth impurity concentration<Second impurity concentration (2)

[0028] The carbon concentration profiles of the first buffer layer 121, the second buffer layer 122, the third buffer layer 123, and the back barrier layer 13 are not limited to these. The first buffer layer 121, the second buffer layer 122, the third buffer layer 123, and the back barrier layer 13 only need to have their average concentrations satisfy the above-mentioned formula (1) or (2). For example, the first buffer layer 121, the second buffer layer 122, the third buffer layer 123, and the back barrier layer 13 may have a gradient in which the impurity concentration changes continuously within the layer, as shown in FIG. 4. For example, the first buffer layer 121, the second buffer layer 122, the third buffer layer 123, and the back barrier layer 13 may have a peak in the layer that exceeds the above-mentioned impurity concentration range, as shown in FIG. 5. For example, the first buffer layer 121, the second buffer layer 122, the third buffer layer 123 and the back barrier layer 13 may have impurity concentrations that change stepwise so that multiple concentration regions are formed within the layers, as shown in FIG.

[0029] The thickness of each of the first buffer layer 121, the second buffer layer 122, and the third buffer layer 123 is such that the third buffer layer 123 has the smallest thickness, and the first buffer layer 121 and the back barrier layer have approximately the same thickness, as shown in the following equation (3): second region<first region≦third region (3)

[0030] The channel layer 14 constitutes a part of the current path between the source electrode S and the drain electrode D. The channel layer 14 is a region where carriers (two-dimensional electron gas layer 2DEG) are accumulated due to the difference in polarization charge between the channel layer 14 and the barrier layer 16. The channel layer 14 is made of an epitaxially grown compound semiconductor. The channel layer 14 is made of, for example, epitaxially grown gallium nitride (GaN).

[0031] The channel layer 14 is an epitaxially grown nitride semiconductor, Al ｘ３ In ｙ３ Ga （１－ｘ３－ｙ３）N (0≦x3<1, 0≦y3<1, x3+y3≦1). The channel layer 14 may be made of undoped u-GaN to which no impurities are added. This suppresses impurity scattering of carriers in the channel layer 14, and achieves carrier transport with high mobility.

[0032] The channel layer 14 may be composed of at least one of InGaN (indium gallium nitride), InN (indium nitride), AlGaN (aluminum gallium nitride), and AlInGaN (aluminum indium gallium nitride). The channel layer 14 may have a stacked structure composed of multiple layers with different compositions. In such a case, the channel layer 14 can suppress impurity scattering of carriers. Therefore, the channel layer 14 can further increase carrier mobility.

[0033] The channel layer 14 can be formed, for example, by epitaxially growing gallium nitride (GaN) at about 900° C. to 1100° C. The channel layer 14 has a thickness of, for example, 30 nm to 300 nm.

[0034] The spacer layer 15 is intended to suppress a decrease in carrier mobility of the two-dimensional electron gas layer 2DEG. The spacer layer 15 is made of, for example, aluminum nitride (AlN) epitaxially grown on the channel layer 14. By providing an AlN layer, which is a binary compound, between the channel layer 14 and the barrier layer 7, the spacer layer 15 can reduce the influence of alloy scattering from the barrier layer 16, which is a ternary or quaternary compound, on the two-dimensional electron gas layer 2DEG formed near the interface between the spacer layer 15 and the channel layer 14, thereby suppressing a decrease in carrier mobility.

[0035] The spacer layer 15 may contain Ga or In due to the influence of diffusion from the channel layer 14 or the barrier layer 7, or may be an Al layer to which Ga or In is intentionally added to such an extent that the channel characteristics are not impaired. ｘ４ In ｙ４ Ga （１－ｘ４－ｙ４）N (0<x4≦1, 0≦y4<1, 0≦x4+y4≦1). The spacer layer 15 can be omitted if a reduction in carrier mobility can be tolerated.

[0036] The barrier layer 16 corresponds to a specific example of a "second buffer layer" according to an embodiment of the present disclosure. The barrier layer 16 is made of a nitride semiconductor having a band gap larger than the band gap of the channel layer 14. The barrier layer 16 is provided on the spacer layer 15. The barrier layer 16 can accumulate carriers in a region of the channel layer 14 near the barrier layer 16 due to spontaneous polarization or piezoelectric polarization. As a result, in the semiconductor device 1, a two-dimensional electron gas layer 2DEG with high mobility and high carrier concentration can be formed in a region near the interface between the channel layer 14 and the spacer layer 15.

[0037] The barrier layer 16 is made of a nitride semiconductor in which two-dimensional electron gas accumulates in a region near the interface between the channel layer 14 and the spacer layer 15 due to the difference in polarization charge between the barrier layer 16 and the channel layer 14. The barrier layer 16 is made of an epitaxially grown nitride semiconductor, Al ｘ５ In ｙ５ Ga （１－ｘ５－ｙ５） N (0≦x5<1, 0≦y5<1, x5+y5≦1).

[0038] The barrier layer 16 is made of, for example, undoped u-Al, which is not doped with impurities. ｘ１ In （１－ｘ１） The barrier layer 16 may be made of GaN. This suppresses impurity scattering of carriers in the channel layer 14, realizing carrier transport with high mobility. Furthermore, since the barrier layer 16 can reduce lattice mismatch with GaN, it is possible to obtain crystals with excellent single crystallinity. If it is desired to increase the concentration of two-dimensional electron gas, n-type impurities such as silicon (Si) or germanium (Ge) may be added to the barrier layer 16.

[0039] The cap layer 17 is intended to suppress oxidation of the barrier layer 16. The cap layer 17 is provided on the barrier layer 16. The cap layer 17 and the channel layer 14 are made of, for example, epitaxially grown gallium nitride (GaN). If the effect of an oxide film formed on the outermost surface of the barrier layer 16 due to oxidation is not a problem, the cap layer 17 can be omitted.

[0040] The contact layer 18 constitutes a part of the current path between the source electrode S and the drain electrode D arranged with the gate electrode G therebetween. As shown in FIG. 1 , the contact layer 18 is provided below each of the source electrode S and the drain electrode D arranged with the gate electrode G therebetween. Each contact layer 18 below each of the source electrode S and the drain electrode D is electrically connected to the two-dimensional electron gas layer 2DEG.

[0041] The contact layer 18 is made of, for example, Alx6Iny6Ga1-x6-6yN (0≦x6<1, 0≦y6<1, x6+y6≦1). １９ cm －３ It is preferable that the source electrode S and the drain electrode D have a carrier concentration of 1×10 or more. This reduces the contact resistance between the source electrode S and the drain electrode D and the contact layers 18 below them. In order to achieve the above carrier concentration, n-type impurities such as silicon (Si) or germanium (Ge) are introduced into the contact layers 18 to a desired carrier concentration (1×10 １９ cm －３ The contact layer 18 preferably has a sheet resistance of, for example, 250 Ω / □ or less and a carrier mobility of 30 cm 2 / V·s or more.

[0042] The contact layer 18 can be formed as follows. First, a semiconductor stack, in which the buffer layer 12, back barrier layer, channel layer 14, spacer layer 15, barrier layer 16, and cap layer 17 are stacked in this order, is patterned in a region where the source electrode S and drain electrode D are to be formed, and an opening is formed on the side of the channel layer 14 to a depth where a two-dimensional electron gas layer 2DEG is formed. The side of the opening may be vertical or tapered. Then, the contact layer 18 is formed by, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or sputtering. In this case, the contact layer 18 preferably contains a c-axis-oriented surface as its main component, but may also be polycrystalline or amorphous. The n-type impurity may be added during the formation of the contact layer 18 or after the formation of the contact layer 18 by ion implantation or diffusion.

[0043] The source electrode S and the drain electrode D are both made of a conductive material. The source electrode S and the drain electrode D are each provided on the contact layer 18. The source electrode S and the drain electrode D are formed so as to cover the entire upper surface of the contact layer 18. The source electrode S and the drain electrode D have a layered structure in which a titanium (Ti) layer, an aluminum (Al) layer, a nickel (Ni) layer, and a gold (Au) layer are sequentially layered from the contact layer 18 side, and are subjected to heat treatment as necessary.

[0044] The insulating film 19 is provided on the cap layer 17 and covers the source electrode S and the drain electrode D. The insulating film 19 has an opening 19H between the source electrode S and the drain electrode D. The width of the opening 19H (the opening width in the X-axis direction in FIG. 1) is, for example, less than 1 μm, more preferably 0.25 μm or less. The insulating film 19 is made of an insulating material. Examples of the insulating material include silicon nitride (SiN), silicon oxide (SiO ２ ), aluminum oxide (Al ２ O ３ ) and hafnium oxide (HfO ２The insulating film 19 may be a single layer film made of the above insulating material, or may be a multilayer film in which a plurality of layers made of the above insulating material are stacked.

[0045] The gate electrode G is provided on the cap layer 17. The gate electrode G is a Schottky gate that forms a Schottky junction by contacting the cap layer 17 through an opening 19H provided in the insulating film 19. The width of the gate electrode G that contacts the cap layer 17, in other words, the width of the opening 19H, is defined as the gate length Lg. In other words, the gate electrode G has a gate length Lg of less than 1 μm, more preferably 0.25 μm or less. The gate electrode G has a layered structure in which a nickel (Ni) layer and a gold (Au) layer are sequentially stacked from the cap layer 17 side.

[0046] An insulating film may be provided between the gate electrode G and the cap layer 17. In this case, a MIS (Metal-Insulator-Oxide) gate structure is formed. The insulating film may be made of silicon nitride (SiN), silicon oxide (SiO ２ ), aluminum oxide (Al ２ O ３ ) and hafnium oxide (HfO ２ ), nickel oxide (NiO), magnesium oxide (MgO), etc. The insulating film may be a single layer film made of the above material, or a multilayer film in which multiple layers made of the above material are stacked.

[0047] [Operations and Effects] The semiconductor device 1 of this embodiment has a layered structure in which a substrate 11, a buffer layer 12, a back barrier layer 13, a channel layer 14, a spacer layer 15, a barrier layer 16, and a cap layer 17 are layered in this order. The buffer layer 12 and the back barrier layer 13 are layered in this order between the substrate 11 and the channel layer 14. The buffer layer 12 and the back barrier layer 13 each contain an impurity. The buffer layer 12 has, in this order from the substrate 11 side, a first buffer layer 121, a second buffer layer 122, and a third buffer layer 123. The first buffer layer 121 has a first impurity concentration, and the third buffer layer 123 has a second impurity concentration. The back barrier layer 13 has a larger band gap than the channel layer 14 and a third impurity concentration. The impurity concentrations of the first buffer layer 121, the second buffer layer 122, and the back barrier layer 13 have a relationship of first impurity concentration < third impurity concentration < second impurity concentration. This improves the crystallinity of the buffer layer, suppresses the increase in crystal defects and trap sources caused by doping impurities, and improves the breakdown voltage, and further prevents electrons from leaking from the channel layer to the buffer layer side by the back barrier layer 13. This will be explained below.

[0048] In recent years, research and development of HEMTs using nitride semiconductors has been actively pursued. Compared with Si, GaAs, and the like, nitride semiconductors have a larger band gap and polarization specific to hexagonal crystals. Therefore, HEMTs using nitride semiconductors are expected to be transistors capable of low resistance, high breakdown voltage, and high-speed operation. Specifically, HEMTs are expected to be applied to power devices, radio frequency (RF) devices, and the like. For example, HEMTs using AlGaN for the barrier layer have been put to practical use in base stations for satellite communications or wireless communications. HEMTs using AlInN for the barrier layer are expected to achieve even higher output power because they can achieve a higher two-dimensional electron gas concentration than HEMTs using AlGaN for the barrier layer.

[0049] Compared with HEMTs currently in practical use for power devices, HEMTs used in RF devices are required to have smaller source-drain distances (Lsd) and gate lengths (Lg). A phenomenon known as drain-induced barrier lowering (DIBL) occurs when a large drain voltage is applied to a structure with a narrow gate length (Lg) (hereinafter referred to as a short gate structure). This phenomenon causes an increase in buffer leakage current and power consumption, as shown in FIG. 7.

[0050] Buffer leakage current can be suppressed by increasing the resistance of the buffer layer. However, doping the buffer layer with impurities (C or Fe) to increase its resistance increases the electron trap level and reduces the crystallinity, which increases the occurrence of current collapse and gate leakage. There is a trade-off between buffer leakage and current collapse / gate leakage.

[0051] For this reason, semiconductor elements have been developed in which the buffer layer 120 is made up of a low carbon concentration layer and a high carbon concentration layer, as in Comparative Example 1 shown in FIG. 8 , or in which a low carbon concentration layer is sandwiched between high carbon concentration layers of the buffer layer 120, as in Comparative Example 2 shown in FIG. 8 , thereby increasing the resistance of the buffer layer while maintaining crystallinity. However, in HEMTs with a short gate structure for RF devices, it has been difficult to achieve both sufficient suppression of buffer leakage and suppression of current collapse and gate leakage.

[0052] In contrast, in the present embodiment, as described above, the first buffer layer 121 having a first impurity concentration is provided on the substrate 11 side of the buffer layer 12, and the third buffer layer 123 having a second impurity concentration is provided on the channel layer 14 side. In addition, the back barrier layer 13 having a larger band gap than the channel layer 14 and a third impurity concentration is provided between the buffer layer 12 and the channel layer 14. The impurity concentrations of the first buffer layer 121, the second buffer layer 122, and the back barrier layer 13 have the relationship: first impurity concentration < third impurity concentration < second impurity concentration. This improves the crystallinity of the buffer layer and suppresses an increase in crystal defects and trap sources caused by doping with impurities, while improving the breakdown voltage. Furthermore, the back barrier layer 13 prevents electrons from leaking from the channel layer to the buffer layer. As a result, as shown in FIGS. 9 to 11 , the semiconductor device 1 (example) of this embodiment has reduced buffer leakage, gate leakage, and drain current degradation (current collapse) compared to a general semiconductor device (comparative example).

[0053] As described above, the semiconductor device 1 of this embodiment can simultaneously achieve low buffer leakage, low gate leakage, and low current collapse.

[0054] Next, modified examples and application examples of the present disclosure will be described. Note that components corresponding to those in the semiconductor device 1 of the above embodiment are given the same reference numerals and descriptions thereof will be omitted.

[0055] 12 is a schematic diagram illustrating an example of a cross-sectional configuration of a semiconductor device (semiconductor device 2) according to a modification of the present disclosure. FIG. 13 is a diagram illustrating an example of a carbon concentration profile of the buffer layer 12 and the back barrier layer 13 shown in FIG.

[0056] In the above embodiment, the buffer layer 12 has been described as having a three-layer structure including a first buffer layer 121, a second buffer layer 122, and a third buffer layer 123, each having a different impurity concentration, but the present invention is not limited to this. The semiconductor device of this modification omits the second buffer layer 122 and has a two-layer structure including the first buffer layer 121 and the third buffer layer 123. The impurity concentrations of the first buffer layer 121, the third buffer layer 123, and the back barrier layer 13 are higher than the carbon concentration of the first buffer layer 121 and lower than the carbon concentration of the third buffer layer 123, as shown in the above formula (1). Except for this, the semiconductor device 2 has substantially the same configuration as the semiconductor device 1 of the above embodiment.

[0057] Even with this configuration, the semiconductor device 2 of this modification can achieve the same effects as those of the above embodiment.

[0058] 3. Application Examples The semiconductor devices 1 and 2 of the present disclosure are applied to various products. For example, either the semiconductor device 1 or 2 of the present disclosure is applied to various electric circuits, various electronic devices, etc. Examples of the electronic devices include power devices and high-frequency devices. Specific examples include power supply devices and wireless communication devices. The power supply devices and wireless communication devices include electric circuits having, for example, power amplifiers and high-frequency switches.

[0059] For example, in fifth-generation mobile communications (5G), which use radio waves in a higher frequency band, radio wave propagation loss becomes greater. Therefore, it is desirable for wireless communication devices compatible with 5G to transmit radio waves at higher power. A wireless communication device (e.g., wireless communication device 1000 and wireless communication device 2000) to which either of the semiconductor devices 1 and 2 of the present disclosure is applied can improve device characteristics as described above, thereby enabling wireless communication with high output, low power consumption, and high reliability. In other words, the wireless communication device 1000 is more suitable for use in fifth-generation mobile communications (5G).

[0060] The wireless communication device may be mounted on any mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor). The wireless communication device may also be mounted on any surgical system, such as an endoscopic surgery system or a microsurgery system. Note that the wireless communication device is merely an example of an electronic device.

[0061] A wireless communication device (e.g., a wireless communication device 1000 and a wireless communication device 2000) to which either the semiconductor device 1 or 2 of the present disclosure is applied will be described with reference to Fig. 14 and Fig. 15. Fig. 14 is a perspective view showing a configuration example of the wireless communication device 1000 of Application Example 1. Fig. 15 is a block diagram showing a configuration example of the wireless communication device 2000 of Application Example 2.

[0062] 14 , the wireless communication device 1000 includes, for example, a substrate 1010, a plurality of edge antennas 1020, and a front-end component group 1030. This wireless communication device 1000 is an antenna-integrated module in which the edge antennas 1020 and the front-end component group 1030 are integrated and mounted as a single module. The edge antennas 1020 are formed in an array on the substrate 1010. The front-end component group 1030 includes a switch 1031, a low-noise amplifier 1032, a band-pass filter 1033, a power amplifier 1034, and the like. The front-end component group 1030 functions as an electric circuit.

[0063] Such a wireless communication device 1000 is used, for example, as a transceiver for communications. Either of the semiconductor devices 1 and 2 of the present disclosure may be applied to, for example, transistors constituting the switch 1031, the low-noise amplifier 1032, or the power amplifier 1034. This allows the wireless communication device 1000 to achieve the same effects as any of the above-described embodiments and modifications.

[0064] As shown in FIG. 15 , the wireless communication device 2000 includes an antenna (ANT) 2010, an antenna switch circuit 2020, a high power amplifier (HPA) 2030, a radio frequency integrated circuit (RFIC) 2040, a baseband unit 2050, an audio output unit (MIC) 2060, a data output unit (DT) 2070, and an interface unit (I / F) 2080.

[0065] The wireless communication device 2000 is used, for example, as a mobile phone system having multiple functions such as voice and data communication and LAN (local area network) connection. Either of the semiconductor devices 1 and 2 of the present disclosure may be applied to transistors that constitute, for example, an antenna switch circuit 2020, a high-power amplifier 2030, a high-frequency integrated circuit 2040, or a baseband unit 2050. This allows the wireless communication device 2000 to achieve the same effects as any of the above-described embodiments and modifications.

[0066] The technology according to the present disclosure has been described above by way of embodiments, modifications, and application examples. However, the technology according to the present disclosure is not limited to the above embodiments, and various modifications are possible.

[0067] Furthermore, not all of the configurations and operations described in the above embodiments are necessarily essential to the configurations and operations of the present disclosure. For example, among the components in the above embodiments, components that are not recited in the independent claims that represent the superordinate concept of the present disclosure should be understood as optional components.

[0068] Terms used throughout this specification and the appended claims should be interpreted as "open-ended" terms. For example, the terms "including" or "including" should be interpreted as "not limited to the manner described as including." The term "having" should be interpreted as "not limited to the manner described as having."

[0069] The terms used in this specification include terms that are used merely for the convenience of description and are not intended to limit the configuration or operation. For example, terms such as "right," "left," "upper," and "lower" merely indicate directions in the drawings to which reference is made. Furthermore, the terms "inner" and "outer" merely indicate directions toward and away from the center of a focused element, respectively. The same applies to similar terms and terms of a similar meaning.

[0070] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0071] The present technology can also be configured as follows. According to the present technology configured as follows, the crystallinity of the buffer layer is improved, and the breakdown voltage is increased while suppressing an increase in crystal defects and trap sources caused by doping with impurities, and further, a first barrier layer prevents electrons from leaking from the channel layer to the buffer layer. Therefore, it is possible to simultaneously achieve low buffer leakage, low gate leakage, and low current collapse. [1] A semiconductor device comprising: a substrate; a channel layer provided on one surface of the substrate; a buffer layer provided between the substrate and the channel layer and containing an impurity; and a first barrier layer provided between the buffer layer and the channel layer, containing the impurity and having a larger band gap than the channel layer, wherein the buffer layer has a first region on the substrate side having a first impurity concentration and a second region on the channel layer side having a second impurity concentration; the first barrier layer has a third impurity concentration; and the impurity concentrations of the first region, the second region, and the first barrier layer satisfy the relationship shown in Formula (1) below. (Equation 1) first impurity concentration<third impurity concentration<second impurity concentration (1) [2] The semiconductor device according to [1], wherein the buffer layer further has a third region between the first region and the second region and having a fourth impurity concentration, and the impurity concentrations of the first region, the second region, the third region, and the first barrier layer satisfy the relationship of the following equation (2): (Equation 2) first impurity concentration<third impurity concentration≦fourth impurity concentration<second impurity concentration (2) [3] The semiconductor device according to [1] or [2], wherein the buffer layer and the first barrier layer each contain carbon atoms as the impurity. [4] The semiconductor device according to [2] or [3], wherein the thicknesses of the first region, the second region, and the third region in the stacking direction satisfy the relationship of the following equation (3). (Equation 3) second region<first region≦third region (3) [5] The semiconductor device according to any one of [2] to [4], wherein the impurity concentration in each of the first region, the second region, and the third region changes stepwise or continuously. [6] The first region has a density of 1e17 cm －３the second region has an average carbon concentration of 1e17 cm －３ Larger 5e18cm －３ the third region has an average carbon concentration of 5e18 cm －３ Larger than 1e20cm －３ The semiconductor device according to any one of [2] to [5], wherein the first region has a thickness of 400 nm or less, the second region has a thickness of 400 nm to 1500 nm, and the third region has a thickness of 300 nm or less. [8] The semiconductor device according to any one of [1] to [7], further comprising: a second barrier layer provided on the side of the channel layer opposite to the substrate; and a gate electrode provided on the side of the second barrier layer opposite to the channel layer, wherein the gate length of the gate electrode is less than 1 μm. [9] The semiconductor device according to [8], further comprising: a spacer layer between the channel layer and the second barrier layer.

[10] The semiconductor device according to [8] or [9], further comprising: a cap layer between the second barrier layer and the gate electrode.

[11] The buffer layer is Al ｘ１ Ga （１－ｘ１） In ｙ１

[12] The semiconductor device according to any one of [1] to

[11] , wherein the buffer layer is made of gallium nitride.

[13] The first barrier layer is made of Al ｘ２ Ga （１－ｘ２） In ｙ２

[14] The semiconductor device according to any one of [1] to

[13] , wherein the first barrier layer is made of a nitride semiconductor containing aluminum.

[15] The semiconductor device according to any one of [1] to

[14] , wherein the substrate is a silicon substrate.

[16] An electric circuit comprising a semiconductor device comprising: a substrate; a channel layer provided on one surface side of the substrate; a buffer layer provided between the substrate and the channel layer and containing an impurity; and a first barrier layer provided between the buffer layer and the channel layer, containing the impurity and having a larger band gap than the channel layer, wherein the buffer layer has a first region having a first impurity concentration on the substrate side and a second region having a second impurity concentration on the channel layer side, and the first barrier layer has a third impurity concentration, and the impurity concentrations of the first region, the second region, and the first barrier layer satisfy the relationship of the following mathematical formula (1). (Equation 4) first impurity concentration<third impurity concentration<second impurity concentration (1)

[17] An electronic device comprising an electric circuit having a semiconductor device, the semiconductor device comprising: a substrate, a channel layer provided on one surface side of the substrate, a buffer layer provided between the substrate and the channel layer and containing an impurity, and a first barrier layer provided between the buffer layer and the channel layer, containing the impurity and having a larger band gap than the channel layer, the buffer layer having a first region on the substrate side and having a first impurity concentration and a second region on the channel layer side and having a second impurity concentration, the first barrier layer having a third impurity concentration, the impurity concentrations of the first region, the second region and the first barrier layer satisfy the relationship of the following equation (1): (Equation 5) first impurity concentration<third impurity concentration<second impurity concentration (1)

[0072] This application claims priority based on Japanese Patent Application No. 2024-097968, filed on June 18, 2024, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0073] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: a substrate; a channel layer provided on one surface side of the substrate; a buffer layer provided between the substrate and the channel layer and containing an impurity; and a first barrier layer provided between the buffer layer and the channel layer, containing the impurity and having a larger band gap than the channel layer, wherein the buffer layer has a first region on the substrate side having a first impurity concentration and a second region on the channel layer side having a second impurity concentration, and the first barrier layer has a third impurity concentration, and the impurity concentrations of the first region, the second region and the first barrier layer satisfy the relationship of the following mathematical formula (1): (Mathematical Formula 1) First impurity concentration<Third impurity concentration<Second impurity concentration (1) 2. The semiconductor device according to claim 1, wherein the buffer layer further includes a third region between the first region and the second region and having a fourth impurity concentration, and the impurity concentrations of the first region, the second region, the third region, and the first barrier layer have the relationship of the following mathematical formula (2): first impurity concentration<third impurity concentration≦fourth impurity concentration<second impurity concentration (2).

3. The semiconductor device according to claim 1, wherein said buffer layer and said first barrier layer each contain carbon atoms as said impurities.

4. The semiconductor device according to claim 2, wherein the thicknesses of the first region, the second region, and the third region in the stacking direction satisfy the relationship of the following formula (3): second region<first region≦third region (3).

5. The semiconductor device according to claim 2, wherein the impurity concentration in each of the first region, the second region, and the third region varies stepwise or continuously.

6. The first region is 1e17 cm －３ the second region has an average carbon concentration of 1e17 cm －３ Larger 5e18cm －３ the third region has an average carbon concentration of 5e18 cm －３ Larger than 1e20cm －３ 3. The semiconductor device according to claim 2, having an average carbon concentration of:

7. The semiconductor device according to claim 2, wherein the first region has a thickness of 400 nm or less, the second region has a thickness of 400 nm or more and 1500 nm or less, and the third region has a thickness of 300 nm or less.

8. The semiconductor device according to claim 1, further comprising: a second barrier layer provided on the opposite side of said channel layer from said substrate; and a gate electrode provided on the opposite side of said second barrier layer from said channel layer, wherein a gate length of said gate electrode is less than 1 μm.

9. The semiconductor device according to claim 8, further comprising a spacer layer between said channel layer and said second barrier layer.

10. The semiconductor device according to claim 8, further comprising a cap layer between said second barrier layer and said gate electrode.

11. The buffer layer is Al ｘ１ Ga （１－ｘ１） In ｙ１ 2. The semiconductor device according to claim 1, wherein the semiconductor device is made of a nitride semiconductor of N (0≦x1≦1, 0≦y1<1, 0<x1+y1≦1).

12. The semiconductor device according to claim 1, wherein said buffer layer is made of gallium nitride.

13. The first barrier layer is Al ｘ２ Ga （１－ｘ２） In ｙ２ 2. The semiconductor device according to claim 1, wherein the semiconductor device is made of a nitride semiconductor of N (0≦x2≦1, 0≦y2<1, 0<x2+y2≦1).

14. The semiconductor device according to claim 1, wherein the first barrier layer is made of a nitride semiconductor containing aluminum.

15. The semiconductor device according to claim 1, wherein the substrate is a silicon substrate.

16. An electric circuit comprising a semiconductor device comprising: a substrate; a channel layer provided on one surface side of the substrate; a buffer layer provided between the substrate and the channel layer and containing an impurity; and a first barrier layer provided between the buffer layer and the channel layer, containing the impurity and having a larger band gap than the channel layer, wherein the buffer layer has a first region on the substrate side having a first impurity concentration and a second region on the channel layer side having a second impurity concentration, and the first barrier layer has a third impurity concentration, and the impurity concentrations of the first region, the second region and the first barrier layer satisfy the relationship of the following mathematical formula (1): (Mathematical Formula 4) first impurity concentration<third impurity concentration<second impurity concentration (1) 17. An electronic device comprising an electric circuit having a semiconductor device, the semiconductor device comprising: a substrate; a channel layer provided on one surface side of the substrate; a buffer layer provided between the substrate and the channel layer and containing an impurity; and a first barrier layer provided between the buffer layer and the channel layer, containing the impurity and having a larger band gap than the channel layer, the buffer layer having a first region on the substrate side and having a first impurity concentration and a second region on the channel layer side and having a second impurity concentration, the first barrier layer having a third impurity concentration, and the impurity concentrations of the first region, the second region and the first barrier layer satisfy the relationship of the following mathematical formula (1): (Mathematical Formula 5) first impurity concentration<third impurity concentration<second impurity concentration (1)

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