Drive circuit

Abstract

An output-side circuit (12, 42, 52) comprises an on-drive circuit (16) that performs on-driving of a switching element (4, 4A, 4B) on the basis of a drive signal, an off-drive circuit (17) that performs off-driving of the switching element on the basis of the drive signal, and an output-side prohibition holding circuit (18, 43, 53) that detects the gate voltage of the switching element and outputs an output-side holding signal on the basis of the detection result. An input-side circuit (11) comprises an input-side prohibition holding circuit (22) that outputs an input-side holding signal, from when the drive signal switches from a condition of off-driving the switching element to a condition of on-driving the switching element, until a prescribed first holding period has elapsed, and a prohibition signal generation circuit (23) that, on the basis of a drive command signal, the output-side holding signal, and the input-side holding signal, generates an on prohibition signal that prohibits on-driving of the switching element, and outputs the on-prohibition signal to a counter arm-side drive circuit.

Description

Drive circuit CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2024-100514, filed on June 21, 2024, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a drive circuit that drives a switching element that constitutes one of upper and lower arms connected in series.

[0003] For example, in a drive circuit that drives two switching elements that constitute upper and lower arms connected in series in a half-bridge circuit, a dead time is provided during which both of the two switching elements are turned off in order to prevent short circuits between the upper and lower arms.In this specification, one of the upper and lower arms that is the target of drive by the drive circuit will sometimes be referred to as the "own arm," and the other arm that is not the target of drive by the drive circuit will sometimes be referred to as the "opposing arm."

[0004] In this case, the drive circuit drives the switching elements based on a drive command signal provided by an external control device including an MCU. The MCU is an abbreviation for Micro Controller Unit. In the above configuration, the control device sets the period during which both switching elements are turned off by shifting the timing of the on-drive of the upper and lower arms, and generates and transmits a drive command signal based on this to the drive circuit, thereby providing a dead time.

[0005] In the above configuration, if the period during which both switching elements are turned off is set longer than necessary in consideration of various variations, the dead time will be longer and losses will increase. To improve this, it is possible to adopt a control method that prohibits the switching elements of the opposing arm from being turned on, i.e., drives them off, during the period during which the switching elements of the own arm are turned on. An example of such a control method is the technology disclosed in Patent Document 1. Hereinafter, the technology disclosed in Patent Document 1 may be referred to as the prior art.

[0006] In the conventional technology, when it is determined that the switching element of its own arm is off by monitoring the gate voltage, current state, etc. of the switching element of its own arm, it permits the drive circuit that drives the switching element of the opposing arm to turn on, in other words, it transmits a signal to cancel the prohibition of on-drive. With such conventional technology, it is possible to control so as to shorten the dead time.

[0007] Patent No. 3336488

[0008] In the prior art, during short-pulse drive in which the pulse width of the drive command signal issuing an ON command is short, for example, on the order of several hundred nanoseconds, the above-described control may not be able to keep up, resulting in a problem in which the switching elements of the upper and lower arms are simultaneously turned ON. Below, such a problem will be described using an example in which, during short-pulse drive, the drive command signal for the arm in question changes from a state issuing an OFF command, to a state issuing an ON command, and then back to a state issuing an OFF command.

[0009] In the prior art, during short pulse driving, even if the drive command signal input to the drive circuit of the own arm is at a level commanding ON, if the output of the drive circuit is still in an operating state of OFF driving, the drive circuit of the opposing arm is permitted to be driven ON. However, in this state, in the drive circuit of the own arm, the drive command signal commanding ON is transmitted to subsequent stages while various delays occur internally, and as a result, the switching element of the own arm is driven ON with a delay.

[0010] At this time, the drive circuit for the opposing arm is enabled to turn on the switching elements, causing both the upper and lower arm switching elements to be in an on-drive operating state, resulting in a short circuit between the upper and lower arms. This problem can be solved by lengthening the dead time more than necessary, but doing so makes it difficult to drive with a shorter on-time, resulting in another problem of poor controllability.

[0011] An object of the present disclosure is to provide a drive circuit that can prevent the occurrence of a problem in which the upper and lower arms are simultaneously turned on while maintaining good controllability.

[0012] In one aspect of the present disclosure, the drive circuit is a drive circuit that drives a switching element that constitutes one of upper and lower arms connected in series. In this case, the one arm is referred to as a local arm, and the other arm is referred to as an opposing arm. The drive circuit includes: an input-side circuit that generates a drive signal for driving the switching element based on a drive command signal applied from an external device and an on-inhibit signal output from a drive circuit on the opposing arm side; an output-side circuit that operates on a power supply different from that of the input-side circuit and drives the switching element based on the drive signal; and a signal transmission circuit that transmits signals between the input-side circuit and the output-side circuit.

[0013] The output side circuit includes an ON drive circuit that drives the switching element ON by charging the gate charge of the switching element based on the drive signal, an OFF drive circuit that drives the switching element OFF by discharging the gate charge of the switching element based on the drive signal, and an output side inhibit hold circuit that detects the gate voltage of the switching element and outputs an output side hold signal based on the detection result.

[0014] The input side circuit includes an input side prohibition holding circuit that outputs an input side hold signal until a predetermined first hold period has elapsed since the drive signal switches from a state that drives the switching element off to a state that drives the switching element on, and an prohibition signal generation circuit that generates the on prohibition signal that prohibits the on driving of the switching element based on the drive command signal, the output side hold signal, and the input side hold signal, and outputs the on prohibition signal to the drive circuit on the opposing arm side.

[0015] According to the above configuration, a drive command signal commanding a relatively short time ON is transmitted with a delay from the input circuit to the output circuit within the drive circuit, thereby ensuring that an ON-prohibition signal is transmitted to the drive circuit on the opposing arm during a period when the output circuit may be driving the switching element ON. This control prevents short-circuiting of the upper and lower arms without unnecessarily lengthening the dead time. Therefore, according to the above configuration, it is possible to prevent the occurrence of problems with the upper and lower arms being turned ON simultaneously while maintaining good controllability.

[0016] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which Fig. 1 is a diagram schematically illustrating the configuration of a drive circuit according to a first embodiment, Fig. 2 is a timing chart schematically illustrating the operating waveforms of each part during short pulse driving according to the first embodiment, Fig. 3 is a timing chart schematically illustrating the operating waveforms of each part during normal pulse driving according to the first embodiment, Fig. 4 is a diagram schematically illustrating the configuration of a drive circuit according to a comparative example, Fig. 5 is a timing chart schematically illustrating the operating waveforms of each part during short pulse driving according to the comparative example, Fig. 6 is a timing chart schematically illustrating the operating waveforms of each part during normal pulse driving according to the comparative example, and Fig. 7 is a timing chart schematically illustrating the operating waveforms of each part during normal pulse driving according to the comparative example. 10 is a diagram schematically showing the configuration of a drive circuit according to a third embodiment, FIG. 11 is a timing chart schematically showing the operating waveforms of each part during short pulse driving according to the third embodiment, and FIG. 12 is a timing chart schematically showing the operating waveforms of each part during normal pulse driving according to the third embodiment.

[0017] Hereinafter, several embodiments will be described with reference to the drawings. Note that substantially the same components in each embodiment will be denoted by the same reference numerals and the description thereof will be omitted. (First Embodiment) Hereinafter, the first embodiment will be described with reference to FIGS. 1 to 6.

[0018] 1, drive circuits 1A and 1B of this embodiment drive switching elements 4A and 4B that constitute upper and lower arms connected in series between a pair of DC power supply lines 2 and 3. In this case, drive circuit 1A drives switching element 4A that constitutes the upper arm, and drive circuit 1B drives switching element 4B that constitutes the lower arm. The upper and lower arms including switching elements 4A and 4B constitute, for example, one phase of a three-phase inverter circuit.

[0019] The drive circuits 1A and 1B drive switching elements that constitute one of the upper and lower arms connected in series, and they have the same configuration. The switching elements 4A and 4B also have the same configuration. Therefore, in this specification, when it is not necessary to distinguish between the drive circuits 1A and 1B and the switching elements 4A and 4B, the drive circuits 1A and 1B and the switching elements 4A and 4B will be referred to collectively with the alphabet suffix omitted. Furthermore, in this specification, the various components and signals provided corresponding to the drive circuits 1A and 1B and the switching elements 4A and 4B will be distinguished by adding the same alphabet suffix to the reference numerals, and when it is not necessary to distinguish between them, the drive circuits 1A and 1B and the switching elements 4A and 4B will be referred to collectively with the alphabet suffix omitted.

[0020] In this case, when viewed from the perspective of drive circuit 1A, the configuration on the side of switching element 4A, which is the drive target, is the own arm, and the configuration on the side of switching element 4B, which is not the drive target, is the opposing arm. Also, in this case, when viewed from the perspective of drive circuit 1B, the configuration on the side of switching element 4B, which is the drive target, is the own arm, and the configuration on the side of switching element 4A, which is not the drive target, is the opposing arm.

[0021] The switching element 4 is a power device, and in this case, for example, an N-channel MOS transistor. The drain of the switching element 4A is connected to the high-potential side DC power supply line 2. The source of the switching element 4A is connected to the drain of the switching element 4B. The source of the switching element 4B is connected to the low-potential side DC power supply line 3. The gate of the switching element 4A is connected to terminals P1, P2, and P3 of the drive circuit 1A via gate resistors R1A, R2A, and R3A. The gate of the switching element 4B is connected to terminals P1, P2, and P3 of the drive circuit 1B via gate resistors R1B, R2B, and R3B.

[0022] The control device 5 includes, for example, an MCU and a PMIC, and controls the operation of the drive circuit 1. PMIC is an abbreviation for Power Management IC. The control device 5 generates and outputs a drive command signal S1A that commands the drive of the upper arm switching element 4A and a drive command signal S1B that commands the drive of the lower arm switching element 4B. The drive circuit 1A drives the switching element 4A based on the drive command signal S1A provided by the control device 5. The drive circuit 1B drives the switching element 4B based on the drive command signal S1B provided by the control device 5.

[0023] The drive command signal S1A is a binary signal that commands the switching element 4A to be turned on when at a high level and commands the switching element 4A to be turned off when at a low level. The drive command signal S1B is a binary signal that commands the switching element 4B to be turned on when at a high level and commands the switching element 4B to be turned off when at a low level.

[0024] The drive circuit 1 is configured as an IC and includes an input circuit 11, an output circuit 12, and a signal transmission circuit 13. IC is an abbreviation for Integrated Circuit. The input circuit 11 generates a drive signal S3 for driving the switching element 4 based on a drive command signal S1 applied from the outside and an on-inhibit signal S2 output from the drive circuit 1 on the opposing arm side.

[0025] The drive signal S3 is a binary signal. In this case, a high level of the drive signal S3 corresponds to a state in which the switching element 4 is turned on, and a low level of the drive signal S3 corresponds to a state in which the switching element 4 is turned off. The on-inhibit signal S2 is a binary signal. In this case, the on-inhibit signal S2 is a signal that is valid when it is at a low level, i.e., a low-active signal. The output-side circuit 12 operates on a power supply different from that of the input-side circuit 11, and drives the switching element 4 based on the drive signal S3.

[0026] The signal transmission circuit 13 transmits signals between the input circuit 11 and the output circuit 12. In this case, the input circuit 11 and the output circuit 12 are configured as separate chips. Specifically, the input circuit 11 is configured as a low-voltage chip with a relatively low power supply voltage, and the output circuit 12 is configured as a high-voltage chip with a relatively high power supply voltage. Therefore, in this embodiment, the signal transmission circuit 13 is configured to include insulated communication circuits 14 and 15 that perform insulated communication between the input circuit 11 and the output circuit 12, and to transmit signals via insulated communication by these insulated communication circuits 14 and 15.

[0027] The output side circuit 12 includes an ON drive circuit 16, an OFF drive circuit 17, and an output side prohibition holding circuit 18. A drive signal S4 output from the insulated communication circuit 14 of the signal transmission circuit 13 is input to the ON drive circuit 16, the OFF drive circuit 17, and the output side prohibition holding circuit 18. The drive signal S4 is a signal having the same logic as the binary drive signal S3 output from the input side circuit 11, but is delayed by the delay time in the insulated communication circuit 14 of the signal transmission circuit 13 relative to the drive signal S3.

[0028] The ON drive circuit 16 drives the switching element 4 to ON by charging the gate charge of the switching element 4 based on the drive signal S4. The output terminal of the ON drive circuit 16 is connected to the terminal P1. Specifically, the ON drive circuit 16 drives the switching element 4 to ON when the drive signal S4 is at a high level. The OFF drive circuit 17 drives the switching element 4 to OFF by discharging the gate charge of the switching element 4 based on the drive signal S4. The output terminal of the OFF drive circuit 17 is connected to the terminal P2. Specifically, the OFF drive circuit 17 drives the switching element 4 to OFF when the drive signal S4 is at a low level.

[0029] The output inhibit holding circuit 18 detects the gate voltage of the switching element 4 and outputs the output hold signal S5 based on the detection result. The output hold signal S5 is a binary signal. In this case, the output hold signal S5 is a signal that is valid when it is at a low level, that is, a low active signal. Therefore, "the output inhibit holding circuit outputs the output hold signal" means that the output hold signal becomes low level.

[0030] The output-side inhibit holding circuit 18 includes a gate voltage detection circuit 19. The gate voltage detection circuit 19 detects the gate voltage of the switching element 4 based on the signal at terminal P3 and outputs a binary signal representing the detection result. The output signal of the gate voltage detection circuit 19 goes low when the gate voltage of the switching element 4 is equal to or higher than a predetermined threshold voltage, and goes high when the gate voltage is below the threshold voltage.

[0031] The above-mentioned threshold voltage value may be set appropriately based on the gate threshold voltage of the switching element 4. In this case, the output signal of the gate voltage detection circuit 19 becomes the output-side hold signal S5. The output-side hold signal S5 output from the output-side prohibition hold circuit 18 is provided to the insulated communication circuit 15 of the signal transmission circuit 13.

[0032] The input-side circuit 11 includes a drive signal generation circuit 21, an input-side prohibition holding circuit 22, and an prohibition signal generation circuit 23. The drive signal generation circuit 21 generates a drive signal S3 based on the drive command signal S1 and the on-prohibition signal S2. Specifically, the drive signal generation circuit 21 is an AND circuit, one input terminal of which is connected to terminal P4 and the other input terminal of which is connected to terminal P5. The drive command signal S1 output from the control device 5 is applied to terminal P4. The on-prohibition signal S2 output from the drive circuit 1 on the opposing arm side is applied to terminal P5.

[0033] The drive signal generation circuit 21 generates and outputs a drive signal S3 representing the logical product of the drive command signal S1 and the on-inhibit signal S2. The drive signal S3 output from the drive signal generation circuit 21 is provided to an input-side inhibit holding circuit 22 and also to the insulated communication circuit 14 of the signal transmission circuit 13. The input-side inhibit holding circuit 22 outputs an input-side hold signal S6 until a predetermined first hold period T1 has elapsed after the drive signal S3 switches from a low level, which drives the switching element 4 off, to a high level, which drives the switching element 4 on.

[0034] The input hold signal S6 is a binary signal. In this case, the input hold signal S6 is a signal that is valid when it is at a high level, that is, a high-active signal. Therefore, "the input inhibit hold circuit outputs the input hold signal" means that the input hold signal becomes high level.

[0035] In this case, the drive signal S3 is input to the input prohibition holding circuit 22. The input prohibition holding circuit 22 generates an input hold signal S6, which is a signal that holds the drive signal S3 for a fixed period of time. Specifically, the input prohibition holding circuit 22 generates an input hold signal S6 that rises in synchronization with the drive signal S3 and falls a fixed period later than the drive signal S3. The period from the rising edge to the falling edge of the input hold signal S6 generated by the input prohibition holding circuit 22 corresponds to the first hold period T1 described above.

[0036] The inhibit signal generating circuit 23 generates an on-inhibit signal S2 that inhibits on-driving of the switching element 4 based on the drive command signal S1, the input-side hold signal S6, and the output-side hold signal S7, and outputs the on-inhibit signal S2 to the drive circuit 1 on the opposing arm side. Specifically, the inhibit signal generating circuit 23 is an AND circuit having two inverting input terminals and one non-inverting input terminal. The drive command signal S1 is supplied to one inverting input terminal of the inhibit signal generating circuit 23, and the input-side hold signal S6 is supplied to the other inverting input terminal.

[0037] The output-side hold signal S7 output from the insulated communication circuit 15 of the signal transmission circuit 13 is input to the non-inverting input terminal of the inhibit signal generation circuit 23. The output-side hold signal S7 is a signal having the same logic as the binary output-side hold signal S5 output from the output circuit 12, but is delayed relative to the output-side hold signal S5 by the delay time in the insulated communication circuit 15 of the signal transmission circuit 13. The inhibit signal generation circuit 23 generates and outputs an on-inhibit signal S2 that represents the logical product of a signal obtained by inverting the logic of the drive command signal S1, a signal obtained by inverting the logic of the input-side hold signal S6, and the output-side hold signal S7.

[0038] The output terminal of the inhibit signal generating circuit 23 is connected to terminal P6, which is in turn connected to terminal P5 of the driver circuit 1 on the opposing arm side. As will be described in detail later, in the above configuration, the output inhibit holding circuit 18 and the input inhibit holding circuit 22 are configured to generate the output hold signal S5 and the input hold signal S6 so that the period during which the output hold signal S7 is output and the period during which the input hold signal S6 is output overlap.

[0039] Next, the operation of the above configuration will be described with reference to the timing charts of Figures 2 and 3. During the period from time ta when the drive command signal S1 changes from low level to high level to time tb when the drive command signal S1 changes from high level to low level, that is, during short pulse drive when the pulse width of the drive command signal S1 is short, for example, on the order of several hundred nanoseconds, the operating waveforms of the various components are as shown in Figure 2. During normal pulse drive when the pulse width of the drive command signal S1 is longer than during short pulse drive, the operating waveforms of the various components are as shown in Figure 3.

[0040] The operation of each part when the drive command signal S1 for the own arm changes from a low level indicating an OFF state, to a high level indicating an ON state, and back to a low level indicating an OFF state will be described below. In this case, the configuration on the switching element 4A side is the own arm, and the configuration on the switching element 4B side is the opposing arm.

[0041] [1] Operation of the Own Arm The drive signal 3A remains low at time ta, but then changes to high at time t3 when the on-inhibit signal S2A changes from low to high. At this time, the input-side hold signal S6A changes from low to high. The input-side hold signal S6A changes to low when the first hold period T1 has elapsed since time t3. The drive signal S4A changes to high at time t4, when a delay time d1 has elapsed since time t3. The delay time d1 corresponds to a circuit delay in the isolated communication circuit 14, etc.

[0042] The gate voltage VgA of the switching element 4A starts to rise when a delay time d2 has elapsed since time t4 when the drive signal S4A goes high. The delay time d2 corresponds to a circuit delay in the ON drive circuit 16, an element delay in the gate resistor R1A and the gate of the switching element 4A, etc. The switching element 4A turns on at time t5 when the gate voltage reaches the gate threshold voltage.

[0043] At this time, output-side hold signal S5A changes from high to low. Output-side hold signal S7A changes to low when delay time d3 has elapsed since time t5. Delay time d3 corresponds to a circuit delay in isolated communication circuit 15. Note that the timing at which output-side hold signal S7A changes to low occurs before the timing at which input-side hold signal S6A changes to low. In other words, in this case, the period during which output-side hold signal S7A is output and the period during which input-side hold signal S6A is output overlap.

[0044] At time tb when the drive command signal S1A changes from high to low, the on-inhibit signal S2A and the drive signal S3A change to low. The drive signal S4A changes to low when a delay time d4 has elapsed since time tb. The delay time d4 corresponds to a circuit delay in the insulated communication circuit 14. The gate voltage VgA of the switching element 4A begins to decrease when a delay time d5 has elapsed since the drive signal S4A changed to low.

[0045] Delay time d5 corresponds to the circuit delay in off drive circuit 17, the element delay in gate resistor R2A and the gate of switching element 4A, etc. Switching element 4A turns off at time t6 when its gate voltage reaches the gate threshold voltage. At this time, output hold signal S5A changes from low to high. Output hold signal S7A changes to high when delay time d6 has elapsed since time t6. Delay time d6 corresponds to the circuit delay in isolated communication circuit 15, etc.

[0046] [2] Operation of the Opposing Arm Side The drive command signal S1B changes from high to low at time ta. At this time, the on-inhibit signal S2B and drive signal S3B change from high to low. The drive signal S4B changes to low at time t1, which is a delay time d4 after time ta. The gate voltage VgB of the switching element 4B begins to decrease when a delay time d5 has elapsed since time t1, when the drive signal S4B changed to low.

[0047] Switching element 4B turns off at time t2 when its gate voltage reaches the gate threshold voltage. At this time, output-side holding signal S5B changes from low to high. Output-side holding signal S7B changes to high at time t3, which is a delay time d6 after time t2. Thereafter, drive command signal S1B changes from low to high at time tb. Drive signal S3B remains low at time tb, but then changes to high at time t7 when on-inhibit signal S2B changes from low to high.

[0048] At this time, the input-side hold signal S6B transitions from low to high. The input-side hold signal S6B transitions to low when the first hold period T1 has elapsed since time t7. The drive signal S4B transitions to high at time t8, which is when delay time d1 has elapsed since time t7. The gate voltage VgB of the switching element 4B begins to rise when delay time d2 has elapsed since time t8, when the drive signal S4B transitioned to high.

[0049] Switching element 4B turns on at time t9 when its gate voltage reaches the gate threshold voltage. At this time, output hold signal S5B changes from high to low. Output hold signal S7B changes to low when delay time d3 has elapsed from time t9. Note that the timing at which output hold signal S7B changes to low occurs before the timing at which input hold signal S6B changes to low. In other words, in this case, the period during which output hold signal S7B is output and the period during which input hold signal S6B is output overlap.

[0050] As described above, with the above configuration, the on-inhibit signal S2B is output to the opposite arm drive circuit 1B from the time when the on-drive condition is satisfied in the input side circuit 11, that is, from the time ta when the drive command signal S1A changes from low level to high level, and this state is maintained for a certain period. Also, with the above configuration, the first hold period T1 during which the output of the input side hold signal S6 is maintained is set to a period equivalent to the sum of the delay times d1, d2, and d3.

[0051] According to the present embodiment described above, the drive command signal S1, which commands ON for a relatively short time, is transmitted with a delay from the input circuit 11 to the output circuit 12 inside the drive circuit 1, so that the ON-inhibit signal S2 is reliably transmitted to the drive circuit 1 on the opposing arm during a period when the output circuit 12 may turn ON the switching element 4. By implementing such control, a short circuit between the upper and lower arms is prevented without unnecessarily lengthening the dead time. Therefore, according to the present embodiment, it is possible to prevent the occurrence of a problem in which the upper and lower arms are simultaneously turned ON while maintaining good controllability.

[0052] The effects obtained by this embodiment become clearer when compared with a comparative example in which some components of the embodiment are omitted. As shown in Figure 4, drive circuit 31 of the comparative example differs from drive circuit 1 of this embodiment in that it includes input circuit 32 instead of input circuit 11. Input circuit 32 differs from input circuit 11 in that it does not include input prohibition holding circuit 22 and includes prohibition signal generation circuit 33 instead of prohibition signal generation circuit 23.

[0053] The prohibition signal generating circuit 33 is an AND circuit, the inverting input terminal of which receives the drive command signal S1, and the non-inverting input terminal of which receives the output-side hold signal S7 output from the insulating communication circuit 15 of the signal transmission circuit 13. The prohibition signal generating circuit 33 generates and outputs an on-prohibition signal S2 that represents the logical product of the drive command signal S1 and the output-side hold signal S7.

[0054] As shown in the timing charts of Figures 3 and 6, the configuration of this embodiment and the configuration of the comparative example do not cause the problem of the upper and lower arms being turned on simultaneously during normal pulse driving. However, as shown in the timing chart of Figure 5, in the configuration of the comparative example, during short pulse driving, even when the drive command signal S1A input to the drive circuit 1A of the own arm is at a high level, there is a period during which the gate voltage VgA of the switching element 4A is less than the gate threshold value, and as a result, there is a period during which the on-inhibit signal S2B is not output to the drive circuit 1B of the opposing arm.

[0055] At this time, in the drive circuit 1A of the own arm, the drive command signal S1A commanding ON is transmitted to subsequent stages despite various internal delays, resulting in the switching element 4A of the own arm being turned ON with a delay. Meanwhile, in the drive circuit 1B of the opposite arm, ON drive is permitted at this time, so the switching element 4B is turned ON. As a result, both the upper and lower arm switching elements 4A, 4B are in an ON drive operating state, causing a short circuit between the upper and lower arms. This problem can be solved by making the dead time longer than necessary, but doing so makes it difficult to drive with a shorter ON time, resulting in another problem of poor controllability.

[0056] In contrast to this, in the configuration of this embodiment, an on-inhibit signal S2B is output to the drive circuit 1B on the opposing arm side as soon as possible after a high-level drive command signal S1A is given, and the output is maintained for a certain period determined based on an internal delay time. Therefore, as shown in the timing chart of FIG. 2, the problem of the upper and lower arms being turned on simultaneously does not occur even during short pulse drive.

[0057] Second Embodiment A second embodiment will now be described with reference to Figures 7 to 9. As shown in Figure 7, drive circuits 41A and 41B of this embodiment differ from drive circuits 1A and 1B of the first embodiment in that they include an output circuit 42 instead of output circuit 12. Output circuit 42 differs from output circuit 12 in that they include an output prohibit holding circuit 43 instead of output prohibit holding circuit 18. Output prohibit holding circuit 43 includes an AND circuit 44 in addition to a gate voltage detection circuit 19 similar to that of output prohibit holding circuit 18.

[0058] The drive signal S4 is input to the inverting input terminal of the AND circuit 44, and the signal S5 output from the gate voltage detection circuit 19 is input to its non-inverting input terminal. The AND circuit 44 generates and outputs a signal representing the logical product of a signal obtained by inverting the logic of the drive signal S4 and the signal S5. In this case, the signal output from the AND circuit 44 becomes the output-side hold signal S41. With this configuration, the output-side inhibit hold circuit 43 starts outputting the output-side hold signal S41 from the point in time when the drive signal S4 switches from a low level representing an OFF state of the switching element 4 to a high level representing an ON state.

[0059] Next, the operation of the above configuration will be described with reference to the timing charts of Figures 8 and 9. The operating waveforms of each part during short pulse driving are, for example, as shown in Figure 8. The operating waveforms of each part during normal pulse driving are, for example, as shown in Figure 9. Below, we will explain the operation of each part when the drive command signal S1 for the own arm changes from a low level indicating an OFF command, to a high level indicating an ON command, and then back to a low level indicating an OFF command. In this case, the configuration on the switching element 4A side is considered to be the own arm, and the configuration on the switching element 4B side is considered to be the opposing arm.

[0060] [1] Operation of the Own Arm The drive signal 3A remains low at time ta, but then changes to high at time t3 when the on-inhibit signal S2A changes from low to high. At this time, the input-side hold signal S6A changes from low to high. The input-side hold signal S6A changes to low when the first hold period T41 has elapsed since time t3.

[0061] Drive signal S4A transitions to high level when delay time d1 has elapsed since time t3. At this time, output hold signal S41A transitions from high to low. Output hold signal S7A transitions to low level when delay time d3 has elapsed since time t4. Note that the timing at which output hold signal S7A transitions to low level occurs before the timing at which input hold signal S6A transitions to low level. In other words, in this case, the period during which output hold signal S7A is output and the period during which input hold signal S6A is output overlap.

[0062] The gate voltage VgA of the switching element 4A begins to rise when a delay time d2 has elapsed since the drive signal S4A went high. The switching element 4A turns on at time t5 when the gate voltage reaches the gate threshold voltage. At this time, the signal S5A goes from high to low. At time tb when the drive command signal S1A goes from high to low, the on-inhibit signal S2A and the drive signal S3A go low.

[0063] Drive signal S4A transitions to low level when delay time d4 has elapsed since time tb. Gate voltage VgA of switching element 4A begins to decrease when delay time d5 has elapsed since drive signal S4A transitioned to low level. Switching element 4A turns off at time t6 when its gate voltage reaches the gate threshold voltage. At this time, signal S5A and output-side holding signal S41A transition from low level to high level. Output-side holding signal S7A transitions to high level at time t7, when delay time d6 has elapsed since time t6.

[0064] [2] Operation of the Opposing Arm Side The drive command signal S1B changes from high to low at time ta. At this time, the on-inhibit signal S2B and drive signal S3B change from high to low. The drive signal S4B changes to low at time t1, which is a delay time d4 after time ta. The gate voltage VgB of the switching element 4B begins to decrease when a delay time d5 has elapsed since time t1, when the drive signal S4B changed to low.

[0065] Switching element 4B turns off at time t2 when its gate voltage reaches the gate threshold voltage. At this time, signal S5B and output-side holding signal S41B change from low to high. Output-side holding signal S7B changes to high at time t3, which is a delay time d6 after time t2. Thereafter, drive command signal S1B changes from low to high at time tb. Drive signal S3B remains low at time tb, but then changes to high at time t7 when on-inhibit signal S2B changes from low to high.

[0066] At this time, the input-side hold signal S6B changes from low to high. Note that the input-side hold signal S6B changes to low when the first hold period T41 has elapsed since time t6. The drive signal S4B changes to high at time t8, when the delay time d1 has elapsed since time t7. At this time, the output-side hold signal S41B changes from high to low.

[0067] Output hold signal S7B goes low when delay time d3 has elapsed since time t8. The timing at which output hold signal S7B goes low occurs before the timing at which input hold signal S6B goes low. In other words, in this case, the period during which output hold signal S7B is output and the period during which input hold signal S6B is output overlap.

[0068] The gate voltage VgB of the switching element 4B starts to rise when a delay time d2 has elapsed since the drive signal S4B went high. The switching element 4B turns on at time t9 when the gate voltage reaches the gate threshold voltage. At this time, the signal S5B goes from high to low.

[0069] As described above, with the above configuration, the on-inhibit signal S2B is output to the opposing arm drive circuit 1B from the time point when the on-drive condition is satisfied in the input side circuit 11, that is, from the time point ta when the drive command signal S1A changes from low level to high level, and this state is maintained for a certain period. Also, with the above configuration, the first hold period T41 during which the output of the input side hold signal S6 is maintained is set to a period equivalent to the sum of the delay times d1 and d3.

[0070] The present embodiment described above not only provides the same effects as the first embodiment, but also the following effect. That is, according to the present embodiment, the first hold period T41, during which the output of the input hold signal S6 is held, is shortened compared to the first hold period T1 in the first embodiment. Therefore, according to the present embodiment, it is possible to perform on-drive with a shorter pulse width while preventing the occurrence of short circuits between the upper and lower arms, thereby improving controllability.

[0071] Third Embodiment A third embodiment will now be described with reference to Figures 10 to 12. As shown in Figure 10, drive circuits 51A and 51B of this embodiment differ from drive circuits 41A and 41B of the second embodiment in that they include an output circuit 52 instead of output circuit 42. Output circuit 52 differs from output circuit 42 in that they include an output prohibition holding circuit 53 instead of output prohibition holding circuit 43. Output prohibition holding circuit 53 differs from output prohibition holding circuit 43 in that they additionally include a hold circuit 54 and an AND circuit 55 instead of AND circuit 44.

[0072] The drive signal S4 is input to the holding circuit 54. The holding circuit 54 outputs the signal S51 until a predetermined period T51 has elapsed since the drive signal S4 switches from a low level, which drives the switching element 4 to an ON state, to a high level, which drives the switching element 4 to an OFF state.

[0073] The period T51 can be set to a period corresponding to a delay time equivalent to the circuit delay in the ON drive circuit 16, the element delay in the gate resistor R1 and the gate of the switching element 4, the circuit delay in the gate voltage detection circuit 19, etc. The signal S51 is a binary signal. In this case, the signal S51 is a signal that is valid when at a high level, that is, a high-active signal. Therefore, "the holding circuit 54 outputs the signal S51" means that the signal S51 becomes a high level.

[0074] The AND circuit 55 has two inverting input terminals and one non-inverting input terminal. The drive signal S4 is applied to one inverting input terminal of the AND circuit 55, and the signal S51 output from the holding circuit 54 is applied to the other inverting input terminal. The signal S5 output from the gate voltage detection circuit 19 is input to the non-inverting input terminal of the AND circuit 55. The AND circuit 55 generates and outputs a signal representing the logical AND of the drive signal S4, the signal S51, and the signal S5. In this case, the signal output from the AND circuit 55 becomes the output-side holding signal S52.

[0075] With this configuration, the output side prohibition holding circuit 53 holds the output of the output side holding signal S52 until a predetermined second holding period T2 has elapsed after the drive signal S4 switches from a low level, which indicates that the switching element 4 is turned off, to a high level, which indicates that the switching element 4 is turned on.

[0076] Next, the operation of the above configuration will be described with reference to the timing charts of Figures 11 and 12. The operating waveforms of each part during short pulse driving are, for example, as shown in Figure 11. The operating waveforms of each part during normal pulse driving are, for example, as shown in Figure 12. Below, we will explain the operation of each part when the drive command signal S1 for the own arm changes from a low level indicating an OFF command, to a high level indicating an ON command, and then back to a low level indicating an OFF command. In this case, the configuration on the switching element 4A side is considered to be the own arm, and the configuration on the switching element 4B side is considered to be the opposing arm.

[0077] [1] Operation of the Own Arm The drive signal 3A remains low at time ta, but then changes to high at time t3 when the on-inhibit signal S2A changes from low to high. At this time, the input-side hold signal S6A changes from low to high. The input-side hold signal S6A changes to low when the first hold period T41 has elapsed since time t3.

[0078] Drive signal S4A transitions to high level at time t4, which is a delay time d1 after time t3. At this time, signal S51A transitions from low level to high level, and output hold signal S52A transitions from high level to low level. Signal S51A transitions to low level when period T51 has elapsed since time t4. Output hold signal S7A transitions to low level when delay time d3 has elapsed since time t4. The timing at which output hold signal S7A transitions to low level occurs before the timing at which input hold signal S6A transitions to low level. In other words, in this case, the period during which output hold signal S7A is output and the period during which input hold signal S6A is output overlap.

[0079] The gate voltage VgA of the switching element 4A begins to rise when a delay time d2 has elapsed since the drive signal S4A went high. The switching element 4A turns on at time t5 when the gate voltage reaches the gate threshold voltage. At this time, the signal S5A goes from high to low. At time tb when the drive command signal S1A goes from high to low, the on-inhibit signal S2A and the drive signal S3A go low.

[0080] Drive signal S4A transitions to low level when delay time d4 has elapsed since time tb. Gate voltage VgA of switching element 4A begins to decrease when delay time d5 has elapsed since drive signal S4A transitioned to low level. Switching element 4A turns off at time t6 when its gate voltage reaches the gate threshold voltage. At this time, signal S5A and output-side holding signal S52A transition from low level to high level. Output-side holding signal S7A transitions to high level when delay time d6 has elapsed since time t6.

[0081] [2] Operation of the Opposing Arm Side The drive command signal S1B changes from high to low at time ta. At this time, the on-inhibit signal S2B and drive signal S3B change from high to low. The drive signal S4B changes to low at time t1, which is a delay time d4 after time ta. The gate voltage VgB of the switching element 4B begins to decrease when a delay time d5 has elapsed since time t1, when the drive signal S4B changed to low.

[0082] Switching element 4B turns off at time t2 when its gate voltage reaches the gate threshold voltage. At this time, signal S5B and output-side holding signal S52B change from low to high. Output-side holding signal S7B changes to high at time t3, which is a delay time d6 after time t2. Thereafter, drive command signal S1B changes from low to high at time tb. Drive signal S3B remains low at time tb, but then changes to high at time t7 when on-inhibit signal S2B changes from low to high.

[0083] At this time, the input-side hold signal S6B changes from low to high. The input-side hold signal S6B changes to low when the first hold period T41 has elapsed since time t7. The drive signal S4B changes to high at time t8, when delay time d1 has elapsed since time t7. At this time, the signal S51B changes from low to high, and the output-side hold signal S52B changes from high to low. The signal S51B changes to low when the period T51 has elapsed since time t8.

[0084] Output hold signal S7B goes low when delay time d3 has elapsed since time t8. The timing at which output hold signal S7B goes low occurs before the timing at which input hold signal S6B goes low. In other words, in this case, the period during which output hold signal S7B is output and the period during which input hold signal S6B is output overlap.

[0085] The gate voltage VgB of the switching element 4B starts to rise when a delay time d2 has elapsed since the time t8 when the drive signal S4B went high. The switching element 4B turns on at the time t9 when the gate voltage reaches the gate threshold voltage. At this time, the signal S5B goes from high to low.

[0086] As described above, with the above configuration, when the on-drive condition is satisfied in the input-side circuit 11, that is, when the drive command signal S1A changes from low level to high level, the on-inhibit signal S2B is output to the opposing arm drive circuit 1B, and this state is maintained for a certain period of time. Furthermore, with the above configuration, the first hold period T41 during which the output of the input-side hold signal S6 is maintained is set to a period equivalent to the sum of the delay times d1 and d3. Furthermore, with the above configuration, the second hold period T2 during which the output of the output-side hold signal S52 is maintained is set to a period equivalent to the delay time d2, etc. This embodiment also achieves the same effects as the second embodiment.

[0087] (Other Embodiments) The present disclosure is not limited to the embodiments described above and illustrated in the drawings, and can be modified, combined, or expanded as desired without departing from the spirit of the present disclosure. The numerical values ​​shown in the above embodiments are merely examples, and the present disclosure is not limited to these.

[0088] In each of the above embodiments, the input side circuit 11 and the output side circuits 12, 42, 52 are configured on separate chips, but this is not limiting. For example, if there are no problems with the withstand voltage of the elements, the input side circuit 11 and the output side circuits 12, 42, 52 can also be configured on the same single chip.

[0089] In each of the above embodiments, the signal transmission circuit 13 is configured to include the insulated communication circuits 14 and 15, but this is not limited to this. For example, the signal transmission circuit 13 may be configured to include a level shifter when the input side circuit 11 and the output side circuits 12, 42, and 52 are configured on the same single chip.

[0090] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0091] In addition to the inventions described in the claims, the present disclosure also includes the following inventions: [1] A drive circuit for driving a switching element (4, 4A, 4B) constituting one of upper and lower arms connected in series, wherein, assuming that the one arm is a local arm and the other of the upper and lower arms is an opposing arm, the drive circuit comprises: an input-side circuit (11) that generates a drive signal for driving the switching element based on a drive command signal given from outside and an on-inhibit signal output from a drive circuit on the opposing arm side, an output-side circuit (12, 42, 52) that operates on a power supply different from that of the input-side circuit and drives the switching element based on the drive signal, and a signal transmission circuit (13) that transmits signals between the input-side circuit and the output-side circuit, wherein the output-side circuit comprises: an on-drive circuit (16) that drives the switching element on by charging a gate charge of the switching element based on the drive signal, and an off-drive circuit (17) that drives the switching element off by discharging a gate charge of the switching element based on the drive signal; a gate voltage of the switching element and an output-side inhibit holding circuit (18, 43, 53) that detects the gate voltage of the switching element and outputs an output-side hold signal based on the detection result, wherein the input-side circuit comprises: an input-side inhibit holding circuit (22) that outputs the input-side hold signal until a predetermined first hold period has elapsed since the drive signal switched from a state that drives the switching element off to a state that drives the switching element on, and an inhibit signal generating circuit (23) that generates the on-inhibit signal that inhibits on-driving of the switching element based on the drive command signal, the output-side hold signal, and the input-side hold signal, and outputs the on-inhibit signal to the drive circuit on the opposite arm side. [2] The drive circuit according to [1], wherein the output-side inhibit holding circuit (43) starts outputting the output-side hold signal from the time the drive signal switched from a state that drives the switching element off to a state that drives the switching element on.[3] The drive circuit according to [1] or [2], wherein the output-side inhibit holding circuit (53) holds the output of the output-side hold signal until a predetermined second hold period has elapsed since the drive signal switched from a state representing off-drive of the switching element to a state representing on-drive. [4] The drive circuit according to any one of [1] to [3], wherein the output-side inhibit holding circuit and the input-side inhibit holding circuit are configured to generate the output-side hold signal and the input-side hold signal so that a period during which the output-side hold signal is output overlaps with a period during which the input-side hold signal is output. [5] The drive circuit according to any one of [1] to [4], wherein the signal transmission circuit is an isolated communication circuit (14, 15) that performs isolated communication between the input-side circuit and the output-side circuit, and is configured to transmit signals via the isolated communication.

Claims

1. A drive circuit for driving a switching element (4, 4A, 4B) constituting one of upper and lower arms connected in series, wherein the one arm is defined as a local arm and the other arm of the upper and lower arms is defined as an opposing arm, the drive circuit comprising: an input side circuit (11) for generating a drive signal for driving the switching element based on a drive command signal given from outside and an on-inhibit signal output from a drive circuit on the opposing arm side; an output side circuit (12, 42, 52) that operates on a power source different from that of the input side circuit and drives the switching element based on the drive signal; and a signal transmission circuit (13) for transmitting signals between the input side circuit and the output side circuit, wherein the output side circuit comprises: an on drive circuit (16) that turns on the switching element by charging a gate charge of the switching element based on the drive signal; and an off drive circuit (17) that turns off the switching element by discharging a gate charge of the switching element based on the drive signal. an output-side inhibit hold circuit (18, 43, 53) that detects a gate voltage of the switching element and outputs an output-side hold signal based on the detection result, wherein the input-side circuit comprises: an input-side inhibit hold circuit (22) that outputs an input-side hold signal until a predetermined first hold period has elapsed since the drive signal switched from a state that drives the switching element off to a state that drives the switching element on; and an inhibit signal generation circuit (23) that generates the on-inhibit signal that inhibits on-driving of the switching element based on the drive command signal, the output-side hold signal, and the input-side hold signal, and outputs the on-inhibit signal to the drive circuit on the opposite arm side.

2. The drive circuit according to claim 1, wherein the output-side inhibit hold circuit (43) starts outputting the output-side hold signal at the point when the drive signal switches from a state representing OFF drive of the switching element to a state representing ON drive.

3. A drive circuit as described in claim 2, wherein the output-side inhibit hold circuit (53) holds the output of the output-side hold signal until a predetermined second hold period has elapsed after the drive signal has switched from a state representing OFF drive of the switching element to a state representing ON drive.

4. A drive circuit as claimed in any one of claims 1 to 3, wherein the output-side inhibit hold circuit and the input-side inhibit hold circuit are configured to generate the output-side hold signal and the input-side hold signal so that the period during which the output-side hold signal is output overlaps with the period during which the input-side hold signal is output.

5. A drive circuit as claimed in any one of claims 1 to 3, wherein the signal transmission circuit is an insulated communication circuit (14, 15) that performs insulated communication between the input side circuit and the output side circuit, and is configured to transmit signals via the insulated communication.

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