Semiconductor device

Abstract

This semiconductor device comprises: a substrate having a first surface and a second surface on the opposite side from the first surface; a buffer layer covering the first surface of the substrate; a wiring part including at least one wiring layer on the buffer layer; an electrode pad provided on the wiring layer and electrically connected to at least one wiring layer; an electronic component electrically connected to the electrode pad; and a rectifying element electrically connected to the electronic component via at least one wiring layer. The rectifying element includes a gallium nitride layer in contact with the buffer layer. The buffer layer and the gallium nitride layer each have a crystal structure.

Description

Semiconductor Devices

[0001] An embodiment of the present invention relates to a semiconductor device in which one or more electronic components are mounted on a substrate.

[0002] System on Package (SoP) is a technology that integrates multiple integrated circuits (IC chips) with different functions on a substrate into a single package, enabling functional integration. System on Package offers several advantages over System on Chip (SoC), which integrates multiple integrated circuits with different functions into a single chip. For example, System on Package can reduce parasitic capacitance between interconnects, avoiding signal delay issues and reducing power consumption.

[0003] US Patent Application Publication No. 2020 / 0212033

[0004] Substrates used in system-on-packages can be broadly classified by material into resin-based, silicon-based, ceramic-based, and glass-based. Glass epoxy substrates are a common resin-based material, but glass epoxy substrates have problems with thermal stability, flatness, and shape stability. On the other hand, silicon-based and ceramic-based substrates have superior thermal stability and mechanical properties compared to resin-based substrates, but are not suitable for large area applications and have the problem of being expensive. Glass substrates can be made large in area and can be inexpensive, making them a strong candidate for system-on-package substrates. However, glass substrates have the problem of low thermal conductivity.

[0005] A semiconductor device according to one embodiment of the present invention includes a substrate having a first surface and a second surface opposite to the first surface, a buffer layer covering the first surface of the substrate, a wiring section including at least one wiring layer on the buffer layer, an electrode pad provided on the wiring layer and electrically connected to the at least one wiring layer, an electronic component electrically connected to the electrode pad, and a rectifying element electrically connected to the electronic component via the at least one wiring layer. The rectifying element includes a gallium nitride layer in contact with the buffer layer, and the buffer layer and the gallium nitride layer have a crystalline structure.

[0006] A semiconductor device according to one embodiment of the present invention includes a substrate having a first surface and a second surface opposite to the first surface, a first buffer layer covering the first surface, a second buffer layer covering the second surface, a first wiring section including at least one first wiring layer on the first buffer layer, a second wiring section including at least one second wiring layer on the second buffer layer, a first electrode pad provided on the first wiring layer and electrically connected to the at least one first wiring layer, a second electrode pad provided on the second wiring layer and electrically connected to the at least one second wiring layer, a first electronic component electrically connected to the first electrode pad, a second electronic component electrically connected to the second electrode pad, a first rectifying element electrically connected to the first electronic component via the at least one first wiring layer, and a second rectifying element electrically connected to the second electronic component via the at least one second wiring layer. The first rectifying element includes a first gallium nitride based semiconductor layer in contact with a first buffer layer, and the second rectifying element includes a second gallium nitride based semiconductor layer in contact with a second buffer layer, and the first buffer layer, the second buffer layer, and the first gallium nitride based semiconductor layer, and the second gallium nitride based semiconductor layer have a crystalline structure.

[0007] 1 is a cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a partial structure of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing an example of a protection circuit constituted by a rectifying element provided in a semiconductor device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing a partial structure of a wiring layer provided in a semiconductor device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 8 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the embodiments exemplified below. For clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual form, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements that are considered to be identical or substantially identical are indicated by the same reference numerals (or reference numerals with A, B, etc., suffixed to the reference numerals), and redundant explanations may be omitted as appropriate. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish each element and have no further meaning unless otherwise specified.

[0009] In this specification, when a component or region is referred to as being "on (or under)" another component or region, unless otherwise specified, this includes not only the case where it is directly above (or directly under) the other component or region, but also the case where it is above (or under) the other component or region, i.e., the case where another component is included between the component or region and above (or under) the other component or region.

[0010] 1 shows an example of the configuration of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a substrate 102, a buffer layer 104A, a rectifying element 106A, a wiring layer 108A, and electronic components 112 (112-1, 112-2, 112-3).

[0011] The substrate 102 is a flat plate-like member having a first surface S1 and a second surface S2 opposite to the first surface S1. The thickness of the substrate 102 is, for example, in the range of 0.4 mm to 1.2 mm. In this embodiment, a glass substrate is used as the substrate 102. A glass substrate is a substrate that does not have a crystalline structure and can also be called an amorphous substrate.

[0012] The glass substrate used in the semiconductor device 100 of this embodiment has an expansion coefficient of 50×10 －７ / °C and a strain point of 600°C or higher. The glass substrate preferably has an alkali metal content of 0.1% or less, such as sodium (Na). Examples of such glass substrates include glass substrates made of aluminoborosilicate glass, aluminosilicate glass, and aluminoborosilicate silicate glass. Such glass substrates are used in liquid crystal displays and organic electroluminescence (organic EL) displays, and large-area glass substrates known as "mother glass" are commercially available. In this embodiment, a large glass substrate known as "mother glass" can be used as the substrate 102, thereby improving the productivity of the semiconductor device 100.

[0013] As the substrate 102, in addition to a glass substrate, it is also possible to use a flexible resin substrate such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate.

[0014] A buffer layer 104A is provided on the first surface S1 of the substrate 102. The buffer layer 104A is provided so as to cover the entire surface of the first surface S1. In addition, a buffer layer 104B (shown by a dotted line) may be provided as an additional configuration on the second surface S2 side of the substrate 102. In this embodiment, it is sufficient that the buffer layer 104A is provided on the first surface S1, but by adding the buffer layer 104B to the second surface S2 as well, the force acting on the substrate 102 due to the internal stress of the film forming the buffer layer can be offset.

[0015] The wiring layer 108A is provided on the upper layer side of the buffer layer 104A. The wiring layer 108A includes a wiring pattern (not shown) and an insulating layer (not shown) covering the wiring pattern. The wiring layer 108A includes, as wiring patterns, a wiring pattern forming a power line, a wiring pattern forming a common line, a wiring pattern forming a signal line, and the like. These wiring patterns form a predetermined circuit and are provided to drive the electronic components 112 (112-1, 112-2, 112-3). The wiring pattern may have a structure in which multiple layers are stacked with insulating layers sandwiched between them (a so-called multi-layer wiring structure). In this case, the wiring layer 108A may include through-hole wiring for interconnecting the wiring patterns located on the upper and lower layers.

[0016] Electrode pads 110 are provided on the upper surface of the wiring layer 108A (the surface opposite to the first surface S1 of the substrate 102). The electrode pads 110 are electrically connected to the wiring pattern that constitutes the wiring layer 108A. The electrode pads 110 are used to mount electronic components 112 (112-1, 112-2, 112-3) on the substrate 102. The number and arrangement of the electrode pads 110 are arbitrary, and are provided as appropriate depending on the specifications and arrangement of the terminals of the electronic components 112 (112-1, 112-2, 112-3). Note that while FIG. 1 shows electronic components 112-1, 112-2, and 112-3 as an example, there is no limitation on the number and arrangement of electronic components mounted on the substrate 102.

[0017] The electronic components 112 (112-1, 112-2, 112-3) have various functions, such as an arithmetic processing function for performing arithmetic processing on digital signals, a storage function for storing data and programs, a sensing function for detecting physical quantities, a communication function for transmitting and receiving information, and a power supply control function for controlling power supply voltage. The electronic components 112-1, 112-2, and 112-3 may each have the same function or different functions. Furthermore, the electronic components 112-1, 112-2, and 112-3 may each have one of the functions exemplified above, or may have multiple functions.

[0018] If the electronic component 112-1 has a processing function, the electronic component 112-1 may be a general-purpose processor such as a central processing unit (CPU) or a graphics processing unit (GPU), an application-specific integrated circuit such as an ASIC, a programmable gate array such as an FPGA, or an AI-dedicated processor that speeds up the processing of artificial intelligence. If the electronic component 112-2 has a storage function, the electronic component 112-2 may be a memory device such as a volatile memory (RAM), a non-volatile memory, or a read-only memory (ROM). If the electronic component 112-3 has a sensing function, the electronic component 112-3 may be an optical sensor that detects light, a gas sensor that detects specific gas species, an acceleration sensor that detects acceleration, or the like. Furthermore, if the electronic component 112-3 has a communication function, the electronic component may have a wireless communication circuit. The communication circuit may be a communication circuit that transmits and receives high-frequency signals using an antenna or a coil, or an optical communication circuit that transmits and receives optical signals using a light-receiving element and a light-emitting element, or the like. If the electronic component 112-3 has a power supply control function, the electronic component 112-3 may be a power supply control circuit, a converter (AC / DC converter, DC / DC converter), or a power semiconductor element such as a power transistor.

[0019] The electronic components 112 (112-1, 112-2, 112-3) may be provided as bare chips separated from a semiconductor wafer, or as semiconductor (IC) packages in which bare chips are sealed in packages. The electronic components 112 (112-1, 112-2, 112-3) may have a configuration in which semiconductor (IC) chips are stacked three-dimensionally using a system-on-chip (SoC). The electronic components 112 may also be passive elements such as resistors, capacitors, coils, transformers, and crystal oscillators.

[0020] There is no limitation on the structure for electrically connecting the electronic components 112 (112-1, 112-2, 112-3) and the electrode pads 110. For example, the electronic components 112 (112-1, 112-2, 112-3) and the electrode pads 110 may be connected by conductive bumps 111. The conductive bumps 111 may be solder bumps or copper (Cu) bumps.

[0021] A rectifying element 106A is provided on the buffer layer 104A. The rectifying element 106A is not mounted on the substrate 102 as an individual component, but is formed by a semiconductor film deposited on the buffer layer 104A. Because the rectifying element 106A is formed of a thin film, it is provided so as to be embedded in the wiring layer 108A.

[0022] The rectifying element 106A is a diode. Alternatively, the rectifying element 106A may be formed of a thyristor or a MOSFET (metal oxide semiconductor field effect transistor). While FIG. 1 shows an example in which one rectifying element 106A is disposed on the substrate 102, there is no limitation on the number of rectifying elements. For example, one or more rectifying elements may be provided on the substrate 102 corresponding to each of the electronic components 112-1, 112-2, and 112-3.

[0023] The rectifying element 106A is connected to a power supply line (not shown) formed in the wiring layer 108A and is used to form a protection circuit that prevents overvoltage. For example, as shown in FIG. 1 , when a DC power supply 150 is connected, a power supply terminal 109A and a common terminal 109B are provided on the wiring layer 108a. In this case, the rectifying element 106A can be connected between the power supply terminal 109A and the common terminal 109B to form a protection circuit that prevents overvoltage. The rectifying element 106A also forms a protection circuit against static electricity and may be provided between a signal input terminal (not shown) and the electronic component 112.

[0024] FIG. 2 is a partial cross-sectional view of the semiconductor device 100, and schematically shows the wirings (1082, 1084, 1086, 1088) provided in the wiring layer 108A, the electronic component 112, and the rectifying element 106A.

[0025] The wiring layer 108A includes a signal line 1082, a power line 1084, a common line 1086, and a through-wire 1088. FIG. 2 shows these lines schematically, and the configurations of the signal line 1082, the power line 1084, the common line 1086, and the through-wire 1088 are not limited to those shown in the figure. The wiring pattern forming the signal line 1082, the power line 1084, and the common line 1086 in the wiring layer 108A may have a multi-layer wiring structure. The signal line 1082, the power line 1084, and the common line 1086 are electrically connected to the electrode pads 110. The electronic component 112 has an external terminal 1122. The external terminal 1122 of the electronic component 112 disposed on the wiring layer 108A is electrically connected to the electrode pads 110 on the wiring layer 108A side via conductive bumps 111.

[0026] The rectifying element 106A is provided so as to be embedded in the wiring layer 108A. The rectifying element 106A is provided in contact with the buffer layer 104A. The rectifying element 106A may be provided below the lowest wiring pattern among the wiring patterns constituting the wiring layer 108A. The rectifying element 106A has a variety of uses. For example, the rectifying element 106A may be connected between the power supply line 1084 and the common wiring 1086 to form a protection circuit. Because the rectifying element 106A is formed of a semiconductor thin film, it can be fabricated in the wiring layer 108A together with the signal line 1082, the power supply line 1084, and the common wiring 1086.

[0027] 3A, the rectifying element 106A can be connected in parallel between the power line 1084 and the common wiring 1086 to form a protection circuit against overvoltage. Also, as shown in FIG. 3B, the rectifying element 106A-1 can be connected between the signal line 1082 and the power line 1084, and the rectifying element 106A-2 can be connected between the signal line 1082 and the common wiring 1086 to form a protection circuit against static electricity.

[0028] 4 shows a cross-sectional view of the rectifying element 106A. The rectifying element 106A includes a gallium nitride based semiconductor layer 114 in contact with the buffer layer 104A, a first electrode 116 in ohmic contact with the gallium nitride based semiconductor layer 114, and a second electrode 117 forming a Schottky junction therewith. The gallium nitride based semiconductor layer 114 forming the rectifying element 106A may have a structure in which multiple layers are stacked. For example, the gallium nitride based semiconductor layer 114 may include a first gallium nitride based semiconductor layer 1141 in contact with the buffer layer 104A and a second gallium nitride based semiconductor layer 1142 stacked on the first gallium nitride based semiconductor layer 1141.

[0029] The structure of the gallium nitride based semiconductor layer 114 is not limited, but may have a structure in which the end portion of the second gallium nitride based semiconductor layer 1142 is recessed inward so as to expose the upper surface of the first gallium nitride based semiconductor layer 1141. Such a structure can ensure an area sufficient for the first electrode 116 to make ohmic contact with the first gallium nitride based semiconductor layer 1141, and also ensure an area sufficient for the second electrode 117 to form a Schottky junction with the second gallium nitride based semiconductor layer 1142.

[0030] The rectifying element 106A is preferably covered with a first insulating layer 120. The first insulating layer 120 is an inorganic insulating layer formed of silicon nitride, silicon oxide, or the like. The first insulating layer 120 is provided with a first contact hole CH11 exposing the first gallium nitride based semiconductor layer 1141 and a second contact hole CH12 exposing the second gallium nitride based semiconductor layer 1142. The first electrode 116 makes ohmic contact with the first gallium nitride based semiconductor layer 1141 through the first contact hole CH11, and the second electrode 117 forms a Schottky junction with the second gallium nitride based semiconductor layer 1142 through the second contact hole CH12.

[0031] The buffer layer 104A covering the first surface S1 of the substrate 102 has a crystalline structure. The crystals contained in the buffer layer 104A are preferably c-axis oriented. In other words, the buffer layer 104A is preferably a c-axis oriented film. The crystalline structure of the buffer layer 104A preferably has rotational symmetry, and for example, the crystal surface preferably has six-fold symmetry. Examples of such a crystalline structure include a hexagonal close-packed structure, a face-centered cubic structure, or a structure equivalent thereto. A structure equivalent to a hexagonal close-packed structure or a face-centered cubic structure includes a crystalline structure in which the c-axis is not at 90 degrees with respect to the a-axis and b-axis.

[0032] A rectifying element 106A is formed on the buffer layer 104A. The rectifying element 106A is formed of a crystalline gallium nitride based semiconductor layer 114. The substrate 102 is amorphous and does not have a lattice match with the crystalline gallium nitride based semiconductor layer 114. In order to form the crystalline gallium nitride based semiconductor layer 114 on the substrate 102, it is necessary to eliminate the lattice mismatch. By providing the buffer layer 104A having a crystalline structure on the substrate 102, it is possible to eliminate the lattice mismatch and form the crystalline gallium nitride based semiconductor layer 114.

[0033] In detail, the buffer layer 104A has a c-axis oriented crystal structure, which facilitates crystallization of the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142. That is, the buffer layer 104A is a c-axis oriented film, and has a crystal surface with six-fold rotational symmetry such as a hexagonal close-packed structure or a face-centered cubic structure, which makes it possible to control the orientation of the c-axes of the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 so that they grow in the film thickness direction (the direction perpendicular to the major surface of the substrate 102).

[0034] The thickness of the buffer layer 104A is preferably 5 nm to 500 nm, more preferably 10 nm to 200 nm. The thickness can be measured using a contact profilometer or an optical film thickness meter (ellipsometry), or from images obtained using a scanning electron microscope (SEM) or a transmission electron microscope (TEM). When the buffer layer 104A has a thickness within this range, it can have crystals oriented along the c-axis and a flat surface.

[0035] The buffer layer 104A is made of an insulating material. The insulating material for the buffer layer 104A is preferably aluminum nitride (AlN) or aluminum oxide (Al ２ O ３ ), silicon carbide (SiC), lithium niobate (LiNbO), BiLaTiO, SrFeO, SrFeO, BiFeO, BaFeO, ZnFeO, PMnN-PZT, or biological apatite (BAp) can be used. The buffer layer 104A can be fabricated by sputtering using these metal materials or insulating materials.

[0036] By forming the buffer layer 104A from an insulating material, it is possible to form the wiring pattern that constitutes the wiring layer 108A directly on the buffer layer 104A.

[0037] The buffer layer 104A has the function of promoting the crystallization of the gallium nitride based semiconductor layer 114, as well as the function of enhancing heat dissipation. The electronic components 112 mounted on the substrate 102 generate heat during operation. The thermal conductivity of the glass substrate used as the substrate 102 is 1.5 to 1.6 W / m·K, which is a very low value compared to the thermal conductivity of single crystal silicon, which is approximately 150 W / m·K. If the thermal conductivity of the substrate 102 is low, the temperature rises during operation of the semiconductor device 100, which can cause a malfunction. In contrast, the thermal conductivity of aluminum nitride (AlN) used as the buffer layer 104A is 285 to 320 W / m·K, which is comparable to that of metals. Furthermore, aluminum oxide (Al ２ O ３The thermal conductivity of the buffer layer 104A is 20 to 30 W / m·K, which is at least 10 times higher than that of a glass substrate. By providing the buffer layer 104A in contact with the substrate, heat generated by the electronic component 112 can be dissipated, and the temperature rise of the semiconductor device 100 can be suppressed.

[0038] In this way, by providing the buffer layer 104A on the substrate 102, it is possible to form a crystalline gallium nitride based semiconductor layer 114. Furthermore, by providing the buffer layer 104A on the substrate 102, it is possible to improve heat dissipation and dissipate heat generated by the electronic component 112. From the viewpoint of improving heat dissipation, the semiconductor device 100 may be configured such that a heat sink or heat pipe (not shown) is connected to the substrate 102.

[0039] The gallium nitride semiconductor layer 114 constituting the rectifying element 106A is a semiconductor containing gallium nitride. The gallium nitride semiconductor layer 114 is, for example, a binary or ternary III-V group compound semiconductor such as gallium nitride (GaN), indium gallium nitride (InGaN), or aluminum gallium nitride (AlGaN). The gallium nitride semiconductor layer 114 may also be a compound semiconductor such as indium nitride (InN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN). The composition of such a gallium nitride semiconductor layer 114 preferably has a stoichiometric composition, but may deviate from the stoichiometric composition.

[0040] The gallium nitride semiconductor layer 114 preferably has crystallinity. The gallium nitride semiconductor layer 114 is preferably single crystalline, but may be polycrystalline, microcrystalline, or nanocrystalline. The crystalline structure of the gallium nitride semiconductor layer 114 preferably has a wurtzite structure. The gallium nitride semiconductor layer 114 preferably has a c-axis orientation or a (111) orientation.

[0041] The gallium nitride based semiconductor layer 114 may be a single layer, or may have a structure in which multiple layers are stacked. For example, as shown in Fig. 4, the gallium nitride based semiconductor layer 114 may have a structure in which a first gallium nitride based semiconductor layer 1141 and a second gallium nitride based semiconductor layer 1142 are stacked.

[0042] The first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 may have the same conductivity type. For example, the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 may have an n-type conductivity. The conductivity types of the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 may be determined by an impurity element inevitably mixed therein, or may be controlled by an intentionally added dopant (impurity element). Oxygen may be included as an impurity element inevitably contained in the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142. Generally, oxygen acts as a donor impurity for gallium nitride. In order to maintain constant characteristics of the rectifying element 106A, it is preferable that the conductivity of the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 be controlled by an intentionally added dopant. Therefore, the oxygen concentration in the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 is 1×10 １７ / cm ３ It is preferable that it is less than 10 ...

[0043] Silicon (Si) or germanium (Ge) is used as a dopant (donor impurity) added to the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142. The dopant concentration is preferably in a range in which the gallium nitride based semiconductor layer 114 does not degenerate. The dopant concentration in the first gallium nitride based semiconductor layer 1141 is 1×10 １８ / cm ３ 7 x 10 or more １８ / cm ３ The second gallium nitride based semiconductor layer 1142 has a density of 2×10 １７ / cm ３ 6 x 10 or more １７ / cm３ It is preferable to set the dopant concentration in the first gallium nitride based semiconductor layer 1141 within the above range. By setting the dopant concentration in the first gallium nitride based semiconductor layer 1141 within the above range, it is possible to increase the conductivity and form a good ohmic contact with the first electrode 116. Furthermore, by setting the dopant concentration in the second gallium nitride based semiconductor layer 1142 within the above range, it is possible to form a good Schottky junction with the second electrode 117.

[0044] The first gallium nitride based semiconductor layer 1141 is provided in contact with the buffer layer 104A. Since the buffer layer 104A has a c-axis oriented crystal structure, the first gallium nitride based semiconductor layer 1141 can be grown heteroepitaxially, and a similar c-axis oriented crystal can be obtained. The first gallium nitride based semiconductor layer 1141 may include an amorphous structure near the interface with the buffer layer 106, but preferably has crystallinity in a region (bulk) away from the interface. Since the first gallium nitride based semiconductor layer 1141 has a crystalline structure, the second gallium nitride based semiconductor layer 1142 can also have a crystalline structure. The threading dislocation density of the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 can be set to 5×10 ９ / cm ２ When the second gallium nitride based semiconductor layer 1142 has such crystallinity, a Schottky junction with few interface defects can be formed between the second electrode 117 and the second gallium nitride based semiconductor layer 1142.

[0045] The rectifying element 106A according to this embodiment operates using the rectifying characteristics exhibited by the Schottky junction formed between the second gallium nitride based semiconductor layer 1142 and the second electrode 117. Therefore, the rectifying element 106A can also be called a Schottky barrier diode. Furthermore, by reducing the threading dislocation density as described above, the breakdown voltage of the rectifying element 106A can be increased.

[0046] The rectifying element 106A can be formed at a low temperature even on a glass substrate by using a sputtering method to form the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142. That is, by providing the buffer layer 104A having a crystalline structure on the substrate 102, the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 having a crystalline structure can be formed by a sputtering method at a substrate temperature of 600° C. or less.

[0047] The sputtering target to be mounted in the sputtering device is appropriately selected depending on the compositions of the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142. A sintered body of a gallium nitride based semiconductor material is used as the sputtering target. Since the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 have different dopant concentrations, it is preferable to fabricate each layer using a different sputtering target.

[0048] The gas introduced during sputtering (sputtering gas) is argon (Ar), or a mixture of argon (Ar) and nitrogen (N ２ As the sputtering apparatus, a two-pole sputtering apparatus, a magnetron sputtering apparatus, a dual magnetron sputtering apparatus, a facing target sputtering apparatus, an ion beam sputtering apparatus, an inductively coupled plasma (ICP) sputtering apparatus, or the like can be used.

[0049] There are no limitations on the film thicknesses of the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142. The first gallium nitride based semiconductor layer 1141 only needs to form an ohmic contact with the first electrode 116, and has a film thickness of 50 nm to 3000 nm, for example, 200 nm to 1000 nm. The second gallium nitride based semiconductor layer 1142 only needs to form a Schottky junction with the second electrode 117, and has a film thickness of 50 nm to 3000 nm, for example, 200 nm to 1000 nm.

[0050] When the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 are n-type and have a work function of 3 eV to 4 eV, the first electrode 116 is formed of a conductive material having a work function lower than 4.5 eV, and the second electrode 117 is formed of a conductive material having a work function of 4.5 eV or higher. For example, a metal material such as aluminum (Al) or titanium (Ti) can be selected for the first electrode 116. For example, a conductive oxide material such as indium oxide, zinc oxide, or indium tin oxide can be selected for the first electrode 116. For example, a conductive material such as nickel (Ni), gold (Au), platinum (Pt), or silver (Ag) can be selected for the second electrode 117. For the second electrode 117, a metal layer such as aluminum (Al) can be stacked on a layer made of one of these conductive materials.

[0051] 4, the gallium nitride based semiconductor layer 114 constituting the rectifying element 106A has a larger band gap than silicon semiconductors, and has a high breakdown voltage and saturation velocity. For example, when gallium nitride is used as the gallium nitride based semiconductor layer 114, the band gap of gallium nitride is 3.4 eV, the breakdown voltage is 3.3 MV / cm, and the saturation velocity of electrons is about 2.5×10 ７ In contrast, the band gap of silicon is 1.1 eV, the dielectric breakdown voltage is 0.3 MV / cm, and the electron saturation velocity is approximately 1.0 × 10 ７ These physical properties indicate that forming the rectifying element 106A using the gallium nitride based semiconductor layer 114 makes it possible to obtain a high dielectric breakdown voltage, and that the rectifying element 106A is suitable for forming a protection circuit against static electricity.

[0052] The first electrode 116 and the second electrode 117 are connected to the gallium nitride semiconductor layer 114 via a first contact hole CH11 and a second contact hole CH12 provided in the first insulating layer 120. The cross sections of the first contact hole CH11 and the second contact hole CH12 preferably have a tapered shape, as schematically shown in FIG. 4 . In other words, the inner wall surfaces of the first contact hole CH11 and the second contact hole CH12 preferably slope upward. This shape prevents electric field concentration at the edges of the first contact hole CH11 and the second contact hole CH12 when a bias voltage is applied to the first electrode 116 and the second electrode 117, thereby increasing the breakdown voltage of the rectifying element 106A.

[0053] The second electrode 117 forms a Schottky junction with the second gallium nitride based semiconductor layer 1142 through the second contact hole CH12, and further has a structure in which it overlaps the second gallium nitride based semiconductor layer 1142 and extends over the upper surface of the first insulating layer 120. In this way, the second electrode 117 has a structure (field plate structure) in which it protrudes above the second gallium nitride based semiconductor layer 1142 with the insulating layer (first insulating layer 120) in between, which also makes it possible to alleviate electric field concentration and improve the breakdown voltage of the rectifying element 106A.

[0054] 1 to 3, a base insulating layer may be provided between the substrate 102 and the buffer layer 104A. The base insulating layer may have a single-layer structure formed of a single inorganic insulating film, or may have a multi-layer structure in which multiple inorganic insulating layers are stacked. Examples of inorganic insulating materials that form the base insulating layer include silicon nitride, silicon oxide, and silicon oxynitride. For example, the base insulating layer may have a structure in which a silicon nitride film and a silicon oxide film are stacked in this order from the substrate 102 side.

[0055] When a glass substrate is used as the substrate 102, the glass substrate contains a trace amount of alkali metal (such as sodium). Therefore, there is a concern that the alkali metal may contaminate the gallium nitride semiconductor layer 114. In response to this, the insulating base layer has the function of blocking impurities from diffusing from the substrate 102 into the gallium nitride semiconductor layer 114. Therefore, when impurity contamination due to the substrate 102 is a concern, it is preferable to provide the insulating base layer. By providing the insulating base layer, it is possible to expect the effects of improving the crystallinity of the gallium nitride semiconductor layer 114 and reducing the threading dislocation density. Furthermore, by providing the insulating base layer, it is possible to improve the adhesion of the buffer layer 104A. In other words, providing the insulating base layer can prevent peeling of the buffer layer 104A.

[0056] As shown in FIG. 4, by using a gallium nitride based semiconductor layer 114 deposited directly on the buffer layer 104A, the rectifying element 106A can be formed in the wiring layer 108A, and circuits using the rectifying element 106A, such as a protection circuit, can be integrated.

[0057] 5 is a cross-sectional view illustrating the structure of the wiring layer 108A, showing a structure corresponding to region R1 shown in FIG. 2. The wiring layer 108A includes a first wiring layer 1181 formed on the buffer layer 104A, a second wiring layer 1182 provided above the first wiring layer 1181, and an electrode pad 110 provided on the second wiring layer 1182. A first interlayer insulating layer ZM11 is provided between the first wiring layer 1181 and the second wiring layer 1182, and a second insulating layer ZM12 is provided between the second wiring layer 1182 and the electrode pad 110.

[0058] A first through via VH11 is provided in the first interlayer insulating layer ZM11, and a second through via VH12 is provided in the second insulating layer ZM12. A first via plug VP11 is provided in the first through via VH11, electrically connecting the first wiring layer 1181 and the second wiring layer 1182, and a second via plug VP12 is provided in the second through via VH12, electrically connecting the second wiring layer 1182 and the electrode pad 110.

[0059] FIG. 5 also shows an inset of a partially enlarged view of the first wiring layer 1181 corresponding to region R2. The first wiring layer 1181 has a structure in which a plurality of conductive layers are stacked. Specifically, the first wiring layer 1181 has a structure in which a first barrier layer BR11, a first seed layer SL11, and a first bulk conductive layer WL11 are stacked. The first barrier layer BR11 is made of a metal material such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and has a film thickness of about 5 nm to 50 nm. The first seed layer SL11 is provided as a seed layer for forming the first bulk conductive layer WL11 by electroplating. The first seed The layer SL11 has a thickness of approximately 10 nm to 100 nm. The first bulk conductive layer WL11 is formed, for example, of copper (Cu) and has a thickness of approximately 300 nm to 1000 nm. Because the first seed layer SL11 and the first bulk conductive layer WL11 are formed of the same metal material, the boundary between these two layers may not be clearly distinguishable. The first barrier layer BR11 is provided to improve the adhesion of the copper (Cu) that forms the first bulk conductive layer WL11 and to prevent diffusion to the surrounding area.

[0060] The second wiring layer 1182 and the electrode pad 110 also have the same structure as the first wiring layer 1181. The first via plug VP11 has a structure continuing from the core conductive layer WL12 constituting the second wiring layer 1182, and the second via plug VP12 has a structure continuing from the core conductive layer WL13 constituting the electrode pad 110.

[0061] A first cap layer CP11 is provided to cover the first wiring layer 1181, a second cap layer CP12 is provided to cover the second wiring layer 1182, and a third cap layer CP13 is provided to cover the electrode pad 110. The first cap layer CP11, the second cap layer CP12, and the third cap layer CP13 are provided to prevent diffusion of copper (Cu) that forms the core conductive layer. There is no limitation on the film thickness of the first cap layer CP11, the second cap layer CP12, and the third cap layer CP13, but they may have a thickness of approximately 50 nm to 100 nm, for example. An opening OP11 that exposes the top surface of the electrode pad 110 is provided in the third cap layer CP13.

[0062] 6A to 6J, an example of a method for manufacturing the semiconductor device 100 according to this embodiment will be described. The following description will focus on the structure of the rectifying element 106A and wirings provided in the periphery thereof.

[0063] A buffer layer 104A is formed on the substrate 102, and a gallium nitride based semiconductor layer 114 and a first insulating layer 120 are formed thereon. The buffer layer 104A is formed by sputtering. For example, the buffer layer 104A is formed by depositing an aluminum nitride (AlN) film by sputtering. The film thickness of the buffer layer 104A is as described above.

[0064] The gallium nitride based semiconductor layer 114 has a structure in which a first gallium nitride based semiconductor layer 1141 and a second gallium nitride based semiconductor layer 1142 are stacked. The first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 are deposited in this order on the buffer layer 104A. The first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 are deposited over the entire surface of the buffer layer 104A, but are patterned so that these thin films remain in island shapes in the region of the rectifying element 106A. Furthermore, the second gallium nitride based semiconductor layer 1142 is patterned so that the top surface of the first gallium nitride based semiconductor layer 1141 is exposed.

[0065] The first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 are formed of, for example, a gallium nitride film. When forming the films by sputtering, the concentration of oxygen contained in the first gallium nitride based semiconductor layer 1141 and the second gallium nitride based semiconductor layer 1142 is set to 1×10 １７ / cm ３ The film formation chamber is dehydrated and evacuated to a high vacuum so that the impurity concentration in the gallium nitride film is reduced to less than 1×10. During film formation, silicon (Si) is added as a dopant that imparts n-type conductivity. The dopant concentration in the first gallium nitride based semiconductor layer 1141 is 1×10. １８ / cm ３ 7 x 10 or more １８ / cm ３or less, and in the second gallium nitride based semiconductor layer 1142, １７ / cm ３ 6 x 10 or more １７ / cm ３ It is controlled as follows:

[0066] Thereafter, a first insulating layer 120 is formed so as to cover the upper surface of the buffer layer 104A and the gallium nitride based semiconductor layer 114. As the first insulating layer 120, a silicon nitride film or a silicon oxynitride film is formed by sputtering or plasma CVD.

[0067] FIG. 6B shows the step of forming contact holes in the first insulating layer 120 and forming a first electrode 116 in contact with the first gallium nitride based semiconductor layer 1141 and a second electrode 117 in contact with the second gallium nitride based semiconductor layer 1142.

[0068] The first electrode 116 is formed of a conductive material such as aluminum (Al) or titanium (Ti) to form an ohmic contact with the first gallium nitride based semiconductor layer 1141. The second electrode 117 is formed of a conductive material such as nickel (Ni), gold (Au), platinum (Pt), or silver (Ag) to form a Schottky contact with the second gallium nitride based semiconductor layer 1142. In this manner, the rectifying element 106A is formed.

[0069] A second insulating layer 121 used as a passivation film is formed on the upper layer side of the first electrode 116 and the second electrode 117. The second insulating layer 121 is formed by depositing a silicon nitride film or a silicon oxynitride film by sputtering or plasma CVD. Then, a first contact hole CH11 exposing the first electrode 116 and a second contact hole CH12 exposing the second electrode 117 are formed in the second insulating layer 121.

[0070] FIG. 6C shows the step of forming a first barrier layer BR11 and a first seed layer SL11 on the second insulating layer 121, and then forming a mask layer MS11. As described above, the first barrier layer BR11 is formed by sputtering a thin film of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or the like. The first barrier layer BR11 is formed to a thickness of approximately 5 nm to 50 nm. The first seed layer SL11 is formed by sputtering a thin film of copper (Cu). The first seed layer SL11 is formed to a thickness of approximately 10 nm to 100 nm. A mask layer MS11 is formed on the first seed layer SL11. The mask layer MS11 is a mask for forming the first wiring layer 1181 and has an opening pattern corresponding to the pattern of the first bulk conductive layers WL11 and WL12. The mask layer MS11 is formed of photoresist. The opening pattern of the mask layer MS11 exposes the upper surface of the first seed layer SL11.

[0071] FIG. 6D shows the step of forming first bulk conductive layers WL11 and WL12 in the openings of the mask layer MS11. The first bulk conductive layers WL11 and WL12 are formed by growing copper (Cu) on the first seed layer SL11 by electroplating. The thickness of the first bulk conductive layers WL11 and WL12 can be appropriately controlled by the electroplating conditions (concentration of the plating solution, current, time, pulse waveform, etc.). The thickness of the first bulk conductive layers WL11 and WL12 is arbitrary, and may be formed to a thickness of, for example, 300 to 1000 nm. In FIG. 6D, the first bulk conductive layer WL11 forms the power supply line 1084, and the first bulk conductive layer WL12 forms the common wiring 1086.

[0072] 6E shows the step of removing the mask layer MS11 and etching the first seed layer SL11 and the first barrier layer BR11. Because the first seed layer SL11 and the first barrier layer BR11 are thinner than the first bulk conductive layers WL11 and WL12, the first seed layer SL11 and the first barrier layer BR11 can be etched using the first bulk conductive layers WL11 and WL12 as a mask. This etching process forms the power supply line 1084 and the common line 1086 that constitute the first wiring layer 1181.

[0073] 6F illustrates the step of forming a first cap layer CP11 and a first interlayer insulating layer ZM11 on the first wiring layer 1181. The first cap layer CP11 is formed to cover the entire surface of the first wiring layer 1181 and the buffer layer 104A exposed by the first wiring layer 1181. The first cap layer CP11 is preferably formed of a silicon nitride film, but may also be formed of a silicon oxynitride film, a silicon oxide film, or a stacked film of a silicon nitride film and a silicon oxide film. The first cap layer CP11 is provided to prevent diffusion of copper (Cu) forming the first bulk conductive layers WL11 and WL12. The first cap layer CP11 is formed to a thickness of 50 nm to 100 nm. The first cap layer CP11 can be formed by sputtering or plasma CVD.

[0074] The first interlayer insulating layer ZM11 is formed using a photosensitive resin composition. Examples of photosensitive resin compositions that can be used include a composition containing a precursor of a phenolic resin material, a polyimide resin material, an epoxy resin material, or the like, and a photosensitive group. The first interlayer insulating layer ZM11 can be formed by applying such a photosensitive resin composition onto the first cap layer CP11 and curing it by exposure. There are no limitations on the thickness of the first interlayer insulating layer ZM11, but it is preferable to form it to a thickness of 3 μm to 10 μm, for example, 5 μm.

[0075] Because the first interlayer insulating layer ZM11 is formed of a photosensitive resin composition, the first through vias VH11, VH12, and VH13 can be formed at the same time. The first through via VH11 is a through hole for exposing the upper surface of the power supply line 1084 formed as the first wiring layer 1181, the first through via VH12 is a through hole for exposing the upper surface of the second electrode 117, and the first through via VH13 is a through hole for exposing the common wiring 1086. The first cap layer CP11 remains on the bottom surfaces of the first through vias VH11, VH12, and VH13, but because the first cap layer CP11 is thin, it can be removed by using the first interlayer insulating layer ZM11 as an etching mask.

[0076] 6G shows the step of forming a second barrier layer BR21 and a second seed layer SL21 on the first interlayer insulating layer ZM11, and then forming a mask layer MS21. The second barrier layer BR21 and the second seed layer SL21 are provided to cover the upper surface of the first insulating layer ZM11 and the inner wall and bottom surfaces of the first through-vias VH11, VH12, and VH13 (the upper surfaces of the power supply line 1084, the second electrode 117, and the common wiring 1086). A mask layer MS21 is formed on the second seed layer SL21. The mask layer MS21 is a mask for forming the second wiring layer 1182 and has an opening pattern corresponding to the pattern of the second bulk conductive layers WL21 and WL22. The opening pattern of the mask layer MS21 exposes the upper surface of the second seed layer SL21.

[0077] 6H shows the step of forming second bulk conductive layers WL21 and WL22 in the openings of the mask layer MS21. The second bulk conductive layers WL21 and WL22 are fabricated in the same manner as the first bulk conductive layers WL11 and WL12. In this process, a plating layer is grown to fill not only the upper surface of the first interlayer insulating layer ZM11 but also the first through vias VH11, VH12, and VH13. As a result, first via plugs VP11, VP12, and VP13 can be formed so as to be continuous with the second bulk conductive layers WL21 and WL22.

[0078] 6I shows the step of removing the mask layer MS21 and etching the second seed layer SL21 and the second barrier layer BR21 to form a second wiring layer 1182. The second wiring layer 1182 includes second bulk conductive layers WL21 and WL22. The second bulk conductive layer WL21 is electrically connected to the first bulk conductive layer WL11 (power line 1084) by a first via plug VP11. The second bulk conductive layer WL22 is electrically connected to the second electrode 117 and the first bulk conductive layer WL12 (common wiring 1086) by first via plugs VP12 and VP13.

[0079] Similar processes are then performed to form a second interlayer insulating layer Z21 on the second wiring layer 1182, a second through-via VH21, a third barrier layer BR31, a third seed layer SL31, and a third bulk conductive layer WL31, thereby forming an electrode pad 110 on the second insulating layer ZM21, as shown in FIG. 6J . In FIG. 6J , the electrode pad 110 formed of the third bulk conductive layer WL31 is electrically connected to the power line 1084 by a second via plug VP21. A third cap layer CP31 is provided on the second insulating layer ZM11. The third cap layer CP31 has an opening OP1 that exposes the top surface of the electrode pad 110 (third bulk conductive layer WL31).

[0080] 6J, the rectifying element 106A has a structure in which the first electrode 116 is connected to the power line 1084 and the second electrode 117 is connected to the common wiring 1086. Note that the connection structure of the rectifying element 106A is an example, and the connection structure of the rectifying element 106A is not limited to the structure shown in the figure. The rectifying element 106A can be formed anywhere within the surface of the substrate 102 and can be appropriately connected to wiring included in the wiring layer 108A. Although not shown, the electrode pad 110 electrically connected to the signal line 1082 can be fabricated using a similar process and structure.

[0081] 6A to 6J, the rectifying element 106A is formed on the substrate 102, and then, in a subsequent process, a wiring pattern for forming the wiring layer 108A can be formed. The rectifying element 106A can be connected to the wiring that constitutes the wiring layer 108A during this process. Then, by connecting the electronic component 112 to the electrode pad 110, the semiconductor device 100 shown in FIGS. 1 and 2 can be completed.

[0082] 7 is a diagram schematically illustrating the arrangement of the wiring layer 108A and electronic components 112 (112-1, 112-2). FIG. 7 shows an example in which the rectifying elements 106A-1, 106A-2 are provided between a power supply line 1084 that is drawn into the electronic components 112-1, 112-2 and a common wiring 1086. The power supply line 1084 is connected to the power supply terminal 109A and is routed within the wiring layer 108A. The common wiring 1086 is connected to the common terminal 109B and is routed within the wiring layer 108A. Similarly, the signal line 1082 that transmits a digital signal is connected to the signal input terminal 109C and is similarly routed within the wiring layer 108A.

[0083] In this layout, the wiring width of the power supply line 1084 is wider in the layer connected to the electronic components 112-1 and 112-2 than the wiring width of the signal line formed in the same layer. In other words, even if the wiring layer 108A has a multi-layer wiring structure, when comparing the wiring widths of the top layer connected to the electronic component 112, the wiring width of the power supply line 1084 is configured to be the widest compared to the other wiring (signal line 1082). By making the width of the power supply line 1084 wider than the wiring width of the other wiring, it is possible to reduce wiring resistance and power consumption. It is also possible to increase the wiring thickness by overlapping wiring layers, thereby reducing wiring resistance.

[0084] The semiconductor device 100 according to this embodiment can reduce costs for components by using a glass substrate as the substrate 102. By using a glass substrate as the substrate 102, a large-area substrate can be employed, thereby improving productivity. A buffer layer 104A with high thermal conductivity is provided on the surface of the glass substrate used as the substrate 102, thereby achieving high heat dissipation properties and improving the thermal stability of the semiconductor device 100.

[0085] In the semiconductor device 100 according to this embodiment, the rectifying element 106A can be formed on the substrate 102, and a protection circuit against static electricity and overvoltage can be formed. By forming the rectifying element 106A using the gallium nitride based semiconductor layer 114, a high reverse breakdown voltage can be achieved.

[0086] Second Embodiment This embodiment illustrates an example of a semiconductor device 100 including a rectifier circuit. The following description will focus on differences from the first embodiment, and redundant descriptions of common parts will be omitted as appropriate.

[0087] 8 shows an example of the configuration of a semiconductor device 100 according to this embodiment. The semiconductor device 100 has a similar configuration to the first embodiment in that a buffer layer 104A is provided on a substrate 102 and electronic components 112 are mounted thereon, but differs in that a rectifier circuit 140 is built in. In other words, the semiconductor device 100 according to this embodiment differs from the first embodiment in that an AC power supply 152 is directly connected to a power supply terminal 109A and converted to DC by the built-in rectifier circuit 140.

[0088] FIG. 9 shows an example of a rectifier circuit 140. The rectifier circuit 140 has a full-wave rectifier circuit in which four rectifier elements 106A-1, 106A-2, 106A-3, and 106A-4 are bridge-connected. The bridge circuit of the rectifier elements 106A-1, 106A-2, 106A-3, and 106A-4 is connected to an AC power supply 152 and inverts the negative voltage side of the AC input to output a pulsating current. A DC output can be obtained by smoothing the output side of this bridge circuit with a capacitor 142. Then, by connecting the output of the rectifier circuit 140 to an electrode pad 110, DC power can be supplied to an electronic component 112 (load).

[0089] The rectifying elements 106A-1, 106A-2, 106A-3, and 106A-4 have a structure similar to that of the rectifying element 106A shown in FIG. 4. In other words, a Schottky barrier diode made of a gallium nitride based semiconductor layer 114 formed on the buffer layer 104A can be applied as the diode constituting the rectifying circuit 140. The capacitor 142 can also be formed on the substrate 102 in a similar manner. For example, the capacitor 142 can be formed simultaneously during the process of forming the rectifying element 106A and the wiring layer 108A, using the conductive layers forming the first electrode 116 and the second electrode 117, the second insulating layer 121, and the conductive layers forming the power supply line 1084 and the common wiring 1086.

[0090] The semiconductor device 100 according to this embodiment has a built-in rectifier circuit 140, and therefore can be driven by directly connecting to an AC power source without using an AC / DC converter. In other words, an external rectifier circuit can be omitted, and miniaturization can be achieved. The semiconductor device 100 according to this embodiment is similar to the first embodiment except for having the rectifier circuit 140, and can achieve the same effects.

[0091] Third Embodiment This embodiment illustrates an example of a semiconductor device 100 in which a rectifying element 106B, a wiring layer 108B, and an electronic component 112-2 are provided on the second surface S2 side in addition to the first surface S1 side of the substrate 102. The following description will focus on differences from the first embodiment, and redundant descriptions of common parts will be omitted as appropriate.

[0092] FIG. 10 shows a partial cross-sectional structure of the semiconductor device 100 according to this embodiment. A buffer layer 104A, a rectifying element 106A, and a wiring layer 108A are provided on the first surface S1 side of the substrate 102, and an electronic component 112-1 is mounted thereon. The configurations of the buffer layer 104A, the rectifying element 106A, and the wiring layer 108A are the same as those in the first embodiment. A buffer layer 104B, a rectifying element 106A, and a wiring layer 108B are provided on the second surface S2 side of the substrate 102, and an electronic component 112-2 is mounted thereon. The configurations of the rectifying element 106B and the wiring layer 108B are the same as those of the corresponding configurations on the first surface S1 side. The buffer layer 104B is similar to the buffer layer 104A provided on the first surface S1 side, but may have a different film thickness, as described below.

[0093] The wiring layer 108A on the first surface S1 side of the substrate 102 and the wiring layer 108B on the second surface S2 side may be connected by a through electrode 1089 that penetrates the substrate 102. Fig. 10 shows an example in which the common wirings 1088 are connected to each other by the through electrode 1089, but the signal line 1082 and the power line 1084 may also be connected by the through electrode 1089.

[0094] The electronic components 112-1 mounted on the first surface S1 of the substrate 102 and the electronic components 112-2 mounted on the second surface S2 may have the same function or different functions. For example, the electronic components 112-1 related to logic semiconductors (ICs) that process digital data, such as a central processing unit (CPU) or memory, may be mounted on the first surface S1, and the electronic components 112-2 related to power semiconductors that control and convert power may be mounted on the second surface S2. In other words, the electronic components 112 mounted on the first surface S1 and the second surface S2 of the substrate 102 may be different depending on the amount of heat generated.

[0095] For example, an electronic component 112-1 that generates a relatively small amount of heat, such as a logic semiconductor (IC), may be mounted on the first surface S1 side, and an electronic component 112-2 that generates a large amount of heat, such as a power semiconductor, may be mounted on the second surface S2 side. In this case, in order to improve the heat dissipation performance on the second surface S2 side, it is preferable to make the film thickness of the buffer layer 104B on the second surface S2 side larger than the film thickness of the buffer layer 104A on the first surface S1 side.

[0096] According to this embodiment, by providing a rectifying element 106A and a wiring layer 108A on the first surface S1 of the substrate 102 and a rectifying element 106B and a wiring layer 108B on the second surface S2, electronic components can be mounted on both surfaces. The wiring patterns of the wiring layers 108A and 108B can be freely designed, and the wiring patterns on the front and back surfaces of the substrate 102 can be connected by through-electrodes. This allows various electronic components 112 to be mounted on the semiconductor device 100. Furthermore, as described above, by optimizing the buffer layers 104A and 104B formed on the first surface S1 and the second surface S2 of the substrate 102, heat dissipation characteristics can be differentiated, allowing electronic components with different heat dissipation values ​​and withstand voltages to be mounted on the front and back surfaces. This configuration reduces the thermal impact of electronic components that generate a large amount of heat on other electronic components, thereby improving the reliability of the semiconductor device 100.

[0097] The semiconductor device 100 according to this embodiment is similar to the first embodiment except that a rectifying element 106B and a wiring layer 108B are also provided on the second surface S2 of the substrate 102 and an electronic component 112-2 is mounted thereon, and similar effects can be obtained. Furthermore, the configuration of the semiconductor device 100 according to this embodiment can be implemented by appropriately combining the configuration shown in the second embodiment.

[0098] The various configurations of the semiconductor device exemplified as one embodiment of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, semiconductor devices in which a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions, based on the semiconductor device disclosed in this specification and drawings, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0099] Even if there are other effects and advantages different from those brought about by the aspects of the embodiments disclosed in this specification, if they are clear from the description in this specification or can be easily predicted by a person skilled in the art, they are naturally understood to be brought about by the present invention.

[0100] 100: semiconductor device, 102: substrate, 104A, 104B: buffer layer, 106A, 106B: rectifying element, 108A, 108B: wiring layer, 1082: signal line, 1084: power line, 1086: common wiring, 1088: through wiring, 1089: through electrode, 109A: power terminal, 109B: common terminal, 109C: signal input terminal, 110: electrode pad, 111: conductive bump, 112, 112 -1, 112-2, 112-3: electronic components, 1122: external terminal, 114: gallium nitride based semiconductor layer, 1141: first gallium nitride based semiconductor layer, 1142: second gallium nitride based semiconductor layer, 116: first electrode, 117: second electrode, 1181: first wiring layer, 1182: second wiring layer, 120: first insulating layer, 121: second insulating layer, 140: rectifier circuit, 142: capacitor, 150: DC power supply, 152: AC power supply, BR11: first barrier layer, BR21: second barrier layer, BR31: third barrier layer, CH11: first contact hole, CH12: second contact hole, CP11: first cap layer, CP21: second cap layer, CP31: third cap layer, MS11, MS21: mask layer, OP11: opening, S1: first surface, S2: second surface, SL11: first seed layer, SL21: 2 seed layer, SL31: third seed layer, VH11, 12, 13: first through via, VH21: second through via, VH31: third through via, VP11, VP12, VP13: first via plug, VP12: second via plug, WL11, WL12: first bulk conductive layer, WL21, WL22: second bulk conductive layer, WL31: third bulk conductive layer, ZM11: first interlayer insulating layer, ZM12: second interlayer insulating layer

Claims

a substrate having a first surface and a second surface opposite the first surface; a buffer layer covering the first surface of the substrate; a wiring section including at least one wiring layer on the buffer layer; an electrode pad provided on the wiring layer and electrically connected to the at least one wiring layer; an electronic component electrically connected to the electrode pad; a rectifying element electrically connected to the electronic component via the at least one wiring layer, the rectifying element includes a gallium nitride layer in contact with the buffer layer, The semiconductor device is characterized in that the buffer layer and the gallium nitride layer have a crystalline structure. 　 The semiconductor device according to claim 1 , wherein said buffer layer and said gallium nitride layer have a c-axis oriented crystal structure. 　 the gallium nitride layer includes a first gallium nitride based semiconductor layer on the buffer layer, a second gallium nitride based semiconductor layer on the first gallium nitride based semiconductor layer, a first electrode, and a second electrode; the first gallium nitride based semiconductor layer and the second gallium nitride based semiconductor layer have n-type conductivity; the electrical conductivity of the second gallium nitride based semiconductor layer is lower than the electrical conductivity of the first gallium nitride based semiconductor layer; the first electrode is in ohmic contact with the first gallium nitride based semiconductor layer; The semiconductor device according to claim 1 , wherein said second electrode forms a Schottky junction with said second gallium nitride based semiconductor layer. 　 an insulating layer covering the first gallium nitride based semiconductor layer and the second gallium nitride based semiconductor layer; the first electrode is in contact with the first gallium nitride based semiconductor layer through a first contact hole provided in the insulating layer; the second electrode forms a Schottky junction with the second gallium nitride based semiconductor layer through a second contact hole provided in the insulating layer; 4. The semiconductor device according to claim 3, wherein the first contact hole and the second contact hole have a tapered cross section. 　 The threading dislocation density of the first gallium nitride based semiconductor layer and the second gallium nitride based semiconductor layer is 5×10 ９ / cm ２ 4. The semiconductor device according to claim 3, wherein: 　 The dopant concentration of the second gallium nitride based semiconductor layer is 2×10 １７ ~6 x 10 １７ / cm ３ and the dopant concentration of the first gallium nitride based semiconductor layer is 1×10 １８ ~7 x 10 １８ / cm ３ 4. The semiconductor device according to claim 3, wherein the range is: 　 The oxygen concentration of the first gallium nitride based semiconductor layer and the second gallium nitride based semiconductor layer is 1×10 １７ / cm ３ The semiconductor device according to claim 6 , wherein the thickness is less than 100 μm.

5. The semiconductor device according to claim 4, wherein said second electrode has a field plate structure extending onto said second gallium nitride based semiconductor layer via said insulating layer. 　 the wiring section includes a power supply line electrically connected to the electronic component and a signal line for transmitting a digital signal, 2. The semiconductor device according to claim 1, wherein the width of said power supply line is wider than the width of said signal line.

10. The semiconductor device according to claim 9, wherein the rectifying element is connected to the power supply line to form a protection circuit.

10. The semiconductor device according to claim 9, wherein the rectifying element is connected to the signal line to form a protection circuit. 　 a power supply terminal provided on the substrate; and a rectifier circuit connected to the power supply terminal; The semiconductor device according to claim 1 , wherein the rectifier circuit includes the rectifier element.

2. The semiconductor device according to claim 1, wherein the rectifying element is a Schottky barrier diode. 　 a substrate having a first surface and a second surface opposite the first surface; a first buffer layer covering the first surface; and a second buffer layer covering the second surface. a first wiring section including at least one first wiring layer on the first buffer layer; and a second wiring section including at least one second wiring layer on the second buffer layer. a first electrode pad provided on the first wiring layer and electrically connected to the at least one first wiring layer; and a second electrode pad provided on the second wiring layer and electrically connected to the at least one second wiring layer. a first electronic component electrically connected to the first electrode pad; and a second electronic component electrically connected to the second electrode pad. a first rectifying element electrically connected to the first electronic component via the at least one first wiring layer, and a second rectifying element electrically connected to the second electronic component via the at least one second wiring layer, the first rectifying element includes a first gallium nitride based semiconductor layer in contact with the first buffer layer, and the second rectifying element includes a second gallium nitride based semiconductor layer in contact with the second buffer layer; The first buffer layer, the second buffer layer, the first gallium nitride based semiconductor layer, and the second gallium nitride based semiconductor layer have a crystalline structure. A semiconductor device characterized by:

15. The semiconductor device according to claim 14, wherein said first buffer layer, said second buffer layer, said first gallium nitride based semiconductor layer, and said second gallium nitride based semiconductor layer have a c-axis oriented crystal structure. 　 The first gallium nitride based semiconductor layer is a first n-type gallium nitride based semiconductor layer on the first buffer layer, a second n-type gallium nitride based semiconductor layer on the first n-type gallium nitride based semiconductor layer, a first electrode, and a second electrode, the electrical conductivity of the n-type second gallium nitride based semiconductor layer is lower than the electrical conductivity of the n-type first gallium nitride based semiconductor layer; the first electrode is in ohmic contact with the n-type first gallium nitride based semiconductor layer, and the second electrode forms a Schottky junction with the n-type second gallium nitride based semiconductor layer; the second gallium nitride based semiconductor layer, a third n-type gallium nitride layer on the second buffer layer, a fourth n-type gallium nitride layer on the third n-type gallium nitride layer, a third electrode, and a fourth electrode; the electrical conductivity of the n-type fourth gallium nitride layer is lower than the electrical conductivity of the n-type third gallium nitride layer; The semiconductor device according to claim 14 , wherein the third electrode is in ohmic contact with the n-type third gallium nitride layer, and the fourth electrode forms a Schottky junction with the n-type fourth gallium nitride layer. 　 a first insulating layer covering the n-type first gallium nitride based semiconductor layer and the n-type second gallium nitride based semiconductor layer; the first electrode is in contact with the n-type first gallium nitride based semiconductor layer through a first contact hole provided in the first insulating layer; the second electrode forms a Schottky junction with the n-type second gallium nitride based semiconductor layer through a second contact hole provided in the first insulating layer; a second insulating layer covering the n-type third gallium nitride layer and the n-type fourth gallium nitride layer; the third electrode is in contact with the n-type third gallium nitride layer through a third contact hole provided in the second insulating layer; the fourth electrode forms a Schottky junction with the n-type fourth gallium nitride layer through a fourth contact hole provided in the second insulating layer; 17. The semiconductor device according to claim 16, wherein the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole have a tapered cross section. 　 the threading dislocation density of the n-type first gallium nitride based semiconductor layer, the n-type second gallium nitride based semiconductor layer, the n-type third gallium nitride layer, and the n-type fourth gallium nitride layer is 5×10 ９ / cm ２ 17. The semiconductor device according to claim 16, wherein: 　 The dopant concentration of the n-type second gallium nitride based semiconductor layer and the n-type fourth gallium nitride layer is 2×10 １７ ~6 x 10 １７ / cm ３ and the dopant concentrations of the n-type first gallium nitride based semiconductor layer and the n-type third gallium nitride layer are 1×10 １８ ~7 x 10 １８ / cm ３ 17. The semiconductor device according to claim 16, wherein the range is: 　 the oxygen concentration of the n-type first gallium nitride based semiconductor layer, the n-type second gallium nitride based semiconductor layer, the n-type third gallium nitride layer, and the n-type fourth gallium nitride layer is 1×10 １７ / cm ３ The semiconductor device according to claim 19, wherein the 　 18. The semiconductor device according to claim 17, having a field plate structure in which the second electrode extends onto the n-type second gallium nitride based semiconductor layer via the first insulating layer, and the fourth electrode extends onto the n-type fourth gallium nitride layer via the second insulating layer. 　 the first wiring portion includes a power supply line electrically connected to the first electronic component and a signal line for transmitting a digital signal, 15. The semiconductor device according to claim 14, wherein the width of said power supply line is wider than the width of said signal line.

23. The semiconductor device according to claim 22, wherein the first rectifying element is connected to the power supply line and forms a protection circuit.

23. The semiconductor device according to claim 22, wherein the first rectifying element is connected to the signal line and forms a protection circuit. 　 a power supply terminal provided on the substrate; and a rectifier circuit connected to the power supply terminal; The semiconductor device according to claim 14 , wherein the rectifier circuit includes the first rectifier element. 　 The semiconductor device according to claim 14 , wherein the first rectifying element and the second rectifying element are Schottky barrier diodes.

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