Transistor, display device, electronic device including transistor, and method for manufacturing same

Abstract

A transistor according to an embodiment of the present disclosure may comprise: a buffer layer disposed on a substrate; an oxide semiconductor layer including a first region, a second region, and a channel region disposed between the first region and the second region; a buffer layer disposed under the semiconductor layer; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer and overlapping the channel region; and an interlayer insulating layer disposed on the gate electrode. The concentration of hydrogen (H) in the buffer layer may be in a range of 4×1020atoms / cm3 to 20×1020atoms / cm3.

Description

Transistor, display device, electronic device including transistor, and method for manufacturing the same

[0001] The present disclosure relates to a transistor, a display device, an electronic device including a transistor, and a method for manufacturing the same.

[0002] As information technology advances, the importance of display devices, the medium connecting users and information, is growing. Accordingly, research and development are continuously being conducted to improve the reliability of display devices.

[0003] One aspect of the present disclosure is to provide a transistor having improved reliability and a display device including the same.

[0004] One aspect of the present disclosure is to provide a manufacturing method for manufacturing a transistor with improved reliability.

[0005] A transistor according to an embodiment of the present disclosure comprises: a buffer layer disposed on a substrate; an oxide semiconductor layer disposed on the substrate and including a first region, a second region, and a channel region disposed between the first region and the second region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer and overlapping the channel region; and an interlayer insulating layer disposed on the gate electrode, wherein a hydrogen (H) concentration in the buffer layer is 4×10 20 atoms / cm 3 20×10 20 atoms / cm 3 It could be.

[0006] In an embodiment, at a temperature of 400°C, the concentration of hydrogen gas (H2) released from the buffer layer is 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 And, at a temperature of 400℃, the concentration of moisture (H2O) released from the buffer layer is 1Х10 19atoms / cm 3 20Х10 19 atoms / cm 3 It could be.

[0007] In an embodiment, at a temperature of 400°C, the concentration of hydrogen gas (H2) released from the buffer layer is 1Х10 19 atoms / cm 3 5X10 19 atoms / cm 3 It could be.

[0008] In an embodiment, at a temperature of 400°C, the concentration of moisture (H2O) released from the buffer layer is 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 It could be.

[0009] In some embodiments, the hydrogen (H) concentration within the gate insulating layer is 5Х10 20 atoms / cm 3 30Х10 20 atoms / cm 3 It could be.

[0010] In an embodiment, at a temperature of 400°C, the concentration of hydrogen gas (H2) released from the gate insulating layer is 10Х10 19 atoms / cm 3 60Х10 19 atoms / cm 3 It could be.

[0011] In some embodiments, the hydrogen concentration within the interlayer insulation layer is 4Х10 20 atoms / cm 3 20Х10 20 atoms / cm 3 It could be.

[0012] In an embodiment, at a temperature of 400°C, the concentration of hydrogen gas (H2) released from the interlayer insulation layer is 1Х1019 atoms / cm 3 10Х10 19 atoms / cm 3 It could be.

[0013] In an embodiment, at a temperature of 400°C, the concentration of hydrogen gas (H2) released from the interlayer insulation layer is 1Х10 19 atoms / cm 3 7Х10 inland 19 atoms / cm 3 It could be.

[0014] Depending on the embodiment, the threshold voltage of the transistor may be between 0 V and -3.5 V.

[0015] According to an embodiment, the surface resistance of the interlayer insulating layer may be 1200Ω / □ or less.

[0016] In some embodiments, the gate electrode may comprise aluminum.

[0017] A method for manufacturing a transistor according to an embodiment of the present disclosure comprises the steps of forming a buffer layer; forming a semiconductor layer on the buffer layer, the semiconductor layer including a first region, a second region, and a channel region disposed between the first region and the second region; forming a gate insulating layer disposed on the semiconductor layer; forming a gate electrode disposed on the gate insulating layer and overlapping the channel region; and forming an interlayer insulating layer disposed on the gate electrode, wherein the buffer layer has a hydrogen (H) concentration of 4×10 20 atoms / cm 3 20×10 20 atoms / cm 3 It can be formed like this.

[0018] In an embodiment, the gate insulating layer has a hydrogen (H) concentration of 5Х10 within the gate insulating layer. 20 atoms / cm 3 30Х10 20atoms / cm 3 It is formed like this, The interlayer insulation layer has a hydrogen (H) concentration of 4Х10 20 atoms / cm 3 20Х10 20 atoms / cm 3 It can be formed like this.

[0019] In an embodiment, the buffer layer has a concentration of hydrogen gas (H2) released from the buffer layer of 1Х10 at a temperature of 400°C. 19 atoms / cm 3 10Х10 19 atoms / cm 3 , and the concentration of moisture (H2O) released from the buffer layer is 1Х10 19 atoms / cm 3 20Х10 19 atoms / cm 3 is formed so that the gate insulating layer has a concentration of hydrogen gas (H2) released from the gate insulating layer of 10Х10 at a temperature of 400°C. 19 atoms / cm 3 60Х10 19 atoms / cm 3 is formed so that the interlayer insulating layer has a concentration of hydrogen gas (H2) released from the interlayer insulating layer at a temperature of 400°C of 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 It can be formed to become.

[0020] According to an embodiment, the step of forming the semiconductor layer may include: forming a base oxide semiconductor layer including an oxide semiconductor; patterning the base oxide semiconductor layer to form a buffer semiconductor layer; and doping impurities into both ends of the buffer semiconductor layer.

[0021] A display device according to an embodiment of the present disclosure comprises: a light-emitting element; and a transistor electrically connected to the light-emitting element, wherein the transistor comprises: a buffer layer disposed on a substrate; an oxide semiconductor layer disposed on the buffer layer, the oxide semiconductor layer including a first region, a second region, and a channel region disposed between the first region and the second region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer, the gate electrode overlapping the channel region; and an interlayer insulating layer disposed on the gate electrode, wherein a hydrogen (H) concentration in the buffer layer is 4×10 20 atoms / cm 3 20×10 20 atoms / cm 3 It could be.

[0022] In some embodiments, the hydrogen (H) concentration within the gate insulating layer is 5Х10 20 atoms / cm 3 30Х10 20 atoms / cm 3 , and the hydrogen (H) concentration within the interlayer insulation layer is 4Х10 20 atoms / cm 3 20Х10 20 atoms / cm 3 And, at a temperature of 400℃, the concentration of hydrogen gas (H2) released from the buffer layer is 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 And, at a temperature of 400℃, the concentration of moisture (H2O) released from the buffer layer is 1Х10 19 atoms / cm 3 20Х10 19 atoms / cm 3 And, at a temperature of 400℃, the concentration of hydrogen gas (H2) released from the gate insulating layer is 10Х10 19 atoms / cm 3 60Х10 19 atoms / cm3 And, at a temperature of 400℃, the concentration of hydrogen gas (H2) released from the interlayer insulation layer is 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 It could be.

[0023] Depending on the embodiment, the threshold voltage of the transistor may be between 0 V and -3.5 V.

[0024] According to an embodiment, the surface resistance of the interlayer insulating layer is 1200Ω / □ or less, and the gate electrode may include aluminum.

[0025] An electronic device according to an embodiment of the present disclosure includes a processor and a display device, wherein the display device includes a light-emitting element; and a transistor electrically connected to the light-emitting element, wherein the transistor includes: a buffer layer disposed on a substrate; an oxide semiconductor layer disposed on the buffer layer, the oxide semiconductor layer including a first region, a second region, and a channel region disposed between the first region and the second region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer, the gate electrode overlapping the channel region; and an interlayer insulating layer disposed on the gate electrode, wherein a hydrogen (H) concentration in the buffer layer is 4×10 20 atoms / cm 3 20×10 20 atoms / cm 3 It could be.

[0026] According to an embodiment of the present disclosure, a transistor with improved reliability and a display device including the same can be provided.

[0027] According to an embodiment of the present disclosure, a manufacturing method for manufacturing a transistor with improved reliability can be provided.

[0028] FIG. 1 is a schematic plan view illustrating a transistor according to an embodiment.

[0029] Figure 2 is a schematic cross-sectional view taken along lines Ⅰ to Ⅰ' of Figure 1.

[0030] Figure 3 is a graph showing the threshold voltage of a transistor according to the concentration of hydrogen gas (H2) released from a buffer layer at a temperature of 400°C.

[0031] Figure 4 is a graph showing the threshold voltage of a transistor according to the concentration of moisture (H2O) released from a buffer layer at a temperature of 400°C.

[0032] Figure 5 is a graph showing the threshold voltage difference of a transistor according to the concentration of hydrogen gas (H2) released from the gate insulating layer at a temperature of 400°C.

[0033] Figures 6, 7, 8, 9, 10, 11, and 12 are schematic cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment.

[0034] Fig. 13 is a schematic plan view illustrating a display device according to an embodiment.

[0035] Fig. 14 is a schematic cross-sectional view illustrating the display panel of Fig. 13.

[0036] Figure 15 is a schematic circuit diagram showing the electrical connection relationship of components included in each of the pixels illustrated in Figure 13.

[0037] Fig. 16 is a schematic cross-sectional view showing a pixel according to an embodiment.

[0038] Figure 17 is a block diagram of an electronic device according to one embodiment.

[0039] FIG. 18 is a schematic diagram of an electronic device according to various embodiments.

[0040] This disclosure may be subject to various modifications and takes various forms. Specific embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the disclosure to any specific form, but rather to encompass all modifications, equivalents, and alternatives falling within the spirit and technical scope of the disclosure.

[0041] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present disclosure, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0042] In this disclosure, terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but should be understood to not preemptively exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. In addition, when a part such as a layer, film, region, or plate is said to be "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. In addition, in this specification, when a part such as a layer, film, region, or plate is said to be formed on another part, the direction in which it is formed is not limited to the upper direction, but also includes the case where it is formed in the side or lower direction. Conversely, when a part such as a layer, film, region, or plate is said to be "under" another part, this includes not only the case where it is "directly below" the other part, but also the case where there is another part in between.

[0043] The present disclosure relates to a transistor, a display device, an electronic device including a transistor, and a method for manufacturing the same. Hereinafter, a transistor, a display device, an electronic device including a transistor, and a method for manufacturing the same according to an embodiment will be described with reference to the attached drawings.

[0044] Fig. 1 is a schematic plan view illustrating a transistor according to an embodiment. Fig. 2 is a schematic cross-sectional view taken along lines Ⅰ to Ⅰ' of Fig. 1. Fig. 3 is a graph showing the threshold voltage of a transistor according to the concentration of hydrogen gas (H2) released from a buffer layer at a temperature of 400°C. In the graph of Fig. 3, the X-axis represents the concentration of hydrogen gas (H2) released from the buffer layer (BFL), and the unit is 10 19 atoms / cm 3, and the Y-axis represents the threshold voltage at the initial operation of the transistor (T), and the unit is volt (V). Fig. 4 is a graph showing the threshold voltage of the transistor according to the concentration of moisture (H2O) released from the buffer layer at a temperature of 400°C. In the graph of Fig. 4, the X-axis represents the concentration of moisture (H2O) released from the buffer layer (BFL), and the unit is 10 19 atoms / cm 3 , and the Y-axis represents the threshold voltage at the initial operation of the transistor (T), and the unit is volts (V). Fig. 5 is a graph showing the difference in threshold voltage of the transistor according to the concentration of hydrogen gas (H2) released from the gate insulating layer at a temperature of 400°C. In the graph of Fig. 5, the X-axis represents the concentration of hydrogen gas (H2) released from the gate insulating layer (GI), and the unit is 10 19 atoms / cm 3 , and the Y-axis is the difference between the threshold voltage during initial operation and after operation of the transistor (T), and the unit is millivolt (mV).

[0045] For convenience of explanation, in the present disclosure, the direction in which the plane in which the transistor (T) is placed extends is indicated as the first direction (DR1) and the second direction (DR2), and the vertical direction in the cross-section is indicated as the third direction (DR3).

[0046] Referring to FIGS. 1 and 2, a transistor (T) according to an embodiment may include a gate electrode (GE), a semiconductor layer (SCP), a source electrode (e.g., one of the first electrode (EL1) and the second electrode (EL2)), and a drain electrode (DE) (e.g., one of the first electrode (EL1) and the second electrode (EL2)). According to an embodiment, the transistor (T) may have a lower metal pattern (BML). The transistor (T) according to the present disclosure may be a transistor including an oxide semiconductor as an active layer.

[0047] The semiconductor layer (SCP) is disposed on the buffer layer (BFL) and may include a first region (FA), a second region (SA), and a channel region (CHA) (or a third region) positioned between the first region (FA) and the second region (SA). In an embodiment, the first region (FA) and the second region (SA) may be doped with impurities to have conductivity. The channel region (CHA) may overlap the gate electrode (GE) and may be an intrinsic semiconductor layer that is not doped with impurities.

[0048] The channel region (CHA) may be a region overlapping with the gate electrode (GE). The first region (FA) may be in contact with one end of the channel region (CHA) and may be electrically connected to the first electrode (EL1). The second region (SA) may be in contact with the other end of the channel region (CHA) and may be electrically connected to the second electrode (EL2).

[0049] In an embodiment, the semiconductor layer (SCP) may include an oxide semiconductor. For example, the semiconductor layer (SCP) may include an oxide semiconductor including at least one of indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), and magnesium (Mg).

[0050] In an embodiment, the semiconductor layer (SCP) may include a back surface (or lower surface) and an upper surface that face each other in the thickness direction of the substrate (SUB) (for example, the third direction (DR3)). The back surface of the semiconductor layer (SCP) may be in contact with the buffer layer (BFL), and the upper surface of the semiconductor layer (SCP) may be in contact with the gate insulating layer (GI), the first electrode (EL1), the second electrode (EL2), and the interlayer insulating layer (ILD).

[0051] The substrate (SUB) may include an insulating material such as glass, organic polymer, crystal, etc. The substrate (SUB) may be a rigid substrate or a flexible substrate. The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystalline glass substrate.

[0052] The flexible substrate may be one of a film substrate including a polymer organic material and a plastic substrate. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate.

[0053] A buffer layer (BFL) may be disposed between the substrate (SUB) and the semiconductor layer (SCP). The buffer layer (BFL) may be disposed under the semiconductor layer (SCP).

[0054] A buffer layer (BFL) (or first insulating layer) may be disposed on a substrate (SUB). The buffer layer (BFL) may prevent impurities from diffusing into the semiconductor layer (SCP). The buffer layer (BFL) may be an inorganic insulating film including an inorganic material. The buffer layer (BFL) may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy), or may include at least one of a metal oxide such as aluminum oxide (AlOx). In an embodiment, the buffer layer (BFL) may include silicon oxide (SiOx). The buffer layer (BFL) may be provided as a single layer, but may also be provided as a multilayer having at least two layers or more. When the buffer layer (BFL) is provided as a multilayer, each layer may be formed of the same material or may be formed of different materials.

[0055] The buffer layer (BFL) may contain hydrogen (H). The concentration of hydrogen (H) in the buffer layer (BFL) is 4Х10 20 atoms / cm 3 20Х10 20 atoms / cm 3 It could be.

[0056] The buffer layer (BFL) is 1Х10 at a temperature of 350℃ to 450℃ 19 atoms / cm 3 10Х10 19 atoms / cm 3 can release hydrogen gas (H2). For example, the buffer layer (BFL) can release 1Х10 at a temperature of 400℃. 19 atoms / cm 3 10Х10 19 atoms / cm 3 It can release hydrogen gas (H2).

[0057] In the embodiment, the buffer layer (BFL) has a temperature of 1Х10 at a temperature of 400°C. 19 atoms / cm 3 5X10 19 atoms / cm 3It can release hydrogen gas (H2). In the embodiment, the buffer layer (BFL) has a temperature of 1Х10 at a temperature of 400°C. 19 atoms / cm 3 4X10 19 atoms / cm 3 It can release hydrogen gas (H2).

[0058] The transistor (T) according to the present disclosure can emit hydrogen gas (H2) in the aforementioned numerical range at a temperature of 400°C, since the buffer layer (BFL) contains hydrogen (H) in the aforementioned numerical range. Accordingly, the transistor (T) can have a target threshold voltage and high reliability. In the present disclosure below, the target threshold voltage of the transistor (T) can be about -2.5 V. For example, the target threshold voltage of the transistor (T) can be 0 V to -3.5 V. Experimentally, it may be desirable for the transistor (T) to have a threshold voltage of 0 V to -3.5 V in order to have high reliability without excessively increasing the driving current.

[0059] Referring to Figure 3, hydrogen gas (H2) is 1X10 from the buffer layer (BFL). 19 atoms / cm 3 10Х10 19 atoms / cm 3 As the amount of discharge is increased, it can be seen that the transistor (T) generally has a threshold voltage of 0 V to -3.5 V.

[0060] In the embodiment, the buffer layer (BFL) is 1Х10 at a temperature of 350°C to 450°C. 19 atoms / cm 3 20Х10 19 atoms / cm 3 can release moisture (H2O). For example, the buffer layer (BFL) can release 1Х10 at a temperature of 400℃. 19 atoms / cm 3 20Х10 19atoms / cm 3 It can release moisture (H2O). Hereinafter, in the present disclosure, moisture (H2O) released at a temperature of 350°C to 450°C can be released in the form of a gas (e.g., water vapor).

[0061] In the embodiment, the buffer layer (BFL) has a temperature of 1Х10 at a temperature of 400°C. 19 atoms / cm 3 10Х10 19 atoms / cm 3 can release moisture (H2O). In the embodiment, the buffer layer (BFL) has a temperature of 5Х10 at a temperature of 400°C. 19 atoms / cm 3 10Х10 19 atoms / cm 3 can release moisture (H2O). In an embodiment, the buffer layer (BFL) has a temperature of 6Х10 at a temperature of 400°C. 19 atoms / cm 3 10Х10 19 atoms / cm 3 The transistor (T) according to the present disclosure can have a target threshold voltage and high reliability as the buffer layer (BFL) releases moisture (H2O) in the aforementioned numerical range at a temperature of 400°C.

[0062] Referring to Figure 4, moisture (H2O) from the buffer layer (BFL) is 1Х10 19 atoms / cm 3 20Х10 19 atoms / cm 3 As the amount of discharge is increased, it can be seen that the transistor (T) generally has a threshold voltage of 0 V to -3.5 V.

[0063] At a temperature of 400℃, as more hydrogen gas (H2) and moisture (H2O) are released from the insulating layer of the transistor (T), the threshold voltage of the transistor (T) may tend to a negative value. However, if the threshold voltage of the transistor (T) has an excessively large negative value, the driving current may increase, which may lower the reliability of the transistor (T). Therefore, it may be desirable for the transistor (T) to have a threshold voltage of 0 V to -3.5 V.

[0064] In the embodiment, the buffer layer (BFL) can release hydrogen gas (H2) and moisture (H2O) in the aforementioned numerical range at a temperature of 400°C, and the transistor (T) can have a threshold voltage of 0 V to -3.5 V, so that the reliability of the transistor (T) can be improved.

[0065] In an embodiment, a lower metal pattern (BML) may be placed between a substrate (SUB) and a buffer layer (BFL).

[0066] A lower metal pattern (BML) may be a first conductive layer positioned between a substrate (SUB) and a buffer layer (BFL). The lower metal pattern (BML) may be electrically connected to a second electrode (EL2) through a contact hole that sequentially penetrates an interlayer insulating layer (ILD) and a buffer layer (BFL). In this case, the driving range of a predetermined voltage supplied to a gate electrode (GE) of a transistor (T) may be widened. The lower metal pattern (BML) may be electrically connected to the second electrode (EL2) to stabilize a channel region (CHA) of a semiconductor layer (SCL). In addition, since the lower metal pattern (BML) is electrically connected to the second electrode (EL2), floating of the lower metal pattern (BML) may be prevented.

[0067] The lower metal pattern (BML) may be formed as a single layer made of a suitable (or selected) material from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag) and alloys thereof, or may be formed as a double layer or multilayer structure of a low-resistance material such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) or silver (Ag) to reduce wiring resistance. In an embodiment, the lower metal pattern (BML) may include aluminum (Al).

[0068] In an embodiment, the lower metal pattern (BML) may overlap with the semiconductor layer (SCP). The lower metal pattern (BML) may be utilized as a light-shielding member that protects the transistor (T) by blocking light that may enter from the back surface of the substrate (SUB). To this end, the lower metal pattern (BML) may be composed of a light-shielding and / or light-absorbing material. For example, the lower metal pattern (BML) may be composed of an opaque metal layer.

[0069] A gate insulating layer (GI) may be disposed on a semiconductor layer (SCP). The gate insulating layer (GI) may be disposed between the semiconductor layer (SCP) and a gate electrode (GE).

[0070] The gate insulating layer (GI) (or second insulating layer) may include the same material as the buffer layer (BFL) or may include a suitable (or selected) material from among the materials exemplified as constituent materials of the buffer layer (BFL). For example, the gate insulating layer (GI) may be an inorganic insulating film including an inorganic material.

[0071] The gate insulating layer (GI) may contain hydrogen (H). The concentration of hydrogen (H) in the gate insulating layer (GI) is 5X10 20 atoms / cm 3 30Х10 20 atoms / cm 3 It could be.

[0072] The gate insulating layer (GI) can release more hydrogen gas (H2) than the buffer layer (BFL) at a temperature of 350°C to 450°C. The gate insulating layer (GI) can release 10Х10 hydrogen gas at a temperature of 350°C to 450°C. 19 atoms / cm 3 60Х10 19 atoms / cm 3 can release hydrogen gas (H2). For example, the gate insulating layer (GI) can release hydrogen gas (H2) at a temperature of 400℃. 19 atoms / cm 3 60Х10 19 atoms / cm 3 It can release hydrogen gas (H2).

[0073] The transistor (T) according to the present disclosure can release hydrogen gas (H2) from the gate insulating layer (GI) in the aforementioned numerical range at a temperature of 400°C, as the gate insulating layer (GI) contains hydrogen (H) in the aforementioned numerical range. Accordingly, the transistor (T) can have high reliability. In order for the transistor (T) to have high reliability, it may be preferable that the threshold voltage difference value between the initial operation and the post-operation operation be 75 mV or less.

[0074] Referring to Fig. 5, at a temperature of 400°C, hydrogen gas (H2) is released from the gate insulating layer (GI) at a rate of 10Х10 19 atoms / cm 3 60Х10 19 atoms / cm 3 As much as is emitted, it can be confirmed that the threshold voltage difference of the transistor (T) is within 75 mV.

[0075] According to the present disclosure, the transistor (T) can release hydrogen gas (H2) in the above-described range from the gate insulating layer (GI) at a temperature of 400°C, as the gate insulating layer (GI) contains hydrogen (H) in the above-described range. Accordingly, the transistor (T) can have high reliability.

[0076] A gate electrode (GE) can be placed on a gate insulating layer (GI).

[0077] A gate electrode (GE) may overlap a channel region (CHA) of a semiconductor layer (SCP) with a gate insulating layer (GI) therebetween. The gate electrode (GE) may be made of a conductive material, such as a metal. For example, the gate electrode (GE) may include at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof. In an embodiment, the gate electrode (GE) may include aluminum (Al). The gate electrode (GE) may be utilized as an anti-doping layer to prevent impurities from being doped into the channel region (CHA). The gate electrode (GE) may define the channel region (CHA) of the semiconductor layer (SCP).

[0078] An interlayer dielectric layer (ILD) may be disposed on the gate electrode (GE).

[0079] An interlayer insulating layer (ILD) (or third insulating layer) may be provided and / or formed over the entire surface of the gate electrode (GE) and the buffer layer (BFL). The interlayer insulating layer (ILD) may include the same material as the buffer layer (BFL) or may include one or more materials suitable (or selected) from the materials exemplified as constituent materials of the buffer layer (BFL). As an example, the interlayer insulating layer (ILD) may be an inorganic insulating film including an inorganic material, but is not limited thereto. According to an embodiment, the interlayer insulating layer (ILD) may be an organic insulating film including an organic material. The organic insulating film may include, for example, at least one of a polyacrylate resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimides resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfides resin, and a benzocyclobutene resin.

[0080] The interlayer dielectric layer (ILD) may contain hydrogen (H). In an embodiment, the concentration of hydrogen (H) in the interlayer dielectric layer (ILD) is 4Х10 20 atoms / cm 3 20Х10 20 atoms / cm 3 It could be.

[0081] The interlayer insulation (ILD) has a temperature of 1Х10 at a temperature of 350℃ to 450℃. 19 atoms / cm 3 10Х10 19 atoms / cm 3 can release hydrogen gas (H2). For example, the interlayer dielectric (ILD) can release 1Х10 at a temperature of 400℃.19 atoms / cm 3 10Х10 19 atoms / cm 3 It can release hydrogen gas (H2).

[0082] In the embodiment, the interlayer insulation layer (ILD) has a temperature of 1Х10 at a temperature of 400°C. 19 atoms / cm 3 7Х10 inland 19 atoms / cm 3 can release hydrogen gas (H2). In an embodiment, the interlayer insulating layer (ILD) has a temperature of 1Х10 at a temperature of 400°C. 19 atoms / cm 3 6Х10 19 atoms / cm 3 It can release hydrogen gas (H2).

[0083] The transistor (T) according to the present disclosure can release hydrogen gas (H2) from the interlayer insulating layer (ILD) in the aforementioned numerical range, as the interlayer insulating layer (ILD) contains hydrogen (H) in the aforementioned numerical range. Accordingly, the interlayer insulating layer (ILD) can have a sheet resistance of 1200Ω / □ or less and can have high reliability. Experimentally, it may be desirable for the transistor (T) to have a sheet resistance of 1200Ω / □ or less in order to have high reliability.

[0084] A first electrode (EL1) and a second electrode (EL2) can be arranged on the interlayer insulating layer (ILD).

[0085] A first electrode (EL1) is positioned on an interlayer insulating layer (ILD) so as to overlap a first region (FA) of a semiconductor layer (SCP) and can be electrically connected to the first region (FA) of the semiconductor layer (SCP) through a contact hole penetrating one region of the interlayer insulating layer (ILD). A second electrode (EL2) is positioned on the interlayer insulating layer (ILD) so as to overlap a second region (SA) of the semiconductor layer (SCP) and can be electrically connected to the second region (SA) of the semiconductor layer (SCP) through a contact hole penetrating another region of the interlayer insulating layer (ILD).

[0086] The first electrode (EL1) and the second electrode (EL2) may be spaced apart from each other on an interlayer insulating layer (ILD) on the gate electrode (GE). One of the first electrode (EL1) and the second electrode (EL2) may be a source electrode, and the other may be a drain electrode.

[0087] Each of the first and second electrodes (EL1, EL2) may include a conductive material, such as a metal. Each of the first and second electrodes (EL1, EL2) may include the same material as the lower metal pattern (BML) or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the lower metal pattern (BML).

[0088] A passivation layer may be provided on the first and second electrodes (EL1, EL2) to protect the first and second electrodes (EL1, EL2).

[0089] Figures 6 to 12 are schematic cross-sectional views illustrating a method for manufacturing a transistor according to an embodiment.

[0090] Hereinafter, a transistor according to an embodiment will be sequentially described according to a manufacturing method with reference to FIGS. 6 to 12.

[0091] In the embodiment, the manufacturing steps of the transistor are described as being performed sequentially according to the cross-section, but it is obvious that some steps depicted as being performed sequentially may be performed simultaneously, the order of each step may be changed, some steps may be omitted, or other steps may be included between each step, as long as the technical scope of the invention is not changed.

[0092] Referring to FIG. 6, a method for manufacturing a transistor (T) may include a step of forming a lower metal pattern (BML) on a substrate (SUB).

[0093] The substrate (SUB) may be a glass substrate, but may also be one of a variety of substrates used in typical semiconductor device processes, such as a plastic substrate or a silicon substrate.

[0094] A bottom metal pattern (BML) can be formed by depositing a conductive material on one side (or upper side) of a substrate (SUB) to form a conductive layer, and then patterning the formed conductive layer using a photolithography process using a mask. The conductive material may be, for example, a single layer of metal, or multiple layers of metals or alloys thereof, but is not limited thereto.

[0095] Referring to FIG. 6, a method for manufacturing a transistor (T) may include a step of forming a buffer layer (BFL) on a lower metal pattern (BML) and a substrate (SUB).

[0096] The step of forming a buffer layer (BFL) is to ensure that the concentration of hydrogen (H) in the buffer layer (BFL) is 4Х10 20 atoms / cm 3 20Х10 20 atoms / cm 3 This may include a step of forming a buffer layer (BFL). The concentration of hydrogen (H) in the buffer layer (BFL) can be controlled by controlling process conditions such as the temperature of the chamber in which deposition of the buffer layer (BFL) is performed, the partial pressure of oxygen in the chamber, and the deposition time.

[0097] The step of forming the buffer layer (BFL) is to form the buffer layer (BFL) at a temperature of 350°C to 450°C for 1X10 19 atoms / cm 3 10Х10 19 atoms / cm 3 may include a step of forming a buffer layer (BFL) to release hydrogen gas (H2). For example, the step of forming a buffer layer (BFL) may include forming a buffer layer (BFL) at a temperature of 400°C to 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 It may include a step of forming to release hydrogen gas (H2).

[0098] In the embodiment, the step of forming the buffer layer (BFL) is performed by forming the buffer layer (BFL) at a temperature of 400°C and 1Х10 19 atoms / cm 3 5X10 19 atoms / cm 3 A step of forming a buffer layer (BFL) to release hydrogen gas (H2) may be included. In an embodiment, the step of forming a buffer layer (BFL) may include forming a buffer layer (BFL) at a temperature of 400°C and a temperature of 1Х10 19 atoms / cm 3 4X10 19 atoms / cm 3 It may include a step of forming to release hydrogen gas (H2).

[0099] The step of forming the buffer layer (BFL) is to form the buffer layer (BFL) at a temperature of 350°C to 450°C for 1X10 19 atoms / cm 3 20Х10 19 atoms / cm 3 may include a step of forming a buffer layer (BFL) to release moisture (H2O). For example, the step of forming a buffer layer (BFL) may include forming a buffer layer (BFL) at a temperature of 400°C to 1Х10 19 atoms / cm 3 20Х1019 atoms / cm 3 It may include a step of forming to release moisture (H2O).

[0100] In the embodiment, the step of forming the buffer layer (BFL) is performed by forming the buffer layer (BFL) at a temperature of 400°C and 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 A step of forming a buffer layer (BFL) to release moisture (H2O) may be included. In an embodiment, the step of forming a buffer layer (BFL) may include forming a buffer layer (BFL) at a temperature of 400°C to 5Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 A step of forming a buffer layer (BFL) to release moisture (H2O) may be included. In an embodiment, the step of forming a buffer layer (BFL) may include forming a buffer layer (BFL) at a temperature of 400°C to 6Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 It may include a step of forming to release moisture (H2O).

[0101] The buffer layer (BFL) can be formed by a CVD (Chemical Vapor Deposition) method or a sputtering method using a gas containing silane and nitrogen oxide (N2O), but the method for forming the buffer layer (BFL) is not limited thereto.

[0102] In an embodiment, the buffer layer (BFL) may be provided in the form of a multilayer including a double layer. For example, when the buffer layer (BFL) is composed of a double layer including a first layer and a second layer sequentially laminated, the first layer and the second layer may be composed of different materials among inorganic materials and may be formed through different processes, but is not limited thereto. In an embodiment, the first layer and the second layer may include the same material and be formed through a continuous process.

[0103] In an embodiment, a heat treatment process may be performed after the buffer layer (BFL) is formed. Through the heat treatment process, the hydrogen (H) concentration of the buffer layer (BFL) can be controlled, and the hydrogen (H) content of the buffer layer (BFL) can be optimized to minimize the influence on the semiconductor layer (SCP) (or defects in the semiconductor layer (SCP)).

[0104] Referring to Fig. 8, a method for manufacturing a transistor (T) may include a step of forming a buffer semiconductor layer (SCP'). After forming a base oxide semiconductor layer (not shown) on the buffer layer (BFL), the base oxide semiconductor layer may be patterned through a photolithography process using a mask to form the buffer semiconductor layer (SCP'). The buffer semiconductor layer (SCP') may be an intrinsic semiconductor that is not doped with impurities.

[0105] Referring to FIGS. 9 and 10, a method for manufacturing a transistor (T) may include a step of forming a gate insulating layer (GI) and a gate electrode (GE) on a buffer semiconductor layer (SCP').

[0106] The step of forming a gate insulating layer (GI) and a gate electrode (GE) may include a step of sequentially forming a first base layer (BSL1) and a second base layer (BSL2) on a buffer semiconductor layer (SCP') and a buffer layer (BFL) using at least one of a CVD (Chemical Vapor Deposition) method and a sputtering method.

[0107] According to an embodiment, the gate insulating layer (GI) may be formed by a CVD (Chemical Vapor Deposition) method or a sputtering method using a gas containing silane and nitrogen oxide (N2O), but the method of forming the gate insulating layer (GI) is not limited thereto.

[0108] The first base layer (BSL1) may be a base material of a gate insulating layer (GI). The first base layer (BSL1) may be etched to form a gate insulating layer (GI). The second base layer (BSL2) may be a base material of a gate electrode (GE). The second base layer (BSL2) may be etched to form a gate electrode (GE).

[0109] In an embodiment, after forming the first base layer (BSL1), surface treatment may be performed. The surface treatment may include a heat treatment process, for example, an annealing process.

[0110] The step of forming a gate insulating layer (GI) and a gate electrode (GE) may include a step of etching a first base insulating layer (BSL1) and a second base insulating layer (BSL2) to form the gate insulating layer (GI) and the gate electrode (GE). The second base layer (BSL2) may be patterned by performing a photolithography process using a mask, and the gate electrode (GE) may be formed. The gate electrode (GE) may overlap a portion of the buffer semiconductor layer (SCP'). For example, the gate electrode (GE) may overlap a central region of the buffer semiconductor layer (SCP'). In this case, both end portions of the buffer semiconductor layer (SCP') may not be covered by the gate electrode (GE).

[0111] In a photolithography process for forming a gate electrode (GE), a gate insulating layer (GI) may be formed by removing a portion of a first base layer (BSL1) using the gate electrode (GE) as an etching mask. The gate insulating layer (GI) may have a width substantially the same as or similar to that of the gate electrode (GE), but is not limited thereto. The gate electrode (GE) and the gate insulating layer (GI) may overlap.

[0112] The step of forming the gate insulating layer (GI) is to have a concentration of hydrogen (H) in the gate insulating layer (GI) of 5Х10 20 atoms / cm 3 30Х10 20 atoms / cm 3 This may include a step of forming a gate insulating layer (GI). The concentration of hydrogen (H) in the gate insulating layer (GI) can be controlled by controlling process conditions such as the temperature of the chamber in which deposition of the gate insulating layer (GI) is performed, the partial pressure of oxygen in the chamber, and the deposition time.

[0113] The step of forming the gate insulating layer (GI) is to form the gate insulating layer (GI) at a temperature of 350°C to 450°C at a temperature of 10Х10 19 atoms / cm 3 60Х10 19atoms / cm 3 may include a step of forming a gate insulating layer (GI) to emit hydrogen gas (H2). For example, the step of forming a gate insulating layer (GI) may include forming a gate insulating layer (GI) at a temperature of 400°C to 10Х10 19 atoms / cm 3 60Х10 19 atoms / cm 3 It may include a step of forming to release hydrogen gas (H2).

[0114] Referring to FIG. 11, a method for manufacturing a transistor (T) may include a step of forming a semiconductor layer (SCP). An end of a buffer semiconductor layer (SCP') not covered by a gate electrode (GE) may be doped with an impurity, and a semiconductor layer (SCP) including a first region (FA) and a second region (SA) having conductivity may be formed.

[0115] The semiconductor layer (SCP) is positioned between the first region (FA) and the second region (SA) and may include a channel region (CHA) that is not doped with impurities and overlaps the gate electrode (GE).

[0116] Referring to FIG. 12, a method for manufacturing a transistor (T) may include a step of forming an interlayer insulating layer (ILD) on a gate electrode (GE), a semiconductor layer (SCP), and a buffer layer (BFL).

[0117] The interlayer dielectric layer (ILD) can be formed by a chemical vapor deposition (CVD) method using a gas containing silane and nitrogen oxide (N2O) or a sputtering method, but the method for forming the interlayer dielectric layer (ILD) is not limited thereto.

[0118] The interlayer insulating layer (ILD) may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material. In the step of forming the interlayer insulating layer (ILD), the interlayer insulating layer (ILD) may be partially opened so that a first region (FA) of the semiconductor layer (SCP), a second region (SA) of the semiconductor layer (SCP), and a region corresponding to the lower metal pattern (BML) are removed.

[0119] The step of forming the interlayer dielectric layer (ILD) is to ensure that the concentration of hydrogen (H) in the interlayer dielectric layer (ILD) is 4Х10 20 atoms / cm 3 20Х10 20 atoms / cm 3 This may include a step of forming an interlayer dielectric layer (ILD). The concentration of hydrogen (H) in the interlayer dielectric layer (ILD) can be controlled by controlling process conditions such as the temperature of the chamber in which deposition of the interlayer dielectric layer (ILD) is performed, the partial pressure of oxygen in the chamber, and the deposition time.

[0120] The step of forming the interlayer insulation layer (ILD) is to form the interlayer insulation layer (ILD) at a temperature of 350°C to 450°C for 1X10 19 atoms / cm 3 10Х10 19 atoms / cm 3 may include a step of forming an interlayer insulating layer (ILD) to emit hydrogen gas (H2). For example, the step of forming an interlayer insulating layer (ILD) may include forming an interlayer insulating layer (ILD) at a temperature of 400°C to 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 It may include a step of forming to release hydrogen gas (H2).

[0121] In the embodiment, the step of forming the interlayer insulating layer (ILD) is performed at a temperature of 400°C and a temperature of 1Х10 19 atoms / cm 3 7Х10 inland 19 atoms / cm3 A step of forming the interlayer insulating layer (ILD) to emit hydrogen gas (H2) may be included. In an embodiment, the step of forming the interlayer insulating layer (ILD) may include forming the interlayer insulating layer (ILD) at a temperature of 400°C to 1Х10 19 atoms / cm 3 6Х10 19 atoms / cm 3 It may include a step of forming to release hydrogen gas (H2).

[0122] After the interlayer insulating layer (ILD) is formed, a process of forming a first electrode (EL1) and a second electrode (EL2) spaced apart from each other on the interlayer insulating layer (ILD) may be performed. The first electrode (EL1) may be electrically connected to a first region (FA) of the semiconductor layer (SCP), and the second electrode (EL2) may be electrically connected to a second region (SA) of the semiconductor layer (SCP).

[0123] The transistor (T) manufactured through the above-described process can be employed in various electronic devices, for example, in a display device. The display device includes a light-emitting element and a transistor electrically connected to the light-emitting element, and can employ the transistor (T) according to the above-described embodiment as the transistor.

[0124] Fig. 13 is a schematic plan view illustrating a display device according to an embodiment. Fig. 14 is a schematic cross-sectional view illustrating the display panel of Fig. 13.

[0125] In FIGS. 13 and 14, for convenience, the structure of a display device (DD) and a display panel (DP) provided in the display device (DD) is briefly illustrated with a focus on a display area (DA) where an image is displayed.

[0126] Referring to FIGS. 13 and 14, a display panel (DP) (or display device (DD)) according to an embodiment may include a substrate (SUB), pixels (PXL) arranged on the substrate (SUB), a driving unit provided on the substrate (SUB) and driving the pixels (PXL), and a wiring unit connecting the pixels (PXL) and the driving unit.

[0127] The substrate (SUB) may be capable of transmitting light by including a transparent insulating material. The substrate (SUB) may be a rigid substrate or a flexible substrate. The substrate (SUB) may include the same material as the substrate (SUB) described with reference to FIGS. 1 and 2.

[0128] One area on the substrate (SUB) may be provided as a display area (DA) in which pixels (PXL) are arranged, and the remaining area on the substrate (SUB) may be provided as a non-display area (NDA). For example, the substrate (SUB) may include a display area (DA) including pixel areas in which each pixel (PXL) is arranged, and a non-display area (NDA) arranged around the display area (DA) (or adjacent to the display area (DA)).

[0129] The display area (DA) can have various shapes. For example, the display area (DA) can be provided in various shapes, such as a closed polygon with straight sides, a circle or ellipse with curved sides, a semicircle or semi-ellipse with straight and curved sides, etc.

[0130] A non-display area (NDA) may be provided on at least one side of the display area (DA). For example, the non-display area (NDA) may surround the periphery of the display area (DA). A driving unit for driving pixels (PXL) and a portion of a wiring unit (for example, fan-out lines) connecting the pixels (PXL) and the driving unit may be provided in the non-display area (NDA). The non-display area (NDA) may correspond to a bezel area of ​​the display device (DD).

[0131] Pixels (PXL) may be provided in a display area (DA) of a substrate (SUB). Each pixel (PXL) may be the smallest unit for displaying an image. The pixels (PXL) may include a light-emitting element that emits white light and / or colored light. Each pixel (PXL) may emit one of red, green, and blue colors, but is not limited thereto, and may also emit colors such as cyan, magenta, and yellow.

[0132] The pixels (PXL) may be arranged in a matrix form along rows (or pixel rows) extending in a first direction (DR1) and columns (or pixel columns) extending in a second direction (DR2) intersecting the first direction (DR1). However, the arrangement form of the pixels (PXL) is not particularly limited, and may be arranged in various forms. In the drawing, the pixels (PXL) are illustrated as having a rectangular shape, but are not limited thereto, and may be modified into various shapes. In addition, when a plurality of pixels (PXL) are provided, they may be provided to have different areas (or sizes). For example, in the case of pixels (PXL) that emit light of different colors, the pixels (PXL) for each color may be provided in different areas (or sizes) or different shapes.

[0133] The driving unit can control the driving of each pixel (PXL) by providing signals and power to each pixel (PXL) through the wiring unit.

[0134] Each pixel (PXL) may include a pixel circuit layer (PCL), a display element layer (DPL), and an encapsulation layer (TFE) located on a substrate (SUB).

[0135] A pixel circuit layer (PCL) is provided on a substrate (SUB) and may include a plurality of transistors and signal lines connected to the transistors. For example, each transistor may have a semiconductor layer, a gate electrode, a first terminal, and a second terminal sequentially stacked with an insulating layer therebetween. At least one of the plurality of transistors may correspond to the transistor (T) described above. The semiconductor layer may include an oxide semiconductor. The gate electrode, the first terminal, and the second terminal may include at least one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), but are not limited thereto. In addition, the pixel circuit layer (PCL) may include at least one insulating layer.

[0136] A display element layer (DPL) may be disposed on the pixel circuit layer (PCL). The display element layer (DPL) may include a light-emitting element that emits light. The light-emitting element may be, for example, an organic light-emitting diode, but is not limited thereto. According to an embodiment, the light-emitting element may be an inorganic light-emitting element including an inorganic light-emitting material or a light-emitting element that changes the wavelength of the emitted light using quantum dots to emit light.

[0137] An encapsulation layer (TFE) may be disposed on the display element layer (DPL). The encapsulation layer (TFE) may be in the form of an encapsulation substrate or an encapsulation film formed of a multilayer film. When the encapsulation layer (TFE) is in the form of the encapsulation film, it may include an inorganic film and / or an organic film. For example, the encapsulation layer (TFE) may be in the form of an inorganic film, an organic film, and an inorganic film sequentially laminated. The encapsulation layer (TFE) can prevent external air and moisture from penetrating into the display element layer (DPL) and the pixel circuit layer (PCL).

[0138] Figure 15 is a schematic circuit diagram showing the electrical connection relationship of components included in each of the pixels illustrated in Figure 13.

[0139] Referring to FIGS. 13 to 15, a pixel (PXL) may include a light-emitting element (LD) and a pixel circuit (PXC) electrically connected to the light-emitting element (LD) to drive the light-emitting element (LD).

[0140] The pixel electrode (AE) (or anode electrode) of the light emitting element (LD) can be electrically connected to the pixel circuit (PXC). The light emitting element (LD) generates light of a predetermined brightness in response to the amount of current supplied from the pixel circuit (PXC). To this end, the second driving power supply (ELVSS) electrically connected to the common electrode (CE) (or cathode electrode) of the light emitting element (LD) during the driving period of the display device (DD) can be set to a lower voltage than the first driving power supply (ELVDD), but is not limited thereto.

[0141] When a pixel (PXL) is located in the i-th row and j-th column in the display area (DA), a pixel circuit (PXC) of the pixel (PXL) may be electrically connected to the i-th scan line (Si) and the j-th data line (DLj). In addition, the pixel circuit (PXC) may be electrically connected to the i-th sensing line (SLi) and the j-th reference voltage line (RFj).

[0142] The pixel circuit (PXC) can control the amount of current flowing from the first driving power supply (ELVDD) to the second driving power supply (ELVSS) via the light emitting element (LD) in response to a data signal (or data voltage).

[0143] The pixel circuit (PXC) may include first, second, and third transistors (T1, T2, T3) and a storage capacitor (Cst).

[0144] The first transistor (T1) is a driving transistor for controlling a driving current applied to a light-emitting element (LD), and can be electrically connected between a first driving power source (ELVDD) and the light-emitting element (LD). Specifically, a first terminal of the first transistor (T1) can be electrically connected to the first driving power source (ELVDD) through a driving voltage line (DVL), a second terminal of the first transistor (T1) can be electrically connected to a second node (N2), and a gate electrode of the first transistor (T1) can be electrically connected to the first node (N1). The first transistor (T1) can control the amount of driving current applied to the light-emitting element (LD) from the first driving power source (ELVDD) through the second node (N2) according to a voltage applied to the first node (N1). In an embodiment, the first terminal of the first transistor (T1) may be a drain electrode, and the second terminal of the first transistor (T1) may be a source electrode, but is not limited thereto. Depending on the embodiment, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0145] The second transistor (T2) may be a switching transistor that selects a pixel (PXL) in response to a scan signal and activates the pixel (PXL), and may be electrically connected between the j-th data line (DLj) and the first node (N1). A first terminal of the second transistor (T2) may be electrically connected to the j-th data line (DLj), a second terminal of the second transistor (T2) may be electrically connected to the first node (N1), and a gate electrode of the second transistor (T2) may be electrically connected to the i-th scan line (Si). The first terminal and the second terminal of the second transistor (T2) may be different terminals, for example, if the first terminal is a drain electrode, the second terminal may be a source electrode.

[0146] In this way, the second transistor (T2) can be turned on when a scan signal of a gate-on voltage (e.g., a high level voltage) is supplied from the ith scan line (Si), thereby electrically connecting the jth data line (DLj) and the first node (N1). The second transistor (T2) can transmit a data signal to the gate electrode of the first transistor (T1).

[0147] The third transistor (T3) can be turned on when a sensing signal is supplied from the ith sensing line (SLi) to electrically connect the jth reference voltage line (RFj) to the first transistor (T1) (or the second node (N2)). A first terminal of the third transistor (T3) is electrically connected to the jth reference voltage line (RFj), a second terminal of the third transistor (T3) is electrically connected to the second node (N2), and a gate electrode of the third transistor (T3) can be electrically connected to the ith sensing line (SLi).

[0148] The third transistor (T3) may be a sensing transistor that operates to supply a reference voltage (Vref) transmitted through the j-th reference voltage line (RFj) to the second node (N2) or to sense the voltage or current of the second node (N2) or the j-th reference voltage line (RFj). Here, the reference voltage (Vref) may be a voltage lower than the voltage of the first driving power supply (ELVDD) and / or a data voltage, for example, a voltage of an initialization power supply.

[0149] The storage capacitor (Cst) may include a first storage electrode and a second storage electrode. The first storage electrode of the storage capacitor (Cst) may be electrically connected to a first node (N1), and the second storage electrode of the storage capacitor (Cst) may be electrically connected to a second node (N2). The storage capacitor (Cst) charges a data voltage corresponding to a data signal supplied to the first node (N1) during one frame period. The storage capacitor (Cst) may store a voltage corresponding to a difference between a voltage of a gate electrode of the first transistor (T1) and a voltage of the second node (N2).

[0150] In an embodiment, at least one of the first, second, and third transistors (T1, T2, T3) included in the pixel circuit (PXC) may be an oxide transistor. At least one of the first, second, and third transistors (T1, T2, T3) may be the transistor (T) described above. As an example, the transistor (T) may be the first transistor (T1) described with reference to FIG. 15.

[0151] For example, the first transistor (T1) can be implemented as an NMOS including an oxide semiconductor having a low off current.

[0152] The structure of the pixel circuit (PXC) can be variously modified. For example, the pixel circuit (PXC) may further include at least one transistor element, such as a transistor element for initializing the first node (N1) and / or a transistor element for controlling the light-emitting time of the light-emitting element (LD), or other circuit elements, such as a boosting capacitor for boosting the voltage of the first node (N1). For example, the pixel circuit (PXC) may be configured to include five transistor elements and two capacitors. According to an embodiment, the pixel circuit (PXC) may also include seven transistor elements and two capacitors.

[0153] Fig. 16 is a schematic cross-sectional view showing a pixel according to an embodiment.

[0154] Referring to FIGS. 13 to 16, a pixel (PXL) according to an embodiment may be located in a pixel area (PXA) provided in a display area (DA). The pixel area (PXA) may include an emitting area (EMA) and a non-emitting area (NEA).

[0155] The pixel circuit layer (PCL) and the display element layer (DPL) may be arranged to overlap each other on one surface of the substrate (SUB). For example, the pixel area (PXA) of the substrate (SUB) may include a pixel circuit layer (PCL) arranged on one surface of the substrate (SUB) and a display element layer (DPL) arranged on the pixel circuit layer (PCL). However, the mutual positions of the pixel circuit layer (PCL) and the display element layer (DPL) on the substrate (SUB) may vary depending on the embodiment.

[0156] The substrate (SUB) may be capable of transmitting light by including a transparent insulating material. The substrate (SUB) may be a rigid substrate or a flexible substrate.

[0157] In each pixel area (PXA) of the pixel circuit layer (PCL), circuit elements (e.g., transistors (T)) constituting a pixel circuit (PXC) and predetermined signal wires electrically connected to the circuit elements can be arranged.

[0158] In each pixel area (PXA) of the display element layer (DPL), a light emitting element (LD) electrically connected to a pixel circuit (PXC) can be arranged.

[0159] A pixel circuit layer (PCL) may include a pixel circuit (PXC) including a transistor (T), and insulating layers disposed between the components of the transistor (T). For example, the insulating layers may include a buffer layer (BFL), a gate insulating layer (GI), an interlayer insulating layer (ILD), and a via layer (VIA) sequentially stacked on a substrate (SUB) along a third direction (DR3).

[0160] A via layer (VIA) may be provided and / or formed over the entire surface of the first and second electrodes (EL1, EL2) of the transistor (T) and the interlayer insulating layer (ILD). The via layer (VIA) may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material. The inorganic insulating film may include, for example, at least one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The organic insulating film may include, for example, at least one of polyacrylates, epoxy, phenol, polyamides, polyimides, unsaturated polyesters, polyphenylene ethers, polyphenylene sulfides, and benzocyclobutene. In an embodiment, the via layer (VIA) may be an organic insulating film including an organic material. The via layer (VIA) may also be utilized as a planarization layer to alleviate a step difference caused by components located thereunder.

[0161] The via layer (VIA) may be partially opened to expose a portion of the transistor (T) to electrically connect the light emitting element (LD) and the transistor (T).

[0162] A display element layer (DPL) may be positioned on the via layer (VIA).

[0163] The display element layer (DPL) may include a light emitting element (LD) and a pixel defining layer (PDL).

[0164] The light emitting element (LD) may include a pixel electrode (AE), an emission layer (EML), and a common electrode (CE). Although not directly illustrated in the drawing, the light emitting element (LD) may be electrically connected to a transistor (T).

[0165] The pixel electrode (AE) may be provided and / or formed on a via layer (VIA). The pixel electrode (AE) may be an anode electrode of a light-emitting element (LD). The pixel electrode (AE) may be located at least in the light-emitting area (EMA).

[0166] The pixel electrode (AE) may be composed of a material having reflectivity. For example, the pixel electrode (AE) may be composed of a conductive material (or materials). The conductive material may include an opaque metal. The opaque metal may include, for example, metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. However, the material of the pixel electrode (AE) is not limited to the above-described embodiment. According to an embodiment, the pixel electrode (AE) may include a transparent conductive material (or materials). The transparent conductive material (or material) may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), and conductive polymers such as poly(3,4-ethylenedioxythiophene) (PEDOT). When the pixel electrode (AE) includes a transparent conductive material (or material), a separate conductive layer made of an opaque metal may be added to reflect light emitted from the light-emitting layer (EML) in the image display direction of the display device (DD) (or in the upper direction of the encapsulation layer (TFE)).

[0167] A pixel defining layer (PDL) is positioned in a non-emission area (NEA) and can define an emission area (EMA) of each pixel (PXL). The pixel defining layer (PDL) can include an aperture (OP) arranged in an area corresponding to an area of ​​a pixel electrode (AE). The aperture (OP) of the pixel defining layer (PDL) can correspond to each emission area (EMA).

[0168] The pixel defining layer (PDL) may be composed of an organic insulating layer including an organic material. The organic material may include polyacrylates, epoxy resins, phenol resins, polyamides, polyimides, unsaturated polyesters, polyphenylene ethers, polyphenylene sulfides, and benzocyclobutene resins. In some embodiments, the pixel defining layer (PDL) may include a light absorbing material or may be coated with a light absorbing agent to absorb light introduced from the outside. For example, the pixel defining layer (PDL) may include a carbon-based black pigment. However, the present invention is not limited thereto.

[0169] The pixel defining layer (PDL) can protrude in a third direction (DR3) from the via layer (VIA) along the perimeter of the emitting area (EMA).

[0170] An emission layer (EML) can be placed in an aperture (OP) that is not covered by a pixel electrode (AE).

[0171] The light-emitting layer (EML) can be positioned only on the pixel electrode (AE) within the opening (OP) of the pixel defining layer (PDL). The light-emitting layer (EML) can be supplied to a target area of ​​the corresponding pixel (PXL) (for example, an upper area of ​​the pixel electrode (AE) not covered by the pixel defining layer (PDL)) by an inkjet printing method or a process using a mask, but the method of forming the light-emitting layer (EML) is not limited thereto. The light-emitting layer (EML) can have a multilayer thin film structure including a light generation layer that generates light. For example, the light emitting layer (EML) may include, but is not limited to, a hole injection layer that injects holes, a hole transport layer that has excellent hole transport properties and increases the chance of recombination of holes and electrons by suppressing the movement of electrons that are not combined in the light generating layer, the light generating layer that emits light by the recombination of injected electrons and holes, a hole blocking layer that suppresses the movement of holes that are not combined in the light generating layer, an electron transport layer that smoothly transports electrons to the light generating layer, and an electron injection layer that injects electrons.

[0172] A common electrode (CE) may be placed on the emission layer (EML).

[0173] The common electrode (CE) may be a cathode electrode of a light emitting element (LD). The common electrode (CE) may be a common layer commonly provided to pixels (PXL). The common electrode (CE) may be provided in a plate shape across the display area (DA). The common electrode (CE) may be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting layer (EML). The common electrode (CE) may be formed of a metal material to have a relatively thin thickness or may be formed of a transparent conductive material. For example, the common electrode (CE) may be composed of various transparent conductive materials. The common electrode (CE) includes at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide, and may be implemented to be substantially transparent or translucent so as to satisfy a predetermined light transmittance. Accordingly, light emitted from the light emitting layer (EML) located under the common electrode (CE) can be emitted through the common electrode (CE) and the encapsulating layer (TFE).

[0174] An encapsulating layer (TFE) may be positioned on the common electrode (CE).

[0175] The encapsulation layer (TFE) may be formed as a single film, but may also be formed as a multi-film. The encapsulation layer (TFE) may include a plurality of insulating films covering the light emitting element (LD). Specifically, the encapsulation layer (TFE) may include at least one inorganic film and at least one organic film. For example, the encapsulation layer (TFE) may have a structure in which inorganic films and organic films are alternately laminated. According to an embodiment, the encapsulation layer (TFE) may be an encapsulation substrate that is disposed on the light emitting element (LD) and bonded to the substrate (SUB) via a sealant.

[0176] The encapsulation layer (TFE) may include first, second, and third encapsulation layers (ENC1, ENC2, ENC3) sequentially positioned on the common electrode (CE). The first encapsulation layer (ENC1) may be positioned on the display element layer (DPL) and may span at least a portion of the display area (DA) and the non-display area (NDA). The second encapsulation layer (ENC2) may be positioned on the first encapsulation layer (ENC1) and may span at least a portion of the display area (DA) and the non-display area (NDA). The third encapsulation layer (ENC3) may be positioned on the second encapsulation layer (ENC2) and may span at least a portion of the display area (DA) and the non-display area (NDA). According to an embodiment, the third encapsulation layer (ENC3) may be positioned over the entire display area (DA) and the non-display area (NDA).

[0177] In the embodiment, the first and third encapsulating layers (ENC1, ENC3) may each be formed of an inorganic film including an inorganic material, and the second encapsulating layer (ENC2) may be formed of an organic film including an organic material. The inorganic film may include, for example, silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). The organic film may include an organic insulating material such as polyacrylates resin, epoxy resin, phenol resin, polyamides resin, polyimides resin, unsaturated polyesters resin, polyphenylene resin, polyphenylenesulfides resin, or benzocyclobutene (BCB).

[0178] In some embodiments, an optical layer including a color conversion layer and a color filter layer may be disposed on the encapsulating layer (TFE).

[0179] The display device according to the embodiment can be applied to various electronic devices. An electronic device according to one embodiment includes the display device described above, and may further include a module or device having additional functions in addition to the display device.

[0180] Fig. 17 is a block diagram of an electronic device according to one embodiment. Referring to Fig. 17, an electronic device (10) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0181] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0182] The memory (13) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (13), an image data signal and / or an input control signal is transmitted to the display module (11), and the display module (11) can process the received signal and output image information through a display screen.

[0183] The power module (14) may include a power supply module such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of the electronic device (10).

[0184] At least one of the components of the electronic device (10) described above may be included in the display device according to the embodiments described above. In addition, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device.

[0185] FIG. 18 is a schematic diagram of an electronic device according to various embodiments.

[0186] Referring to FIG. 18, various electronic devices to which display devices according to embodiments are applied may include not only image display electronic devices such as a smart phone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), and a desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), a head-mounted display (10_2b), and a smart watch (10_2c), and vehicle electronic devices (10_3) including display modules such as a CID (Center Information Display) and a room mirror display placed on an instrument panel, center fascia, or dashboard of an automobile.

[0187] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or having ordinary knowledge in the art that the present invention can be variously modified and changed within a scope that does not depart from the technical scope of the present invention as set forth in the claims to be described below.

[0188] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the patent claims.

Claims

1. A buffer layer placed on a substrate; An oxide semiconductor layer disposed on a buffer layer, the oxide semiconductor layer including a first region, a second region, and a channel region disposed between the first region and the second region; A gate insulating layer disposed on the semiconductor layer; A gate electrode disposed on the gate insulating layer and overlapping the channel region; and Including an interlayer insulating layer disposed on the gate electrode, The hydrogen (H) concentration in the above buffer layer is 4×10 20 atoms / cm 3 20×10 20 atoms / cm 3 Person, display device.

2. In paragraph 1, At a temperature of 400°C, the concentration of hydrogen gas (H2) released from the buffer layer is 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 And, At a temperature of 400°C, the concentration of moisture (H2O) released from the buffer layer is 1Х10 19 atoms / cm 3 20Х10 19 atoms / cm 3 Person, display device.

3. In paragraph 1, At a temperature of 400°C, the concentration of hydrogen gas (H2) released from the buffer layer is 1Х10 19 atoms / cm 3 5X10 19 atoms / cm 3 Person, display device.

4. In paragraph 1, At a temperature of 400°C, the concentration of moisture (H2O) released from the buffer layer is 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 Person, display device.

5. In paragraph 1, The hydrogen (H) concentration in the above gate insulating layer is 5Х10 20 atoms / cm 3 30Х10 20 atoms / cm 3 Person, display device.

6. In paragraph 5, At a temperature of 400°C, the concentration of hydrogen gas (H2) released from the gate insulating layer is 10Х10 19 atoms / cm 3 60Х10 19 atoms / cm 3 Person, display device.

7. In paragraph 1, The hydrogen concentration within the interlayer insulation layer is 4Х10 20 atoms / cm 3 20Х10 20 atoms / cm 3 Person, display device.

8. In paragraph 7, At a temperature of 400°C, the concentration of hydrogen gas (H2) released from the interlayer insulation is 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 Person, display device.

9. In paragraph 7, At a temperature of 400°C, the concentration of hydrogen gas (H2) released from the interlayer insulation is 1Х10 19 atoms / cm 3 7Х10 inland 19 atoms / cm 3 Person, display device.

10. In paragraph 1, A display device wherein the threshold voltage of the above transistor is 0 V to -3.5 V.

11. In paragraph 10, The surface resistance of the above interlayer insulation layer is 1200Ω / □ or less, A display device, wherein the gate electrode comprises aluminum.

12. Step of forming a buffer layer; A step of forming a semiconductor layer including a first region, a second region, and a channel region disposed between the first region and the second region on the buffer layer; A step of forming a gate insulating layer disposed on the semiconductor layer; A step of forming a gate electrode disposed on the gate insulating layer and overlapping the channel region; and comprising a step of forming an interlayer insulating layer disposed on the gate electrode; The above buffer layer has a hydrogen (H) concentration of 4×10 20 atoms / cm 3 20×10 20 atoms / cm 3 A method for manufacturing a transistor, wherein the transistor is formed in this manner.

13. In paragraph 12, The gate insulating layer has a hydrogen (H) concentration of 5Х10 20 atoms / cm 3 30Х10 20 atoms / cm 3 It is formed like this, The interlayer insulation layer has a hydrogen (H) concentration of 4Х10 20 atoms / cm 3 20Х10 20 atoms / cm 3 A method for manufacturing a transistor, wherein the transistor is formed in this manner.

14. In paragraph 12, The above buffer layer has a concentration of hydrogen gas (H2) released from the buffer layer of 1Х10 at a temperature of 400℃. 19 atoms / cm 3 10Х10 19 atoms / cm 3 , and the concentration of moisture (H2O) released from the buffer layer is 1Х10 19 atoms / cm 3 20Х10 19 atoms / cm 3 It is formed to become, The gate insulating layer has a concentration of hydrogen gas (H2) released from the gate insulating layer of 10Х10 at a temperature of 400°C. 19 atoms / cm 3 60Х10 19 atoms / cm 3 It is formed to become, The interlayer insulation layer has a concentration of hydrogen gas (H2) released from the interlayer insulation layer at a temperature of 400°C of 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 A method for manufacturing a transistor, wherein the transistor is formed to be .

15. In paragraph 14, The step of forming the semiconductor layer is: A step of forming a base oxide semiconductor layer including an oxide semiconductor; A step of forming a buffer semiconductor layer by patterning the base oxide semiconductor layer; and A method for manufacturing a transistor, comprising a step of doping impurities on both ends of the buffer semiconductor layer.

16. Processor; and Includes a display device, The above display device, light emitting element; and comprising a transistor electrically connected to the light emitting element; The above transistor, A buffer layer disposed on a substrate; An oxide semiconductor layer disposed on the buffer layer, the oxide semiconductor layer including a first region, a second region, and a channel region disposed between the first region and the second region; A gate insulating layer disposed on the semiconductor layer; A gate electrode disposed on the gate insulating layer and overlapping the channel region; and Including an interlayer insulating layer disposed on the gate electrode, The hydrogen (H) concentration in the above buffer layer is 4×10 20 atoms / cm 3 20×10 20 atoms / cm 3 People, electronic devices.

17. In paragraph 16, The hydrogen (H) concentration in the above gate insulating layer is 5Х10 20 atoms / cm 3 30Х10 20 atoms / cm 3 And, The hydrogen (H) concentration within the interlayer insulation layer is 4Х10 20 atoms / cm 3 20Х10 20 atoms / cm 3 And, At a temperature of 400°C, the concentration of hydrogen gas (H2) released from the buffer layer is 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 And, At a temperature of 400°C, the concentration of moisture (H2O) released from the buffer layer is 1Х10 19 atoms / cm 3 20Х10 19 atoms / cm 3 People, electronic devices.

18. In paragraph 17, At a temperature of 400°C, the concentration of hydrogen gas (H2) released from the gate insulating layer is 10Х10 19 atoms / cm 3 60Х10 19 atoms / cm 3 And, At a temperature of 400°C, the concentration of hydrogen gas (H2) released from the interlayer insulation is 1Х10 19 atoms / cm 3 10Х10 19 atoms / cm 3 People, electronic devices.

19. In paragraph 18, An electronic device wherein the threshold voltage of the transistor is 0 V to -3.5 V.

20. In paragraph 18, The surface resistance of the above interlayer insulation layer is 1200Ω / □ or less, An electronic device wherein the gate electrode comprises aluminum.

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