Display device

Abstract

A display device according to one embodiment of the present invention includes: a substrate including a display area and a peripheral area including a pad area and disposed outside the display area; an inorganic insulating layer disposed on the substrate; a light-emitting element layer disposed on the inorganic insulating layer and including a light-emitting element overlapping the display area in a plan view; a power voltage line disposed between the pad area and the display area in a plan view and including an opening; and a fan-out line extending from the pad area to the display area in a plan view and overlapping at least a portion of the power voltage line. The fan-out line includes a first sub-line disposed on the inorganic insulating layer, a second sub-line inserted into the inorganic insulating layer, and a contact portion electrically connecting the first sub-line and the second sub-line. The contact portion of the fan-out line is located within the opening of the power voltage line in a plan view.

Description

display device

[0001] The present invention relates to a display device.

[0002] A display device is a device that visually displays data. Such a display device includes a substrate divided into a display area and a peripheral area located outside the display area. In the display area, scan lines and data lines are formed by being mutually insulated from each other, and a plurality of pixels connected to the scan lines and the data lines are arranged. In addition, the display area is provided with a transistor and a pixel electrode electrically connected to the transistor, corresponding to each of the pixels. In addition, the display area is provided with a counter electrode that is provided in common with the pixels. The peripheral area may be provided with various wires that transmit electrical signals to the display area, a scan driver, a data driver, a control unit, etc. Such display devices are becoming increasingly diverse in their uses.

[0003] One or more embodiments provide a display device with reduced peripheral area and superior display quality. However, these embodiments are exemplary and do not limit the scope of the present invention.

[0004] According to one or more embodiments, a display device includes a substrate including a display area and a peripheral area including a pad area disposed outside the display area; an inorganic insulating layer disposed on the substrate; a light emitting element layer disposed on the inorganic insulating layer and including a light emitting element overlapping the display area in a plan view; a power voltage line disposed between the pad area and the display area in a plan view and including an opening; and a fan-out wiring extending from the pad area to the display area in a plan view and overlapping at least a portion of the power voltage line; wherein the fan-out wiring includes a first sub-wiring disposed on the inorganic insulating layer, a second sub-wiring inserted into the inorganic insulating layer, and a contact portion electrically connecting the first sub-wiring and the second sub-wiring, wherein in a plan view, the contact portion of the fan-out wiring is located within the opening of the power voltage line.

[0005] In one embodiment, the fan-out wiring further includes an organic insulating layer disposed on the inorganic insulating layer and including a first organic insulating layer and a second organic insulating layer that are sequentially stacked; wherein the inorganic insulating layer includes a first inorganic insulating layer, a second inorganic insulating layer, and a third inorganic insulating layer that are sequentially stacked; and the first sub-wiring of the fan-out wiring is disposed between the inorganic insulating layer and the first organic insulating layer, or between the first organic insulating layer and the second organic insulating layer, and the second sub-wiring of the fan-out wiring may be disposed between the first inorganic insulating layer and the second inorganic insulating layer, or between the second inorganic insulating layer and the third inorganic insulating layer.

[0006] In one embodiment, the display device may further include a semiconductor layer overlapping the display area in a plan view and disposed between the substrate and the first inorganic insulating layer; and a gate electrode overlapping the semiconductor layer in a plan view and disposed between the first inorganic insulating layer and the second inorganic insulating layer.

[0007] In one embodiment, the fan-out wiring includes first fan-out wirings and second fan-out wirings that are alternately arranged, and a first sub-wiring of each of the first fan-out wirings may be arranged on a different layer from a first sub-wiring of each of the second fan-out wirings, and a second sub-wiring of each of the first fan-out wirings may be arranged on a different layer from a second sub-wiring of each of the second fan-out wirings.

[0008] In one embodiment, the power voltage line includes a first sub-power voltage line inserted into the inorganic insulating layer, and a second sub-power voltage line disposed on the inorganic insulating layer and electrically connected to the first sub-power voltage line, and in a plan view, the first sub-power voltage line of the power voltage line overlaps the first sub-wire of the fan-out wiring, and in a plan view, the second sub-power voltage line of the power voltage line overlaps the second sub-wire of the fan-out wiring.

[0009] In one embodiment, the opening of the power voltage line may be located in the first sub-power voltage line of the power voltage line.

[0010] In one embodiment, the inorganic insulating layer further includes a fourth inorganic insulating layer disposed on the third inorganic insulating layer, and the first sub-power voltage line of the power voltage line can be disposed between the third inorganic insulating layer and the fourth inorganic insulating layer.

[0011] In one embodiment, the width of the power voltage line may be greater than the width of the fan-out wiring.

[0012] In one embodiment, the display device further includes a sealing substrate disposed on the light emitting element layer; and a sealing member disposed between the substrate and the sealing substrate and surrounding the display area in a plan view; wherein in a plan view, the fan-out wiring extends across the sealing member, and the contact portion of the fan-out wiring can be located between the sealing member and the pad area.

[0013] In one embodiment, the display device may further include an encapsulation layer disposed on the light-emitting element layer and including at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0014] In one embodiment, the fan-out wiring includes a plurality of fan-out wirings, the power voltage line includes a plurality of openings, and a contact portion of each of the fan-out wirings can be positioned within a corresponding opening among the openings.

[0015] According to one or more embodiments, a display device comprises: a substrate including a display area and a peripheral area including a pad area disposed outside the display area; an inorganic insulating layer disposed on the substrate; a light-emitting element layer disposed on the inorganic insulating layer and including a light-emitting element overlapping the display area in a plan view; a power voltage line disposed between the pad area and the display area in a plan view; And a fan-out wiring extending from the pad area to the display area in a plan view and overlapping at least a portion of the power voltage line; wherein the fan-out wiring includes a first sub-wiring arranged on the inorganic insulating layer, a second sub-wiring inserted into the inorganic insulating layer, and a contact portion electrically connecting the first sub-wiring and the second sub-wiring, and the power voltage line includes a first sub-power voltage line inserted into the inorganic insulating layer, and a second sub-power voltage line arranged on the inorganic insulating layer and electrically connected to the first sub-power voltage line, and in a plan view, the first sub-power voltage line of the power voltage line overlaps the first sub-wiring of the fan-out wiring, and in a plan view, the second sub-power voltage line of the power voltage line overlaps the second sub-wiring of the fan-out wiring, and the first sub-power voltage line of the power voltage line overlaps the first sub-wiring of the fan-out wiring. It is placed on a different floor.

[0016] In one embodiment, the display device further includes an organic insulating layer disposed on the inorganic insulating layer, the organic insulating layer including a first organic insulating layer and a second organic insulating layer sequentially stacked; the inorganic insulating layer includes a first inorganic insulating layer, a second inorganic insulating layer, and a third inorganic insulating layer sequentially stacked; the first sub-wiring of the fan-out wiring may be disposed between the inorganic insulating layer and the first organic insulating layer, or between the first organic insulating layer and the second organic insulating layer, and the second sub-wiring of the fan-out wiring may be disposed between the first inorganic insulating layer and the second inorganic insulating layer, or between the second inorganic insulating layer and the third inorganic insulating layer.

[0017] In one embodiment, the display device may further include a semiconductor layer overlapping the display area in a plan view and disposed between the substrate and the first inorganic insulating layer; and a gate electrode overlapping the semiconductor layer in a plan view and disposed between the first inorganic insulating layer and the second inorganic insulating layer.

[0018] In one embodiment, the display device further includes a fourth inorganic insulating layer disposed on the third inorganic insulating layer, and the first sub-power voltage line of the power voltage line may be disposed between the third inorganic insulating layer and the fourth inorganic insulating layer.

[0019] In one embodiment, the first sub-power voltage line of the power voltage line may include an opening.

[0020] In one embodiment, the contact portion of the fan-out wiring in the plan view may be located within the opening of the first sub-power voltage line.

[0021] In one embodiment, the fan-out wiring includes first fan-out wirings and second fan-out wirings that are alternately arranged, and a first sub-wiring of each of the first fan-out wirings may be arranged on a different layer from a first sub-wiring of each of the second fan-out wirings, and a second sub-wiring of each of the first fan-out wirings may be arranged on a different layer from a second sub-wiring of each of the second fan-out wirings.

[0022] In one embodiment, the display device further includes a sealing substrate disposed on the light emitting element layer; and a sealing member disposed between the substrate and the sealing substrate and surrounding the display area in a plan view; wherein in a plan view, the fan-out wiring extends across the sealing member, and the contact portion of the fan-out wiring can be located between the sealing member and the pad area.

[0023] In one embodiment, the display device may further include an encapsulation layer disposed on the light-emitting element layer and including at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0024] According to one embodiment of the present invention, as described above, the fan-out wiring and power supply voltage lines can be arranged to overlap each other in a plan view, thereby reducing the peripheral area. Furthermore, by reducing the wiring resistance of the fan-out wiring and power supply voltage lines, a display device with superior display quality can be realized. Of course, the scope of the present invention is not limited by these effects.

[0025] The above and other aspects, features and advantages of the embodiments of the present invention will become more apparent from the description taken in conjunction with the accompanying drawings.

[0026] FIG. 1 is a perspective view schematically illustrating a display device according to one embodiment.

[0027] FIG. 2A is a cross-sectional view schematically illustrating the display device of FIG. 1 along line A-A' according to one embodiment.

[0028] FIG. 2b is a cross-sectional view schematically illustrating the display device of FIG. 1 along line A-A' according to one embodiment.

[0029] FIG. 3A is a plan view schematically illustrating a display panel included in a display device according to one embodiment.

[0030] FIG. 3b is a plan view schematically illustrating a display panel included in a display device according to one embodiment.

[0031] FIG. 4a is an equivalent circuit diagram schematically illustrating one subpixel of a display panel according to one embodiment.

[0032] FIG. 4b is an equivalent circuit diagram schematically illustrating one subpixel of a display panel according to one embodiment.

[0033] FIG. 5 is a plan view showing an enlarged portion of a display panel according to one embodiment, and is a plan view showing an enlarged portion of part D of FIG. 3b.

[0034] Fig. 6a is a plan view illustrating a portion of the display panel illustrated in Fig. 5.

[0035] Figure 6b is a plan view illustrating a portion of the display panel illustrated in Figure 5.

[0036] Figure 6c is a plan view illustrating a portion of the display panel illustrated in Figure 5.

[0037] FIG. 6d is a plan view illustrating a portion of the display panel illustrated in FIG. 5.

[0038] Figure 6e is a plan view illustrating a portion of the display panel illustrated in Figure 5.

[0039] FIG. 7 is a cross-sectional view showing a portion of a display panel according to one embodiment, taken along line I-I' of FIG. 5.

[0040] FIG. 8 is a cross-sectional view showing a portion of a display panel according to one embodiment, taken along line II-II' of FIG. 5.

[0041] FIG. 9 is a cross-sectional view showing a portion of a display panel according to one embodiment, taken along line III-III' of FIG. 5.

[0042] Figure 10 is a block diagram of an electronic device according to one embodiment.

[0043] FIG. 11 is a schematic diagram illustrating an electronic device according to various embodiments.

[0044] Reference will now be made in detail to embodiments illustrated in the accompanying drawings, wherein like reference numerals designate like elements throughout the drawings. In this regard, the embodiments may take various forms and should not be construed as limited to the description set forth herein. Accordingly, embodiments are described below with reference to the drawings to illustrate aspects of the present disclosure. The term "and / or" as used herein includes any combination of one or more of the associated listed items. "At least one of a, b, and c" or "at least one of a, b, or c" refers to a case of a, a case of b, a case of c, a case of a and b, a case of a and c, a case of b and c, a, b, and c, or variations thereof.

[0045] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0046] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals and redundant descriptions thereof are omitted.

[0047] In the examples below, terms such as “first”, “second”, etc. are not used in a limiting sense but are used for the purpose of distinguishing one component from another.

[0048] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0049] In the following examples, terms such as “include” or “have” mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0050] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0051] In some embodiments, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0052] In this specification, "A and / or B" refers to the case where it is "A", "B", or "A and B". And, "at least one of A or B" refers to the case where it is "A", "B", or "A and B".

[0053] In the following examples, when it is said that a film, region, component, etc. are connected, it includes cases where the films, regions, components, etc. are directly connected, and / or cases where other films, regions, components, etc. are interposed between the films, regions, components, etc. and are indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it refers to cases where the films, regions, components, etc. are directly electrically connected, and / or cases where other films, regions, components, etc. are interposed between them and are indirectly electrically connected.

[0054] The x-axis, y-axis, and z-axis are not limited to the three axes in the Cartesian coordinate system, but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0055] Fig. 1 is a perspective view schematically showing a display device (1) according to one embodiment.

[0056] Referring to FIG. 1 in one embodiment, a display device (1) can display an image and can include a display area (DA) and a peripheral area (PA). Subpixels (PX) can be arranged in the display area (DA). The peripheral area (PA) can surround at least a portion of the display area (DA). Subpixels (PX) may not be arranged in the peripheral area (PA).

[0057] In one embodiment, FIG. 1 illustrates a display device (1) having a rectangular display area (DA). However, in other embodiments, the display area (DA) may be circular, elliptical, or polygonal, such as a triangle or pentagon. The display device (1) of FIG. 1 illustrates a flat display device, but the display device (1) may be implemented in various forms, such as a flexible, foldable, or rollable display device.

[0058] In one embodiment, a plurality of subpixels (PX) can be arranged in a display area (DA) and can emit light, and the display device (1) can display an image in the display area (DA). In one embodiment, any one of the plurality of subpixels (PX) can emit red light, green light, or blue light. In another embodiment, any one of the plurality of subpixels (PX) can emit red light, green light, blue light, or white light.

[0059] In one embodiment, the display device (1) may have a first length (LT1) in a first direction that is longer than a second length (LT2) in a second direction of the display device (1). The number of the plurality of subpixels (PX) arranged in the first direction may be greater than the number of the plurality of subpixels (PX) arranged in the second direction. In addition, the first direction and the second direction may intersect each other. For example, the first direction and the second direction may be orthogonal to each other. The first direction may be in the x direction and the second direction may be in the y direction. As another example, the first direction and the second direction may form an acute angle with each other or an obtuse angle with each other. In another embodiment, the first length (LT1) may be shorter than the second length (LT2). In yet another embodiment, the first length (LT1) and the second length (LT2) may be equal to each other.

[0060] In one embodiment, the display device (1) may include a liquid crystal display, an electrophoretic display, an organic light emitting display, an inorganic light emitting display, a field emission display, a surface-conduction electron-emitter display, a quantum dot display, a plasma display, a cathode ray display, etc. Hereinafter, an organic light emitting display will be described as an example of a display device (1) according to one embodiment of the present invention, but various types of display devices as described above may be used in other embodiments.

[0061] FIGS. 2A and 2B are cross-sectional views schematically illustrating the display device (1) of FIG. 1 along line A-A', respectively, according to one embodiment.

[0062] In one embodiment, referring to FIGS. 2A and 2B, a display device (1) may include a display panel (10), a cover window, a housing, and the like. The display panel (10) may include a substrate (100), an inorganic insulating layer (200), a light emitting element layer (300), and a sealing structure. The display device (1) may include a display area (DA) and a peripheral area (PA). The display area (DA) and the peripheral area (PA) may be defined in the substrate (100). In other words, the substrate (100) may include the display area (DA) and the peripheral area (PA).

[0063] In one embodiment, the substrate (100) may include a glass material or a polymer resin. The polymer resin may include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. In one embodiment, the substrate (100) may have an alternating laminated structure of a base layer including a polymer resin and a barrier layer including an inorganic insulating material such as silicon oxide or silicon nitride.

[0064] In one embodiment, the inorganic insulating layer (200) may be disposed on the substrate (100) and may overlap the display area (DA) and the peripheral area (PA). In the present specification, the meaning of the first component and the second component overlapping each other means that the first component and the second component overlap each other in a plan view (e.g., the xy plane). The inorganic insulating layer (200) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide. In one embodiment, the zinc oxide may be zinc oxide (ZnO) and / or zinc peroxide (ZnO2).

[0065] In one embodiment, the light emitting element layer (300) may be disposed on the inorganic insulating layer (200) and may overlap the display area (DA). The light emitting element layer (300) may include a light emitting element and may be an organic light emitting diode (OLED) including an organic light emitting layer. In another embodiment, the light emitting element may be an inorganic light emitting diode including an inorganic light emitting layer. The size of the inorganic light emitting diode may be micro-scale or nano-scale. For example, the inorganic light emitting diode may be a micro-scale light emitting diode. In another embodiment, the inorganic light emitting diode may be a nanorod light emitting diode and may include gallium nitride (GaN). In another embodiment, a color conversion layer may be disposed on the nanorod light emitting diode and may include quantum dots. In another embodiment, the light emitting device may be a quantum dot light emitting diode (QLED) comprising a quantum dot light emitting layer.

[0066] In one embodiment, referring to FIG. 2A, the sealing structure may include a sealing substrate (400) and a sealing member (500). The sealing substrate (400) may be disposed on the light-emitting element layer (300). In other words, the light-emitting element layer (300) may be disposed between the substrate (100) and the sealing substrate (400). The sealing substrate (400) may be a transparent member. In one embodiment, the sealing substrate (400) may include glass.

[0067] In one embodiment, the sealing member (500) may be disposed between the substrate (100) and the sealing substrate (400). In one embodiment, the sealing member (500) may be disposed between the inorganic insulating layer (200) and the sealing substrate (400). The sealing member (500) may surround the display area (DA) in a plan view. The sealing member (500) may overlap the peripheral area (PA) in a plan view. Accordingly, the internal space between the light emitting element layer (300) and the sealing substrate (400) may be sealed, and a moisture absorbent and / or a filler may be disposed in the internal space.

[0068] In one embodiment, the sealing member (500) may be a sealant. In another embodiment, the sealing member (500) may include a material that is cured by a laser beam. For example, the sealing member (500) may be frit. Specifically, the sealing member (500) may include an organic sealant such as a urethane-based resin, an epoxy-based resin, an acrylic-based resin, or an inorganic sealant. In one embodiment, the sealing member (500) may include silicone. As the urethane-based resin, for example, urethane acrylate may be used. As the acrylic resin, for example, butylacrylate, ethylhexylacrylate, etc. may be used. Meanwhile, the sealing member (500) may include a material that is cured by heat.

[0069] In one embodiment, referring to FIG. 2B, the sealing structure may include an encapsulation layer (600) including at least one inorganic encapsulation layer and at least one organic encapsulation layer. The at least one inorganic encapsulation layer and the at least one organic encapsulation layer may be alternately stacked. In one embodiment, the encapsulation layer (600) may include a first inorganic encapsulation layer (610), an organic encapsulation layer (620), and a second inorganic encapsulation layer (630) that are sequentially stacked. The first inorganic encapsulation layer (610) and the second inorganic encapsulation layer (630) may contact each other in a peripheral area (PA). Each of the first inorganic encapsulation layer (610) and the second inorganic encapsulation layer (630) may include an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide. In one embodiment, the zinc oxide may be zinc oxide (ZnO) and / or zinc peroxide (ZnO2).

[0070] In one embodiment, the organic encapsulating layer (620) may include a polymer-based material. Examples of polymer-based materials include acrylic resins, epoxy resins, polyimides, and polyethylene. In one embodiment, the organic encapsulating layer (620) may include acrylate.

[0071] In another embodiment, the sealing structure may simultaneously include the sealing substrate (400) and sealing member (500) of FIG. 2a and the sealing layer (600) of FIG. 2b.

[0072] In one embodiment, a touch sensor layer may be arranged on the sealing structure and may acquire coordinate information according to an external input, for example, a touch event.

[0073] In one embodiment, an anti-reflection layer may be disposed on the touch sensor layer. The anti-reflection layer may reduce the reflectance of light incident on the display device (1). In one embodiment, the anti-reflection layer may include a phase retarder and / or a polarizer. The phase retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include a stretchable synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a predetermined array. The phase retarder and the polarizer may further include a protective film.

[0074] In another embodiment, the anti-reflection layer may include a black matrix and color filters. The color filters may be arranged in consideration of the color of light emitted from the light-emitting elements of the display device (1). Each color filter may include a red, green, or blue pigment or dye. Alternatively, each color filter may further include quantum dots in addition to the aforementioned pigments or dyes. In another embodiment, some of the color filters may not include the aforementioned pigments or dyes, and may include scattering particles such as titanium oxide.

[0075] In another embodiment, the antireflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected by the first and second reflective layers may destructively interfere with each other, thereby reducing the external light reflectance.

[0076] FIGS. 3A and 3B are schematic plan views of a display panel included in a display device according to one embodiment, respectively. FIG. 3B illustrates a sealing member (500) arranged to surround a display area (DA) while omitting some of the components of FIG. 3A. For example, FIG. 3B omits the second power supply voltage line and the first and second scan drivers.

[0077] In one embodiment, referring to FIGS. 3A and 3B, a substrate (100) of a display panel (10) may include a display area (DA) and a peripheral area (PA). A subpixel (PX) may be arranged in the display area (DA). A plurality of subpixels (PX) may be provided in the display area (DA). Each subpixel (PX) may be implemented as a light-emitting element such as an organic light-emitting diode. Each subpixel (PX) may emit light of, for example, red, green, blue, or white.

[0078] In one embodiment, a subpixel circuit driving a subpixel (PX) may be connected to a signal line or voltage line for controlling on / off and brightness of a light-emitting element. For example, FIGS. 3A and 3B illustrate a data line (DL) and a scan line (SL) as signal lines, and illustrate a driving voltage line (PL) as a voltage line. The subpixel (PX) may be electrically connected to the data line (DL). The scan line (SL) may extend in a first direction (e.g., x direction). The data line (DL) may extend in a second direction (e.g., y direction). In addition, the subpixel (PX) may be connected to the driving voltage line (PL). In a plan view, the scan line (SL), the data line (DL), and the driving voltage line (PL) may overlap with the display area (DA).

[0079] In one embodiment, a peripheral area (PA) may be arranged adjacent to a display area (DA). The peripheral area (PA) may surround the display area (DA). A subpixel (PX) may not be arranged in the peripheral area (PA). The peripheral area (PA) may include a pad area (PADA). The pad area (PADA) may be arranged outside the display area (DA). In one embodiment, a plurality of pad areas (PADA) may be provided. In other words, the pad area (PADA) may include a plurality of pad areas (PADA). In one embodiment, the pad areas (PADA) may be arranged in a direction parallel to a first direction (e.g., the x direction). Although FIGS. 3A and 3B illustrate a plurality of pad areas (PADA), in another embodiment, the display device (1) may include a single pad area (PADA). Although FIGS. 3a and 3b illustrate that the pad area (PADA) is positioned outside the display area (DA) in the -y direction, in other embodiments, the pad area (PADA) may be positioned outside the display area (DA) in the y direction, the -x direction, or the x direction.

[0080] In one embodiment, a plurality of pads (51, 52, 53, 54, 55, 56, 57) may be arranged in the pad area (PADA). The pad area (PADA) is exposed without being covered by an insulating layer and may be electrically connected to a control unit (not shown) such as a flexible printed circuit board or a driving driver IC chip. The control unit may convert a plurality of image signals transmitted from the outside into a plurality of image data signals and transmit the converted signals to the display area (DA) through the pads of the pad area (PADA). In addition, the control unit may receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, generate a control signal for controlling the driving of the scan drivers (41, 42), and transmit the control signal to the scan drivers (41, 42) through the pad (56) of the pad area (PADA). The control unit can transmit different voltages to the first power voltage line (20) and the second power voltage line (30) through the pads (55) and (57) of the pad area (PADA), respectively. In addition, the fan-out wirings (FL) can transmit various signals and / or voltages to the display area (DA).

[0081] In one embodiment, the peripheral area (PA) may include external circuits for driving subpixels (PX). For example, a first power voltage line (20), a second power voltage line (30), a first scan driver (41), a second scan driver (42), and a fan-out wiring (FL) may be arranged in the peripheral area (PA).

[0082] In one embodiment, the first power voltage line (20) may be arranged between the pad area (PADA) and the display area (DA). The first power voltage line (20) may be arranged to correspond to the lower part of the display area (DA) in the peripheral area (PA). In one embodiment, the first power voltage line (20) may include a first-first power voltage line (21) extending in a second direction (e.g., y direction) and a first-second power voltage line (22) connected to the first-first power voltage line (21) and extending in a first direction (e.g., x direction). The first power voltage line (20) may be electrically connected to a driving voltage line (PL) arranged in the display area (DA). In addition, the first power voltage line (20) may be electrically connected to a pad (55) of the pad area (PADA).

[0083] In one embodiment, the second power voltage line (30) can transmit a different voltage from the first power voltage line (20) and can be arranged between the pad area (PADA) and the display area (DA). The second power voltage line (30) can be arranged to partially surround the display area (DA) in the peripheral area (PA). In one embodiment, the second power voltage line (30) can extend along the remaining sides of the display area (DA) except for one side adjacent to the first power voltage line (20). However, the present invention is not limited thereto. In another embodiment, the second power voltage line (30) can be arranged to correspond to all sides of the display area (DA). In another embodiment, various modifications are possible, such as the second power voltage line (30) can be arranged to correspond to one side or two sides of the display area (DA). The second power voltage line (30) can be electrically connected to the pad (57) of the pad area (PADA).

[0084] In one embodiment, the first power supply voltage line (20) can provide a driving voltage (ELVDD, see FIG. 4a) to each subpixel (PX), and the second power supply voltage line (30) can provide a common voltage (ELVSS, see FIG. 4a) to each subpixel (PX). For example, the driving voltage (ELVDD) can be provided to each subpixel (PX) through a driving voltage line (PL) electrically connected to the first power supply voltage line (20). The common voltage (ELVSS) can be connected to a counter electrode of an organic light-emitting diode provided in each subpixel (PX) and a peripheral area (PA).

[0085] In one embodiment, the first scan driver (41) can apply a scan signal to each subpixel (PX) through a scan line (SL). The second scan driver (42) can be positioned on the opposite side of the first scan driver (41) with respect to the display area (DA) and can be approximately parallel to the first scan driver (41). Some of the subpixel circuits of the subpixels (PX) arranged in the display area (DA) can be electrically connected to the first scan driver (41), and the rest can be electrically connected to the second scan driver (42).

[0086] Although FIG. 3A illustrates an embodiment in which the scan drivers (41, 42) are arranged on both sides of the display area (DA), the present invention is not limited thereto. In other embodiments, the scan drivers (41, 42) may be arranged on only one side of the display area (DA), or, when the scan drivers (41, 42) are arranged on a printed circuit board or the like, they may not be arranged in the peripheral area (PA), and various other modifications are possible.

[0087] In one embodiment, a fan-out wiring (FL) may extend from a pad area (PADA) to a display area (DA) and overlap with a peripheral area (PA) in a plan view. In one embodiment, a plurality of fan-out wirings (FL) may be provided. In one embodiment, the fan-out wiring (FL) may be a signal line. For example, the fan-out wiring (FL) may be electrically connected to a data line (DL). In another embodiment, the fan-out wiring (FL) may be a voltage line. The fan-out wiring (FL) may be electrically connected to pads (51, 52, 53, 54) of the pad area (PADA), respectively. The fan-out wiring (FL) may transmit an electrical signal and / or voltage received from a control unit through the pad area (PADA) to the display area (DA).

[0088] In one embodiment, the fan-out wiring (FL) may overlap at least a portion of the first power voltage line (20) in the plan view. For example, the fan-out wiring (FL) may overlap a portion of the first-first power voltage line (21).

[0089] In one embodiment, referring to FIG. 3B, a sealing member (500) may be positioned in a peripheral area (PA) and may surround a display area (DA) in a plan view. The sealing member (500) may be positioned between a pad area (PADA) and the display area (DA). In one embodiment, a fan-out wiring (FL) may extend across the sealing member (500) in a plan view.

[0090] More detailed information about the fan-out wiring (FL) and the first power voltage line (20) according to embodiments of the present invention will be described later.

[0091] FIG. 4a is an equivalent circuit diagram schematically illustrating one subpixel of a display panel according to one embodiment.

[0092] In one embodiment, referring to FIG. 4A, a subpixel (PX) may include a subpixel circuit (PC) and a light-emitting element (LED) electrically connected to the subpixel circuit (PC). The subpixel circuit (PC) may include a driving transistor (T1), a switching transistor (T2), and a first storage capacitor (Cst). The subpixel (PX) may emit light of, for example, red, green, or blue, or may emit light of, for example, red, green, blue, or white, through the light-emitting element (LED).

[0093] In one embodiment, the switching transistor (T2) is connected to the scan line (SL) and the data line (DL), and can transmit the data voltage or data signal (Dm) input from the data line (DL) to the driving transistor (T1) according to the scan voltage or scan signal (Sn) input from the scan line (SL).

[0094] In one embodiment, the first storage capacitor (Cst) is connected to the switching transistor (T2) and the driving voltage line (PL), and can store a voltage corresponding to the difference between the voltage received from the switching transistor (T2) and the driving voltage (ELVDD) supplied to the driving voltage line (PL).

[0095] In one embodiment, a driving transistor (T1) is connected to a driving voltage line (PL) and a first storage capacitor (Cst), and can control a driving current flowing through a light-emitting element (LED) from the driving voltage line (PL) in response to a voltage value stored in the first storage capacitor (Cst). The light-emitting element (LED) can emit light having a predetermined brightness by the driving current. An opposite electrode (e.g., a cathode) of the light-emitting element (LED) can be supplied with a common voltage (ELVSS).

[0096] Although FIG. 4a illustrates that the subpixel circuit (PC) includes two transistors and one storage capacitor, in other embodiments, the subpixel circuit (PC) may include three or more transistors.

[0097] FIG. 4b is an equivalent circuit diagram schematically showing one subpixel (PX) of a display panel according to another embodiment.

[0098] In one embodiment, referring to FIG. 4B, the subpixel circuit (PC) may include a plurality of transistors (T1 to T7), a first storage capacitor (Cst), and a second storage capacitor (Cbt). The plurality of transistors (T1 to T7), the first storage capacitor (Cst), and the second storage capacitor (Cbt) may be connected to signal lines (SL1, SL2, SLp, SLn, EL, DL), a first initialization voltage line (VIL1), a second initialization voltage line (VIL2), and a driving voltage line (PL). In one embodiment, at least one of the signal lines, the first and second initialization voltage lines (VIL1, VIL2), and / or the driving voltage line (PL) may be shared by neighboring subpixels (PX).

[0099] In one embodiment, the plurality of transistors (T1 to T7) may include a driving transistor (T1), a switching transistor (T2), a compensation transistor (T3), a first initialization transistor (T4), an operation control transistor (T5), a light emission control transistor (T6), and a second initialization transistor (T7). However, the present invention is not necessarily limited thereto.

[0100] In one embodiment, a light emitting diode (LED) may include a subpixel electrode and a counter electrode, and the subpixel electrode of the LED may be connected to a driving transistor (T1) via a light emission control transistor (T6) to receive a driving current, and the counter electrode may be provided with a common voltage (ELVSS). The LED may generate light having a brightness corresponding to the driving current. In one embodiment, the LED may be an organic light emitting diode including an organic light emitting layer.

[0101] In one embodiment, the driving voltage line (PL) can transmit a driving voltage (ELVDD) to the driving transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint1) that initializes the driving transistor (T1) to the subpixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vint2) that initializes the light emitting element (LED) to the subpixel circuit (PC).

[0102] In one embodiment, among the driving transistor (T1), the switching transistor (T2), the compensation transistor (T3), the first initialization transistor (T4), the operation control transistor (T5), the light emission control transistor (T6), and the second initialization transistor (T7), the compensation transistor (T3) and the first initialization transistor (T4) are implemented as NMOS (n-channel MOSFETs), and the remaining transistors can be implemented as PMOS (p-channel MOSFETs).

[0103] In one embodiment, the drain region of the driving transistor (T1) may be electrically connected to a light-emitting element (LED) via a light-emitting control transistor (T6). The driving transistor (T1) may receive a data signal (Dm) according to a switching operation of the switching transistor (T2) and supply a driving current to the light-emitting element (LED).

[0104] In one embodiment, the switching transistor (T2) can be turned on in response to a first scan signal (Sn1) transmitted through a first scan line (SL1) and perform a switching operation to transmit a data signal (Dm) transmitted through a data line (DL) to a source region of the driving transistor (T1).

[0105] In one embodiment, the gate electrode of the compensation transistor (T3) may be connected to the second scan line (SL2). The source region of the compensation transistor (T3) may be connected to the drain region of the driving transistor (T1) and may be connected to the subpixel electrode of the light emitting element (LED) via the light emission control transistor (T6). The drain region of the compensation transistor (T3) may be connected to one electrode of the first storage capacitor (Cst), the source region of the first initialization transistor (T4), and the gate electrode of the driving transistor (T1). The compensation transistor (T3) is turned on in response to the second scan signal (Sn2) received through the second scan line (SL2) to connect the gate electrode and the drain region of the driving transistor (T1) to each other, thereby diode-connecting the driving transistor (T1).

[0106] In one embodiment, a gate electrode of a first initialization transistor (T4) may be connected to a previous scan line (SLp). A drain region of the first initialization transistor (T4) may be connected to a first initialization voltage line (VIL1). A source region of the first initialization transistor (T4) may be connected to one electrode of a first storage capacitor (Cst), a drain region of a compensation transistor (T3), and a gate electrode of a driving transistor (T1). The first initialization transistor (T4) may be turned on according to a previous scan signal (Sn-1) received through the previous scan line (SLp) to transmit a first initialization voltage (Vint1) to a gate electrode of the driving transistor (T1) to perform an initialization operation of initializing a voltage of the gate electrode of the driving transistor (T1).

[0107] In one embodiment, the gate electrode of the second initialization transistor (T7) may be connected to the subsequent scan line (SLn). The source region of the second initialization transistor (T7) may be connected to the subpixel electrode of the light emitting element (LED). The drain region of the second initialization transistor (T7) may be connected to the second initialization voltage line (VIL2). The second initialization transistor (T7) may be turned on according to the subsequent scan signal (Sn+1) transmitted through the subsequent scan line (SLn) to initialize the subpixel electrode of the light emitting element (LED).

[0108] In one embodiment, the first storage capacitor (Cst) may include a first capacitor electrode (CE1) and a second capacitor electrode (CE2). The first capacitor electrode (CE1) may be connected to a gate electrode of a driving transistor (T1), and the second capacitor electrode (CE2) may be connected to a driving voltage line (PL). The first storage capacitor (Cst) may store and maintain a voltage corresponding to a difference between voltages across the driving voltage line (PL) and the gate electrode of the driving transistor (T1), thereby maintaining a voltage applied to the gate electrode of the driving transistor (T1).

[0109] In one embodiment, the second storage capacitor (Cbt) may include a third capacitor electrode (CE3) and a fourth capacitor electrode (CE4). The third capacitor electrode (CE3) may be connected to the first scan line (SL1) and the gate electrode of the switching transistor (T2). The fourth capacitor electrode (CE4) may be connected to the gate electrode of the driving transistor (T1) and the first capacitor electrode (CE1) of the first storage capacitor (Cst). The second storage capacitor (Cbt) may be a boosting capacitor, and when the first scan signal (Sn1) of the first scan line (SL1) is a voltage that turns off the switching transistor (T2), the second storage capacitor (Cbt) may increase the voltage of the node (N) to decrease the voltage (black voltage) that displays black.

[0110] The specific operation of each sub-pixel circuit (PC) according to one embodiment is as follows.

[0111] In one embodiment, during the first initialization period, when the previous scan signal (Sn-1) is supplied through the previous scan line (SLp), the first initialization transistor (T4) is turned on in response to the previous scan signal (Sn-1), and the driving transistor (T1) can be initialized by the first initialization voltage (Vint1) supplied from the first initialization voltage line (VIL1).

[0112] In one embodiment, during a data programming period, when a first scan signal (Sn1) and a second scan signal (Sn2) are supplied through a first scan line (SL1) and a second scan line (SL2), respectively, a switching transistor (T2) and a compensation transistor (T3) may be turned on in response to the first scan signal (Sn1) and the second scan signal (Sn2). At this time, the driving transistor (T1) may be diode-connected by the turned-on compensation transistor (T3) and may be forward-biased. Then, a voltage obtained by compensating for a threshold voltage of the driving transistor (T1) from a data signal (Dm) supplied from a data line (DL) may be applied to a gate electrode of the driving transistor (T1). A driving voltage (ELVDD) and a compensation voltage are applied to both ends of the first storage capacitor (Cst), and a charge corresponding to a voltage difference between the two ends of the first storage capacitor (Cst) can be stored in the first storage capacitor (Cst).

[0113] In one embodiment, during the light emission period, the operation control transistor (T5) and the light emission control transistor (T6) can be turned on by the light emission control signal (En) supplied from the light emission control line (EL). A driving current is generated according to the voltage difference between the voltage of the gate electrode of the driving transistor (T1) and the driving voltage (ELVDD), and the driving current can be supplied to the light emitting element (LED) through the light emission control transistor (T6).

[0114] In one embodiment, during the second initialization period, when a subsequent scan signal (Sn+1) is supplied through the subsequent scan line (SLn), the second initialization transistor (T7) is turned on in response to the subsequent scan signal (Sn+1), and the light emitting element (LED) is initialized by the second initialization voltage (Vint2) supplied from the second initialization voltage line (VIL2).

[0115] In one embodiment, at least one of the plurality of transistors (T1 to T7) may be provided as an oxide-based transistor including an oxide semiconductor, and the remaining transistors may be provided as silicon-based transistors including a silicon semiconductor.

[0116] Specifically, in one embodiment, a driving transistor (T1) that directly affects the brightness of a display device is configured to include a semiconductor layer made of polycrystalline silicon having high reliability, thereby enabling a high-resolution display device to be implemented.

[0117] Meanwhile, oxide semiconductors have high carrier mobility and low leakage current, so even with long driving times, the voltage drop may not be significant. In other words, even when driving at low frequencies, the color change of the image due to the voltage drop is not significant, so low-frequency driving is possible.

[0118] In this embodiment, since oxide semiconductors have the advantage of low leakage current, by employing at least one of the compensation transistor (T3), the first initialization transistor (T4), and the second initialization transistor (T7) connected to the gate electrode of the driving transistor (T1) as an oxide semiconductor, leakage current that may flow to the gate electrode of the driving transistor (T1) can be prevented while reducing power consumption.

[0119] FIG. 5 is a plan view illustrating a portion of a display panel according to one embodiment, and is an enlarged plan view illustrating part D of FIG. 3B. In addition, FIGS. 6A to 6E are plan views illustrating a portion of the display panel illustrated in FIG. 5, respectively, according to one embodiment. FIG. 7 is a diagram schematically illustrating a cross-section taken along line B-B' of FIG. 3B and line I-I' of FIG. 5 according to one embodiment, FIG. 8 is a diagram schematically illustrating a cross-section taken along line B-B' of FIG. 3B and line II-II' of FIG. 5 according to one embodiment, and FIG. 9 is a diagram schematically illustrating a cross-section taken along line B-B' of FIG. 3B and line III-III' of FIG. 5 according to one embodiment.

[0120] First, referring to Fig. 7, the laminated structure of the components included in the display device will be described with a focus on the display area (DA).

[0121] In one embodiment, the display panel (10) in the display area (DA) may include a substrate (100), an inorganic insulating layer (200), a subpixel circuit (PC) organic insulating layer (OIL), a light emitting element layer (300), a sealing substrate (400) as a sealing structure, and a filling layer (700).

[0122] In one embodiment, the substrate (100) includes a display area (DA) and a peripheral area (PA) and may include a glass material or a polymer resin. In one embodiment, the substrate (100) may have an alternating laminated structure of a base layer including a polymer resin and a barrier layer including an inorganic insulating material such as silicon oxide or silicon nitride. For example, the substrate may include a first base layer (101), a first barrier layer (103), a second base layer (105), and a second barrier layer (107) that are sequentially laminated. Each of the first base layer (101) and the second base layer (105) may include a polymer resin, and each of the first barrier layer (103) and the second barrier layer (107) may include an inorganic insulating material.

[0123] In one embodiment, the inorganic insulating layer (200) may be disposed on the substrate (100) and may overlap the display area (DA) and the peripheral area (PA). In one embodiment, the inorganic insulating layer (200) may include a buffer layer (211), a first inorganic insulating layer (213), a second inorganic insulating layer (215), a third inorganic insulating layer (217), a fourth inorganic insulating layer (218), and a fifth inorganic insulating layer (219). The buffer layer (211), the first inorganic insulating layer (213), the second inorganic insulating layer (215), the third inorganic insulating layer (217), the fourth inorganic insulating layer (218), and the fifth inorganic insulating layer (219) may be sequentially laminated on the substrate (100).

[0124] In one embodiment, the subpixel circuit (PC) may include at least one transistor and at least one capacitor. In one embodiment, the subpixel circuit (PC) may include a first transistor (TFT1), a second transistor (TFT2), and a first storage capacitor (Cst). The first transistor (TFT1) may include a first semiconductor layer (Act1), a first gate electrode (GE1), a first source electrode (SE1), and a first drain electrode (DE1). The second transistor (TFT2) may include a second semiconductor layer (Act2), a second gate electrode (GE2), a second source electrode (SE2), and a second drain electrode (DE2). The first storage capacitor (Cst) may include a first capacitor electrode (CE1) and a second capacitor electrode (CE2).

[0125] In one embodiment, a buffer layer (211) may be disposed on the substrate (100). The buffer layer (211) may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and may be a single layer or multiple layers including the aforementioned inorganic insulating material.

[0126] In one embodiment, a lower metal layer (BML) may be disposed between the substrate (100) and the buffer layer (211). The lower metal layer (BML) may overlap at least one of the first semiconductor layer (Act1) and the second semiconductor layer (Act2) in a plan view. In some embodiments, a constant voltage or a signal may be applied to the lower metal layer (BML). The lower metal layer (BML) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multilayer or single layer including the above materials. Since the lower metal layer (BML) overlaps at least one of the first semiconductor layer (Act1) and the second semiconductor layer (Act2) in a plan view, the characteristics of at least one of the first transistor (TFT1) and the second transistor (TFT2) may be improved.

[0127] In one embodiment, at least one of the first semiconductor layer (Act1) and the second semiconductor layer (Act2) may include an oxide semiconductor. In one embodiment, the first semiconductor layer (Act1) may include a silicon semiconductor, and the second semiconductor layer (Act2) may include an oxide semiconductor. The first semiconductor layer (Act1) and the second semiconductor layer (Act2) may include a channel region and a source region and a drain region respectively disposed on both sides of the channel region.

[0128] The first semiconductor layer (Act1) may be disposed between the buffer layer (211) and the first inorganic insulating layer (213). In one embodiment, the first semiconductor layer (Act1) may include a silicon semiconductor. For example, the first semiconductor layer (Act1) may include polysilicon or amorphous silicon.

[0129] The first inorganic insulating layer (213) may be disposed on the buffer layer (211) and the first semiconductor layer (Act1). In one embodiment, the first inorganic insulating layer (213) may be a first gate insulating layer. The first inorganic insulating layer (213) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide.

[0130] In one embodiment, the first gate electrode (GE1) may be disposed between the first inorganic insulating layer (213) and the second inorganic insulating layer (215). The first capacitor electrode (CE1) may be disposed between the first inorganic insulating layer (213) and the second inorganic insulating layer (215). The first gate electrode (GE1) may overlap the first semiconductor layer (Act1). In one embodiment, the first gate electrode (GE1) may overlap the channel region of the first semiconductor layer (Act1).

[0131] In one embodiment, the first capacitor electrode (CE1) and the first gate electrode (GE1) may be integral. However, the present invention is not limited thereto, and in another embodiment, the first capacitor electrode (CE1) may be spaced apart from the first gate electrode (GE1).

[0132] In one embodiment, the first gate electrode (GE1) and the first capacitor electrode (CE1) may be arranged in the same layer and may include the same material. The first gate electrode (GE1), the second gate electrode (GE2), and the first capacitor electrode (CE1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be provided as a multilayer or single layer including the above materials.

[0133] In one embodiment, the second inorganic insulating layer (215) may be disposed on the first gate electrode (GE1), the first capacitor electrode (CE1), and the first inorganic insulating layer (213). In one embodiment, the second inorganic insulating layer (215) may be a second gate insulating layer and may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide.

[0134] In one embodiment, the second capacitor electrode (CE2) may be disposed on the second inorganic insulating layer (215) and may overlap the first gate electrode (GE1) therebelow. The second capacitor electrode (CE2) and the first gate electrode (GE1) may overlap with the second inorganic insulating layer (215) therebetween to form a first storage capacitor (Cst).

[0135] In one embodiment, the second capacitor electrode (CE2) may be disposed on the second inorganic insulating layer (215) and may overlap the first capacitor electrode (CE1) in a plan view. The first capacitor electrode (CE1) and the second capacitor electrode (CE2) may constitute a first storage capacitor (Cst). The second capacitor electrode (CE2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be provided in a multilayer or single layer including the above materials.

[0136] In one embodiment, the third inorganic insulating layer (217) may be disposed on the second capacitor electrode (CE2) and the second inorganic insulating layer (215). In one embodiment, the third inorganic insulating layer (217) may be a first interlayer insulating layer. The third inorganic insulating layer (217) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide.

[0137] In one embodiment, the second semiconductor layer (Act2) may be disposed on the third inorganic insulating layer (217). In one embodiment, the second semiconductor layer (Act2) may include an oxide semiconductor. For example, the second semiconductor layer (Act2) may be formed of a Zn oxide-based material, such as Zn oxide, In—Zn oxide, Ga—In—Zn oxide, etc. In another embodiment, the second semiconductor layer (Act2) may be formed of an IGZO (In—Ga—Zn—O), ITZO (In—Sn—Zn—O), or IGTZO (In—Ga—Sn—Zn—O) semiconductor containing a metal such as indium (In), gallium (Ga), or tin (Sn) in zinc oxide.

[0138] In one embodiment, the fourth inorganic insulating layer (218) may be disposed on the second semiconductor layer (Act2) and the third inorganic insulating layer (217). In one embodiment, the fourth inorganic insulating layer (218) may be a third gate insulating layer. In one embodiment, the fourth inorganic insulating layer (218) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide.

[0139] In one embodiment, the second gate electrode (GE2) may be disposed on the fourth inorganic insulating layer (218) and may be disposed between the fourth inorganic insulating layer (218) and the fifth inorganic insulating layer (219). The second gate electrode (GE2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be provided as a multilayer or single layer including the above materials.

[0140] In one embodiment, the first source electrode (SE1), the first drain electrode (DE1), the second source electrode (SE2), and the second drain electrode (DE2) may be disposed on a fifth inorganic insulating layer (219). In one embodiment, the fifth inorganic insulating layer (219) may be a second interlayer insulating layer. In one embodiment, the fifth inorganic insulating layer (219) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide. The first source electrode (SE1) and the first drain electrode (DE1) may be connected to the first semiconductor layer (Act1) through contact holes of the insulating layers. The second source electrode (SE2) and the second drain electrode (DE2) can be electrically connected to the second semiconductor layer (Act2) through contact holes in the insulating layers.

[0141] In one embodiment, the first source electrode (SE1), the first drain electrode (DE1), and the second source electrode (SE2), the second drain electrode (DE2) may be arranged in the same layer and may include the same material. The first source electrode (SE1), the first drain electrode (DE1), the second source electrode (SE2), and the second drain electrode (DE2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be provided as a multilayer or single layer including the above materials. In one embodiment, the first source electrode (SE1), the first drain electrode (DE1), the second source electrode (SE2), and the second drain electrode (DE2) may have a multilayer structure of Ti / Al / Ti.

[0142] In one embodiment, the lower gate electrode (BGE) may be disposed under the second semiconductor layer (Act2). In one embodiment, the lower gate electrode (BGE) may be disposed between the second inorganic insulating layer (215) and the third inorganic insulating layer (217). In one embodiment, the lower gate electrode (BGE) may receive a gate signal. In this case, the second transistor (TFT2) may have a dual gate electrode structure in which gate electrodes are disposed on the upper and lower portions of the second semiconductor layer (Act2). The lower gate electrode (BGE) may be disposed on the same layer as the second capacitor electrode (CE2) and may include the same material.

[0143] In one embodiment, the gate line (GWL) may be disposed between the fourth inorganic insulating layer (218) and the fifth inorganic insulating layer (219). In one embodiment, the gate line (GWL) may be electrically connected to the lower gate electrode (BGE) through a contact hole provided in the insulating layers. The gate line (GWL) may be disposed in the same layer as the second gate electrode (GE2) and may include the same material. The gate line (GWL) may be integral with the second gate electrode (GE2).

[0144] In one embodiment, the organic insulating layer (OIL) may be disposed on the inorganic insulating layer (200), the first source electrode (SE1), the first drain electrode (DE1), the second source electrode (SE2), and the second drain electrode (DE2). In one embodiment, the organic insulating layer (OIL) may include a first organic insulating layer (OIL1), a second organic insulating layer (OIL2), and a third organic insulating layer (OIL3). The organic insulating layer (OIL) may include an organic material. The first organic insulating layer (OIL1), the second organic insulating layer (OIL2), and the third organic insulating layer (OIL3) may include organic insulators such as general-purpose polymers such as polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0145] In one embodiment, the first connection electrode (CD1) may be disposed on the first organic insulating layer (OIL1). At this time, the first connection electrode (CD1) may be connected to the first drain electrode (DE1) or the first source electrode (SE1) through a contact hole of the first organic insulating layer (OIL1). The first connection electrode (CD1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above materials. The second organic insulating layer (OIL2) and the third organic insulating layer (OIL3) may be disposed to cover the first connection electrode (CD1).

[0146] In one embodiment, the light emitting element layer (300) may be disposed on an organic insulating layer (OIL) and may include a light emitting element (LED) and a bank layer (340). The light emitting element (LED) may include a subpixel electrode (310), a light emitting layer (320), and a counter electrode (330). The light emitting element (LED) may be electrically connected to a subpixel circuit (PC) through a contact hole of the organic insulating layer (OIL). In one embodiment, the subpixel electrode (310) of the light emitting element (LED) may be electrically connected to a first connection electrode (CD1) through a contact hole of the organic insulating layer (OIL).

[0147] In one embodiment, the subpixel electrode (310) may be disposed on an organic insulating layer (OIL) and may be electrically connected to a subpixel circuit (PC). In one embodiment, the organic insulating layer (OIL) may have a contact hole. The subpixel electrode (310) may be electrically connected to the subpixel circuit (PC) through the contact hole of the organic insulating layer (OIL). In one embodiment, the subpixel electrode (310) may be electrically connected to a first source electrode (SE1) or a first drain electrode (DE1). The subpixel electrode (310) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the subpixel electrode (310) may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In yet another embodiment, the subpixel electrode (310) may further include a film formed of ITO, IZO, ZnO, or In2O3 on or under the aforementioned reflective film.

[0148] In one embodiment, a bank layer (340) having an opening (340OP) exposing a central portion of the subpixel electrode (310) may be disposed on the subpixel electrode (310). The bank layer (340) may include an organic insulating material and / or an inorganic insulating material. In some embodiments, the bank layer (340) may include a light-blocking material. The opening (340OP) of the bank layer (340) may define an emission area of ​​light emitted from a light-emitting element (LED).

[0149] In one embodiment, the bank layer (340) may further include a spacer (not shown) protruding in the thickness direction of the substrate (100). The spacer may protrude from the bank layer (340) in a third direction (e.g., the z-direction). The bank layer (340) including the spacer may be formed using a halftone mask. In some embodiments, the spacer may include a different material from the bank layer (340) and may be disposed on the bank layer (340).

[0150] In one embodiment, a light-emitting layer (320) may be disposed in the opening (340OP) of the bank layer (340). The light-emitting layer (320) may include a polymer or a low-molecular organic material that emits light of a predetermined color. Although not illustrated, a first functional layer and a second functional layer may be disposed below and above the light-emitting layer (320), respectively. The first functional layer may include, for example, a hole transport layer (HTL) or a hole transport layer and a hole injection layer (HIL). The second functional layer is an optional component disposed on the light-emitting layer (320). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer and / or the second functional layer may be a common layer formed to entirely cover the substrate (100), similar to the counter electrode (330) described below.

[0151] In one embodiment, the counter electrode (330) may be disposed on the light-emitting layer (320) and may be made of a conductive material having a low work function. For example, the counter electrode (330) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. In another embodiment, the counter electrode (330) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0152] In another embodiment, a sealing substrate (400) may be placed on a light-emitting element (LED). A filling layer (700) may be placed between the light-emitting element (LED) and the sealing substrate (400) in the display area (DA). The filling layer (700) may include a filler.

[0153] In one embodiment, referring to FIG. 5, the display panel may include a fan-out wiring (FL) and a first-first power voltage line (21) of the first power voltage line (20, refer to FIG. 3b).

[0154] In one embodiment, a fan-out wiring (FL) may be disposed in a peripheral area (PA) and may extend from a pad area (PADA, see FIG. 3b) to a display area (DA, see FIG. 3b). In one embodiment, the fan-out wiring (FL) may extend in a second direction (e.g., the y-direction). In another embodiment, the fan-out wiring (FL) may extend in a direction crossing the first direction (e.g., the x-direction) and the second direction (e.g., the y-direction). The fan-out wiring (FL) may be provided in multiple numbers. In one embodiment, although FIG. 5 illustrates four fan-out wirings (FL) including a contact portion (CTP), the number of fan-out wirings (FL) may be four or more.

[0155] In one embodiment, the first power voltage line (20) may be arranged in the peripheral area (PA). The first power voltage line (20) may be arranged between the pad area (PADA, see FIG. 3b) and the display area (DA, see FIG. 3b). The first-first power voltage line (21) of the first power voltage line (20) may extend in the second direction (e.g., the y direction). In one embodiment, each of the fan-out wirings (FL) may overlap at least a portion of the first power voltage line (20). In one embodiment, the width of the first power voltage line (20) in the first direction (e.g., the x direction) may be greater than the width of one fan-out wiring (FL) in the first direction (e.g., the x direction).

[0156] Hereinafter, the structure of the 1-1 power voltage line (21) and the fan-out wiring (FL) is described assuming that the 1st power voltage line (20), for example, the 1-1 power voltage line (21), and the fan-out wiring (FL) overlap. However, the same description can be applied to the structure of the 2nd power voltage line (30, see FIG. 3a) and the fan-out wiring (FL) when the 2nd power voltage line (30, see FIG. 3a) and the fan-out wiring (FL) overlap.

[0157] In one embodiment, the fan-out wiring (FL) may include first fan-out wirings (FL1) and second fan-out wirings (FL2). The second fan-out wiring (FL2) may be arranged alternately with adjacent first fan-out wirings (FL1) in a plan view. For example, the second fan-out wiring (FL2) may be arranged between adjacent first fan-out wirings (FL1) in a plan view. In other words, the first fan-out wiring (FL1) may be arranged between adjacent second fan-out wirings (FL2) in a plan view. In one embodiment, the second fan-out wiring (FL2) may have a different wiring structure from the first fan-out wiring (FL1), such as being arranged on a different layer or including a different material from the first fan-out wiring (FL1). However, the present invention is not necessarily limited thereto. In another embodiment, the fan-out wiring (FL) may include only the first fan-out wirings (FL1) or the second fan-out wirings (FL2). Hereinafter, the description will be made on the assumption that the fan-out wiring (FL) includes the first fan-out wirings (FL1) and the second fan-out wirings (FL2).

[0158] In one embodiment, a fan-out wiring (FL) may include a first sub-wiring and a second sub-wiring. In a plan view of the fan-out wiring (FL), the first sub-wiring may be arranged closer to the pad area (PADA) than the second sub-wiring, and the second sub-wiring may be arranged closer to the display area (DA) than the first sub-wiring. For example, the first fan-out wiring (FL1) may include a first-first sub-wiring (FL1a) and a first-second sub-wiring (FL1b). In the plan view, the first-first sub-wiring (FL1a) of the first fan-out wiring (FL1) may be arranged closer to the pad area (PADA) than the first-second sub-wiring (FL1b). In addition, the second fan-out wiring (FL2) may include a second-first sub-wiring (FL2a) and a second-second sub-wiring (FL2b). In the floor plan, the 2-1 sub-wiring (FL2a) of the 2nd fan-out wiring (FL2) can be placed closer to the pad area (PADA) than the 2-2 sub-wiring (FL2b).

[0159] In one embodiment, the first sub-wiring and the second sub-wiring of the fan-out wiring (FL) may be arranged in different layers. The first sub-wiring of the fan-out wiring (FL) may be arranged on an inorganic insulating layer (200), and the second sub-wiring of the fan-out wiring (FL) may be inserted into the inorganic insulating layer (200). For example, the first sub-wiring of the fan-out wiring (FL) may be arranged between the inorganic insulating layer (200) and the first organic insulating layer (OIL1), or between the first organic insulating layer (OIL1) and the second organic insulating layer (OIL2). The second sub-wiring of the fan-out wiring (FL) may be arranged between the first inorganic insulating layer (213) and the second inorganic insulating layer (215), or between the second inorganic insulating layer (215) and the third inorganic insulating layer (217). The second sub-wiring of the fan-out wiring (FL) can be electrically connected to the first sub-wiring at the contact portion (CTP).

[0160] Referring to FIGS. 5, 6b, 6d, and 7 in one embodiment, the first-first sub-wiring (FL1a) and the first-second sub-wiring (FL1b) of the first fan-out wiring (FL1) may be arranged on different layers. The first-first sub-wiring (FL1a) of the first fan-out wiring (FL1) may be arranged between the fifth inorganic insulating layer (219) and the first organic insulating layer (OIL1). The first-first sub-wiring (FL1a) may be arranged on the same layer as the first source electrode (SE1), the first drain electrode (DE1), the second source electrode (SE2), and the second drain electrode (DE2) arranged in the display area (DA), and may include the same material. The first-second sub-wiring (FL1b) may be arranged between the second inorganic insulating layer (215) and the third inorganic insulating layer (217). The first-second sub-wiring (FL1b) may be arranged on the same layer as the second capacitor electrode (CE2) of the first storage capacitor (Cst) of the display area (DA) and may include the same material.

[0161] In one embodiment, the first-first sub-wiring (FL1a) and the first-second sub-wiring (FL1b) of the first fan-out wiring (FL1) in the plan view can be electrically connected at the first contact portion (CTP1). The first-second sub-wiring (FL1b) of the first fan-out wiring (FL1) can be connected to the first-first sub-wiring (FL1a) through the contact hole (CT1) of the first contact portion (CTP1).

[0162] In one embodiment, referring to FIGS. 5, 6a, 6e, and 8, the second-first sub-wiring (FL2a) and the second-second sub-wiring (FL2b) of the second fan-out wiring (FL2) may be arranged on different layers. The second-first sub-wiring (FL2a) of the second fan-out wiring (FL2) may be arranged between the first organic insulating layer (OIL1) and the second organic insulating layer (OIL2). The second-first sub-wiring (FL2a) may be arranged on the same layer as the first connection electrode (CD1) of the display area (DA) and may include the same material. The second-second sub-wiring (FL2b) may be arranged between the first inorganic insulating layer (213) and the second inorganic insulating layer (215). The second-second sub-wiring (FL2b) is arranged on the same layer as the first capacitor electrode (CE1) and the first gate electrode (GE1) arranged in the display area (DA), and may include the same material.

[0163] In one embodiment, the second-first sub-wiring (FL2a) and the second-second sub-wiring (FL2b) of the second fan-out wiring (FL2) in the plan view may be electrically connected at the second contact portion (CTP2). The second-first sub-wiring (FL2a) of the second fan-out wiring (FL2) may be electrically connected to the second-second sub-wiring (FL2b) via the first connecting member (CM1). The second-first sub-wiring (FL2a) of the second fan-out wiring (FL2) may be electrically connected to the first connecting member (CM1) via the contact hole (CT3). The first connecting member (CM1) may be electrically connected to the second-second sub-wiring (FL2b) via the contact hole (CT2). The first connecting member (CM1) may be disposed between the fifth inorganic insulating layer (219) and the first organic insulating layer (OIL1). The first connecting member (CM1) may be disposed on the same layer as the first source electrode (SE1), the first drain electrode (DE1), the second source electrode (SE2), and the second drain electrode (DE2), and may include the same material.

[0164] As described above in one embodiment, the first fan-out wiring (FL1) is provided with a first-first sub-wiring (FL1a) and a first-second sub-wiring (FL1b) arranged in different layers, thereby reducing the resistance of the wiring. The second fan-out wiring (FL2) is provided with a second-first sub-wiring (FL2a) and a second-second sub-wiring (FL2b) arranged in different layers, thereby reducing the resistance of the wiring.

[0165] In one embodiment, referring to FIG. 5, the contact portion (CTP) of the fan-out wiring (FL) in the plan view may be located outside the sealing member (500, see FIG. 3b). For example, the first contact portion (CTP1) of the first fan-out wiring (FL1) may be located between the sealing member (500) and the pad area (PADA). The second contact portion (CTP2) of the second fan-out wiring (FL2) may be located between the sealing member (500) and the pad area (PADA). Accordingly, even if a laser is used in the process of bonding the sealing member (500) and the sealing substrate (400), it is possible to prevent the first sub-wiring of the fan-out wiring (FL) arranged on the inorganic insulating layer (200, see FIGS. 7 and 8), for example, the 1-1 sub-wiring (FL1a) of the first fan-out wiring (FL1) and the 2-1 sub-wiring (FL2a) of the second fan-out wiring (FL2), from being damaged by the laser, that is, it is possible to prevent the resistance of the 1-1 sub-wiring (FL1a) of the first fan-out wiring (FL1) and the 2-1 sub-wiring (FL2a) of the second fan-out wiring (FL2) from increasing.

[0166] As described above in one embodiment, the second fan-out wiring (FL2) may be arranged on a different layer from the first fan-out wiring (FL1). For example, the second-first sub-wiring (FL2a) of the second fan-out wiring (FL2) may be arranged on a different layer from the first-first sub-wiring (FL1a) of the first fan-out wiring (FL1). The second-second sub-wiring (FL2b) of the second fan-out wiring (FL2) may be arranged on a different layer from the first-second sub-wiring (FL1b) of the first fan-out wiring (FL1). However, the present invention is not necessarily limited thereto. In another embodiment, the second-first sub-wiring (FL2a) of the second fan-out wiring (FL2) may be arranged on a different layer from the first-first sub-wiring (FL1a) of the first fan-out wiring (FL1), but the second-second sub-wiring (FL2b) of the second fan-out wiring (FL2) may be arranged on the same layer as the first-second sub-wiring (FL1b) of the first fan-out wiring (FL1). In another embodiment, the second-first sub-wiring (FL2a) of the second fan-out wiring (FL2) may be arranged on the same layer as the first-first sub-wiring (FL1a) of the first fan-out wiring (FL1), but the second-second sub-wiring (FL2b) of the second fan-out wiring (FL2) may be arranged on a different layer from the first-second sub-wiring (FL1b) of the first fan-out wiring (FL1).

[0167] Referring to FIG. 5 in one embodiment, the first-first power supply voltage line (21) may include a first sub-power supply voltage line (21a) and a second sub-power supply voltage line (21b). The first sub-power supply voltage line (21a) may be arranged closer to the pad area (PADA) than the second sub-power supply voltage line (21b) in the plan view. In other words, the second sub-power supply voltage line (21b) may be arranged closer to the display area (DA) than the first sub-power supply voltage line (21a) in the plan view.

[0168] In one embodiment, the first sub-power voltage line (21a) may overlap the first sub-wire of the fan-out wiring (FL) in the plan view. For example, the first sub-power voltage line (21a) may overlap the first-first sub-wire (FL1a) of the first fan-out wiring (FL1) and the second-first sub-wire (FL2a) of the second fan-out wiring (FL2) in the plan view. The second sub-power voltage line (21b) may overlap the second sub-wire of the fan-out wiring (FL) in the plan view. For example, the second sub-power voltage line (21b) may overlap the first-second sub-wire (FL1b) of the first fan-out wiring (FL1) and the second-second sub-wire (FL2b) of the second fan-out wiring (FL2) in the plan view.

[0169] In one embodiment, the first-first power supply line (21) may include an opening (21H) in the plan view. The openings (21H) may be provided in multiple numbers. The openings (21H) of the first-first power supply line (21) may be located in the first sub-power supply line (21a). In the plan view, the contact portion (CTP) of the fan-out wiring (FL) may be located within the opening (21H) of the first sub-power supply line (21a). For example, each of the first contact portions (CTP1) of the first fan-out wirings (FL1) may be located within a corresponding one of the openings (21H) of the first sub-power supply line (21a) in the plan view. Each of the second contact portions (CTP2) of the second fan-out wirings (FL2) can be located within a corresponding opening (21H) among the openings (21H) of the first sub-power voltage line (21a) in the plan view.

[0170] In one embodiment, referring to FIGS. 5, 6c, 6e, and 9, the first sub-voltage line (21a) and the second sub-voltage line (21b) may be disposed on different layers. The first sub-voltage line (21a) may be inserted into the inorganic insulating layer (200), and the second sub-voltage line (21b) may be disposed on the inorganic insulating layer (200). In one embodiment, the first sub-voltage line (21a) may be disposed between the fourth inorganic insulating layer (218) and the fifth inorganic insulating layer (219). The first sub-voltage line (21a) may be disposed on the same layer as the second gate electrode (GE2) of the second transistor (TFT2) in the display area (DA), and may include the same material. The second sub-voltage line (21b) may be arranged between the first organic insulating layer (OIL1) and the second organic insulating layer (OIL2). The second sub-voltage line (21b) may be arranged on the same layer as the first connection electrode (CD1) and may include the same material.

[0171] In one embodiment, referring to FIGS. 5, 7, 8, and 9, the first sub-power voltage line (21a) may be arranged on a different layer from the first sub-wire of the fan-out wiring (FL). For example, the first sub-power voltage line (21a) may be arranged on a different layer from the 1-1 sub-wire (FL1a) of the first fan-out wiring (FL1). The first sub-power voltage line (21a) may be arranged on a different layer from the 2-1 sub-wire (FL2a) of the second fan-out wiring (FL2). In addition, the second sub-power voltage line (21b) may be arranged on a different layer from the second sub-wire of the fan-out wiring (FL). For example, the second sub-power voltage line (21b) may be arranged on a different layer from the first-second sub-wiring (FL1b) of the first fan-out wiring (FL1). The second sub-power voltage line (21b) may be arranged on a different layer from the second-second sub-wiring (FL2b) of the second fan-out wiring (FL2).

[0172] In one embodiment, referring to FIGS. 5 and 9, the first sub-power voltage line (21a) of the first-first power voltage line (21) may be electrically connected to the second sub-power voltage line (21b) through the second connecting member (CM2). The second sub-power voltage line (21b) may be electrically connected to the second connecting member (CM2) through the contact hole (CT5). The second connecting member (CM2) may be electrically connected to the first sub-power voltage line (21a) through the contact hole (CT4). The second connecting member (CM2) may be disposed between the fifth inorganic insulating layer (219) and the first organic insulating layer (OIL1). The second connecting member (CM2) is arranged on the same layer as the first source electrode (SE1), the first drain electrode (DE1), the second source electrode (SE2), and the second drain electrode (DE2), and may include the same material.

[0173] According to embodiments of the present invention, the fan-out wiring (FL) includes a first sub-wiring arranged on an inorganic insulating layer (200) and a second sub-wiring inserted into the inorganic insulating layer (200), and the 1-1 power voltage line (21) that at least partially overlaps the fan-out wiring (FL) includes a first sub-power voltage line (21a) inserted into the inorganic insulating layer (200) and a second sub-power voltage line (21b) arranged on the inorganic insulating layer (200), and the first sub-power voltage line (21a) of the 1-1 power voltage line (21) overlaps the first sub-wiring of the fan-out wiring (FL) but is arranged on a different layer from the first sub-wiring, and the second sub-power voltage line (21b) of the 1-1 power voltage line (21) overlaps the second sub-wiring of the fan-out wiring (FL) but is arranged on a different layer from the second sub-wiring. Can be arranged on the top. In addition, the contact portion (CTP) electrically connecting the first sub-wiring and the second sub-wiring of the fan-out wiring (FL) in the plan view can be arranged within the opening (21H) of the 1-1 power voltage line (21). According to an embodiment of the present invention, the fan-out wiring (FL) is provided with the first sub-wiring and the second sub-wiring arranged in different layers, so that the resistance of the wiring can be reduced. At the same time, the fan-out wiring (FL) can be designed to overlap the 1-1 power voltage line (21) without changing the path, so that the dead space of the display device can be reduced.

[0174] The display device according to the present embodiment can be applied to various electronic devices. An electronic device according to the present embodiment can include the display device described above (e.g., the display device of FIG. 1), and in addition to the display device, can further include a module or device having additional functions.

[0175] FIG. 10 is a block diagram illustrating an electronic device according to one embodiment.

[0176] Referring to FIG. 17, an electronic device (1000) according to one embodiment may include a display module (1001), a processor (1002), a memory (1003), and a power module (1004).

[0177] The processor (1002) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0178] The memory (1003) may store data information necessary for the operation of the processor (1002) or the display module (1001). When the processor (1002) executes an application stored in the memory (1003), an image data signal and / or an input control signal is transmitted to the display module (1001), and the display module (1001) can process the received signal and output image information through a display screen.

[0179] The power module (1004) may include a power supply module, such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of the electronic device (1000).

[0180] At least one of the components of the electronic device (1000) described above may be included in the display device according to the embodiments described above. In addition, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module (1001), and the processor (1002), memory (1003), and power module (1004) may be provided in the form of other devices within the electronic device (1000) other than the display device.

[0181] In one embodiment, a display module (1001) included in a display device can be driven according to an image data signal and an input control signal received from a processor (1002).

[0182] FIG. 11 is a schematic diagram illustrating an electronic device according to various embodiments.

[0183] Referring to FIG. 11, various electronic devices to which display devices according to embodiments are applied may include not only image display electronic devices such as a smart phone (1000a), a tablet PC (1000b), a laptop (1000c), a TV (1000d), and a desk monitor (1000e), but also wearable electronic devices including display modules such as smart glasses (1000f), a head-mounted display (1000g), and a smart watch (1000h), and vehicle electronic devices (1000i) including display modules such as a CID (Center Information Display) and a room mirror display placed on an instrument panel, center fascia, or dashboard of an automobile.

[0184] It is to be understood that the embodiments described herein are to be considered illustrative only and not limiting. The description of features or aspects of each embodiment should generally be considered to apply to other similar features or aspects of other embodiments. While one or more embodiments have been described with reference to the drawings, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the claims. Furthermore, the embodiments or portions of the embodiments may be combined, in whole or in part, without departing from the scope of the present invention.

Claims

1. A substrate including a display area and a peripheral area including a pad area arranged outside the display area; An inorganic insulating layer disposed on the above substrate; A light-emitting element layer including a light-emitting element disposed on the above-described inorganic insulating layer and overlapping the display area in a plan view; A power voltage line disposed between the pad area and the display area in the plan view and including an opening; and Including a fan-out wiring extending from the pad area to the display area in the plan view and overlapping at least a portion of the power voltage line; The fan-out wiring includes a first sub-wiring arranged on the inorganic insulating layer, a second sub-wiring inserted into the inorganic insulating layer, and a contact portion electrically connecting the first sub-wiring and the second sub-wiring. A display device in which the contact portion of the fan-out wiring in the plan view is located within the opening of the power voltage line.

2. In paragraph 1, It further includes an organic insulating layer including a first organic insulating layer and a second organic insulating layer, which are sequentially stacked on the inorganic insulating layer; The above inorganic insulating layer includes a first inorganic insulating layer, a second inorganic insulating layer, and a third inorganic insulating layer that are sequentially laminated, The first sub-wiring of the fan-out wiring is arranged between the inorganic insulating layer and the first organic insulating layer, or between the first organic insulating layer and the second organic insulating layer, A display device in which the second sub-wiring of the fan-out wiring is disposed between the first inorganic insulating layer and the second inorganic insulating layer, or between the second inorganic insulating layer and the third inorganic insulating layer.

3. In paragraph 2, A semiconductor layer overlapping the display area in the plan view and disposed between the substrate and the first inorganic insulating layer; and A display device further comprising a gate electrode overlapping the semiconductor layer in a plan view and positioned between the first inorganic insulating layer and the second inorganic insulating layer.

4. In paragraph 1, The above fan-out wiring includes first fan-out wiring and second fan-out wiring that are arranged alternately, The first sub-wiring of each of the first fan-out wirings is arranged on a different layer from the first sub-wiring of each of the second fan-out wirings, A display device, wherein the second sub-wiring of each of the first fan-out wirings is arranged on a different layer from the second sub-wiring of each of the second fan-out wirings.

5. In paragraph 2, The above power voltage line includes a first sub-power voltage line inserted into the inorganic insulating layer, and a second sub-power voltage line disposed on the inorganic insulating layer and electrically connected to the first sub-power voltage line. In the plan view, the first sub-power voltage line of the power voltage line overlaps the first sub-wire of the fan-out wiring, A display device in which the second sub-power voltage line of the power voltage line overlaps the second sub-wire of the fan-out wiring in the plan view.

6. In paragraph 5, A display device, wherein the opening of the power voltage line is located in the first sub-power voltage line of the power voltage line.

7. In paragraph 5, The above inorganic insulating layer further includes a fourth inorganic insulating layer disposed on the third inorganic insulating layer, A display device in which the first sub-power voltage line of the above power voltage line is disposed between the third inorganic insulating layer and the fourth inorganic insulating layer.

8. In paragraph 1, A display device in which the width of the power voltage line is greater than the width of the fan-out wiring.

9. In paragraph 1, A sealing substrate disposed on the light emitting element layer; and Further comprising a sealing member disposed between the substrate and the sealing substrate and surrounding the display area in a plan view; In the plan view, the fan-out wiring extends across the sealing member, A display device in which the contact portion of the fan-out wiring is located between the sealing member and the pad area.

10. In paragraph 1, A display device further comprising an encapsulation layer disposed on the light-emitting element layer and including at least one inorganic encapsulation layer and at least one organic encapsulation layer.

11. In paragraph 1, The above fan-out wiring includes fan-out wiring, The above power voltage line includes a plurality of the above openings, A display device, wherein each contact portion of the fan-out wirings is located within a corresponding opening among the openings.

12. A substrate including a display area and a peripheral area including a pad area arranged outside the display area; An inorganic insulating layer disposed on the above substrate; A light-emitting element layer including a light-emitting element disposed on the above-described inorganic insulating layer and overlapping the display area in a plan view; A power voltage line arranged between the pad area and the display area in the plan view; and Including a fan-out wiring extending from the pad area to the display area in the plan view and overlapping at least a portion of the power voltage line; The fan-out wiring includes a first sub-wiring arranged on the inorganic insulating layer, a second sub-wiring inserted into the inorganic insulating layer, and a contact portion electrically connecting the first sub-wiring and the second sub-wiring. The above power voltage line includes a first sub-power voltage line inserted into the inorganic insulating layer, and a second sub-power voltage line disposed on the inorganic insulating layer and electrically connected to the first sub-power voltage line. In the plan view, the first sub-power voltage line of the power voltage line overlaps the first sub-wire of the fan-out wiring, In the plan view, the second sub-power voltage line of the power voltage line overlaps the second sub-wire of the fan-out wiring, A display device in which the first sub-power voltage line of the above power voltage line is arranged on a different layer from the first sub-wire of the fan-out wiring.

13. In paragraph 12, It further includes an organic insulating layer including a first organic insulating layer and a second organic insulating layer, which are sequentially stacked on the inorganic insulating layer; The above inorganic insulating layer includes a first inorganic insulating layer, a second inorganic insulating layer, and a third inorganic insulating layer that are sequentially laminated, The first sub-wiring of the fan-out wiring is arranged between the inorganic insulating layer and the first organic insulating layer, or between the first organic insulating layer and the second organic insulating layer, A display device in which the second sub-wiring of the fan-out wiring is disposed between the first inorganic insulating layer and the second inorganic insulating layer, or between the second inorganic insulating layer and the third inorganic insulating layer.

14. In paragraph 13, A semiconductor layer overlapping the display area in the plan view and disposed between the substrate and the first inorganic insulating layer; and A display device further comprising a gate electrode overlapping the semiconductor layer in a plan view and positioned between the first inorganic insulating layer and the second inorganic insulating layer.

15. In paragraph 13, The above inorganic insulating layer further includes a fourth inorganic insulating layer disposed on the third inorganic insulating layer, A display device in which the first sub-power voltage line of the above power voltage line is disposed between the third inorganic insulating layer and the fourth inorganic insulating layer.

16. In paragraph 12, A display device, wherein the first sub-power voltage line of the power voltage line includes an opening.

17. In paragraph 16, A display device, wherein the contact portion of the fan-out wiring in the plan view is located within the opening of the first sub-power voltage line.

18. In paragraph 12, The above fan-out wiring includes first fan-out wiring and second fan-out wiring that are arranged alternately, The first sub-wiring of each of the first fan-out wirings is arranged on a different layer from the first sub-wiring of each of the second fan-out wirings, A display device, wherein the second sub-wiring of each of the first fan-out wirings is arranged on a different layer from the second sub-wiring of each of the second fan-out wirings.

19. In an electronic device including a display device, The above display device, A substrate comprising a display area and a peripheral area including a pad area disposed outside the display area; An inorganic insulating layer disposed on the above substrate; A light-emitting element layer including a light-emitting element disposed on the above-described inorganic insulating layer and overlapping the display area in a plan view; A power voltage line disposed between the pad area and the display area in the plan view and including an opening; and Including a fan-out wiring extending from the pad area to the display area in the plan view and overlapping at least a portion of the power voltage line; The fan-out wiring includes a first sub-wiring arranged on the inorganic insulating layer, a second sub-wiring inserted into the inorganic insulating layer, and a contact portion electrically connecting the first sub-wiring and the second sub-wiring. An electronic device in which the contact portion of the fan-out wiring in the plan view is located within the opening of the power voltage line.

20. In paragraph 19, display module; processor; power module; and memory; including more, An electronic device, wherein the display device includes one of the display module, the processor, the power module, or the memory.

Images