Display device

Abstract

An embodiment of the present invention provides a display device comprising a first pixel circuit disposed in each of multiple island portions and connected to a first data line, wherein the first pixel circuit comprises: a first transistor which is connected between a first driving-voltage line and a light-emitting element, and controls current supplied to the light-emitting element, and a first capacitor connected between an initialization voltage line and a first node connected to a gate of the first transistor; a second transistor which is connected between the first node and a second node, and includes a gate connected to a first gate line; a second capacitor connected between the first data line and the second node; and a third transistor which is connected between the second node and a third node connected to the light-emitting element, and includes a gate connected to a second gate line.

Description

display device

[0001] The present invention relates to the structure of a display device.

[0002] As display devices that visually display electrical signals evolve, a variety of display devices with superior characteristics, such as thinness, weight reduction, and low power consumption, are being introduced. For example, flexible display devices that can be folded or rolled are being introduced. Recently, active research and development is underway on display devices with diverse structures, such as stretchable display devices capable of transforming into various forms.

[0003] Embodiments of the present invention aim to provide a display device with improved resolution and display quality. However, these tasks are exemplary and do not limit the scope of the present invention.

[0004] One embodiment of the present invention provides a display device, including a substrate having a plurality of island portions and a plurality of bridge portions connecting the plurality of island portions defined thereon; a first pixel circuit disposed on each of the plurality of island portions and connected to a first data line; and a light-emitting element disposed on each of the plurality of island portions and connected to the first pixel circuit; wherein the first pixel circuit includes: a first transistor connected between a first driving voltage line and the light-emitting element and controlling a current supplied to the light-emitting element; a first capacitor connected between a first node connected to a gate of the first transistor and an initialization voltage line; a second transistor connected between the first node and a second node and including a gate connected to a first gate line; a second capacitor connected between the first data line and the second node; and a third transistor connected between the second node and a third node connected to the light-emitting element and including a gate connected to the second gate line.

[0005] In one embodiment, the first capacitor includes a first capacitor electrode and a second capacitor electrode disposed on the first capacitor electrode, wherein the first capacitor electrode may be part of a gate of the first transistor.

[0006] In one embodiment, the second capacitor includes a third capacitor electrode and a fourth capacitor electrode disposed on the third capacitor electrode, wherein the third capacitor electrode may be disposed on the same layer as the gate of the first transistor.

[0007] In one embodiment, a first insulating layer may be interposed between the first capacitor electrode and the second capacitor electrode, and between the third capacitor electrode and the fourth capacitor electrode.

[0008] In one embodiment, the first pixel circuit further includes a third capacitor connected between the third node and the initialization voltage line, wherein the third capacitor may include a fifth capacitor electrode and a sixth capacitor electrode on the fifth capacitor electrode.

[0009] In one embodiment, the sixth capacitor electrode may be formed integrally with the second capacitor electrode.

[0010] In one embodiment, the plurality of bridge portions may include a first bridge portion connecting adjacent first island portions in a first direction; and a second bridge portion connecting adjacent second island portions in a second direction intersecting the first direction.

[0011] In one embodiment, the first gate line and the second gate line may extend along the first direction on the plurality of island portions and the first bridge portion.

[0012] In one embodiment, the first gate line and the second gate line may be arranged on the same layer on the first bridge portion.

[0013] In one embodiment, on the first bridge portion, the first gate line, the initialization voltage line, and the first driving voltage line may be arranged on different layers.

[0014] In one embodiment, on the first bridge portion, the initialization voltage line may be arranged on the first gate line, and the first driving voltage line may be arranged on the initialization voltage line.

[0015] In one embodiment, on the second bridge portion, the first data line, the initialization voltage line, and the first driving voltage line may be arranged on different layers.

[0016] In one embodiment, on the second bridge section, the initialization voltage line may be arranged on the first data line, and the first driving voltage line may be arranged on the initialization voltage line.

[0017] In one embodiment, the device further includes a second pixel circuit disposed in each of the plurality of island portions and connected to a second data line; and a third pixel circuit disposed in each of the plurality of island portions and connected to a third data line; wherein the first pixel circuit, the second pixel circuit, and the third pixel circuit may be sequentially disposed along the first direction.

[0018] In one embodiment, the first data line, the second data line, and the third data line may extend along the second direction on the plurality of island portions and the second bridge portion.

[0019] In one embodiment, the first data line, the second data line, and the third data line may be arranged on the same layer on the second bridge portion.

[0020] In one embodiment, the initialization voltage line and the first driving voltage line may have a planar mesh pattern.

[0021] In one embodiment, the initialization voltage line may include a horizontal initialization voltage line extending along the first direction on the plurality of island portions and the first bridge portion; and a vertical initialization voltage line extending along the second direction on the plurality of island portions and the second bridge portion.

[0022] In one embodiment, the first driving voltage line may include a first horizontal driving voltage line extending along the first direction on the plurality of island portions and the first bridge portion; and a first vertical driving voltage line extending along the second direction on the plurality of island portions and the second bridge portion.

[0023] In one embodiment, the first driving voltage line supplies a second voltage lower than the first voltage supplied by the first driving voltage line, and further includes a second driving voltage line connected to the light emitting element, wherein the second driving voltage line may include a second horizontal driving voltage line extending along the first direction on the plurality of island portions and the first bridge portion; and a second vertical driving voltage line extending along the second direction on the plurality of island portions and the second bridge portion.

[0024] In one embodiment, each of the plurality of islands may further include a first circuit region in which the first pixel circuit is arranged, a second circuit region in which the second pixel circuit is arranged, and a third circuit region in which the third pixel circuit is arranged.

[0025] In one embodiment, the vertical initialization voltage line, the first vertical driving voltage line, and the second vertical driving voltage line each extend to pass through one of the first circuit area, the second circuit area, and the third circuit area, and the vertical initialization voltage line, the first vertical driving voltage line, and the second vertical driving voltage line may be arranged in different circuit areas.

[0026] In one embodiment, each of the horizontal initialization voltage line, the first horizontal driving voltage line, and the second horizontal driving voltage line may extend to pass through the first circuit area, the second circuit area, and the third circuit area.

[0027] Another embodiment of the present invention provides a display device, comprising: a substrate defining a plurality of island portions and a plurality of bridge portions connecting the plurality of island portions; a first pixel circuit disposed on each of the plurality of island portions and connected to a first data line; and a voltage wiring supplying a voltage to the first pixel circuit; wherein the plurality of bridge portions include a first bridge portion connecting adjacent first island portions in a first direction, and a second bridge portion connecting adjacent second island portions in a second direction intersecting the first direction, and wherein the voltage wiring includes a horizontal voltage wiring extending along the first direction on the first bridge portion and the plurality of island portions; and a vertical voltage wiring extending along the second direction on the second bridge portion and the plurality of island portions, wherein the horizontal voltage wiring and the vertical voltage wiring intersect in a plane on each of the plurality of island portions.

[0028] In one embodiment, the display further includes a second pixel circuit disposed in each of the plurality of island portions and connected to a second data line; and a third pixel circuit disposed in each of the plurality of island portions and connected to a third data line; and in each of the plurality of island portions, a first circuit region in which the first pixel circuit is disposed, a second circuit region in which the second pixel circuit is disposed, and a third circuit region in which the third pixel circuit is disposed may be sequentially disposed along the first direction.

[0029] In one embodiment, the vertical voltage wiring includes a first vertical driving voltage line supplying a first voltage to each of the first pixel circuit, the second pixel circuit, and the third pixel circuit; a second vertical driving voltage line supplying a second voltage lower than the first voltage to a light-emitting element electrically connected to the first pixel circuit, the second pixel circuit, or the third pixel circuit; and a vertical initialization voltage line supplying an initialization voltage to each of the first pixel circuit, the second pixel circuit, and the third pixel circuit; wherein the first vertical driving voltage line, the second vertical driving voltage line, and the vertical initialization voltage line may each extend to pass through one circuit area of ​​the first circuit area, the second circuit area, and the third circuit area.

[0030] In one embodiment, the first vertical driving voltage line, the second vertical driving voltage line, and the vertical initialization voltage line may be respectively arranged in different circuit areas.

[0031] In one embodiment, the horizontal voltage wiring includes a first horizontal driving voltage line supplying a first voltage to each of the first pixel circuit, the second pixel circuit, and the third pixel circuit; a second horizontal driving voltage line supplying a second voltage lower than the first voltage to a light-emitting element electrically connected to the first pixel circuit, the second pixel circuit, or the third pixel circuit; and a horizontal initialization voltage line supplying an initialization voltage to each of the first pixel circuit, the second pixel circuit, and the third pixel circuit; wherein the first horizontal driving voltage line, the second horizontal driving voltage line, and the horizontal initialization voltage line may extend to pass through all of the first circuit area, the second circuit area, and the third circuit area, respectively.

[0032] In one embodiment, the first pixel circuit may include a first transistor connected between a first driving voltage line and the light-emitting element and controlling a current supplied to the light-emitting element; a first capacitor connected between a first node connected to a gate of the first transistor and an initialization voltage line; a second transistor connected between the first node and a second node and including a gate connected to the first gate line; a second capacitor connected between the first data line and the second node; and a third transistor connected between the second node and a third node connected to the light-emitting element and including a gate connected to the second gate line.

[0033] In one embodiment, the first pixel circuit may further include a third capacitor connected between the third node and the initialization voltage line.

[0034] In one embodiment, the first gate line and the second gate line may extend along the first direction on the plurality of island portions and the first bridge portion.

[0035] In one embodiment, on the first bridge portion, the first gate line, the initialization voltage line, and the first driving voltage line may be arranged on different layers.

[0036] In one embodiment, the first data line may extend along the second direction over the plurality of island portions and the second bridge portion.

[0037] In one embodiment, on the second bridge portion, the first data line, the initialization voltage line, and the first driving voltage line may be arranged on different layers.

[0038] One embodiment of the present invention provides an electronic device including a display device, wherein the display device includes a substrate having a plurality of island portions and a plurality of bridge portions connecting the plurality of island portions defined thereon; a first pixel circuit disposed on each of the plurality of island portions and connected to a first data line; and a light-emitting element disposed on each of the plurality of island portions and connected to the first pixel circuit; wherein the first pixel circuit includes: a first transistor connected between a first driving voltage line and the light-emitting element and controlling a current supplied to the light-emitting element; a first capacitor connected between a first node connected to a gate of the first transistor and an initialization voltage line; a second transistor connected between the first node and a second node and including a gate connected to a first gate line; a second capacitor connected between the first data line and the second node; and a third transistor connected between the second node and a third node connected to the light-emitting element and including a gate connected to the second gate line.

[0039] According to embodiments of the present invention, a display device with improved display quality and resolution can be provided. As described herein, the display device can display an image in a simultaneous emission manner by applying a pixel circuit that receives a data voltage using a program capacitor (Cpr), and can improve the resolution of the display device by reducing the area of ​​the pixel circuit region of the first island portion where the pixel circuit is arranged. The above-described effects are exemplary, and the scope of the present invention is not limited by these effects.

[0040] FIG. 1 is a perspective view schematically showing a display device according to one embodiment of the present invention.

[0041] FIG. 2a and FIG. 2b are perspective views showing the display device of FIG. 1 extended in the first direction.

[0042] Figure 2c is a perspective view showing the display device of Figure 1 extended in the second direction.

[0043] Figure 2d is a perspective view showing the display device of Figure 1 extended in the first direction and the second direction.

[0044] Figure 2e is a perspective view showing the display device of Figure 1 extended in the third direction.

[0045] Figure 3 is a schematic plan view of a display device according to one embodiment of the present invention.

[0046] FIG. 4A is an enlarged plan view of part A of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0047] FIG. 4b is an enlarged plan view of part A of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0048] FIG. 4c is an enlarged plan view of part A of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0049] FIG. 4d is an enlarged plan view of part A of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0050] FIG. 5 is a cross-sectional view schematically showing a first island portion and a first bridge portion arranged in a display area of ​​a display device according to one embodiment of the present invention.

[0051] Figure 6 is an equivalent circuit diagram of a subpixel of a display device according to one embodiment of the present invention.

[0052] FIG. 7a is a cross-sectional view schematically showing a light-emitting element of a display device according to one embodiment of the present invention.

[0053] FIG. 7b is a cross-sectional view schematically showing a light-emitting element of a display device according to one embodiment of the present invention.

[0054] FIG. 8 is a schematic diagram showing components of pixel circuits arranged in a first island portion of a display device according to one embodiment of the present invention.

[0055] Figures 9a to 9g are schematic layout diagrams showing the components of the pixel circuits illustrated in Figure 8 layer by layer.

[0056] Fig. 10 is a schematic drawing of an initialization voltage line among the components of the display device illustrated in Fig. 8.

[0057] FIG. 11 is a schematic drawing of a first driving voltage line among the components of the display device illustrated in FIG. 8.

[0058] Fig. 12 is a schematic drawing of a second driving voltage line among the components of the display device illustrated in Fig. 8.

[0059] FIG. 13 is a cross-sectional view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0060] FIGS. 14A to 14G are perspective views schematically illustrating embodiments of an electronic device including a display device according to one embodiment of the present invention, respectively.

[0061] Figure 15 is a block diagram of an electronic device according to one embodiment of the present invention.

[0062] FIG. 16 is a schematic diagram of electronic devices according to various embodiments of the present invention.

[0063] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0064] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are assigned the same drawing numbers, and redundant descriptions thereof will be omitted.

[0065] In the examples below, the terms "first," "second," etc., are not used in a restrictive sense, but rather to distinguish one component from another. The terms "first," "second," etc., may be interpreted as being expressed as "1st," "2nd," etc., throughout this specification.

[0066] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0067] In the following examples, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0068] In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only a case where it is directly on top of the other part, but also a case where another film, region, component, etc. is interposed in between.

[0069] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0070] In some embodiments, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0071] In the following examples, when it is said that a film, region, component, etc. are connected, it includes not only cases where the films, regions, and components are directly connected, but also cases where other films, regions, and components are interposed between the films, regions, and components and thus indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it includes not only cases where the films, regions, and components are directly electrically connected, but also cases where other films, regions, and components are interposed between them and thus indirectly electrically connected.

[0072] The x-axis, y-axis, and z-axis are not limited to the three axes in the Cartesian coordinate system, but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0073] The term "substantially" as used herein means approximately or actually. The term "substantially equal" means approximately or actually the same. The term "substantially the same" means approximately or actually the same. The term "substantially perpendicular" means approximately or actually perpendicular. The term "substantially parallel" means approximately or actually parallel. The term "substantially simultaneously" means occurring approximately or actually at the same time.

[0074] FIG. 1 is a perspective view schematically illustrating a display device according to one embodiment of the present invention. FIGS. 2A and 2B are perspective views illustrating the display device of FIG. 1 extended in a first direction. FIG. 2C is a perspective view illustrating the display device of FIG. 1 extended in a second direction. FIG. 2D is a perspective view illustrating the display device of FIG. 1 extended in the first and second directions. FIG. 2E is a perspective view illustrating the display device of FIG. 1 extended in a third direction.

[0075] Referring to FIG. 1, a display device (1) may be a stretchable display device that can expand or contract in various directions. The display device (1) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a plurality of pixels. The display device (1) may provide a predetermined image using light emitted from the plurality of pixels. The non-display area (NDA) may be arranged outside the display area (DA). The non-display area (NDA) may entirely surround the display area (DA).

[0076] The display device (1) can be stretched in a first direction (e.g., the x direction and / or the -x direction) by an external force applied by an external object or a user. In one embodiment, as illustrated in FIGS. 2A and 2B, a display area (DA) and / or a non-display area (NDA) of the display device (1) can be stretched in the first direction (e.g., the x direction and / or the -x direction). For example, as illustrated in FIG. 2A, the display device (1) can be stretched along the x direction and the -x direction, or can be stretched in the x direction or the -x direction while one side of the display device (1) is fixed. FIG. 2B illustrates an example in which the display device (1) is stretched along the x direction while one side is fixed.

[0077] The display device (1) can be stretched in a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a user. In one embodiment, as illustrated in FIG. 2c, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be stretched in the y direction and the -y direction. In another embodiment, one side of the display device (1) can be fixed while being stretched in the y direction or the -y direction.

[0078] The display device (1) can be extended in a plurality of directions, for example, a first direction (e.g., the x direction and / or the -x direction) and a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a part of a human body. As illustrated in Fig. 2d, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be extended in the ±x direction and the ±y direction.

[0079] The display device (1) can be elongated in a third direction (e.g., the z direction or the -z direction) by an external force applied by an external object or a part of a human body. In one embodiment, FIG. 2e illustrates that a part of the display device (1), for example, a part of the display area (DA), protrudes in the z direction. In another embodiment, a part of the display device (1), for example, a part of the display area (DA), can protrude along the -z direction (or be sunken along the z direction).

[0080] Although FIGS. 2A to 2E illustrate the display device (1) extending in the first direction, the second direction, and / or the third direction, the present invention is not limited thereto. In other embodiments, the display device (1) may be variously deformed into an irregular shape, such as being bent or twisted along two or more axes.

[0081] Figure 3 is a schematic plan view of a display device according to one embodiment of the present invention.

[0082] A plurality of pixels (PX) may be arranged in a display area (DA) of a substrate (100). The plurality of pixels (PX) may include a first pixel (PX1) that emits light with a first color, a second pixel (PX2) that emits light with a second color, and a third pixel (PX3) that emits light with a third color. For example, the first pixel (PX1) may be a red pixel, the second pixel (PX2) may be a green pixel, and the third pixel (PX3) may be a blue pixel. The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may each include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor, and may be a pixel driving circuit that controls driving of the light-emitting element. A plurality of conductive lines (e.g., gate lines (GL), data lines (DL), and voltage lines) that provide electrical signals to the pixels (PX) may be arranged in the display area (DA).

[0083] A unit pixel (PXu) composed of a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3) can be repeatedly arranged in a predetermined pattern in the x direction and the y direction. The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) within the unit pixel (PXu) can be connected to the same gate line (GL) and can be connected to a corresponding data line (DL), respectively.

[0084] A driving circuit for providing electrical signals to light-emitting elements arranged in the display area (DA) and pixel circuits electrically connected to the light-emitting elements may be arranged in a non-display area (NDA) surrounding the display area (DA). A gate driving circuit (GDC) may be arranged in a first non-display area (NDA1) and a second non-display area (NDA2) arranged on both sides of the display area (DA). The gate driving circuit (GDC) may be connected to gate lines arranged in the display area (DA).

[0085] Although FIG. 3 illustrates that a gate driving circuit (GDC) is disposed in each of the first non-display area (NDA1) and the second non-display area (NDA2), the present invention is not limited thereto. In another embodiment, the gate driving circuit (GDC) may be disposed in either the first non-display area (NDA1) or the second non-display area (NDA2). Part or all of the gate driving circuit (GDC) may be formed directly in the non-display area (NDA) during the process of forming a transistor constituting a pixel circuit in the display area (DA).

[0086] The data driving circuit (DDC) may be disposed in a third non-display area (NDA3) and / or a fourth non-display area (NDA4) connecting the first non-display area (NDA1) and the second non-display area (NDA2). In one embodiment, FIG. 3 illustrates that the data driving circuit (DDC) is disposed in the fourth non-display area (NDA4). In another embodiment, the data driving circuit (DDC) may be disposed in each of the third non-display area (NDA3) and the fourth non-display area (NDA4).

[0087] The data driving circuit (DDC) may be formed in the form of an integrated circuit chip. In one embodiment, the data driving circuit (DDC) may be directly disposed on the fourth non-display area (NDA4) of the substrate (100) as illustrated in FIG. 3 in a COG (Chip On Glass) or COP (Chip On Plastic) manner. In another embodiment, the display device (1) may further include a flexible circuit board (not shown) electrically connected through a terminal portion (not shown) disposed on the fourth non-display area (NDA4) of the substrate (100), and the data driving circuit (DDC) may be disposed on the flexible circuit board.

[0088] The elongation rate of the non-display area (NDA) may be equal to or less than the elongation rate of the display area (DA). In one embodiment, the elongation rates of the non-display areas (NDAs) may be different for each area. For example, the first non-display area (NDA1), the second non-display area (NDA2), and the third non-display area (NDA3) may have substantially the same elongation rates, but the elongation rate of the fourth non-display area (NDA4) may be less than the elongation rates of each of the first non-display area (NDA1), the second non-display area (NDA2), and the third non-display area (NDA3).

[0089] FIG. 4A is an enlarged plan view of part A of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0090] Referring to FIG. 4a, the display device (1) may include first island portions (11) spaced apart from each other along a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a display area (DA), and first bridge portions (12) connecting adjacent first island portions (11).

[0091] Each first island portion (11) may be connected to a plurality of first bridge portions (12). For example, each first island portion (11) may be connected to four first bridge portions (12). Two first bridge portions (12) may be arranged on both sides of the first island portion (11) along a first direction (e.g., x direction or -x direction), and the remaining two first bridge portions (12) may be arranged on both sides of the first island portion (11) along a second direction (e.g., y direction or -y direction). In one embodiment, four first bridge portions (12) may be connected to four sides of the first island portion (11), respectively. Each of the four first bridge portions (12) may be adjacent to each corner of the first island portion (11).

[0092] The first bridge portions (12) may be spaced apart from each other by first openings (CS1) positioned between the first bridge portions (12). In one embodiment, the first openings (CS1) having an approximately H shape and the first openings (CS1) having an approximately I shape obtained by rotating the aforementioned H shape by 90 degrees may be alternately and repeatedly arranged along the first direction (e.g., the x direction or the -x direction) and the second direction (e.g., the y direction or the -y direction). Both ends of each first bridge portion (12) are connected to each of the adjacent first island portions (11), and one side of each first bridge portion (12) may be spaced apart from one side of the adjacent first island portion (11) and / or one side of another first bridge portion (12) by the first openings (CS1).

[0093] The display device (1) may include second island portions (21) spaced apart from each other in a non-display area, for example, the first non-display area (NDA1) illustrated in FIG. 4a, and second bridge portions (22) connecting adjacent second island portions (21).

[0094] Each second island portion (21) may extend along a first direction (e.g., the x direction or the -x direction). The second island portions (21) may be spaced apart from each other along a second direction (e.g., the y direction or the -y direction) intersecting the first direction (e.g., the x direction or the -x direction). Each second island portion (21) may include drivers of a gate drive circuit (GDC, FIG. 2) described with reference to FIG. 3.

[0095] The second bridge portion (22) may have a serpentine shape. The length of the second bridge portion (22) may be greater than the shortest distance between adjacent second island portions (21) along the second direction (e.g., the y direction or the -y direction). In one embodiment, the second bridge portion (22) may have a shape of approximately omega (Ω) that is convex toward the first direction (e.g., the x direction or the -x direction). The second bridge portions (22) may be arranged between adjacent second island portions (21), but may be spaced apart from each other.

[0096] The second bridge portions (22) between adjacent second island portions (21) can be spaced apart from each other by the second opening portions (CS2). Between the adjacent second island portions (21), the second opening portions (CS2) and the second bridge portions (22) can be alternately arranged along the first direction (e.g., the x direction or the -x direction). The second opening portions (CS2) can have the same shape. Both ends of each second bridge portion (22) are connected to the adjacent second island portions (21), but one side of each second bridge portion (22) can be spaced apart from the side of the adjacent second island portion (21) and / or one side of another second bridge portion (22) by the second opening portions (CS2).

[0097] Any one of the second island portions (21) arranged in the first non-display area (NDA1) may correspond to the first island portions (11) of a plurality of rows arranged in the display area (DA). For example, any one of the second island portions (21) arranged in the first non-display area (NDA1) may correspond to the first island portions (11) arranged in the (i)th row and the first island portions (11) arranged in the (i+1)th row in the display area (DA) (wherein, i is a positive number greater than 0). Although FIG. 4A illustrates that one second island portion (21) corresponds to two rows of the first island portions (11), the present invention is not limited thereto. In another embodiment, any one of the second island units (21) arranged in the first non-display area (NDA1) may correspond to n rows of the first island units (11) arranged in the display area (DA) (where n is a positive integer greater than or equal to 3).

[0098] A non-display area, for example, a first non-display area (NDA1), may include a first sub-non-display area (SNDA1) in which the aforementioned second island portions (21) and second bridge portions (22) are arranged, and a second sub-non-display area (SNDA2) between the first sub-non-display area (SNDA1) and the display area (DA). Third bridge portions (23) may be arranged in the second sub-non-display area (SNDA2) to connect the display area (DA) and the first sub-non-display area (SNDA1). One end of the third bridge portion (23) may be connected to the second island portion (21) and / or the second bridge portion (22), and the other end of the third bridge portion (23) may be connected to the first island portion (11) and / or the first bridge portion (12).

[0099] The third bridge portion (23) may have a serpentine shape. In one embodiment, the shape of the third bridge portion (23) may be different from the shapes of each of the first bridge portion (12) and the second bridge portion (22). In one embodiment, as illustrated in FIG. 4A, the third bridge portion (23) may have a shape of approximately omega (Ω) that is convex in the second direction (e.g., the y direction or the -y direction). Among adjacent third bridge portions (23) arranged along the second direction (e.g., the y direction or the -y direction), one may have a structure that is symmetrical to each other, such as being convex in the y direction and the other being convex in the -y direction. Between the third bridge portions (23), a structure may be formed in which third openings (CS3) and fourth openings (CS4) of different shapes are repeated. The width of the third bridge portion (23) may be different from the width of the first bridge portion (12) and the width of the second bridge portion (22). In one embodiment, the width of the third bridge portion (23) may be greater than the width of the first bridge portion (12) and less than the width of the second bridge portion (22).

[0100] FIG. 4a shows that the second island portion (21) and the second bridge portion (22) of the non-display area, for example, the first non-display area (NDA1), have different shapes from the first island portion (11) and the first bridge portion (12) of the display area (DA), respectively. In another embodiment of the present invention, the second island portion (21) and the second bridge portion (22) of the non-display area may have the same shapes as the first island portion (11) and the first bridge portion (12) of the display area (DA), respectively.

[0101] FIG. 4b is an enlarged plan view of part A of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0102] Referring to Fig. 4b, the display device (1) includes first island portions (11) that are spaced apart from each other in the display area (DA) and first bridge portions (12) that connect adjacent first island portions (11) that are spaced apart from each other by a first opening (CS1). The structure of the display area (DA) of Fig. 4b may be the same as the structure of the display area (DA) described above with reference to Fig. 4a.

[0103] The display device (1) may include second island portions (21) and second bridge portions (22) arranged in a non-display area, for example, a first non-display area (NDA1). In one embodiment, the second island portions (21) and the second bridge portions (22) may have substantially the same shape as the first island portions (11) and the first bridge portion (12), respectively.

[0104] The second island portions (21) can be spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a non-display area, for example, a first non-display area (NDA1). Each of the second bridge portions (22) can connect adjacent second island portions (21). The second bridge portions (22) can be spaced apart from each other by a second opening (CS2) located between the second bridge portions (22).

[0105] The second opening (CS2) may have substantially the same shape as the first opening (CS1). For example, the second opening (CS2) having an approximately H shape and the second opening (CS2) having an approximately I shape may be alternately and repeatedly arranged in a non-display area, for example, the first non-display area (NDA1). The two ends of each second bridge portion (22) are connected to each of the adjacent second island portions (21), and one side of each second bridge portion (2) may be spaced apart from one side of the adjacent second island portion (21) and / or one side of another second bridge portion (22) by the second opening (CS2).

[0106] Each second island section (21) can be connected to four second bridge sections (22). Each second island section (21) can include drivers of the gate drive circuit (GDC, FIG. 2) described with reference to FIG. 3.

[0107] The second island portions (21) of any one row arranged in the first non-display area (NDA1) may correspond to the first island portions (11) of any one row arranged in the display area (DA). For example, the second island portions (21) arranged in the (i)th row along the first direction (e.g., the x direction or the -x direction) in the first non-display area (NDA1) may correspond to the first island portions (11) arranged in the same row, e.g., the (i)th row, in the display area (DA) (wherein, i is a positive number greater than 0).

[0108] The display device (1) may include third bridge units (23) arranged in a second sub-non-display area (SNDA2) for connecting a display area (DA) and a first sub-non-display area (SNDA1). The non-display area, for example, the first non-display area (NDA1), may include a first sub-non-display area (SNDA1) in which second island units (21) and second bridge units (22) are arranged, and a second sub-non-display area (SNDA2) including third bridge units (23) and positioned between the first sub-non-display area (SNDA1) and the display area (DA). The third bridge unit (23) may be substantially the same as the first bridge unit (12) and the second bridge unit (22). For example, the width of the third bridge unit (23) may be the same as the width of the first bridge unit (12) and the width of the second bridge unit (22).

[0109] FIG. 4c is an enlarged plan view of part A of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0110] Referring to FIG. 4c, the display device (1) may include first island portions (11) spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in the display area (DA) and first bridge portions (12) connecting adjacent first island portions (11).

[0111] The first bridge portions (12) may be arranged to be spaced apart from each other by a first opening (CS1) located between the first bridge portions (12). The first bridge portion (12) may have a winding shape. For example, as illustrated in FIG. 4c, the first bridge portion (12) may have a shape roughly similar to the letter 'S'.

[0112] Each first island portion (11) may be connected to a plurality of first bridge portions (12). For example, each first island portion (11) may be connected to four first bridge portions (12). Two first bridge portions (12) may be arranged on both sides of the first island portion (11) along a first direction (e.g., x direction or -x direction), and the remaining two first bridge portions (12) may be arranged on both sides of the first island portion (11) along a second direction (e.g., y direction or -y direction). The four first bridge portions (12) may be connected to four sides of the first island portion (11), respectively. Each of the four first bridge portions (12) may be adjacent to each corner of the first island portion (11).

[0113] The display device (1) may include second island portions (21) spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a non-display area, for example, a first non-display area (NDA1) illustrated in FIG. 4c, and second bridge portions (22) connecting adjacent second island portions (21).

[0114] The second bridge portions (22) may be spaced apart from each other by a second opening (CS2) positioned between the second bridge portions (22). The second bridge portion (22) may have a winding shape. For example, as illustrated in FIG. 4C, the second bridge portion (22) may have a shape roughly similar to the letter S. The size and / or width of the second bridge portion (22) may be different from the size and / or width of the first bridge portion (12). For example, the size and / or width of the second bridge portion (22) may be larger than the size and / or width of the first bridge portion (12). The radius of curvature of the rounded portion of the second bridge portion (22) may be different from the radius of curvature of the rounded portion of the first bridge portion (12). For example, the radius of curvature of the rounded portion of the second bridge portion (22) may be greater than the radius of curvature of the rounded portion of the first bridge portion (12).

[0115] Each second island portion (21) can be connected to a plurality of second bridge portions (22). Each second island portion (21) can be connected to four second bridge portions (22). Two second bridge portions (22) can be arranged on both sides of the second island portion (21) along a first direction (e.g., x direction or -x direction), and the remaining two second bridge portions (22) can be arranged on both sides of the second island portion (21) along a second direction (e.g., y direction or -y direction). In one embodiment, four second bridge portions (22) can be respectively connected to four sides of the second island portion (21). Each second bridge portion (22) can be connected to a central portion of each side of the second island portion (21).

[0116] The second island portions (21) of one row arranged in the first non-display area (NDA1) may correspond to the first island portions (11) of a plurality of rows arranged in the display area (DA). For example, the second island portions (21) of one row arranged in the first non-display area (NDA1) may correspond to the first island portions (11) arranged in the (i)-th row of the display area (DA) and the first island portions (11) arranged in the (i+1)-th row (here, i is a positive integer greater than 0). In another embodiment, the second island portions (21) of one row may correspond to n rows of the first island portions (11) (here, n is a positive integer greater than 3).

[0117] A non-display area, for example, a first non-display area (NDA1), may include a first sub-non-display area (SNDA1) in which the aforementioned second island portions (21) and second bridge portions (22) are arranged, and a second sub-non-display area (SNDA2) between the first sub-non-display area (SNDA1) and the display area (DA). Third bridge portions (23) may be arranged in the second sub-non-display area (SNDA2) to connect the display area (DA) and the first sub-non-display area (SNDA1). One end of the third bridge portion (23) may be connected to the second island portion (21), and the other end of the third bridge portion (23) may be connected to the first island portion (11). For example, one end of the third bridge portion (23) may be connected to the central portion of one side of the second island portion (21), and the other end of the third bridge portion (23) may be connected to the central portion of one side of the first island portion (11).

[0118] The third bridge portion (23) may have a serpentine shape. In one embodiment, the shape of the third bridge portion (23) may be different from the shapes of each of the first bridge portion (12) and the second bridge portion (22). The width of the third bridge portion (23) may be different from the width of the first bridge portion (12) and the width of the second bridge portion (22). The width of the third bridge portion (23) may be larger than the width of the first bridge portion (12) and smaller than the width of the second bridge portion (22). Third openings (CS3) and fourth openings (CS4) of different shapes may be alternately arranged between the third bridge portions (23) in the second direction (e.g., the y direction or the -y direction).

[0119] FIG. 4d is an enlarged plan view of part A of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0120] Referring to FIG. 4d, the display device (1) may include first island portions (11) spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in the display area (DA) and first bridge portions (12) connecting adjacent first island portions (11).

[0121] The first bridge portions (12) may be arranged to be spaced apart from each other by a first opening (CS1) located between the first bridge portions (12). The first bridge portion (12) may have a winding shape. For example, as illustrated in FIG. 4d, the first bridge portion (12) may have a shape roughly similar to the letter 'S'.

[0122] Each first island portion (11) may be connected to a plurality of first bridge portions (12). For example, each first island portion (11) may be connected to four first bridge portions (12). Two first bridge portions (12) may be arranged on both sides of the first island portion (11) along a first direction (e.g., x direction or -x direction), and the remaining two first bridge portions (12) may be arranged on both sides of the first island portion (11) along a second direction (e.g., y direction or -y direction). The four first bridge portions (12) may be connected to four sides of the first island portion (11), respectively. Each of the four first bridge portions (12) may be connected to a central portion of each side of the first island portion (11).

[0123] The display device (1) includes second island portions (21) spaced apart from each other in a first non-display area (NDA1) and second bridge portions (22) connecting adjacent second island portions (21) spaced apart from each other by a second opening (CS2). The structure of the first non-display area (NDA1) of FIG. 4d may be the same as the structure of the first non-display area (NDA1) described above with reference to FIG. 4c.

[0124] A non-display area, for example, a first non-display area (NDA1), may include a first sub-non-display area (SNDA1) in which the second island portions (21) and second bridge portions (22) described above are arranged, and a second sub-non-display area (SNDA2) between the first sub-non-display area (SNDA1) and the display area (DA). Third bridge portions (23) may be arranged in the second sub-non-display area (SNDA2) to connect the display area (DA) and the first sub-non-display area (SNDA1). The structure of the second sub-non-display area (SNDA2) of FIG. 4d may be the same as the structure of the second sub-non-display area (SNDA2) described above with reference to FIG. 4c.

[0125] FIG. 5 is a cross-sectional view schematically showing a first island portion and a first bridge portion arranged in a display area of ​​a display device according to one embodiment of the present invention.

[0126] Referring to FIG. 5, the first island portion (11) and the first bridge portion (12) arranged in the display area (DA) may be spaced apart from each other with the first opening (CS1) therebetween. The first island portion (11) includes light-emitting elements (LEDs) and circuits electrically connected thereto for driving the light-emitting elements, such as pixel circuits (PC), and the first bridge portion (12) may include wiring (WL) electrically connected to pixel circuits (PC) arranged in each of the adjacent first island portions (11).

[0127] Looking at the first island portion (11), a buffer layer (111) including an inorganic insulator is disposed on a substrate (100), and a pixel circuit (PC) may be disposed on the buffer layer (111). An insulating layer (IL) including an inorganic insulator and / or an organic insulator may be disposed between the pixel circuit (PC) and the light-emitting element (LED). The light-emitting element (LED) is disposed on the insulating layer (IL) and may be electrically connected to the corresponding pixel circuit (PC). The light-emitting elements (LED) may emit light of different colors or the same color. In one embodiment, the light-emitting elements (LED) may emit red, green, and blue light, respectively. In some embodiments, the light-emitting elements (LED) may emit white light. In another embodiment, the light-emitting elements (LED) may emit red, green, blue, and white light, respectively.

[0128] The substrate (100) may include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. In one embodiment, the substrate (100) may be a single layer including the aforementioned polymer resin. In another embodiment, the substrate (100) may be a multilayer structure including a base layer including the aforementioned polymer resin and a barrier layer including an inorganic insulating material. The substrate (100) including the polymer resin may have flexible, rollable, and bendable properties.

[0129] In one embodiment, FIG. 5 illustrates three pixel circuits (PC) arranged in each first island portion (11) and three light-emitting elements (LEDs) connected to each pixel circuit (PC), but the present invention is not limited thereto. In another embodiment, the number of pixel circuits (PCs) and light-emitting elements (LEDs) arranged in the first island portion (11) may be one, two, four or more.

[0130] The encapsulation layer (300) may be disposed on a light-emitting element (LED) and may protect the light-emitting element (LED) from external force and / or moisture permeation. The encapsulation layer (300) may include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer (300) may include a structure in which an inorganic encapsulation layer including an inorganic insulating material, an organic encapsulation layer including an organic insulating material, and an inorganic encapsulation layer including an inorganic insulating material are laminated. In other embodiments, the encapsulation layer (300) may include an organic material such as a resin. In some embodiments, the encapsulation layer (300) may include urethane epoxy acrylate. The encapsulation layer (300) may include a photosensitive material, for example, a material such as a photoresist.

[0131] Looking at the first bridge portion (12), an insulating layer (IL) including an organic insulating material may be placed on the substrate (100). When the display device (1) is stretched, the first bridge portion (12), which is relatively subject to a large amount of deformation, may not have a layer including an inorganic insulating material that is prone to cracking, unlike the first island portion (11).

[0132] In one embodiment, the substrate (100) corresponding to the first bridge portion (12) may have the same laminated structure as the substrate (100) corresponding to the first island portion (11). In one embodiment, the substrate (100) corresponding to the first bridge portion (12) and the substrate (100) corresponding to the first island portion (11) may be polymer resin layers formed together in the same process. In another embodiment, the substrate (100) corresponding to the first bridge portion (12) may have a different laminated structure from the substrate (100) corresponding to the first island portion (11). In some embodiments, the substrate (100) corresponding to the first bridge portion (12) may have a multilayer structure including a base layer including a polymer resin and a barrier layer including an inorganic insulating material, and the substrate (100) corresponding to the first bridge portion (12) may have a structure of a polymer resin layer without a layer including an inorganic insulating material.

[0133] The wirings (WL) of the first bridge portion (12) may be signal lines (e.g., gate lines, data lines, etc.) for providing electrical signals to transistors included in the pixel circuit (PC) of the first island portion (11), as described above, or voltage lines (e.g., driving voltage lines, initialization voltage lines, etc.) for providing voltage. A sealing layer (300) may also be arranged in the first bridge portion (12). In another embodiment, the sealing layer (300) may not be present in the first bridge portion (12).

[0134] Referring to FIGS. 4A to 4D and FIG. 5, the substrate (100) corresponding to the first island portion (11) and the substrate (100) corresponding to the first bridge portion (12) may be connected to each other. In other words, the plan views illustrated in FIGS. 4A to 4D may be substantially the same as the plan view of the substrate (100) of FIG. 5. In other words, the substrate (100) may include an area corresponding to the first island portion (11), an area corresponding to the first bridge portion (12), and an opening (100OP1) having the same shape as the first opening (CS1).

[0135] Similarly, the sealing layer (300) corresponding to the first island portion (11) and the sealing layer (300) corresponding to the first bridge portion (12) may be connected to each other. For example, the plan views illustrated in FIGS. 4A to 4D above may be substantially identical to the plan views of the sealing layer (300). In other words, the sealing layer (300) may include an area corresponding to the first island portion (11), an area corresponding to the first bridge portion (12), and an opening (300OP1) having the same shape as the first opening (CS1).

[0136] The circuit-light-emitting element layer (200) between the substrate (100) and the encapsulating layer (300) may include a buffer layer (111), a pixel circuit (PC), a wiring (WL), an insulating layer (IL), and a light-emitting element (LED). Similar to the substrate (100), the plan views previously illustrated in FIGS. 4A to 4D may be substantially identical to the plan views of the circuit-light-emitting element layer (200). In other words, the circuit-light-emitting element layer (200) may include an opening (200OP1) having the same shape as the first opening (CS1).

[0137] Figure 6 is an equivalent circuit diagram of a pixel of a display device according to one embodiment of the present invention.

[0138] Referring to FIG. 6, a pixel (PX, FIG. 3) may include a light-emitting element (LED) and a pixel circuit (PC) connected to the light-emitting element (LED). The pixel circuit (PC) may include a first capacitor (Cst), a second capacitor (Cpr), a third capacitor (Ca), and first to third transistors (T1, T2, T3). The first transistor (T1) may be a driving transistor that outputs a driving current corresponding to a data signal, and the second transistor (T2) and the third transistor (T3) may be switching transistors that transmit a signal. The first electrode and the second electrode of each of the first to third transistors (T1, T2, T3) may be a source or a drain depending on the voltage of the first electrode and the second electrode. For example, depending on the voltage of the first electrode and the second electrode, the first electrode may be a source and the second electrode may be a drain, or the first electrode may be a drain and the second electrode may be a source. Hereinafter, a node where the gate of the first transistor (T1) and the first capacitor electrode of the first capacitor (Cst) are connected may be defined as a first node (N1), a node where the first electrode of the second transistor (T2) and the third capacitor electrode of the second capacitor (Cpr) are connected may be defined as a second node (N2), and a node where the second electrode of the first transistor (T1) and the first electrode of the third transistor (T3) are connected may be defined as a third node (N3).

[0139] A pixel (PX) can be connected to a first gate line (GWL) that transmits a first gate signal (GW), a second gate line (GCL) that transmits a second gate signal (GC), and a data line (DL) that transmits a data signal (DATA). In addition, the pixel (PX) can be connected to a first driving voltage line (VDDL) that transmits a first driving voltage (ELVDD), a second driving voltage line (VSSL) that transmits a second driving voltage (ELVSS), and an initialization voltage line (VIL) that transmits an initialization voltage (Vint).

[0140] A first transistor (T1) may be connected between a first driving voltage line (VDDL) and a light-emitting element (LED). A gate of the first transistor (T1) may be connected to a first node (N1). Accordingly, the gate of the first transistor (T1) may be connected to a first capacitor electrode of a first capacitor (Cst) and a second electrode of a second transistor (T2). The first electrode of the first transistor (T1) may be connected to the first driving voltage line (VDDL). A second electrode of the first transistor (T1) may be connected to a third node (N3). Accordingly, the second electrode of the first transistor (T1) may be connected to a first electrode of a third transistor (T3), a fifth capacitor electrode of a third capacitor (Ca), and a first electrode of the light-emitting element (LED). The first transistor (T1) can receive a data signal (DATA) according to the switching operations of the second transistor (T2) and the third transistor (T3) and control the amount of driving current flowing to the light-emitting element (LED).

[0141] A second transistor (T2) may be connected between a first node (N1) and a second node (N2). A gate of the second transistor (T2) may be connected to a first gate line (GWL). A first electrode of the second transistor (T2) may be connected to a second node (N2) and may be connected to a data line (DL) through a second capacitor (Cpr). A second electrode of the second transistor (T2) may be connected to a first node (N1) and may be connected to a first capacitor electrode of the first capacitor (Cst) and a gate of the first transistor (T1). The second transistor (T2) may be turned on by a first gate signal (GW) transmitted to the first gate line (GWL) to electrically connect the second capacitor (Cpr) and the first capacitor (Cst), and may transmit a data signal (DATA) transmitted to the data line (DL) to the gate of the first transistor (T1).

[0142] A third transistor (T3) may be connected between a second node (N2) and a third node (N3). The third transistor (T3) may include a gate connected to a second gate line (GCL). A first electrode of the third transistor (T3) may be connected to a third node (N3). Accordingly, the first electrode of the third transistor (T3) may be connected to a second electrode of the first transistor (T1), a first electrode of a light-emitting element (LED), and a fifth capacitor electrode of a third capacitor (Ca). A second electrode of the third transistor (T3) may be connected to a second node (N2). Accordingly, the second electrode of the third transistor (T3) may be connected to a third capacitor electrode of a second capacitor (Cpr), and a first electrode of the second transistor (T2). By turning on the second gate signal (GC) transmitted to the second gate line (GCL) of the third transistor (T3), the threshold voltage of the first transistor (T1) can be compensated by diode-connecting the first transistor (T1) together with the second transistor (T2).

[0143] A first capacitor (Cst) may be connected between a first node (N1) and an initialization voltage line (VIL). The first capacitor (Cst) may include a first capacitor electrode and a second capacitor electrode. The first capacitor electrode of the first capacitor (Cst) may be connected to the first node (N1), and may be connected to a gate of a first transistor (T1) and a second electrode of a second transistor (T2). The second capacitor electrode of the first capacitor (Cst) may be connected to an initialization voltage line (VIL). The first capacitor (Cst) may be a storage capacitor and may store a threshold voltage of the first transistor (T1) and a voltage corresponding to a data signal (DATA). The first capacitor (Cst) may change a voltage of the first node (N1) in response to a change in a voltage of the initialization voltage line (VIL).

[0144] A second capacitor (Cpr) may be connected between a second node (N2) and a data line (DL). The second capacitor (Cpr) may include a third capacitor electrode and a fourth capacitor electrode. The third capacitor electrode of the second capacitor (Cpr) may be connected to the second node (N2), a first electrode of the second transistor (T2), and a second electrode of the third transistor (T3). The fourth capacitor electrode of the second capacitor (Cpr) may be connected to the data line (DL). The second capacitor (Cst) may change the voltage of the second node (N2) in response to a change in the voltage of the data line (DL).

[0145] A third capacitor (Ca) may be connected between a first electrode of a light-emitting element (LED) and an initialization voltage line (VIL). The third capacitor (Ca) may include a fifth capacitor electrode and a sixth capacitor electrode. The fifth capacitor electrode of the third capacitor (Ca) may be connected to a third node (N3), and may be connected to a second electrode of the first transistor (T1), a first electrode of the third transistor (T3), and a first electrode of the light-emitting element (LED). The sixth capacitor electrode of the third capacitor (Ca) may be connected to an initialization voltage line (VIL). The third capacitor (Ca) stores and maintains a voltage corresponding to a voltage difference between the first electrode of the light-emitting element (LED) and the initialization voltage line (VIL), thereby improving black gradation or low gradation expression.

[0146] A light emitting element (LED) may be connected between a first transistor (T1) and a second driving voltage line (VSSL). The light emitting element (LED) may include a first electrode (pixel electrode, anode) and a second electrode (counter electrode, a cathode). The first electrode of the light emitting element (LED) may be connected to a third node (N3), and may be connected to a second electrode of the first transistor (T1), a first electrode of the third transistor (T3), and a fifth capacitor electrode of the third capacitor (Ca). The second electrode of the light emitting element (LED) may be connected to a second driving voltage line (VSSL) that provides a second driving voltage (ELVSS). The light emitting element (LED) may emit light with a brightness corresponding to a driving current supplied from the first transistor (T1).

[0147] A pixel (PX) can perform initialization, threshold voltage compensation, data writing, and light emission operations during one frame. Initialization of a light emitting element (LED) may be further performed before light emission. In the initialization section and the threshold voltage compensation section, the second transistor (T2) and the third transistor (T3) operate together to initialize the voltage of the first electrode of the light emitting element (LED) and the voltage of the gate of the first transistor (T1), and compensate for the threshold voltage of the first capacitor (Cst). For example, in the threshold voltage compensation section, the voltage of the first node (N1) may have a value of 'ELVDD_H - |VTH|'. Here, 'VTH' may be a threshold voltage, and 'EVLDD_H' may be a high level value of the first driving voltage (ELVDD).

[0148] In the data writing section, as a plurality of pixels are scanned along a row, a low-level first gate signal (GW) may be sequentially applied to the second transistor (T2) of each pixel circuit (PC). In addition, in the data writing section, a data signal (DATA) may be sequentially applied to the data line (DL) of each pixel circuit (PC). At this time, in the data writing section, the second transistor (T2) may be turned on, and the second transistor (T2) may transfer the input data voltage through the second capacitor (Cpr) to the gate of the first transistor (T1). At this time, the first capacitor (Cst) may serve to store and maintain the data voltage transferred to the gate of the first transistor (T1) through the second transistor (T2).

[0149] Meanwhile, as described above, the third capacitor electrode of the second capacitor (Cpr) may be connected to the second node (N2), and the fourth capacitor electrode may be connected to the data line (DL). Accordingly, as the voltage of the data line (DL) changes, the voltage of the second node (N2) also changes, and the second transistor (T2) may be turned on to store the data voltage of the second node (N2) in the first capacitor (Cst). At this time, since the amount of change in the voltage transmitted to the second node (N2) is transmitted through the second capacitor (Cpr), it may be transmitted at a reduced amount compared to the amount of change in the voltage applied to the data line (DL). For example, in the data write section, the voltage of the first node (N1) may have a value of 'EVLDD_L - |VTH| + aХVdata' due to charge sharing between the first node (N1) and the second node (N2) and coupling through the second capacitor (Cpr). Here, 'ELVDD_L' is a low level value of the first driving voltage (ELVDD), and 'a' may be 'CprF / CstF+CprF'. 'CstF' may be the electrostatic capacitance of the first capacitor (Cst), and 'CprF' may be the electrostatic capacitance of the second capacitor (Cpr).

[0150] In the light-emitting section, the first transistor (T1) is turned on, the second transistor (T2) and the third transistor (T3) are turned off, so that the light-emitting element (LED) can emit light with the current flowing through the first transistor (T1). At this time, the light-emitting element (LED) can emit light while changing the initialization voltage (Vint) from a low voltage to a high voltage when the data voltage is stored in the first capacitor electrode of the first capacitor (cst) of all pixels. In other words, after the data writing section is completed for all pixels, the light-emitting section can be entered simultaneously for all pixels.

[0151] FIG. 7a is a cross-sectional view schematically showing a light-emitting element of a display device according to one embodiment of the present invention.

[0152] Referring to FIG. 7A, a light-emitting element according to one embodiment of the present invention may include an organic light-emitting diode (220) including an organic material. The organic light-emitting diode (220) may include a first electrode (221) disposed on an insulating layer, a second electrode (225) facing the first electrode (221), and a light-emitting layer (223) interposed between the first electrode (221) and the second electrode (225). A first functional layer (222) may be disposed between the first electrode (221) and the light-emitting layer (223), and a second functional layer (224) may be disposed between the light-emitting layer (223) and the second electrode (225).

[0153] The edge of the first electrode (221) may be covered with a bank layer (BKL) including an insulating material. The bank layer (BKL) may include an opening (B-OP) overlapping the central portion of the first electrode (221).

[0154] The first electrode (221) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first electrode (221) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the first electrode (221) may further include a layer formed of ITO, IZO, ZnO, AZO, or In2O3 on / under the aforementioned reflective layer.

[0155] The light-emitting layer (223) may include a polymer or low-molecular organic material that emits light of a predetermined color. The first functional layer (222) may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer (224) may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0156] The second electrode (225) may be formed of a conductive material having a low work function. For example, the second electrode (225) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the second electrode (225) may further include a layer such as ITO, IZO, ZnO, AZO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0157] FIG. 7b is a cross-sectional view schematically showing a light-emitting element of a display device according to one embodiment of the present invention.

[0158] Referring to FIG. 7B, in one embodiment of the present invention, a light-emitting element may include an inorganic light-emitting diode (230) including an inorganic material. The inorganic light-emitting diode (230) may include a first semiconductor layer (231), a second semiconductor layer (232), an intermediate layer (233) between the first semiconductor layer (231) and the second semiconductor layer (232), a first electrode (235) electrically connected to the first semiconductor layer (231), and a second electrode (238) electrically connected to the second semiconductor layer (232). The first electrode (235) and the second electrode (238) of the inorganic light-emitting diode (230) may be electrically connected to a first electrode pad (241) and a second electrode pad (242), respectively, which are disposed on the same layer.

[0159] In some embodiments, the first semiconductor layer (231) may include a p-type semiconductor layer. The p-type semiconductor layer may be selected from semiconductor materials having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with a p-type dopant such as Mg, Zn, Ca, Sr, or Ba.

[0160] The second semiconductor layer (232) may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be selected from semiconductor materials having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with an n-type dopant such as Si, Ge, or Sn.

[0161] The intermediate layer (233) is a region where electrons and holes recombine, and as the electrons and holes recombine, they transition to a lower energy level and can generate light having a corresponding wavelength. The intermediate layer (233) can be formed by including, for example, a semiconductor material having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and can be formed as a single quantum well structure or a multi-quantum well structure (MQW). In addition, it may include a quantum wire structure or a quantum dot structure.

[0162] Although Fig. 7b illustrates that the first semiconductor layer (231) includes a p-type semiconductor layer and the second semiconductor layer (232) includes an n-type semiconductor layer, the present invention is not limited thereto. In another embodiment, the first semiconductor layer (231) may include an n-type semiconductor layer and the second semiconductor layer (232) may include a p-type semiconductor layer.

[0163] Fig. 8 is a schematic diagram illustrating components of pixel circuits arranged in a first island portion of a display device according to one embodiment of the present invention. Figs. 9a to 9g are layout diagrams schematically illustrating, layer by layer, components of the pixel circuits illustrated in Fig. 8.

[0164] As described with reference to FIGS. 4A to 4D, the display device (1) may include a first island portion (11) arranged in a display area (DA) and a plurality of second bridge portions (12) connected to the first island portion (11). The first island portion (11) may include a plurality of pixels, and the first bridge portion (12) may include wires electrically connected to the pixels.

[0165] A first pixel, a second pixel, and a third pixel that emit light of different colors may be arranged in the first island portion (11). The first pixel may include a first light-emitting element and a first pixel circuit (PC1) connected to the first light-emitting element, the second pixel may include a second light-emitting element and a second pixel circuit (PC2) connected to the second light-emitting element, and the third pixel may include a third light-emitting element and a third pixel circuit (PC3) connected to the third light-emitting element. In one embodiment, the first light-emitting element may emit red light, the second light-emitting element may emit green light, and the third light-emitting element may emit blue light.

[0166] A first pixel circuit (PC1) may be arranged in a first circuit area (PCA1), a second pixel circuit (PC2) may be arranged in a second circuit area (PCA2), and a third pixel circuit (PC3) may be arranged in a third circuit area (PCA3). The first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) may be arranged side by side along a first direction (e.g., the x direction).

[0167] Conductive lines extending in the first direction may be arranged on horizontal bridge parts (12a) connected to adjacent first island parts (11) along a first direction (e.g., x direction), and conductive lines extending in the second direction may be arranged on vertical bridge parts (12b) connected to adjacent first island parts (11) along a second direction (e.g., y direction).

[0168] Hereinafter, the conductive lines extending in the first direction and arranged in the first island portion (11) and / or the horizontal bridge portions (12a) may also be referred to as horizontal conductive lines, horizontal voltage lines, or horizontal connection lines. Similarly, the conductive lines extending in the second direction and arranged in the first island portion (11) and / or the vertical bridge portions (12b) may also be referred to as vertical conductive lines, vertical voltage lines, or vertical connection lines. Here, the first direction has been described as the horizontal direction and the second direction as the vertical direction, but the embodiment of the present invention is not limited thereto, and one of different directions that are orthogonal to each other depending on the viewing direction of the display device or the display panel may be referred to as the horizontal direction, and the other may be referred to as the vertical direction. For example, the conductive lines extending and arranged in the first direction may be referred to as vertical conductive lines, and the conductive lines extending and arranged in the second direction may be referred to as horizontal conductive lines.

[0169] The first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may have substantially the same or similar structures. Hereinafter, the respective configurations will be described with a focus on the first pixel circuit (PC1) arranged in the first circuit area (PCA1), and descriptions of the same or similar configurations arranged in the second circuit area (PCA2) and the third circuit area (PCA3) will be omitted.

[0170] The first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may each include the first to third transistors (T1, T2, T3), the first capacitor (Cst), the second capacitor (Cpr), and the third capacitor (Ca) described in FIG. 6.

[0171] The first transistor (T1) can overlap with the first capacitor (Cst). The second transistor (T2), the third transistor (T3), the second capacitor (Cpr), and the third capacitor (Ca) can be arranged above and / or below the first transistor (T1) and / or the first capacitor (Cst) on a plane. For example, as shown in FIG. 8, the second capacitor (Cpr), the second transistor (T2), and the third transistor (T3) can be arranged below the first transistor (T1) on a plane (e.g., in the -y direction). The third capacitor (Ca) can be arranged above the first transistor (T1) on a plane (e.g., in the +y direction).

[0172] The first island portion (11) may include a semiconductor layer (1100), a first conductive layer (1200), a second conductive layer (1300), a third conductive layer (1400), a fourth conductive layer (1500), a fifth conductive layer (1600), and a sixth conductive layer (1700) that are sequentially laminated on a substrate (100, FIG. 5). The semiconductor layer (1100), the first conductive layer (1200), the second conductive layer (1300), the third conductive layer (1400), the fourth conductive layer (1500), the fifth conductive layer (1600), and the sixth conductive layer (1700) may form signal lines and voltage lines connected to a pixel circuit (PC, FIG. 6), and transistors and capacitors included in the pixel circuit (PC, FIG. 6).

[0173] Referring to FIG. 9a, a semiconductor layer (1100) may be disposed on the first island portion (11). A buffer layer (111) may be disposed between the substrate (100, FIG. 5) and the semiconductor layer (1100). The semiconductor layer (1100) may include a silicon semiconductor. For example, the semiconductor layer (1100) may include amorphous silicon or polysilicon. The semiconductor layer (1100) may include a channel region, a source region on both sides of the channel region, and a drain region of each of the first to third transistors (T1, T2, T3). The source region or the drain region may be interpreted as a source electrode or a drain electrode of the transistor, depending on the case.

[0174] The semiconductor layer (1100) may include a first semiconductor pattern (1101). The first semiconductor pattern (1101) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The first semiconductor pattern (1101) may include a first semiconductor layer (A1) of the first transistor (T1), a second semiconductor layer (A2) of the second transistor (T2), and a third semiconductor layer (A3) of the third transistor (T3). The first semiconductor layer (A1), the second semiconductor layer (A2), and the third semiconductor layer (A3) may be integrally connected. For example, the first semiconductor pattern (1101) may include a source region (S1) and a drain region (D1) of a first transistor (T1), a source region (S2) and a drain region (D2) of a second transistor (T2), and a source region (S3) and a drain region (D3) of a third transistor (T3), as shown in FIG. 8.

[0175] Referring to FIG. 9b, a first conductive layer (1200) may be disposed on a semiconductor layer (1100). A gate insulating layer (113, FIG. 13) may be interposed between the semiconductor layer (1100) and the first conductive layer (1200). The first conductive layer (1200) may include a first conductive pattern (1201), a second conductive pattern (1202), a third conductive pattern (1203), a fourth conductive pattern (1204), and a fifth conductive pattern (1205). The first conductive pattern (1201), the second conductive pattern (1202), the third conductive pattern (1203), the fourth conductive pattern (1204), and the fifth conductive pattern (1205) may be disposed in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3).

[0176] The first conductive pattern (1201), the second conductive pattern (1202), the third conductive pattern (1203), the fourth conductive pattern (1204), and the fifth conductive pattern (1205) may include the same material. The first conductive pattern (1201), the second conductive pattern (1202), the third conductive pattern (1203), the fourth conductive pattern (1204), and the fifth conductive pattern (1205) may each include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0177] The first conductive layer (1200) may include a first gate electrode (G1), a second gate electrode (G2), and a third gate electrode (G3) that overlap the first semiconductor layer (A1), the second semiconductor layer (A2), and the third semiconductor layer (A3) of the semiconductor layer (1100), respectively.

[0178] The second conductive pattern (1202) is arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3), and may have an isolated shape. The second conductive pattern (1202) may include the first gate electrode (G1) of the first transistor (T1). The first semiconductor layer (A1) may include a channel area overlapping the second conductive pattern (1202), which is the first gate electrode (G1), and a source area and a drain area arranged on both sides of the aforementioned channel area. In one embodiment, the second conductive pattern (1202) may include the first capacitor electrode (CE1) of the first capacitor (Cst). In other words, the second conductive pattern (1202) may be the first gate electrode (G1) and / or the first capacitor electrode (CE1) of the first capacitor (Cst).

[0179] The third conductive pattern (1203) is arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3), and may have an isolated shape. The third conductive pattern (1203) may include a third gate electrode (G3) of the third transistor (T3). The third semiconductor layer (A3) may include a channel area overlapping the third conductive pattern (1203), which is the third gate electrode (G3), and a source area and a drain area arranged on both sides of the aforementioned channel area.

[0180] The fourth conductive pattern (1204) is arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3), and may have an isolated shape. The fourth conductive pattern (1204) may include the second gate electrode (G2) of the second transistor (T2). The second semiconductor layer (A2) may include a channel area overlapping the fourth conductive pattern (1204), which is the second gate electrode (G2), and a source area and a drain area arranged on both sides of the aforementioned channel area.

[0181] The first conductive pattern (1201) and the fifth conductive pattern (1205) are arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3), respectively, and may have an isolated shape. In one embodiment, the first conductive pattern (1201) may include the fifth capacitor electrode (CE5) of the third capacitor (Ca), and the fifth conductive pattern (1205) may include the third capacitor electrode (CE3) of the second capacitor (Cst). That is, the first capacitor electrode (CE1), which is the lower electrode of the first capacitor (Cst), the third capacitor electrode (CE3), which is the lower electrode of the second capacitor (Cpr), and the fifth capacitor electrode (CE5), which is the lower electrode of the third capacitor (Ca), may be arranged on the same layer.

[0182] Referring to FIG. 9c, a second conductive layer (1300) may be disposed on a first conductive layer (1200). A first interlayer insulating layer (115, FIG. 13) may be interposed between the first conductive layer (1200) and the second conductive layer (1300). The second conductive layer (1300) may include a sixth conductive pattern (1301) and a seventh conductive pattern (1302).

[0183] The sixth conductive pattern (1301) and the seventh conductive pattern (1302) may include the same material. The sixth conductive pattern (1301) and the seventh conductive pattern (1302) may each include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0184] The sixth conductive pattern (1301) may be arranged to overlap the first conductive pattern (1201) and the second conductive pattern (1202). Specifically, the sixth conductive pattern (1301) may include first portions (1311) arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3), and second portions (1312) extending along the first direction (e.g., the x-direction) to connect the first portions (1311) arranged in each of the first circuit area (PCA1), the second circuit area (PCA3), and the third circuit area (PCA3). Each of the first portions (1311) may have an opening (1301OP) having a closed shape.

[0185] The first portions (1311) of the sixth conductive pattern (1301) may overlap with the first conductive pattern (1201). As described above, the first conductive pattern (1201) may correspond to the fifth capacitor electrode (CE5) of the third capacitor (Ca), and therefore, the first portion (1311) overlapping with the first conductive pattern (1201) may correspond to the sixth capacitor electrode (CE6) of the third capacitor (Ca).

[0186] The second portion (1312) of the sixth conductive pattern (1301) may overlap with the second conductive pattern (1202). As described above, the second conductive pattern (1202) may correspond to the first capacitor electrode (CE1) of the first capacitor (Cst), and therefore, the second portion (1312) overlapping with the second conductive pattern (1202) may correspond to the second capacitor electrode (CE2) of the first capacitor (Cst).

[0187] The seventh conductive pattern (1302) is arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3), and may have an isolated shape. The seventh conductive pattern (1302) may be arranged to overlap the fifth conductive pattern (1205). As described above, the fifth conductive pattern (1205) may correspond to the third capacitor electrode (CE3) of the second capacitor (Cpr), and thus the seventh conductive pattern (1302) overlapping the fifth conductive pattern (1205) may correspond to the fourth capacitor electrode (CE4) of the second capacitor (Cpr). The seventh conductive pattern (1302) may be connected to the sixteenth conductive pattern (1409) described below, and may receive a data signal from a data line.

[0188] That is, the second capacitor electrode (CE2), which is the upper electrode of the first capacitor (Cst), the fourth capacitor electrode (CE4), which is the upper electrode of the second capacitor (Cpr), and the sixth capacitor electrode (CE6), which is the upper electrode of the third capacitor (Ca), may be arranged on the same layer. The sixth capacitor electrode (CE6) may be formed integrally with the second capacitor electrode (CE2).

[0189] Referring to FIG. 9d, a third conductive layer (1400) may be disposed on the second conductive layer (1300). A second interlayer insulating layer (117) may be interposed between the second conductive layer (1300) and the third conductive layer (1400). The third conductive layer (1400) may include an eighth conductive pattern (1401), a ninth conductive pattern (1402), a tenth conductive pattern (1403), an eleventh conductive pattern (1404), a twelfth conductive pattern (1405), a thirteenth conductive pattern (1406), a fourteenth conductive pattern (1407), a fifteenth conductive pattern (1408), a sixteenth conductive pattern (1409), and a seventeenth conductive pattern (1410).

[0190] The 8th to 17th challenge patterns (1401, 1402, 1403, 1404, 1405, 1406, 1407, 1408, 1409, 1410) may contain the same material. The eighth to seventeenth challenge patterns (1401, 1402, 1403, 1404, 1405, 1406, 1407, 1408, 1409, 1410) may each include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0191] The eighth conductive pattern (1401) and the sixteenth conductive pattern (1409) may have an isolated shape. The eighth conductive pattern (1401) may include an 8-1 conductive pattern (1401-1) disposed in a first circuit area (PCA1), an 8-2 conductive pattern (1401-2) disposed in a second circuit area (PCA2), and an 8-3 conductive pattern (1401-3) disposed in a third circuit area (PCA3). The sixteenth conductive pattern (1409) may include a 16-1 conductive pattern (1409-1) disposed in a first circuit area (PCA1), a 16-2 conductive pattern (1409-2) disposed in a second circuit area (PCA2), and a 16-3 conductive pattern (1409-3) disposed in a third circuit area (PCA3).

[0192] In one embodiment, the 8th conductive pattern (1401) and the 16th conductive pattern (1409) may constitute a portion of a data line (DL, FIG. 6). For example, the 18-1st conductive pattern (1501-1, FIG. 9e), which will be described later, may be connected to the 8-1st conductive pattern (1401-1) through the 1-1st contact hole (CNT1a) and may be connected to the 16-1st conductive pattern (1409-1) through the 2-1st contact hole (CNT2a). Accordingly, the 8-1st conductive pattern (1401-1), the 16-1st conductive pattern (1409-1), and the 18-1st conductive pattern (1501-1, FIG. 9e) may constitute a first data line (DL1, FIG. 13) that transmits a data voltage to the first pixel circuit (PC1, FIG. 8). Likewise, the 18-2 conductive pattern (1501-2, FIG. 9e) to be described later may be connected to the 8-2 conductive pattern (1401-2) through the 1-2 contact hole (CNT1b) and may be connected to the 16-2 conductive pattern (1409-2) through the 2-2 contact hole (CNT2b). Accordingly, the 8-2 conductive pattern (1401-2), the 16-2 conductive pattern (1409-2), and the 18-2 conductive pattern (1501-2, FIG. 9e) may form a second data line (DL2, FIG. 13) that transmits a data voltage to the second pixel circuit (PC2, FIG. 8). In addition, the 18-3 conductive pattern (1501-3, FIG. 9e) to be described later may be connected to the 8-3 conductive pattern (1401-3) through the 1-3 contact hole (CNT1c) and may be connected to the 16-3 conductive pattern (1409-3) through the 2-3 contact hole (CNT2c). Accordingly, the 8-3 conductive pattern (1401-3), the 16-3 conductive pattern (1409-3), and the 18-3 conductive pattern (1501-3, FIG. 9e) may form a third data line (DL3, FIG. 13) that transmits a data voltage to the third pixel circuit (PC3, FIG. 8).

[0193] Additionally, the 16th challenge pattern (1409) can be connected to the 7th challenge pattern (1302) through the 2nd-4th contact hole (CNT2d). Accordingly, the first to third data lines (DL1, DL2, DL3, FIG. 13) can each apply a data signal to the second capacitor (Cpr).

[0194] The eighth challenge pattern (1401) and the sixteenth challenge pattern (1409) may be arranged to extend from the first island portion (11) to the vertical bridge portion (12b). In FIG. 9, for simplicity, the eighth challenge pattern (1401) and the sixteenth challenge pattern (1409) are illustrated as being disconnected on the vertical bridge portion (12b), but the eighth challenge pattern (1401) and the sixteenth challenge pattern (1409) may be arranged to continue extending on the vertical bridge portion (12b) along the second direction (e.g., the y direction).

[0195] The ninth challenge pattern (1402) may have an isolated shape. However, the ninth challenge pattern (1402) may be arranged to extend along the first direction (e.g., the x-direction) across the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3).

[0196] In one embodiment, the ninth conductive pattern (1402) may form a part of the first driving voltage line (VDDL, FIG. 6). For example, the ninth conductive pattern (1402) may be connected to the 19th conductive pattern (1902, FIG. 9e) and the 25th conductive pattern (1601, FIG. 9f), which will be described later, through the 3-1 contact hole (CNT3a), and may be connected to the 22nd conductive pattern (1905, FIG. 9e) and the 26th conductive pattern (1602, FIG. 9f), which will be described later, through the 3-2 contact hole (CNT3b). In addition, the ninth conductive pattern (1402) may be connected to the first semiconductor pattern (1101) through each of the 4-1st contact hole (CNT4a), the 4-2nd contact hole (CNT4b), and the 4-3rd contact hole (CNT4c).

[0197] The tenth conductive pattern (1403) and the eleventh conductive pattern (1404) may have an isolated shape. The tenth conductive pattern (1403) may be arranged on the left outer side of the first circuit area (PCA1), and the eleventh conductive pattern (1404) may be arranged on the right outer side of the third circuit area (PCA3). In other words, the tenth conductive pattern (1403) and the eleventh conductive pattern (1404) may each be arranged near the horizontal bridge portion (12a). When a component is described as being “near” another component, this may mean that the component is located within a predetermined distance (e.g., a relatively close distance) from the other component.

[0198] In one embodiment, the tenth conductive pattern (1403) and the eleventh conductive pattern (1404) may form part of an initialization voltage line (VIL, FIG. 6). For example, the tenth conductive pattern (1403) may be connected to the twenty-first conductive pattern (1504, FIG. 9e), which will be described later, through the fifth-first contact hole (CNT5a), and may be connected to the sixth conductive pattern (1301) through the sixth-first contact hole (CNT6a), thereby transmitting an initialization voltage to the pixel circuit. The 11th conductive pattern (1404) is connected to the 6th conductive pattern (1301) through the 6-2 contact hole (CNT6b), and is connected to the 20th conductive pattern (1503, FIG. 9e) and the 23rd conductive pattern (1506, FIG. 9e) through the 5-2 contact hole (CNT5b), so as to transmit an initialization voltage to the pixel circuit.

[0199] The twelfth conductive pattern (1405) may have an isolated shape. The twelfth conductive pattern (1405) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The twelfth conductive pattern (1405) may be arranged to extend along the second direction (e.g., the y direction).

[0200] In one embodiment, the 12th conductive pattern (1405) may be a connecting electrode connecting a third capacitor (Ca, FIG. 6), a light-emitting element (LED, FIG. 6), a first transistor (T1, FIG. 6), and a third transistor (T3, FIG. 6). For example, the 12th conductive pattern (1405) may correspond to the third node (N3) of FIG. 6. Specifically, the 12th conductive pattern (1405) may be connected to the first conductive pattern (1201) through the 7-1 contact hole (CNT7a) and may be electrically connected to the third capacitor (Ca, FIG. 6). The 12th conductive pattern (1405) may be connected to the 24th conductive pattern (1507, FIG. 9e), which will be described later, through the 7-2 contact hole (CNT7b) and may be electrically connected to the light-emitting element (LED, FIG. 6). The 12th challenge pattern (1405) is connected to the first semiconductor pattern (1101) through the 7-3 contact hole (CNT7c), and can be electrically connected to the first transistor (T1, FIG. 6) and the third transistor (T3, FIG. 6).

[0201] The 13th conductive pattern (1406) may have an isolated shape. The 13th conductive pattern (1406) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The 13th conductive pattern (1406) may be arranged to extend along the first direction (e.g., the x-direction).

[0202] In one embodiment, the 13th conductive pattern (1406) may be a connection electrode connecting the first transistor (T1, FIG. 6), the second transistor (T2), and the first capacitor (Cst). For example, the 13th conductive pattern (1406) may correspond to the first node (N1) of FIG. 6. Specifically, the 13th conductive pattern (1406) may be connected to the first semiconductor pattern (1101) through the 8-1 contact hole (CNT8a) and may be electrically connected to the second transistor (T2, FIG. 6). The 13th conductive pattern (1406) may be connected to the second conductive pattern (1202) through the 8-2 contact hole (CNT8b) and may be electrically connected to the first transistor (T1, FIG. 6) and the first capacitor (Cst, FIG. 6).

[0203] The fourteenth conductive pattern (1407) and the fifteenth conductive pattern (1408) may be arranged to extend along the first direction (e.g., the x-direction). Specifically, the fourteenth conductive pattern (1407) and the fifteenth conductive pattern (1408) may be arranged on the first island portion (11) and the horizontal bridge portion (12a). The fourteenth conductive pattern (1407) and the fifteenth conductive pattern (1408) may be arranged across the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3).

[0204] In one embodiment, the fourteenth conductive pattern (1407) may correspond to the second gate line (GCL, FIG. 6), and the fifteenth conductive pattern (1408) may correspond to the first gate line (GWL, FIG. 6). The fourteenth conductive pattern (1407) may be connected to the third conductive pattern (1203) through the 9-1st contact hole (CNT9a), the 9-2nd contact hole (CNT9b), and the 9-3rd contact hole (CNT9c), thereby transmitting the second gate signal (GC, FIG. 6) to the third gate electrode (G3) of each pixel circuit. The 15th conductive pattern (1408) is connected to the 4th conductive pattern (1204) through the 10-1 contact hole (CNT10a), the 10-2 contact hole (CNT10b), and the 10-3 contact hole (CNT10c), and can transmit the first gate signal (GW, FIG. 6) to the second gate electrode (G2) of each pixel circuit.

[0205] The seventeenth conductive pattern (1410) may have an isolated shape. The seventeenth conductive pattern (1410) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The seventeenth conductive pattern (1410) may be arranged to extend in the second direction (e.g., the y direction).

[0206] In one embodiment, the seventeenth conductive pattern (1410) may be a connection electrode connecting the second capacitor (Cpr), the second transistor (T2), and the third transistor (T3). For example, the seventeenth conductive pattern (1410) may correspond to the second node (N2) of FIG. 6. Specifically, the seventeenth conductive pattern (1410) may be connected to the first semiconductor pattern (1101) through the 11-1 contact hole (CNT11a), and may be electrically connected to the second transistor (T2, FIG. 6) and the third transistor (T3, FIG. 6). The seventeenth conductive pattern (1410) may be connected to the fifth conductive pattern (1205) through the 11-2 contact hole (CNT11b), and may be electrically connected to the second capacitor (Cpr, FIG. 6).

[0207] Referring to FIG. 9e, a fourth conductive layer (1500) may be disposed on the third conductive layer (1400). A first organic insulating layer (119, FIG. 13) may be interposed between the third conductive layer (1400) and the fourth conductive layer (1500). The fourth conductive layer (1500) may include an 18th conductive pattern (1501), a 19th conductive pattern (1502), a 20th conductive pattern (1503), a 21st conductive pattern (1504), a 22nd conductive pattern (1505), a 23rd conductive pattern (1506), and a 24th conductive pattern (1507).

[0208] The 18th to 24th conductive patterns (1501, 1502, 1503, 1504, 1505, 1506, 1507) may include the same material. The 18th to 24th conductive patterns (1501, 1502, 1503, 1504, 1505, 1506, 1507) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), respectively, and may be formed as a single layer or multiple layers including the aforementioned materials.

[0209] The 18th conductive pattern (1501) may have an isolated shape. The 18th conductive pattern (1501) may include a 18-1 conductive pattern (1501-1) arranged in a first circuit area (PCA1), a 18-2 conductive pattern (1501-2) arranged in a second circuit area (PCA2), and a 18-3 conductive pattern (1501-3) arranged in a third circuit area (PCA3). The 18-1 conductive pattern (1501-1), the 18-2 conductive pattern (1501-2), and the 18-3 conductive pattern (1501-3) may be arranged to extend along the second direction (e.g., the y direction).

[0210] In one embodiment, the 18th conductive pattern (1501) may form a part of a data line (DL, FIG. 6). As described above, the 18-1st conductive pattern (1501-1) may be connected to the 8-1st conductive pattern (1401-1) and the 16-1st conductive pattern (1409-1) to form a first data line that applies a data voltage to a first pixel circuit (PC1, FIG. 8). Similarly, the 18-2nd conductive pattern (1501-2) may be connected to the 8-2nd conductive pattern (1401-2) and the 16-2nd conductive pattern (1409-2) to form a second data line that applies a data voltage to a second pixel circuit (PC2, FIG. 8). The 18-3 challenge pattern (1501-3) can be connected to the 8-3 challenge pattern (1401-3) and the 16-3 challenge pattern (1409-3) to form a third data line that applies a data voltage to the third pixel circuit (PC3, FIG. 8).

[0211] The 19th conductive pattern (1502) may have an isolated shape. The 19th conductive pattern (1502) may be arranged to extend along the second direction (e.g., the y direction). The 19th conductive pattern (1502) may be arranged only within the first circuit area (PCA1) and may not be arranged in the second circuit area (PCA2) and the third circuit area (PCA3). Meanwhile, the 22nd conductive pattern (1505) may have an isolated shape and may be arranged to extend slightly along the second direction (e.g., the y direction). The 22nd conductive pattern (1505) may be arranged on the right outer side of the third circuit area (PCA3).

[0212] In one embodiment, the 19th conductive pattern (1502) and the 22nd conductive pattern (1505) may form a part of a first driving voltage line (VDDL, FIG. 6). For example, the 19th conductive pattern (1502) may receive a first driving voltage (ELVDD, FIG. 6) from the 25th conductive pattern (1601, FIG. 9f), which will be described later, through the 12-1 contact hole (CNT12a), and may serve to transmit the first driving voltage (ELVDD, FIG. 6) in a second direction (e.g., the y direction). The 19th conductive pattern (1502) may be connected to the 9th conductive pattern (1402) through the 3-1 contact hole (CNT3a), and may serve to transmit the first driving voltage (ELVDD, FIG. 6) in a first direction (e.g., the x direction). The 9th conductive pattern (1402) is connected to the 22nd conductive pattern (1505), and the 22nd conductive pattern (1505) can be connected to the 26th conductive pattern (1602, FIG. 9f), which will be described later, through the 12-3 contact hole (CNT12c). In addition, the 19th conductive pattern (1502) can transmit the first driving voltage (ELVDD, FIG. 6) to the 27th conductive pattern (1603, FIG. 9f), which will be described later, through the 12-2 contact hole (CNT12b).

[0213] The 20th conductive pattern (1503) may be arranged to extend in the second direction (e.g., the y direction). The 20th conductive pattern (1503) may be arranged to extend on the first island portion (11) and the vertical bridge portion (12b). In FIG. 9e, for simplicity, the 20th conductive pattern (1503) is shown as being disconnected on the vertical bridge portion (12b). However, the 20th conductive pattern (1503) may be arranged to continue extending along the second direction (e.g., the y direction) on the vertical bridge portion (12b). The 20th conductive pattern (1503) may be arranged only within the third circuit area (PCA3), and may not be arranged in the first circuit area (PCA1) and the second circuit area (PCA2). Meanwhile, the 23rd conductive pattern (1506) may be in an isolated shape.

[0214] The 21st conductive pattern (1504) and the 23rd conductive pattern (1506) may be arranged to extend in the first direction (e.g., the x direction). The 21st conductive pattern (1504) may be arranged on the left outer side of the first circuit area (PCA1) and may be arranged to extend on the horizontal bridge portion (12a), and the 23rd conductive pattern (1506) may be arranged on the right outer side of the third circuit area (PCA3) and may be arranged to extend on the horizontal bridge portion (12a). In FIG. 9e, for simplicity, the 21st conductive pattern (1504) and the 23rd conductive pattern (1506) are shown as being disconnected on the horizontal bridge portion (12a). However, the 21st conductive pattern (1504) and the 23rd conductive pattern (1506) may be arranged to continue extending along the first direction (e.g., the x-direction) on the horizontal bridge portion (12a). Meanwhile, the 23rd conductive pattern (1506) may be arranged to be integrally connected with the 20th conductive pattern (1503).

[0215] In one embodiment, the 20th conductive pattern (1503), the 21st conductive pattern (1504), and the 23rd conductive pattern (1506) may form part of an initialization voltage line (VIL, FIG. 6). For example, the 21st conductive pattern (1504) may be connected to the 10th conductive pattern (1403) to transmit an initialization voltage to the 6th conductive pattern (1301). The 20th conductive pattern (1503) and the 23rd conductive pattern (1506) may be connected to the 11th conductive pattern (1404) connected to the 6th conductive pattern (1301) to transmit an initialization voltage in the second direction and the first direction, respectively.

[0216] The 24th challenge pattern (1507) may have an isolated shape. The 24th challenge pattern (1507) may be arranged to extend slightly in the second direction (e.g., the y direction). The 24th challenge pattern (1507) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3).

[0217] In one embodiment, the 24th conductive pattern (1507) may be a connection electrode connecting a third capacitor (Ca, FIG. 6), a light-emitting element (LED, FIG. 6), a first transistor (T1, FIG. 6), and a third transistor (T3, FIG. 6). For example, the 24th conductive pattern (1507) may correspond to the third node (N3) of FIG. 6. Specifically, the 24th conductive pattern (1507) may be connected to the first conductive pattern (1201) and the first semiconductor pattern (1101) via the 12th conductive pattern (1405), and may be electrically connected to the first transistor (T1, FIG. 6), the third transistor (T3, FIG. 6), and the third capacitor (Ca, FIG. 6). In addition, the 24th challenge pattern (1507) is connected to the 29th challenge pattern (1605, FIG. 9f), which will be described later, through the 13th contact hole (CNT13), and can be electrically connected to a light-emitting element (LED, FIG. 6).

[0218] Referring to FIG. 9f, a fifth conductive layer (1600) may be disposed on the fourth conductive layer (1500). A second organic insulating layer (121, FIG. 13) may be interposed between the fourth conductive layer (1500) and the fifth conductive layer (1600). The fifth conductive layer (1600) may include a 25th conductive pattern (1601), a 26th conductive pattern (1602), a 27th conductive pattern (1603), a 28th conductive pattern (1604), and a 29th conductive pattern (1605).

[0219] The 25th to 29th conductive patterns (1601, 1602, 1603, 1604, 1605) may include the same material. The 25th to 29th conductive patterns (1601, 1602, 1603, 1604, 1605) may each include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0220] The 25th conductive pattern (1601), the 26th conductive pattern (1602), and the 27th conductive pattern (1603) may each have a shape extending from the bridge portion (12). Specifically, the 25th conductive pattern (1601) may be arranged to extend from the horizontal bridge portion (12a) to the first circuit area (PCA1). The 26th conductive pattern (1602) may be arranged to extend from the right outer edge of the third circuit area (PCA3) to the horizontal bridge portion (12a). The 27th conductive pattern (1603) may be arranged to extend from the lower outer edge of the circuit area to the vertical bridge portion (12b). In FIG. 9f, for simplicity, the 25th conductive pattern (1601) and the 26th conductive pattern (1602) appear to be disconnected on the horizontal bridge portion (12a), but the 25th conductive pattern (1601) and the 26th conductive pattern (1602) may be arranged to extend continuously along the first direction (e.g., the x-direction) on the horizontal bridge portion (12a). Similarly, the 27th conductive pattern (1603) also appears to be disconnected on the vertical bridge portion (12b), but the 27th conductive pattern (1603) may be arranged to extend continuously along the second direction (e.g., the y-direction) on the vertical bridge portion (12b).

[0221] In one embodiment, the 25th conductive pattern (1601), the 26th conductive pattern (1602), and the 27th conductive pattern (1603) may form part of a first driving voltage line (VDDL, FIG. 6). For example, the 25th conductive pattern (1601) may be connected to the 19th conductive pattern (1502), the 9th conductive pattern (1402), and the 22nd conductive pattern (1505) to transmit a first driving voltage (ELVDD, FIG. 6). The 26th conductive pattern (1602) is connected to the 22nd conductive pattern (1505) and can transmit the first driving voltage (ELVDD, FIG. 6) in a first direction (e.g., x direction), and the 27th conductive pattern (1603) is connected to the 19th conductive pattern (1502) and can transmit the first driving voltage (ELVDD, FIG. 6) in a second direction (e.g., y direction).

[0222] The 28th conductive pattern (1604) may be arranged to extend in a first direction (e.g., x-direction) and a second direction (e.g., y-direction). Specifically, the 28th conductive pattern (1604) may include a second portion (1642) extending along the first direction, a first portion (1641) extending along the second direction, and a third portion (1643). The second portion (1642) of the 28th conductive pattern (1604) may be arranged to extend along the first direction on the horizontal bridge portion (12a) and the first island portion (11). The first portion (1641) and the third portion (1643) of the 28th conductive pattern (1604) may be arranged to extend along the second direction on the vertical bridge portion (12b) and the first island portion (11). At this time, the first part (1641) and the third part (1643) may be mainly placed within the second circuit area (PCA2).

[0223] In one embodiment, the 28th conductive pattern (1604) may constitute a portion of a second driving voltage line (VSSL, FIG. 6). The 28th conductive pattern (1604) is a pattern in which portions extending in a first direction (e.g., x direction) and a second direction (e.g., y direction) are integrally formed, and may transmit a second driving voltage (ELVSS, FIG. 6) in the first and second directions. The second conductive pattern (1604) may be connected to a second electrode pad (242, FIG. 9g), which will be described later, through a 14th contact hole (CNT14), and may transmit the second driving voltage (ELVSS, FIG. 6) to a light-emitting element (LED, FIG. 6).

[0224] The 29th challenge pattern (1605) may have an isolated shape. The 29th challenge pattern (1605) may be arranged to extend slightly along the second direction (e.g., the y direction). The 29th challenge pattern (1605) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3).

[0225] In one embodiment, the 29th conductive pattern (1605) may be a connecting electrode connecting a third capacitor (Ca, FIG. 6), a light-emitting element (LED, FIG. 6), a first transistor (T1, FIG. 6), and a third transistor (T3, FIG. 6). For example, the 29th conductive pattern (1605) may correspond to the third node (N3) of FIG. 6. Specifically, the 29th conductive pattern (1605) may be connected to the first conductive pattern (1201) and the first semiconductor pattern (1101) via the 24th conductive pattern (1507) and the 12th conductive pattern (1405), and may be electrically connected to the first transistor (T1, FIG. 6), the third transistor (T3, FIG. 6), and the third capacitor (Ca, FIG. 6). In addition, the 29th challenge pattern (1605) can be electrically connected to a light-emitting element (LED, FIG. 6) by being connected to a first electrode pad (241, FIG. 9g) to be described later through a 15th contact hole (CNT15).

[0226] Referring to FIG. 9g, a sixth conductive layer (1700) may be disposed on the fifth conductive layer (1600). A third organic insulating layer (123, FIG. 13) may be interposed between the fifth conductive layer (1600) and the sixth conductive layer (1700). The sixth conductive layer (1700) may include first electrode pads (241) and second electrode pads (242).

[0227] The sixth conductive layer (1700) may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multilayer or single layer including the above materials. In one embodiment, when the first electrode pads (241) and the second electrode pads (242) are connected to electrodes of a light-emitting element (LED, FIG. 6) in a eutectic bonding manner, the sixth conductive layer (1700) may have a multilayer structure including a copper (Cu) layer or may include a copper (Cu) alloy. In another embodiment, the sixth conductive layer (1700) may include a conductive organic material. For example, the sixth conductive layer (1700) may include carbon black, and may be an organic material including carbon black. In another embodiment, the sixth conductive layer (1700) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). Alternatively, the sixth conductive layer (1700) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In another embodiment, the sixth conductive layer (1700) may further include a layer formed of ITO, IZO, ZnO, AZO, or In2O3 on or under the aforementioned reflective layer. For example, the sixth conductive layer (1700) may include an ITO layer / Ag layer / ITO layer.

[0228] The first electrode pads (241) may be arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3), respectively. The first electrode pads (241) may each have an isolated shape. The first electrode pad (241) may be connected to the first conductive pattern (1201) and the first semiconductor pattern (1101) through the 29th conductive pattern (1605), the 24th conductive pattern (1507), and the 12th conductive pattern (1405). Accordingly, the first electrode pad (241) may electrically connect the first electrode of the light-emitting element (LED, FIG. 6) to the first transistor (T1, FIG. 6), the third transistor (T3, FIG. 6), and the third capacitor (Ca, FIG. 6).

[0229] The second electrode pad (242) may be arranged to extend across the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The second electrode pad (242) may have an island shape in which a length in the first direction (e.g., the x direction) is longer than a length in the second direction (e.g., the y direction). The second electrode pad (242) may be provided in common to the light-emitting elements arranged in the first island portion (11). For example, the second electrodes of each of the first light-emitting element, the second light-emitting element, and the third light-emitting element may be connected to the second electrode pad (242). The second electrode pad (242) may be connected to the 28th conductive pattern (1604) through the 14th contact hole (CNT14) to receive a second driving voltage (ELVSS, FIG. 6).

[0230] In one embodiment of the present invention illustrated in FIG. 9g, the light-emitting element includes an inorganic light-emitting diode (230, FIG. 7b), but in other embodiments, the light-emitting element may include an organic light-emitting diode (220, FIG. 7a). For example, the sixth conductive layer (1700) may include a first electrode (221, FIG. 7a) instead of the first electrode pad (241). In this case, the sixth conductive layer (1700) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). Alternatively, the sixth conductive layer (1700) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the sixth conductive layer (1700) may further include a layer formed of ITO, IZO, ZnO, AZO, or In2O3 on / under the aforementioned reflective layer.

[0231] Fig. 10 is a schematic diagram illustrating an initialization voltage line among the components of the display device illustrated in Fig. 8. Fig. 11 is a schematic diagram illustrating a first driving voltage line among the components of the display device illustrated in Fig. 8. Fig. 12 is a schematic diagram illustrating a second driving voltage line among the components of the display device illustrated in Fig. 8.

[0232] First, referring to FIG. 10, an initialization voltage line (VIL) may be arranged on the first island portion (11) and electrically connected to a first pixel circuit (PC1, FIG. 8), a second pixel circuit (PC2, FIG. 8), and a third pixel circuit (PC3, FIG. 8). The initialization voltage line (VIL) may be arranged to extend on the first bridge portion (12) along a first direction (e.g., x direction) and a second direction (e.g., y direction). The extended initialization voltage line (VIL) may transmit an initialization voltage (Vint, FIG. 6) to the pixel circuits of the island portions arranged around the first island portion (11).

[0233] In one embodiment, the initialization voltage line (VIL) may include a horizontal initialization voltage line (VILa) and a vertical initialization voltage line (VILb). The horizontal initialization voltage line (VILa) and the vertical initialization voltage line (VILb) may be arranged to intersect on the first island portion (11). In other words, the initialization voltage line (VIL) may be arranged in a planar mesh pattern.

[0234] As described above, the initialization voltage line (VIL) may include a sixth conductive pattern (1301) disposed on a second conductive layer (1300, FIG. 9c), a tenth conductive pattern (1403), an eleventh conductive pattern (1404) disposed on a third conductive layer (1400, FIG. 9d), a 20th conductive pattern (1503), a twenty-first conductive pattern (1504), and a twenty-third conductive pattern (1506) disposed on a fourth conductive layer (1500, FIG. 9e). Specifically, the 21st conductive pattern (1504) extended from the horizontal bridge portion (12a) to the 1st island portion (11) is connected to the 10th conductive pattern (1403) through the 5-1st contact hole (CNT5a), and the 10th conductive pattern (1403) is connected to the 6th conductive pattern (1301) through the 6-1st contact hole (CNT6a), so that an initialization voltage (Vint, FIG. 6) can be transmitted to the 6th conductive pattern (1301). The 6th conductive pattern (1301) is connected to the 11th conductive pattern (1404) through the 6-2 contact hole (CNT6b), and the 11th conductive pattern (1404) can transmit an initialization voltage (Vint, FIG. 6) to the 20th conductive pattern (1503) and the 23rd conductive pattern (1506) through the 5-2 contact hole (CNT5b). The 20th conductive pattern (1503) that received the initialization voltage can extend to the vertical bridge portion (12b) to transmit the initialization voltage (Vint, FIG. 6) to the pixel circuits arranged at the lower portion of the first island portion (11) in the plane. The 23rd conductive pattern (1506) that received the initialization voltage can extend to the horizontal bridge portion (12a) to transmit the initialization voltage (Vint, FIG. 6) to the pixel circuits arranged at the right side of the first island portion (11) in the plane.

[0235] At this time, the 21st conductive pattern (1504), the 10th conductive pattern (1403), the 6th conductive pattern (1301), the 11th conductive pattern (1404), and the 23rd conductive pattern (1506) are electrically connected to each other so as to sequentially transmit an initialization voltage (Vint, FIG. 6) along a first direction (e.g., x-direction). Accordingly, the 21st conductive pattern (1504), the 10th conductive pattern (1403), the 6th conductive pattern (1301), the 11th conductive pattern (1404), and the 23rd conductive pattern (1506) can form a horizontal initialization voltage line (VILa).

[0236] Likewise, the 20th conductive pattern (1503) can transmit an initialization voltage (Vint, FIG. 6) along the second direction (e.g., the y-direction). Accordingly, the 20th conductive pattern (1503) can form a vertical initialization voltage line (VILb). In one embodiment, the vertical initialization voltage line (VILb) extends to pass through the third circuit area (PCA3) and may not be arranged on the first circuit area (PCA1) and the second circuit area (PCA2).

[0237] Next, referring to FIG. 11, a first driving voltage line (VDDL) may be arranged on the first island portion (11) and electrically connected to a first pixel circuit (PC1, FIG. 8), a second pixel circuit (PC2, FIG. 8), and a third pixel circuit (PC3, FIG. 8). The first driving voltage line (VDDL) may be arranged to extend on the first bridge portion (12) along a first direction (e.g., x direction) and a second direction (e.g., y direction). The extended first driving voltage line (VDDL) may transmit a first driving voltage (EVLDD, FIG. 6) to a pixel circuit of an island portion arranged around the first island portion (11).

[0238] In one embodiment, the first driving voltage line (VDDL) may include a first horizontal driving voltage line (VDDLa) and a first vertical driving voltage line (VDDLb). The first horizontal driving voltage line (VDDLa) and the first vertical driving voltage line (VDDLb) may be arranged to intersect on the first island portion (11). In other words, the first driving voltage line (VDDL) may be arranged in a planar mesh pattern.

[0239] As described above, the first driving voltage line (VDDL) may include a ninth conductive pattern (1402) disposed on a third conductive layer (1400, FIG. 9d), a nineteenth conductive pattern (1502), a twenty-second conductive pattern (1505) disposed on a fourth conductive layer (1500, FIG. 9e), a twenty-fifth conductive pattern (1601), a twenty-sixth conductive pattern (1602), and a twenty-seventh conductive pattern (1603) disposed on a fifth conductive layer (1600, FIG. 9f).

[0240] Specifically, the 25th conductive pattern (1601) extending from the horizontal bridge portion (12a) to the first island portion (11) may include a first region extending to the vertical bridge portion (12b) and a second region connected to the 19th conductive pattern (1502) through the 12-1 contact hole (CNT12a). The first region of the 25th conductive pattern (1601) extends to the vertical bridge portion (12b), so that the first driving voltage line (VDDL) can transmit the first driving voltage (ELVDD, FIG. 6) to pixel circuits arranged on the upper portion of the first island portion (11) in a planar manner. In addition, the second region of the 25th conductive pattern (1601) is connected to the 19th conductive pattern (1502), and the 19th conductive pattern (1502) extends in the second direction (e.g., y direction) and is connected to the 27th conductive pattern (1603) through the 12-2 contact hole (CNT12b), so that the first driving voltage line (VDDL) can transmit the first driving voltage (ELVDD, FIG. 6) to the pixel circuits arranged on the lower side of the first island portion (11) on the plane.

[0241] The 19th conductive pattern (1502) can be connected to the 9th conductive pattern (1402) through the 3-1st contact hole (CNT3a), and the 9th conductive pattern (1402) can extend in the first direction (e.g., the x-direction) and be connected to the 22nd conductive pattern (1505) through the 3-2nd contact hole (CNT3b). The 22nd conductive pattern (1505) is connected to the 26th conductive pattern (1602) through the 12-3rd contact hole (CNT12c), and as the 26th conductive pattern (1602) extends from the horizontal bridge portion (12a), the first driving voltage line (VDDL) can transmit the first driving voltage (ELVDD, FIG. 6) to pixel circuits arranged on the right side of the first island portion (11) on a plane. Meanwhile, the 9th challenge pattern (1402) can be electrically connected to the first semiconductor pattern (1101, FIG. 9a) through the 4-1st contact hole (CNT4a), the 4-2nd contact hole (CNT4b), and the 4-3rd contact hole (CNT4c).

[0242] At this time, the 25th conductive pattern (1601), the 9th conductive pattern (1402), the 22nd conductive pattern (1505), and the 26th conductive pattern (1602) are electrically connected to each other so as to sequentially transmit a first driving voltage (ELVDD, FIG. 6) along a first direction (e.g., x-direction). Accordingly, the 25th conductive pattern (1601), the 9th conductive pattern (1402), the 22nd conductive pattern (1505), and the 26th conductive pattern (1602) can form a first horizontal driving low voltage line (VDDLa).

[0243] Likewise, the 25th conductive pattern (1601), the 19th conductive pattern (1502), and the 27th conductive pattern (1603) are electrically connected to each other to sequentially transmit a first driving voltage (ELVDD, FIG. 6) along a second direction (e.g., y direction). Accordingly, the 25th conductive pattern (1601), the 19th conductive pattern (1502), and the 27th conductive pattern (1603) may form a first vertical driving voltage line (VDDLb). In one embodiment, the first vertical driving voltage line (VDDLb) may extend to pass through the first circuit area (PCA1), and may not be arranged in the second circuit area (PCA2) and the third circuit area (PCA3).

[0244] Next, referring to FIG. 12, a second driving voltage line (VSSL) may be arranged on the first island portion (11) and electrically connected to a first pixel circuit (PC1, FIG. 8), a second pixel circuit (PC2, FIG. 8), and a third pixel circuit (PC3, FIG. 8). The second driving voltage line (VSSL) may be arranged to extend on the first bridge portion (12) along a first direction (e.g., x direction) and a second direction (e.g., y direction). The extended second driving voltage line (VSSL) may transmit a second driving voltage (EVLSS, FIG. 6) to a pixel circuit of an island portion arranged around the first island portion (11).

[0245] In one embodiment, the second driving voltage line (VSSL) may include a second horizontal driving voltage line (VSSLa) and a second vertical driving voltage line (VSSLb). The second horizontal driving voltage line (VSSLa) and the second vertical driving voltage line (VSSLb) may be arranged to intersect on the first island portion (11). In other words, the second driving voltage line (VSSL) may be arranged in a planar mesh pattern.

[0246] As described above, the second driving voltage line (VSSL) may include a 28th conductive pattern (1604) disposed on the fifth conductive layer (1600). The 28th conductive pattern (1604) may include a second portion (1642) extending along a first direction (e.g., x direction), a first portion (1641) extending along a second direction (e.g., y direction), and a third portion (1643). Specifically, the second portion (1642) may extend on the horizontal bridge portion (12a) to transmit a second driving voltage (ELVSS, FIG. 6) to pixel circuits disposed on the left and / or right sides of the first island portion (11) in the plane. The first part (1641) and the third part (1643) extend on the vertical bridge part (12b) and can transmit a second driving voltage (ELVSS, FIG. 6) to pixel circuits arranged on the upper and / or lower sides of the first island part (11) on a plane.

[0247] Accordingly, the second portion (1642) extending along the first direction may constitute a second horizontal driving voltage line (VSSLa). Similarly, the first portion (1641) and the third portion (1643) extending along the second direction may constitute a second vertical driving voltage line (VSSLb). In one embodiment, the second vertical driving voltage line (VSSLb) may extend primarily to pass through the second circuit area (PCA2).

[0248] Referring to FIGS. 10 to 12, vertical voltage lines that transmit voltage to each pixel circuit and extend along a second direction (e.g., y direction) may include a vertical initialization voltage line (VILb), a first vertical drive voltage line (VDDLb), and a second vertical drive voltage line (VSSLb). In one embodiment, the vertical initialization voltage line (VILb), the first vertical drive voltage line (VDDLb), and the second vertical drive voltage line (VSSLb) may each extend to pass through one of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). However, the vertical initialization voltage line (VILb), the first vertical drive voltage line (VDDLb), and the second vertical drive voltage line (VSSLb) may each be arranged in different circuit areas. For example, as shown in FIGS. 10 to 12, the vertical initialization voltage line (VILb) may be arranged in the third circuit area (PCA3), the first vertical driving voltage line (VDDLb) may be arranged in the first circuit area (PCA1), and the second vertical driving voltage line (VSSLb) may be arranged in the second circuit area (PCA2).

[0249] FIG. 13 is a cross-sectional view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0250] Referring to FIG. 13, the substrate (100) corresponding to the first island portion (11, FIG. 8) and the bridge portion (12, FIG. 8) may include a first base layer (101), a first barrier layer (102), a second base layer (103), and a second barrier layer (104). The first base layer (101) and the second base layer (103) may each include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. The first barrier layer (102) and the second barrier layer (104) may each include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0251] First, in the first island section (11), a buffer layer (111) is placed on the substrate (100), and a pixel circuit (PC Fig. 6) can be placed on the buffer layer (111). The buffer layer (111) can include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0252] A semiconductor layer (1100, FIG. 9a) may be disposed on the buffer layer (111). For example, as shown in FIG. 13, a first semiconductor layer (A1) of a first transistor (T1, FIG. 8) may be disposed on the buffer layer (111). The first semiconductor layer (A1) may include polysilicon. Alternatively, the first semiconductor layer (A1) may include amorphous silicon, an oxide semiconductor, an organic semiconductor, or the like.

[0253] A gate insulating layer (113) may be disposed on the first semiconductor layer (A1). The gate insulating layer (113) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide. The gate insulating layer (113) may be a single layer or multilayer including the aforementioned materials.

[0254] A first conductive layer (1200, FIG. 9b) may be disposed on the gate insulating layer (113). For example, as shown in FIG. 13, a first gate electrode (G1) of a first transistor (T1, FIG. 8) may be disposed on the gate insulating layer (113). The first gate electrode (G1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above materials.

[0255] In addition, a first capacitor electrode (CE1) of the first capacitor (Cst), a third capacitor electrode (CE3) of the second capacitor (Cpr), and a fifth capacitor electrode (CE5) of the third capacitor (Ca) may be disposed on the gate insulating layer (113). As described above, the first capacitor electrode (CE1) may be a part of the first gate electrode (G1). The third capacitor electrode (CE3) and the fifth capacitor electrode (CE5) may be disposed on the same layer as the first gate electrode (G1) and may include the same material as the first gate electrode (G1).

[0256] A first interlayer insulating layer (115) may be disposed on the first gate electrode (G1), the third capacitor electrode (CE3), and the fifth capacitor electrode (CE5). The first interlayer insulating layer (115) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or multilayer including the aforementioned materials.

[0257] A second capacitor electrode (CE2) of the first capacitor (Cst), a fourth capacitor electrode (CE4) of the second capacitor (Cpr), and a sixth capacitor electrode (CE6) of the third capacitor (Ca) may be disposed on the first interlayer insulating layer (115). The second capacitor electrode (CE2) may be disposed to overlap the first capacitor electrode (CE1) to form the first capacitor (Cst), the fourth capacitor electrode (CE4) may be disposed to overlap the third capacitor electrode (CE3) to form the second capacitor (Cpr), and the sixth capacitor electrode (CE6) may be disposed to overlap the fifth capacitor electrode (CE5) to form the third capacitor (Ca).

[0258] The second capacitor electrode (CE2), the fourth capacitor electrode (CE4), and the sixth capacitor electrode (CE6) may be arranged on the same layer and may include the same material. The second capacitor electrode (CE2), the fourth capacitor electrode (CE4), and the sixth capacitor electrode (CE6) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above materials.

[0259] A second interlayer insulating layer (117) may be disposed on the second capacitor electrode (CE2), the fourth capacitor electrode (CE4), and the sixth capacitor electrode (CE6). The second interlayer insulating layer (117) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or multiple layers including the aforementioned materials. The buffer layer (111), the gate insulating layer (113), the first interlayer insulating layer (115), and the second interlayer insulating layer (117) may be disposed on the first island portion (11) to form an inorganic insulating layer (IOL).

[0260] A third conductive layer (1400, FIG. 9d) may be disposed on the second interlayer insulating layer (117). For example, as shown in FIG. 13, a 12th conductive pattern (1405) and a 16-1st conductive pattern (1409-1) may be disposed on the second interlayer insulating layer (117). The 12th conductive pattern (1405) may be a connection electrode connecting the third capacitor (Ca) and the light-emitting element (LED, FIG. 6). The 16-1st conductive pattern (1409-1) may constitute a part of the first data line (DL1). The 12th conductive pattern (1405) and the 16-1st conductive pattern (1409-1) may be disposed on the same layer and may include the same material. The 12th challenge pattern (1405) and the 16-1st challenge pattern (1409-1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials.

[0261] A first organic insulating layer (119) may be disposed on the 12th challenge pattern (1405) and the 16-1st challenge pattern (1409-1). The first organic insulating layer (119) may include an organic material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0262] A fourth conductive layer (1500, FIG. 9e) may be disposed on the first organic insulating layer (119). For example, as shown in FIG. 13, a 24th conductive pattern (1507) and a 18-1st conductive pattern (1501-1) may be disposed on the first organic insulating layer (119). The 24th conductive pattern (1507) may be a connection electrode connecting the third capacitor (Ca) and the light-emitting element (LED, FIG. 6). The 18-1st conductive pattern (1501-1) may constitute a part of the first data line (DL1). The 24th conductive pattern (1507) and the 18-1st conductive pattern (1501-1) may be disposed on the same layer and may include the same material. The 24th challenge pattern (1507) and the 18-1st challenge pattern (1501-1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials.

[0263] A second organic insulating layer (121) may be disposed on the 24th challenge pattern (1507) and the 18-1st challenge pattern (1501-1). The second organic insulating layer (121) may include an organic material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0264] A fifth conductive layer (1600, FIG. 9f) may be disposed on the second organic insulating layer (121). For example, as shown in FIG. 13, a 28th conductive pattern (1604) may be disposed on the second organic insulating layer (121). The 28th conductive pattern (1604) may form a second driving voltage line (VSSL, FIG. 6). The 28th conductive pattern (1604) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above materials.

[0265] Next, an organic layer (OL) may be disposed on the substrate (100) on the bridge portion (12). The organic layer (OL) may be an insulating layer disposed on the bridge portion (12) corresponding to the inorganic insulating layer (IOL) of the first island portion (11). The organic layer (OL) may include an organic material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0266] In the horizontal bridge portion (12a), a first gate line (GWL) and a second gate line (GCL) may be arranged on an organic layer (OL). The first gate line (GWL) and the second gate line (GCL) may be arranged on the same layer as the 12th conductive pattern (1405) arranged on the first island portion (11), and may include the same material as the 12th conductive pattern (1405). The first gate line (GWL) and the second gate line (GCL) may extend along a first direction (e.g., x direction) on the horizontal bridge portion (12a) to apply gate signals to a plurality of pixel circuits.

[0267] A first organic insulating layer (119) may be disposed on the first gate line (GWL) and the second gate line (GCL), and a horizontal initialization voltage line (VILa) may be disposed on the first organic insulating layer (119). The horizontal initialization voltage line (VILa) may be disposed on the same layer as the 24th conductive pattern (1507) disposed on the first island portion (11), and may include the same material as the 24th conductive pattern (1507). The horizontal initialization voltage line (VILa) may extend along the first direction (e.g., the x-direction) on the horizontal bridge portion (12a) to transmit an initialization voltage to a plurality of pixel circuits.

[0268] A second organic insulating layer (121) may be disposed on the horizontal initialization voltage line (VILa), and a first horizontal driving voltage line (VDDLa) and a second horizontal driving voltage line (VSSLa) may be disposed on the second organic insulating layer (121). The first horizontal driving voltage line (VDDLa) and the second horizontal driving voltage line (VSSLa) may be disposed on the same layer as the 28th conductive pattern (1604) disposed on the first island portion (11), and may include the same material as the 28th conductive pattern (1604). The first horizontal driving voltage line (VDDLa) and the second horizontal driving voltage line (VSSLa) may extend along the first direction (e.g., the x-direction) on the horizontal bridge portion (12a) to transmit the first driving voltage and the second driving voltage to a plurality of pixel circuits.

[0269] That is, the plurality of gate lines and the plurality of voltage lines arranged on the horizontal bridge portion (12a) may be arranged on different layers. For example, as shown in FIG. 13, the horizontal initialization voltage line (VILa) may be arranged on the first gate line (GWL) and the second gate line (GCL), and the first horizontal driving voltage line (VDDLa) and the second horizontal driving voltage line (VSSLa) may be arranged on the horizontal initialization voltage line (VILa). When the plurality of wires are arranged on different layers as described above, the plurality of gate lines and the plurality of voltage lines may have wiring widths that are relatively wide on the horizontal bridge portion (12a), compared to a structure in which the plurality of wires are arranged on the same layer. Accordingly, the load of the plurality of gate lines and the plurality of voltage lines arranged on the horizontal bridge portion (12a) may be efficiently reduced.

[0270] In the vertical bridge portion (12b), a first data line (DL1), a second data line (DL2), and a third data line (DL3) may be arranged on an organic layer (OL). The first data line (DL1), the second data line (DL2), and the third data line (DL3) may be arranged on the same layer as the twelfth conductive pattern (1405) arranged on the first island portion (11), and may include the same material as the twelfth conductive pattern (1405). The first data line (DL1), the second data line (DL2), and the third data line (DL3) may extend along a second direction (e.g., the y direction) on the vertical bridge portion (12b) to apply data signals to a plurality of pixel circuits.

[0271] A first organic insulating layer (119) may be disposed on the first data line (DL1), the second data line (DL2), and the third data line (DL3), and a vertical initialization voltage line (VILb) may be disposed on the first organic insulating layer (119). The vertical initialization voltage line (VILb) may be disposed on the same layer as the 24th conductive pattern (1507) disposed on the first island portion (11), and may include the same material as the 24th conductive pattern (1507). The vertical initialization voltage line (VILb) may extend along the second direction (e.g., the y direction) on the vertical bridge portion (12b) to transmit an initialization voltage to a plurality of pixel circuits.

[0272] A second organic insulating layer (121) may be disposed on the vertical initialization voltage line (VILb), and a first vertical driving voltage line (VDDLb) and a second vertical driving voltage line (VSSLb) may be disposed on the second organic insulating layer (121). The first vertical driving voltage line (VDDLb) and the second vertical driving voltage line (VSSLb) may be disposed on the same layer as the 28th conductive pattern (1604) disposed on the first island portion (11), and may include the same material as the 28th conductive pattern (1604). The first vertical driving voltage line (VDDLb) and the second vertical driving voltage line (VSSLb) may extend along the second direction (e.g., the y direction) on the vertical bridge portion (12b) to transmit the first driving voltage and the second driving voltage to a plurality of pixel circuits.

[0273] That is, the plurality of data lines and the plurality of voltage lines arranged on the vertical bridge portion (12b) may be arranged on different layers. For example, as shown in FIG. 13, the vertical initialization voltage line (VILb) may be arranged on the first data line (DL1), the second data line (DL2), and the third data line (DL3), and the first vertical driving voltage line (VDDLb) and the second vertical driving voltage line (VSSLb) may be arranged on the vertical initialization voltage line (VILb). When the plurality of wires are arranged on different layers as described above, the plurality of data lines and the plurality of voltage lines may have wiring widths that are relatively wide on the vertical bridge portion (12b) compared to a structure in which the plurality of wires are arranged on the same layer. Accordingly, the load of the plurality of data lines and the plurality of voltage lines arranged on the vertical bridge portion (12b) may be efficiently reduced.

[0274] FIGS. 14A to 14G are perspective views schematically illustrating embodiments of an electronic device including a display device according to one embodiment of the present invention, respectively.

[0275] Referring to FIG. 14A, a display device according to an embodiment of the present invention may be utilized in a wearable electronic device (3100) that can be worn on a part of a user's body. The wearable electronic device (3100) may include a body portion (3110) and a display portion (3120) provided on the body portion (3110). The display device according to embodiments of the present invention may be utilized as the display portion (3120) of the wearable electronic device (3100). As illustrated in FIG. 17A, the wearable electronic device (3100) may be transformable. In one embodiment, it may be utilized as a smart watch or a smartphone, depending on the user's selection.

[0276] FIG. 14B illustrates a medical electronic device (3200). In one embodiment, the medical electronic device (3200) may include a body portion (3210) and a light-emitting portion (3220). A display device according to embodiments of the present invention may be used as the light-emitting portion (3220) of the medical electronic device (3200). The light-emitting portion (3220) may emit light of a certain wavelength band (e.g., infrared, visible light, etc.) to the patient's body. In one embodiment, the body portion (3210) may have a stretchable fiber material and may have a structure that allows the light-emitting portion to be worn on the body of a user.

[0277] FIG. 14C illustrates an educational electronic device (3300). In one embodiment, the educational electronic device may include a display unit (3320) provided within a frame (3310). The display unit (3320) may utilize a display device according to embodiments of the present invention. The display unit (3320) may provide an image such as a sea with crashing waves, a snow-covered mountain, or a volcano with flowing lava, wherein the display unit (3320) may expand in the height direction (e.g., the z direction) to reflect the height of the wave, mountain, or volcano. In some embodiments, a portion of the display unit (3320) may sequentially vary in height along the direction of flowing lava to display the movement of lava in three dimensions. The educational electronic device (3300) may include a plurality of pins (or stroke units, 3330) arranged on the back surface of the display unit (3320) so that the display unit (3320) expands in the height direction. The pins (3330) can be implemented to move along a third direction (e.g., the z direction or the -z direction) so that the image displayed on the display unit (3320) has a three-dimensional height. Fig. 14c illustrates an educational electronic device (3300), but its use is not limited to providing certain image information.

[0278] While the electronic devices illustrated in FIGS. 14A to 14C are described as electronic devices whose shapes can be varied, the present invention is not limited thereto. As described in the embodiments below, display devices according to embodiments of the present invention can be used in electronic devices in which a portion capable of displaying an image (e.g., a screen) is fixed.

[0279] FIG. 14D illustrates a robot (3400) as another electronic device according to one embodiment of the present invention. The robot (3400) can recognize movement or objects using a camera unit (3440) and display a predetermined image to a user through a display unit (3420, 3430). In some embodiments, since the display devices according to one embodiment of the present invention can extend in various directions as described above, they can be assembled into a body frame having a hemispherical shape, and thus the robot (3400) can include a hemispherical display unit (3420, 3430).

[0280] FIG. 14E illustrates a vehicle display device (3500) as another electronic device according to one embodiment of the present invention. The vehicle display device (3500) may include a cluster (3510), a center information display (CID) (3520), and / or a co-driver display. Since the display device according to the embodiment of the present invention can be extended in various directions, it may be used in the cluster (3510), the center information display (CID) (3520), and / or the co-driver display regardless of the shape of the internal frame of the vehicle.

[0281] Although FIG. 14e illustrates that the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display are each separate, the present invention is not limited thereto. In another embodiment, two or more selected from the cluster (3510), the Center Information Display (CID) (3520), and the co-driver display may be connected as one unit.

[0282] In some embodiments, a vehicle display device (3500) may include a button (3540) capable of displaying a predetermined image. Referring to the enlarged view of FIG. 17E, the hemispherical button (3540) may include an object (3542) that provides a button usability by moving in the z-direction or -z-direction, and a display device positioned on the object (3542). In some embodiments, when the object (3542) has a three-dimensionally rounded surface, the display device may also have a three-dimensionally rounded surface.

[0283] FIG. 14F illustrates an electronic device according to one embodiment of the present invention, which is an electronic device (3600) for advertising or display purposes. In some embodiments, the electronic device (3600) for advertising or display purposes may be installed on a fixed structure (3610), such as a wall or a pillar. If the structure (3610) includes a recessed surface, as illustrated in FIG. 17F, the electronic device (3600) for advertising or display purposes may also be positioned along the recessed surface of the structure (3610). In some embodiments, the electronic device (3600) for advertising or display purposes may be installed on the structure (3610) using a heat shrink film or the like.

[0284] FIG. 14G illustrates an electronic device according to one embodiment of the present invention as a controller (3700). The controller (3700) may include an image-type button. For example, the controller (3700) may include first to third button areas (3720, 3730, 3740) in which a portion of the display unit (3710) protrudes in the z direction or protrudes in the -z direction (or is sunken in the z direction). In some embodiments, the first and third button areas (3720, 3740) may protrude in the z direction, and the second button area (3730) may protrude in the -z direction (or is sunken in the z direction).

[0285] The display device according to the embodiment can be applied to various electronic devices. The electronic device according to the embodiment of the present invention can include the display device described above (e.g., the display device of FIG. 1), and in addition to the display device, can further include a module or device having additional functions.

[0286] Figure 15 is a block diagram of an electronic device according to one embodiment of the present invention.

[0287] Referring to FIG. 15, an electronic device (1000) according to one embodiment may include a display module (1001), a processor (1002), a memory (1003), and a power module (1004).

[0288] The processor (1002) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0289] The memory (1003) may store data information necessary for the operation of the processor (1002) or the display module (1001). When the processor (1002) executes an application stored in the memory (1003), an image data signal and / or an input control signal is transmitted to the display module (1001), and the display module (1001) can process the received signal and output image information through a display screen.

[0290] The power module (1004) may include a power supply module such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of the electronic device (1000).

[0291] At least one of the components of the electronic device (1000) described above may be included in the display device according to the embodiments described above. In addition, some of the individual modules functionally included in one module may be included in the display device, and other parts may be provided separately from the display device. For example, the display device may include a display module (1100) and an auxiliary processor among the processors (1002), and the main processor among the processors (1002), the memory (1003), and the power module (1004) may be provided in the form of other devices within the electronic device (1000) rather than the display device.

[0292] In one embodiment, a display module (1001) included in a display device can be driven based on an image data signal and an input control signal received from a processor (1002).

[0293] FIG. 16 is a schematic diagram of electronic devices according to various embodiments of the present invention.

[0294] Referring to FIG. 16, various electronic devices to which the display device according to the embodiments is applied may include not only electronic devices for displaying images such as a smart phone (1000a), a tablet PC (1000b), a notebook (1000c), a TV (1000d), and a desk monitor (1000e), but also wearable electronic devices including display modules such as smart glasses (1000f), a head-mounted display (1000g), and a smart watch (1000h), and a vehicle electronic device (1000i) including a dashboard on which display modules such as a dashboard, a center fascia, a CID (Center Information Display), and a rearview mirror display are arranged.

[0295] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will appreciate that various modifications and variations of the embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A substrate having a plurality of island sections and a plurality of bridge sections connecting the plurality of island sections defined; A first pixel circuit arranged in each of the plurality of islands and connected to a first data line; and A light emitting element disposed in each of the plurality of islands and connected to the first pixel circuit; The above first pixel circuit, A first transistor connected between a first driving voltage line and the light-emitting element and controlling current supplied to the light-emitting element, A first capacitor connected between a first node connected to the gate of the first transistor and an initialization voltage line; A second transistor connected between the first node and the second node and including a gate connected to the first gate line; a second capacitor connected between the first data line and the second node; and A display device comprising a third transistor connected between the second node and the third node connected to the light-emitting element, and including a gate connected to the second gate line.

2. In paragraph 1, The first capacitor includes a first capacitor electrode and a second capacitor electrode disposed on the first capacitor electrode, A display device, wherein the first capacitor electrode is part of the gate of the first transistor.

3. In paragraph 2, The second capacitor includes a third capacitor electrode and a fourth capacitor electrode disposed on the third capacitor electrode, A display device, wherein the third capacitor electrode is disposed on the same layer as the gate of the first transistor.

4. In paragraph 3, A display device, wherein a first insulating layer is interposed between the first capacitor electrode and the second capacitor electrode, and between the third capacitor electrode and the fourth capacitor electrode.

5. In paragraph 2, The first pixel circuit further includes a third capacitor connected between the third node and the initialization voltage line; A display device, wherein the third capacitor includes a fifth capacitor electrode and a sixth capacitor electrode on the fifth capacitor electrode.

6. In paragraph 5, A display device in which the sixth capacitor electrode is formed integrally with the second capacitor electrode.

7. In paragraph 1, The above multiple bridge sections are, A first bridge section connecting adjacent first island sections in the first direction; and A display device comprising a second bridge portion connecting adjacent second island portions in a second direction intersecting the first direction.

8. In paragraph 7, The first gate line and the second gate line extend along the first direction on the plurality of island portions and the first bridge portion, A display device, wherein the first gate line and the second gate line are arranged on the same layer on the first bridge portion.

9. In paragraph 7, A display device, wherein on the first bridge portion, the first gate line, the initialization voltage line, and the first driving voltage line are arranged on different layers.

10. In paragraph 7, A display device, wherein on the second bridge section, the first data line, the initialization voltage line, and the first driving voltage line are arranged on different layers.

11. In paragraph 7, A second pixel circuit arranged in each of the plurality of islands and connected to a second data line; and Further comprising a third pixel circuit arranged in each of the plurality of islands and connected to a third data line; A display device, wherein the first pixel circuit, the second pixel circuit, and the third pixel circuit are sequentially arranged along the first direction.

12. In paragraph 11, The first data line, the second data line, and the third data line extend along the second direction on the plurality of island portions and the second bridge portion, A display device, wherein the first data line, the second data line, and the third data line are arranged on the same layer on the second bridge portion.

13. In paragraph 11, A display device, wherein the initialization voltage line and the first driving voltage line have a planar mesh pattern.

14. In paragraph 11, The above initialization voltage line is, A horizontal initialization voltage line extending along the first direction on the plurality of island portions and the first bridge portion; and A display device comprising: a vertical initialization voltage line extending along the second direction on the plurality of island portions and the second bridge portion.

15. In paragraph 14, The above first driving voltage line is, A first horizontal driving voltage line extending along the first direction on the plurality of island portions and the first bridge portion; and A display device comprising: a first vertical driving voltage line extending along the second direction on the plurality of island portions and the second bridge portion.

16. In paragraph 15, A second voltage lower than the first voltage supplied by the first driving voltage line is supplied, and a second driving voltage line connected to the light emitting element is further included. The above second driving voltage line is, A second horizontal driving voltage line extending along the first direction on the plurality of island portions and the first bridge portion; and A display device comprising: a second vertical driving voltage line extending along the second direction on the plurality of island portions and the second bridge portion.

17. In paragraph 16, A display device, wherein each of the plurality of island sections further includes a first circuit area in which the first pixel circuit is arranged, a second circuit area in which the second pixel circuit is arranged, and a third circuit area in which the third pixel circuit is arranged.

18. In paragraph 17, The vertical initialization voltage line, the first vertical driving voltage line, and the second vertical driving voltage line are each extended to pass through one of the first circuit area, the second circuit area, and the third circuit area, A display device, wherein the vertical initialization voltage line, the first vertical driving voltage line, and the second vertical driving voltage line are each arranged in different circuit areas.

19. In paragraph 17, A display device, wherein each of the horizontal initialization voltage line, the first horizontal driving voltage line, and the second horizontal driving voltage line extends so as to pass through the first circuit area, the second circuit area, and the third circuit area.

20. In an electronic device including a display device, The above display device, A substrate having a plurality of island sections and a plurality of bridge sections connecting the plurality of island sections defined; A first pixel circuit arranged in each of the plurality of islands and connected to a first data line; and A light emitting element disposed in each of the plurality of islands and connected to the first pixel circuit; The above first pixel circuit, A first transistor connected between a first driving voltage line and the light-emitting element and controlling current supplied to the light-emitting element, A first capacitor connected between a first node connected to the gate of the first transistor and an initialization voltage line; A second transistor connected between the first node and the second node and including a gate connected to the first gate line; a second capacitor connected between the first data line and the second node; and An electronic device comprising a third transistor connected between the second node and the third node connected to the light-emitting element, and including a gate connected to the second gate line.

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