Selective ETCH of stack using a hydrogen chloride gas and fluorine containing gas

Abstract

A method of etching recessed features in a silicon containing stack below a mask is provided. An etch gas is provided comprising providing a HCl gas and providing a fluorine containing gas. The etch gas is transformed into a plasma. The stack is exposed to the plasma formed from the etch gas for selectively etching the recessed features in the stack with respect to the mask.

Description

SELECTIVE ETCH OF STACK USING A HYDROGEN CHLORIDE GAS AND FLUORINE CONTAINING GASCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of U.S. Application No. 63 / 662,294, filed lune 20, 2024, which is incorporated herein by reference for all purposes.BACKGROUND

[0002] One process frequently employed during the fabrication of semiconductor devices is the formation of a recessed feature in a stack below a mask. The stack may be alternating / repeating layers into which the recessed feature is formed, or a thick film of a single layer of material. One example context where such a process may occur is memory applications such as dynamic random access memory (DRAM) and “not and” memory devices (NAND). In the manufacturing of some semiconductor devices, metal or other materials may be etched below a mask. As the semiconductor industry advances and device dimensions become smaller, such recessed features become increasingly harder to etch in a uniform manner, especially for high aspect ratio features having narrow widths and / or deep depths.

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0004] To achieve the foregoing and in accordance with the purpose of the present disclosure, a method of etching recessed features in a silicon containing stack below a mask is provided. An etch gas is provided comprising providing a HC1 gas and providing a fluorine containing gas. The etch gas is transformed into a plasma. The stack is exposed to the plasma formed from the etch gas for selectively etching the recessed features in the stack with respect to the mask.

[0005] In another manifestation, an apparatus for etching recessed features in a silicon containing stack below a mask is provided. A substrate support supports a substrate inside a processing chamber. A substrate support temperature controller controls the temperature of the substrate support. A power source provides power to the process chamber. A gas source comprises an HC1 gas source and a fluorine containing gas source. S controller is controllablyconnected to the gas source, the substrate support temperature controller, and the power source and is configured to provide an etch gas, comprising flowing a HC1 gas from the HC1 gas source, flowing a fluorine containing gas from the fluorine containing gas source, transform the etch gas into a plasma using power from the power source, and expose a stack to the plasma for selectively etching the recessed features in the stack with respect to the mask.

[0006] These and other features of the present disclosure will be described in more detail below in the detailed description and in conjunction with the following figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0008] FIG. 1 depicts a flow chart describing a method of etching recessed features into a stack below a carbon containing mask according to various embodiments.

[0009] FIGS. 2A-2B illustrate a schematic cross-sectional illustration of a stack processed according to some embodiments.

[0010] FIG. 3 is a table for Experiment 1 and Experiment 2.

[0011] FIGS. 4A-C are graphs of measurement species produced in Experiment 1 and Experiment 2.

[0012] FIG. 5 shows a semiconductor processing system that may be used in some embodiments.

[0013] FIG. 6 illustrates a computer system for implementing a controller used in some embodiments.

[0014] In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale.DETAILED DESCRIPTION

[0015] The present disclosure will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without some or all of these specific details. In other instances, wellknown process steps and / or structures have not been described in detail in order to not unnecessarily obscure the present disclosure.

[0016] Fabrication of certain semiconductor devices involves etching features into a stack of materials. In various embodiments herein, the stack of materials includes one or more layers of one or more materials below a mask. In some embodiments, at least one layer of the stack contains at least one of silicon, germanium, and metal. Silicon containing layers may contain silicon with the addition of one or more of oxygen, carbon, nitrogen, and germanium, such as silicon nitride (SiN) and silicon oxynitride (SiON). In one example, the stack includes alternating layers of silicon oxide (SiO or SiCh) and polysilicon (OPOP). In some embodiments, the stack comprises an alternating silicon oxide film with silicon nitride films (ONON), or single silicon oxide layer, or single silicon nitride layer, or single silicon layer. In some embodiments, the stack may be a conductive or dielectric layer that may be a metal or silicon containing layer.

[0017] The features etched into a stack may be cylinders, trenches, or other recessed features. The aspect ratio of such a feature is defined as the lateral critical dimension divided by the depth. As the aspect ratio of such features continues to increase, several issues arise including, but not limited to, (1) insufficient mask selectivity, (2) etch resolution, (3) twisting of the features, (4) non-circularity of the features, (5) aspect-ratio dependent etch rate, (6) bowing etch profile, and (7) low etch rate.

[0018] Insufficient mask selectivity is problematic when the etch process removes an excessive amount of the mask, so that no mask remains at the end of the process, or when the amount of mask remaining is insufficient to properly transfer the pattern from the mask to the stack. Mask selectivity is a function of the mask etch rate vs the dielectric feature etch rate. The mask material can be removed from the plasma facing surface as well as inside (isotopically) the feature. Removing the mask from the surface can prevent the maximum etch depth from being reached, removing isotopically expands critical dimensions prematurely during the anisotropic etch. One common result of insufficient mask selectivity is the degradation of the feature profile near the top of the recessed features. Poor mask selectivity can also make upstream mask open processes more challenging resulting in poor pattern transfer from lithography, and also result in excessively large incoming mask bottom CDs severely limiting the subsequent anisotropic dielectric etch. In order to compensate for insufficient mask selectivity, a thicker mask may be formed. However, a thicker mask results in lower mask resolution and an overall higher aspectratio, which causes more issues during the etching of both mask and underlayer materials.

[0019] Twisting refers to random deviations between the intended bottom locations of the features and the actual final bottom locations of the features (e.g., with the final location of a feature corresponding to the position of the bottom of the feature after the feature is etched). For instance, in some cases, it is intended that cylindrical features are etched in a regular array.When some or all features randomly deviate at the bottom away from this array, they are understood to have twisted.

[0020] Non-circularity of the features refers to deviations of the bottom hole shape away from a circular hole shape. This issue is relevant when etching circular features such as cylinders, where it is desired that the bottoms of the recessed features are circular. When the bottom hole shape deviates away from a circular shape, it often forms a shape closer to an ellipse, triangle, or irregular polygon. In many cases, these non-circular shapes are not desirable.

[0021] Aspect-ratio dependent etch rate refers to an issue where the etch rate slows down as the aspect ratio of the features increases. In other words, as the features are etched further into the stack, the etching process slows down. This issue is problematic because it can lead to low throughput and associated high processing costs.

[0022] Bowing etch profile refers to the tendency for the features to etch laterally in the stack such that the final profile bows outwards excessively somewhere along the depth of the features. In other words, the actual maximum critical dimension of the features exceeds the desired maximum critical dimension of the features, which can compromise the integrity of the structures being formed or limit the electrical performance of the final devices.

[0023] Low etch rate refers to an etch rate that is slower than desired for a particular application. Low etch rate is problematic because it leads to long etch times, reduced throughput, and high processing costs.

[0024] Unfortunately, techniques that improve some of these issues, such as insufficient mask selectivity, often make other issues worse. As such, these issues are balanced against one another when designing an etching operation. For example, conventional commercially practiced dielectric etch processes often result in substantial bowing. Previously, such tradeoffs have been difficult to avoid.

[0025] In etching a stack comprising a silicon nitride layer, using a fluorine containing etch gas may create ammonium fluorosilicate salts (AFS) according to the reactionS1F4+2NH3+2HF— »(NH4)2SiFe. Ammonia (NH3) is a byproduct of etching SiN. Excessive AFS formation at the etch front reduces anisotropic etch of the etch front resulting in twisting caused by random direction changes.

[0026] The techniques described herein may be used to etch recessed features into a stack below a mask without some or all of the issues identified above. In other words, the disclosed techniques may be used to etch recessed features into a stack below a mask with a high stack to mask selectivity and with reduced mask twisting, reasonably circular features, an acceptable degree of aspect ratio dependent etch rate, acceptable bowing, and sufficient etch rate. In some embodiments, an etch is provided with an etch gas comprising a hydrogen chloride (HC1) gas and a fluorine (F) containing gas. In some embodiments, the etch gas is oxygen free.

[0027] To facilitate understanding, FIG. 1 is a high level flow chart of a method that may be used in some embodiments. A silicon containing stack with a mask is provided (step 104). FIG. 2A is a schematic cross-sectional view of a stack 204 that may be processed according to some embodiments, where the stack is under a mask 212. In some embodiments, the mask 212 is a carbon containing mask, such as photoresist or amorphous carbon. In some embodiments, the stack 204 may be formed over a substrate 208. In some embodiments, the stack 204 may comprise a silicon containing layer, such as silicon oxide, silicon nitride, or silicon. In some embodiments, the stack is a single bulk layer. In some embodiments, the stack is a plurality of layers. In some embodiments, the stack is a plurality of bilayers, trilayers, or more multiple layers. In some embodiments, one or more layers may be between the mask 212 and the stack. In some embodiments, one or more layers may be between the substrate 208 and the stack 204.

[0028] An etch process is provided for etching the stack 204. In some embodiments, a substrate support that supports the stack is cooled to a cryogenic temperature (step 108). In some embodiments, the substrate support is cooled to a cryogenic temperature below 0° C. In some embodiments, the substrate support is cooled to a temperature below -20° C. In some embodiments, the substrate support is cooled to a temperature below -40° C. In some embodiments, the substrate support is cooled to a temperature below -60° C. In some embodiments, the substrate support is cooled to a temperature below -80° C. In some embodiments, the substrate support is cooled to a temperature in the range of -20° C to 0° C. In some embodiments, the substrate support is not cooled to a cryogenic temperature but is maintained at a temperature of no more than 60° C.

[0029] An etch gas comprising an HC1 gas and a fluorine containing gas is provided (step 1 12). In some embodiments, the etch gas is oxygen free when the mask 212 is a carbon containing mask. In some embodiments, the etch gas is Ch free. In some embodiments, the fluorine containing gas comprises at least one of fluorine (F2), iodine heptafluoride (IF7), silicon tetrafluoride (SiF4), tungsten hexafluoride (WFe), molybdenum hexafluoride (MoFe), nitrogen trifluoride (NF3), sulfur hexafluoride (SFe), phosphorous trifluoride (PF3), phosphorous pentafluoride (PF5), boron trifluoride (BF3), chlorine trifluoride (CIF3) hydrogen fluoride (HF), a hydrofluorocarbon (HxCyFzwhere x, y, and z are positive integers), and a fluorocarbon (CxFywhere x and y are positive integers). In some embodiments, the etch gas may further comprise a carrier gas such as argon (Ar), xenon (Xe), Krypton (Kr), or helium (He). In some embodiments, the etch gas is provided at a pressure of less than 800 mTorr. In some embodiments, the etch gas is provided at a pressure in the range of 0.1 mTorr to 800 mTorr.

[0030] The plasma in various embodiments may be generated from the etch gas (step 116) by a periodic waveform signal, such as a radio frequency (RF) waveform with a power between about 0.1-200 kilowatts (kW), for example between about 10-100 kW, or between about 10-65 kW. In some cases, a dual-frequency RF waveform may be used to generate the plasma. The periodic waveform signal may be sinusoidal or have any designed shape. The shape of the waveform may contain narrow, high voltage peaks. Thus, the RF power may be provided at two or more frequency components, for example, a first frequency component at about 200-400 kilohertz (kHz) and a second frequency component at about 60 megahertz (MHz). Different powers may be provided at each frequency component. For instance, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 10-65 kW, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, for example between about 0.5-8 kW. In some embodiments, the first frequency component (e.g., about 400 kHz) may be provided at a power higher than 65 kW. The lower frequency component of the applied waveform results in a negative bias applied to the substrate resulting in ion acceleration to the substrate. These power levels assume that the RF power is delivered to a single 300 millimeter (mm) wafer. In other cases, three-frequency RF power may be used to generate the plasma.

[0031] In some embodiments, the power may be applied continuously. In some embodiments, the applied RF power may be pulsed. In some embodiments, the pulsed RF may have two, three,or even more states, providing multistate pulsed RF power. For example, a three state pulsing pulses between three different (high, medium, low) power levels. In some embodiments, the high power level has a 1% to 30% duty cycle, the medium power level has a 10% to 90% duty cycle, and the low power level has a 20% to 90% duty cycle. In some embodiments, one of the three power levels is 0 Watts. In some embodiments, the high power level is 2 to 20 times the low power levels, and the medium power level is between the high power level and the low power level. In some embodiments, the RF power is pulsed at repetition rates of 1-50,000 Hz. The RF power may be pulsed between two non-zero values (e.g., between higher power and lower power states) or between zero and a non-zero value (e.g., between off and on states). Where the RF power is pulsed between two non-zero values, the powers may be a higher power state and a lower power state. The lower power state may correspond to an RF power of about 4 kW or lower. A pulsing duty cycle may be in the range of 1-50%. The pulsing may be at a repetition rate in the range of 100 Hz to 20 kHz. The maximum ion energy at the substrate may be relatively high, for example between about 1-30 kilo electron volts (keV). The maximum ion energy is determined by the applied RF power in combination with the details of RF excitation frequencies, electrode sizes, electrode placement, chamber geometry, and plasma interactions. The periodic waveform signal may be pulsed or continuous.

[0032] The stack 204 is exposed to the plasma (step 120) causing recessed features to be selectively etched into the stack 204 with respect to the mask 212. FIG. 2B is a schematic cross- sectional view of a stack 204 after the recessed features 220 have been etched.

[0033] The formation of ammonium salts according to the reaction SiF4+2NH3+2HF— >(NH4)2SiFe increases feature distortion such as causing profile twisting, noncircularity, and a tapered etch front. Since the formation of ammonium salts at cryogenic temperatures increases feature distortion, the reduction of the formation of ammonium salts reduces distortion, so that there is less distortion, less non-circularity, and a wider and flatter etch front. Therefore, some embodiments provide a cryogenic etch with a fast etch rate and reduced distortion. To reduce the AFS formation and improve the dimple twist, chlorine has been added in the form of chlorine (Ch) is added to the discharge. Chlorine provides a competing salt formation reaction with different kinetics and byproducts, reducing AFS formation and improving dimple twist. However, when the Ch flow rate is increased to counteract AFS and improve twisting, mask selectivity, and bow CD are increased. Someembodiments replace Ch gas with an HC1 gas as a chlorine source to increase the mask selectivity without increasing dimple twist and bow growth rate.

[0034] FIG. 3 shows Table 1, that compares an etch process that uses Ch as the chlorine source to an etch process that uses HC1 as the chlorine source. Changing chlorine sources results in significant changes in etch performance with a 33% increase in etch selectivity through a 27% reduction in mask loss rate and a 20% reduction in profile twisting with minimal changes in etch rate, maximum CD, and hole shape distortion.

[0035] FIG.4A shows the plasma reactor simulated ion density for Ch+and Cl+ions using either Ch or HC1 as a chlorine source where all other reactor conditions were kept constant. Plasma simulation of reaction pathways and ion generation mechanisms gives insight into complex plasma compositions where direct measurement of species density can be challenging or impossible. Simulations show that a Ch chlorine source generates an order of magnitude higher Cl+species than HC1 and almost 3 orders of magnitude higher Ch+species than an HC1 source.

[0036] FIG.4B shows the plasma reactor simulated neutral density for Cl and HC1 using either Ch or HC1 as a chlorine source keeping all other reactor conditions constant. Simulations show that the HC1 source maintains higher densities of HC1 with reduced Cl radical generation, whereas reaction pathways with Ch and available hydrogen sources produce three times less HC1 with a concomitant increase in Cl radical generation. This change in ion and neutral species densities with chlorine source is important to provide beneficial pathways to improve the etch process.

[0037] FIG. 4C shows the maximum optical emission intensity of the C-Cl species located at a wavelength of 278nm collected during an etch process that uses either Ch or HC1 as a chlorine source. Using Ch as a chlorine source results in a significant increase in C-Cl emission from the plasma. C-Cl is an etch byproduct of carbon sources within the process chamber that includes the carbon mask. Decreased C-Cl emission when Ch is replaced with HC1 as the chlorine source correlates to the 27% reduction in mask etch rate observed.

[0038] When etching a silicon containing stack in the presence of nitrogen using fluorine as the etchant, AFS salts may form by the reaction SiF4 + 2NFh+2HF<->(NH4)2SiFe, where silicon tetrafluoride (SiF4) and ammonia (NH3) are byproducts. Providing chlorine, as Ch, in the etch gas allows chlorine to occupy open sites so that fluorine cannot react, resulting in the productionof less SiF4. In addition, chlorine causes the formation of ammonium chloride (NH4CI). As a result, less AFS is formed. However, the addition of CI2 causes an increase in the etching of the carbon mask or sidewall deposition. Providing HC1 in the etch gas may create NH4CI according to the reaction NHS+HC1 ->NH4C1, resulting in the formation of less (NH4)2SiFe. By replacing Ch with HC1, the density of HC1 in the plasma is three times the density of HC1 in a plasma formed using CI2. Therefore, providing HC1 gas in the etch gas may reduce the production of AFS and reduce the resulting distortion more than providing CI2 gas. The use of HC1 may be extended to other mask materials beyond using a carbon mask. The AFS suppression is generated from two pathways: 1) Cl occupying sites and preventing F from attaching and forming SiF4, which is needed to create AFS. 2) HC1 formation which reacts with NH3 (nitride etch byproduct) and forms ammonium chloride (NH4CI), preventing formation of AFS. In both mechanisms, only Cl or HC1 is needed. Therefore, replacing CI2 with HC1 will not negatively affect the dimple twist. The nitrogen in the formation of AFS may come from etching silicon nitride or silicon oxynitride.

[0039] In some embodiments, a passivation step may be provided to protect the mask, increasing selectivity, and / or feature sidewalls, improving feature shape. In some embodiments, the passivation step is provided simultaneously with the etching step. In some embodiments, the passivation step is provided sequentially and cyclically with respect to the etching step, where the etching step comprises providing the etch gas, transforming the etch gas into a plasma, and exposing the stack to the plasma. In some embodiments, the cycle is repeated at least once. In some embodiments, the cycle is repeated a plurality of times.Applications

[0040] One application for the disclosed methods is in the context of forming a vertical NAND device. In this case, the material into which the feature is etched may be a repeating layered structure. For instance, the material may include alternating layers of silicon oxide and silicon nitride (ONON). In other embodiments, the stack may comprise alternating layers of silicon oxide and polysilicon (OPOP). The alternating layers form pairs or repeating groups of materials. In various cases, the number of pairs or repeating groups may be between about 10- 500 (e.g., between about 20-1000 individual layers). The features etched into the stack of layers may have a depth between about 2-20 pm, for example between about 5-9 pm. The features mayhave a width between about 40-450 nm, for example between about 50-100 nm or between about 40-85 nm. In some embodiments, the features have a width of less than 100 nm. In some embodiments, the features have a width of less than 85 nm.

[0041] As used herein, “high aspect ratio” as applied to features in a substrate refers to aspect ratios of depth to width on the order of approximately 60: 1 or higher. More preferably, this range may include ratios greater than 100: 1, 120:1, 140:1 , etc., or higher. However, the processes described herein may be beneficial for lower aspect ratios, such as 30:1, or 10:1.

[0042] The dimensional / parametric details provided herein, such as high aspect ratio, thickness, width, depth, etc., are for example and illustration only. Based on the disclosure described herein, it should be understood that varying dimensions / parameters may also be applicable or used.APPARATUS

[0043] The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tools / processes will be used or conducted together in a common fabrication facility.

[0044] Lithographic patterning of a film typically comprises some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a workpiece, e.g., a substrate having a silicon containing film formed thereon, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or other suitable curing tool; (3) exposing the photoresist to visible or ultraviolet (UV) or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove the resist and thereby pattern it using a tool such as a wet bench or a spray developer; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashable hard mask layer (such as an amorphous carbon layer) and another suitable hard mask (such as an antireflective layer) may be deposited prior to applying the photoresist.

[0045] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer toa silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, 300 mm, or 450 mm. The above detailed description assumes the embodiments are implemented on a wafer. However, the embodiments are not so limited. The workpiece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0046] Unless otherwise defined for a particular parameter, the terms “about” and “approximately” as used herein are intended to mean ±10% with respect to a relevant value.

[0047] FIG. 5 is a schematic view of a processing chamber 500 for processing substrates, in an embodiment. In one or more embodiments, the processing chamber 500 comprises a gas distribution plate 506 providing a gas inlet and an electrostatic chuck (ESC) 516, within a processing chamber 504, enclosed by a chamber wall 550. Within the processing chamber 504, the substrate 208 is positioned on top of the ESC 516 so that the ESC 516 is also a substrate support. The ESC 516 may provide a bias from an ESC power source 548. A gas source 510 is connected to the processing chamber 504 through the gas distribution plate 506. In some embodiments, the gas source 510 comprises a HC1 gas source 512, a fluorine containing gas source 518, and possible other gas source 513, such as a carrier gas source. An ESC temperature controller 551 (substrate support temperature controller) is connected to the ESC 516 and provides temperature control of the ESC 516, allowing for the ESC 516 to be cooled to cryogenic temperatures. A power source 530, such as an RF power source, provides a periodic waveform signal, such as RF power, to the ESC 516 and an upper electrode. In this embodiment, the upper electrode is the gas distribution plate 506. In a preferred embodiment, 400 kilohertz (kHz), 13.56 megahertz (MHz), 1 MHz, 2 MHz, 60 MHz, and / or optionally, 27 MHz power sources make up the power source 530 and the ESC power source 548 to provide periodic waveform signals at RF frequencies. A controller 535 is controllably connected to the power source 530, the ESC power source 548, an exhaust pump 520, and the gas source 510. A high flow liner 560 is a liner within the processing chamber 504, which confines gas from the gas source and has slots 562. The slots 562 maintain a controlled flow of gas to pass from the gas source 510 to the exhaust pump 520. An example of such a processing chamber is the Flex® etchsystem manufactured by Lam Research Corporation of Fremont, CA. The process chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0048] FIG. 6 is a high level block diagram illustrating a computer system 600 for implementing the controller 535 used in embodiments of the present inventions. The computer system may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge supercomputer. The computer system 600 may include one or more processors 602 and further can include an electronic display device 604 (for displaying graphics, text, and other data), a main memory 606 (e.g., random access memory (RAM)), storage device 608 (e.g., hard disk drive), removable storage device 610 (e.g., optical disk drive), user interface devices 612 e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and / or a communication interface 614 (e.g., wireless network interface). The communication interface 614 may allow software and / or data to be transferred between the computer system 600 and external devices via a link. The system may also include a communications infrastructure 616 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices / modules may be connected.

[0049] Information transferred via communications interface 614 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 614, via a communication link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and / or other communication channels. With such a communications interface, it is contemplated that the one or more processors 602 might receive information from a network or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments may execute solely upon the processors or may execute over a network such as the Internet in conjunction with remote processors that share a portion of the processing.

[0050] The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM, and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter.Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.

[0051] In some embodiments, the controller 535 is configured to provide an etch gas by flowing HC1 gas and a fluorine containing gas, transforming the etch gas into a plasma, and exposing a stack to the plasma formed from the etch gas to selectively etch features in the stack with respect to the mask.

[0052] It is to be understood that the configurations and / or approaches described herein are exemplary in nature and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated may be performed in the sequence illustrated, in other sequences, in parallel, or in some cases omitted. Likewise, the order of the above described processes may be changed. Certain references have been incorporated by reference herein. It is understood that any disclaimers or disavowals made in such references do not necessarily apply to the embodiments described herein. Similarly, any features described as necessary in such references may be omitted in the embodiments herein. The subject matter of the present disclosure includes all novel and nonobvious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, as well as any and all equivalents thereof.CONCLUSION

[0053] While this disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents, which fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase “A, B, or C” should be construed to mean a logical (“A OR B OR C”), using a non-exclusive logical “OR,” and should not be construed to mean ‘only one of A or B or C. Each step within a process may be an optional step and is not required. Different embodiments may have one or more steps removed or mayprovide steps in a different order. In addition, various embodiments may provide different steps simultaneously instead of sequentially.

Claims

CLAIMSWhat is claimed is:

1. A method of etching recessed features in a silicon containing stack below a mask, comprising: a. providing an etch gas comprising: i. providing a HC1 gas; and ii. providing a fluorine containing gas; b. transforming the etch gas into a plasma; and c. exposing the stack to the plasma formed from the etch gas for selectively etching the recessed features in the stack with respect to the mask.

2. The method of claim 1, further comprising: placing the stack over a substrate support; and cooling the substrate support to a temperature below 0° C.

3. The method of claim 1, wherein the etch gas is Ch free.

4. The method of claim 1 , wherein the etch gas is oxygen free.

5. The method of claim 1, wherein the fluorine containing gas comprises at least one of Fz,IF?, SiF4, WFe, MoFe, NF3, SFe, PF3, PF5, BF3, CIF3, HF, a hydrofluorocarbon, and a fluorocarbon.

6. The method of claim 1 , wherein the stack comprises SiCh and SiN.

7. The method of claim 1, wherein the stack is an ONON stack.

8. The method of claim 1, further comprising providing a passivation step during exposing the stack to the plasma formed from the etch gas.

9. The method of claim 1, further comprising providing a passivation step sequentially after exposing the stack to the plasma formed from the etch gas in a cycle and repeating the cycle at least once.

10. The method of claim 1, wherein the mask is a carbon containing mask.

11. The method of claim 1 , wherein the stack comprises at least one of SiON and SiN.

12. An apparatus for etching recessed features in a silicon containing stack below a mask, comprising: a process chamber; a substrate support for supporting a substrate inside the processing chamber;a substrate support temperature controller; a power source for providing power to the process chamber; a gas source comprising: a HC1 gas source; and a fluorine containing gas source; and a controller, controllably connected to the gas source, the substrate support temperature controller, and power source, configured to: provide an etch gas, comprising: flowing a HC1 gas from the HC1 gas source; flowing a fluorine containing gas from the fluorine containing gas source; transform the etch gas into a plasma using power from the power source; and expose a stack to the plasma for selectively etching the recessed features in the stack with respect to the mask.

13. The apparatus of claim 12, wherein the controller is further configured to cool the substrate support to a temperature below 0° C.

14. The apparatus of claim 12, wherein the etch gas is Ck free.

15. The apparatus of claim 12, wherein the controller is further configured to provide a passivation while exposing the stack to the plasma formed from the etch gas.

16. The apparatus of claim 12, wherein the controller is further configured to provide a passivation sequentially after exposing the stack to the plasma formed from the etch gas in a cycle and repeating the cycle at least once.

17. The apparatus of claim 12, wherein the etch gas is oxygen free.

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