Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises a base substrate (1), a first insulating layer (2), and an active layer (3); the first insulating layer (2) is arranged on one side of the base substrate (1); a first recessed portion (21) is provided on the first insulating layer (2); the first recessed portion (21) has at least one first sidewall (211); the distance between the first sidewall (211) and the base substrate (1) increases as the distance between the first sidewall (211) and the edge of the first recessed portion (21) decreases; the included angle between the first sidewall (211) and the base substrate (1) is greater than or equal to 5° and less than or equal to 20°; and at least part of the active layer (3) at least located on the first sidewall (211) is facing away from one side of the base substrate (1). The carrier mobility of a thin-film transistor of the array substrate is high, thereby reducing the power consumption of the array substrate and improving the overall performance.

Description

Array substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to an array substrate and a display device. BACKGROUND

[0002] Low Temperature Poly-Silicon (LTPS) material has a higher mobility 50cm 2 / V·s~200cm 2 / V·s, which is beneficial to the miniaturization of Thin Film Transistor (TFT), thereby improving the aperture ratio of the display device, strengthening the definition, etc.; however, with the development of the display industry, there is an increasing demand for higher resolution VR (Virtual Reality) / AR (Augmented Reality) products, and higher resolution means that a TFT with higher mobility is needed. In particular, with the rise of micro-LED (micro-Light Emitting Diode) display technology, a TFT with higher performance, especially higher mobility, is needed to drive micro-LED, which puts higher requirements on the performance of LTPS-TFT.

[0003] At present, the TFT in the array substrate cannot meet the above requirements.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0005] SUMMARY

[0006] The present disclosure aims to overcome the shortcomings of the prior art and provide an array substrate and a display device.

[0007] According to one aspect of the present disclosure, an array substrate is provided, comprising:

[0008] a substrate substrate;

[0009] a first insulating layer provided on one side of the substrate substrate, the first insulating layer being provided with a first recessed portion, the first recessed portion having at least one first side wall, the distance between the first side wall and the substrate substrate increasing as the distance from the edge of the first recessed portion decreases, and the included angle between the first side wall and the substrate substrate being greater than or equal to 5° and less than or equal to 20°;

[0010] An active layer is located at least on a side of the first sidewall facing away from the substrate.

[0011] In an example embodiment of the present disclosure, the first insulating layer has a thermal conductivity greater than or equal to 1 W / (m·K) and less than or equal to 3 W / (m·K).

[0012] In an example embodiment of the present disclosure, the first sidewall has a width greater than or equal to 0.5 μm and less than or equal to 10 μm, the width being a dimension between an opening edge of the first recess and a bottom wall edge of the first recess.

[0013] In an example embodiment of the present disclosure, the first sidewall is recessed toward a side close to the substrate or the first sidewall protrudes toward a side away from the substrate.

[0014] In an example embodiment of the present disclosure, the first insulating layer has a first plane facing away from the substrate, and the first sidewall is smoothly connected to the first plane; a portion of the active layer located on a side of the first sidewall away from the substrate does not form a grain boundary, and forms a sub-grain boundary; a portion of the active layer located on a side of the first plane away from the substrate forms a grain boundary; and / or, a portion of the active layer located on a side of the bottom wall of the first recess away from the substrate forms a grain boundary.

[0015] In an example embodiment of the present disclosure, the active layer forms a grain boundary column, a projection of the grain boundary column on the substrate at least partially overlaps with a projection of a connecting line of the first sidewall and the first plane on the substrate; and / or, a projection of the grain boundary column on the substrate at least partially overlaps with a projection of a connecting line of the first sidewall and the bottom wall of the first recess on the substrate.

[0016] In an example embodiment of the present disclosure, the active layer comprises a first conductive connection portion, a channel portion and a second conductive connection portion connected in sequence, the second conductive connection portion is closer to the bottom wall of the first recess relative to the first conductive connection portion, the channel portion is located on a side of the first sidewall away from the substrate, the channel portion comprises a crystal grain, and a size of the crystal grain is in a micron level.

[0017] In an example embodiment of the present disclosure, the array substrate further comprises:

[0018] A planarization layer group is located on a side of the active layer away from the substrate, the planarization layer group fills the first recess, and a side of the planarization layer group away from the substrate is a plane.

[0019] In an example embodiment of the present disclosure, the first conductive connection part is a source connection part, the second conductive connection part is a drain connection part, and the array substrate further comprises:

[0020] a gate insulating layer group disposed on a side of the active layer away from the substrate substrate, and a first via hole disposed on the gate insulating layer group;

[0021] a gate electrode layer disposed on a side of the gate insulating layer group away from the substrate substrate, and a gate electrode included in the gate electrode layer;

[0022] a second insulating layer group disposed on a side of the gate electrode layer away from the substrate substrate, and a second via hole disposed on the second insulating layer group and connected to the first via hole;

[0023] a first conductive layer disposed on a side of the second insulating layer away from the substrate substrate, and a source electrode and a drain electrode included in the first conductive layer, the source electrode connected to the source connection part through the first via hole and the second via hole, and the drain electrode connected to the drain connection part through the first via hole and the second via hole.

[0024] In an example embodiment of the present disclosure, the first side walls are oppositely disposed in two; the active layers are spaced apart in two, and each of the two active layers is located on at least one side of at least part of the two first side walls away from the substrate substrate, or the active layer is located on at least one side of at least part of the two first side walls away from the substrate substrate and covers the bottom wall of the first recess;

[0025] The gate electrodes are disposed in two, and each of the two gate electrodes is oppositely disposed with each of the two channel parts; or the gate electrode is disposed in one, and the one gate electrode is oppositely disposed with the two channel parts;

[0026] The drain electrodes are disposed in two, and each of the two drain electrodes is connected with each of the two second conductive connection parts; or the drain electrode is disposed in one, and the one drain electrode is connected with the two second conductive connection parts.

[0027] In an example embodiment of the present disclosure, the array substrate further comprises:

[0028] a first conductor part disposed on a side of the substrate substrate, the first insulating layer disposed on a side of the first conductor part away from the substrate substrate, the bottom wall of the first recess penetrating to the first conductor part, and at least part of the first conductor part connected with the second conductive connection part;

[0029] a second conductor part disposed on a side of the first insulating layer away from the substrate substrate, and at least part of the second conductor part connected with the first conductive connection part;

[0030] a gate insulating layer group disposed on a side of the second conductor portion and the active layer away from the substrate;

[0031] a gate layer disposed on a side of the gate insulating layer group away from the substrate, the gate layer comprising a gate;

[0032] a second insulating layer group disposed on a side of the gate layer away from the substrate.

[0033] In an exemplary embodiment of the present disclosure, the first conductor portion comprises a source and a first trace, the second conductive connection portion is a source connection portion, the second conductor portion comprises a drain and a second trace, and the first conductive connection portion is a drain connection portion; or, the first conductor portion comprises a drain and a first trace, the second conductive connection portion is a drain connection portion, the second conductor portion comprises a source and a second trace, and the first conductive connection portion is a source connection portion.

[0034] In an exemplary embodiment of the present disclosure, the second conductor portion is made of metal, at least part of the first conductive connection portion is located on a side of the second conductor portion away from the substrate, and the thickness of the overlap portion between the second conductor portion and the first conductive connection portion is greater than or equal to 500 angstroms and less than or equal to 1000 angstroms; or, the second conductor portion is made of doped low-temperature polysilicon or doped low-temperature polycrystalline oxide.

[0035] In an exemplary embodiment of the present disclosure, the first sidewalls are oppositely arranged in two; the active layers are arranged in two, and each of the two active layers is located on at least part of a side of at least one of the two first sidewalls away from the substrate, or the active layers are located on at least part of a side of at least one of the two first sidewalls away from the substrate and cover the bottom wall of the first recess;

[0036] The gates are arranged in two, and each of the two gates is oppositely arranged with one of the two channel portions; or, the gates are arranged in one, and one of the gates is oppositely arranged with the two channel portions.

[0037] The source or the drain of the first conductor portion is arranged in two, and each of the two sources or the two drains is connected with one of the two second conductive connection portions; or, the source or the drain of the first conductor portion is arranged in one, and one of the sources or the drains is connected with the two second conductive connection portions.

[0038] In an exemplary embodiment of the present disclosure, the gate insulating layer group comprises:

[0039] at least one inorganic insulating layer disposed on a side of the active layer away from the substrate, the inorganic insulating layer being provided with a second recess, a projection of the second recess on the substrate being located within a projection of the first recess on the substrate.

[0040] In an example embodiment of the present disclosure, the gate insulating layer group further comprises:

[0041] a filling insulating layer disposed on a side of the inorganic insulating layer away from the substrate, the filling insulating layer filling the second recess, so that a side of the gate insulating layer group away from the substrate is planar, and the gate insulating layer group is the planarization layer group.

[0042] In an example embodiment of the present disclosure, in a third direction perpendicular to the substrate, a minimum thickness of the gate insulating layer group between the drain connection and the gate is greater than a maximum thickness of the gate insulating layer group between the source connection and the gate.

[0043] In an example embodiment of the present disclosure, the second recess has at least one second side wall, a distance between the second side wall and the substrate increases as a distance from an edge of the second recess decreases, and an included angle between the second side wall and the substrate is greater than or equal to 5° and less than or equal to 20°; the gate is disposed on a side of at least part of the second side wall away from the substrate; and the second insulating layer group comprises:

[0044] at least one inorganic layer disposed on a side of the gate layer away from the substrate, the inorganic layer being provided with a third recess, a projection of the third recess on the substrate being located within a projection of the second recess on the substrate;

[0045] a filling layer disposed on a side of the inorganic layer away from the substrate, the filling layer filling the third recess, so that a side of the second insulating layer group away from the substrate is planar, and the second insulating layer group is the planarization layer group.

[0046] In an example embodiment of the present disclosure, the first conductive connection is a drain connection, the second conductive connection is a source connection, and the array substrate further comprises:

[0047] a gate layer disposed on a side of the substrate, the gate layer comprising a gate, and the first insulating layer being disposed on a side of the gate layer away from the substrate;

[0048] a second insulating layer group disposed on a side of the active layer away from the substrate, the second insulating layer group being provided with a second via hole;

[0049] A first conductive layer is disposed on a side of the second insulating layer group away from the substrate, and the first conductive layer includes a source electrode and a drain electrode, the source electrode is connected to the source electrode connecting part through the second via, and the drain electrode is connected to the drain electrode connecting part through the second via.

[0050] In an exemplary embodiment of the present disclosure, the second insulating layer group includes:

[0051] At least one inorganic layer is disposed on a side of the active layer away from the substrate, and a third recessed part is disposed on the inorganic layer, and a projection of the third recessed part on the substrate is located within a projection of the first recessed part on the substrate.

[0052] A filling layer is disposed on a side of the inorganic layer away from the substrate, and the filling layer fills the third recessed part, so that a side of the second insulating layer group away from the substrate is a flat surface, and the second insulating layer group is the planarization layer group.

[0053] In an exemplary embodiment of the present disclosure, in a third direction perpendicular to the substrate, a minimum thickness of the first insulating layer between the drain electrode connecting part and the gate electrode is greater than a maximum thickness of the first insulating layer between the source electrode connecting part and the gate electrode.

[0054] In an exemplary embodiment of the present disclosure, the first side walls are oppositely disposed as two, and the active layers are spaced apart as two, and each of the two active layers is located on at least a side of at least part of the two first side walls away from the substrate, or the active layer is located on at least a side of at least part of the two first side walls away from the substrate and covers a bottom wall of the first recessed part.

[0055] The gate electrodes are disposed as two, and each of the two gate electrodes is oppositely disposed with each of the two channel parts, or the gate electrode is disposed as one, and the one gate electrode is oppositely disposed with the two channel parts.

[0056] The source electrodes are disposed as two, and each of the two source electrodes is connected with each of the two first conductive connecting parts, or the source electrode is disposed as one, and the one source electrode is connected with the two first conductive connecting parts.

[0057] According to another aspect of the present disclosure, a display device is provided, including the array substrate of any one of the above.

[0058] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0059] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure. It is to be understood that the drawings are only schematic, and that they do not purport to be to scale with respect to one another. The embodiments will be described with reference to the drawings in conjunction with the detailed description, which serves to explain the principles of the present disclosure.

[0060] FIG. 1 is a structural schematic diagram of a first exemplary embodiment of an array substrate according to the present disclosure.

[0061] FIG. 2 is a schematic diagram of laser energy decomposition when performing a laser annealing process on an active material layer.

[0062] FIG. 3 is a structural schematic diagram of polysilicon formed when the laser energy is high.

[0063] FIG. 4 is a structural schematic diagram of polysilicon formed when the laser energy is medium.

[0064] FIG. 5 is a structural schematic diagram of polysilicon formed when the laser energy is low.

[0065] FIG. 6 is a structural schematic diagram of a detailed structure of a first recess portion in FIG. 1.

[0066] FIG. 7 is a structural schematic diagram of a detailed structure of another exemplary embodiment of the first recess portion in FIG. 1.

[0067] FIG. 8 is a schematic diagram of a cross-sectional view of the array substrate according to the present disclosure after forming an active layer.

[0068] FIG. 9 is a structural schematic diagram of a second exemplary embodiment of an array substrate according to the present disclosure.

[0069] FIG. 10 is a structural schematic diagram of a third exemplary embodiment of an array substrate according to the present disclosure.

[0070] FIG. 11 is a structural schematic diagram of a fourth exemplary embodiment of an array substrate according to the present disclosure.

[0071] FIG. 12 is a structural schematic diagram of a fifth exemplary embodiment of an array substrate according to the present disclosure.

[0072] FIG. 13 is a structural schematic diagram of a sixth exemplary embodiment of an array substrate according to the present disclosure.

[0073] FIG. 14 is a structural schematic diagram of a seventh exemplary embodiment of an array substrate according to the present disclosure.

[0074] FIG. 15 is a structural schematic diagram of an eighth exemplary embodiment of an array substrate according to the present disclosure.

[0075] FIGS. 16-19 are structural schematic diagrams of various processes for manufacturing the array substrate in FIG. 1.

[0076] FIGS. 20 to 22 are structural schematic views of respective processes of manufacturing the array substrate in FIG. 13.

[0077] FIG. 23 is a structural schematic view of one process of manufacturing the array substrate in FIG. 11.

[0078] BRIEF DESCRIPTION OF DRAWINGS 1, substrate; 2, first insulating layer; 21, first recessed portion; 211, first sidewall; 2111, first portion; 2112, second portion; 22, first plane; 3a, active material layer; 3b, transition layer; 3, active layer; 31, first conductive connection portion; 32, channel portion; 33, second conductive connection portion; 34, crystal grain; 35, grain boundary; 36, sub-grain boundary; 37, grain boundary row; 4, gate insulating layer group; 41, first via; 42, inorganic insulating layer; 421, second recessed portion; 4211, second sidewall; 422, first sub-via; 43, filling insulating layer; 431, second sub-via; 5, gate electrode layer; 51, gate electrode; 6, second insulating layer group; 61, second via; 62, inorganic layer; 621, third recessed portion; 622, third sub-via; 63, filling layer; 631, fourth sub-via; 7, first conductive layer; 71, source electrode; 72, drain electrode; 8, first conductor portion; 81, first wiring; 9, second conductor portion; 91, second wiring; 10, buffer layer; 11, planarization layer group; Z, third direction. DETAILED DESCRIPTION

[0079] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the specification. Moreover, the figures can not be to scale and some features can be exaggerated to show details of particular implementations. Measures of thicknesses and lengths and the like can not be drawn to scale for clarity.

[0080] Although relative terms such as "on", "under", "lower", "upper" and the like can be used herein to describe one element's relationship to another element as the device is positioned on a plane, a surface, and / or a frame of reference, the device can be oriented in any direction and the relative terms are used herein for convenience to describe the orientations of the device as shown in the drawings. It will be understood that, if the device were turned over, such that the "upper" portion is then an "under" portion, the "under" portion, according to this description, would be the "upper" portion. When a structure is "on" another structure, it can mean that the structure is formed directly on the other structure, or that the structure is "directly on" the other structure, or that the structure is "indirectly on" the other structure by having one or more structures intervening therebetween.

[0081] The terms "one", "a", "an", "the", and "at least one" are used to indicate that "one or more" of the identified element(s) / component(s) / etc. is / are present; the terms "includes", "including", and "has" are used inclusively to mean that something can be present and / or there can be additional items present; the terms "first", "second", and "third" are used merely as labels, and are not meant to impose numerical limitations of their objects.

[0082] In the present application, unless specifically defined otherwise and limited in the present application, the term "connected" should be interpreted broadly, for example, "connected" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through intermediate media. "And / or", is only a description of the relationship between the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent: A exists alone, A and B exist together, B exists alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0083] The example embodiments of the present disclosure provide an array substrate, which can include a substrate 1, a first insulating layer 2, and an active layer 3, as shown in FIGS. 1-23. The first insulating layer 2 is arranged on one side of the substrate 1, and the first insulating layer 2 is provided with a first recess 21, the first recess 21 has at least one first side wall 211, the distance between the first side wall 211 and the substrate 1 increases as the distance from the edge of the first recess 21 decreases, and the included angle between the first side wall 211 and the substrate 1 is greater than or equal to 5° and less than or equal to 20°. The active layer 3 is at least located on at least one side of the first side wall 211 away from the substrate 1.

[0084] The array substrate of the present disclosure, on the one hand, the first side wall 211 makes the laser energy received by the active material layer 3a be moderate, so that the crystal nucleus formed by the active material layer 3a on the first side wall 211 is less, and the crystal nucleus can grow along the first side wall 211, so that the size of the crystal grain 34 included in the active layer 3 is larger, and the mobility of the carrier of the formed thin film transistor is larger, thereby reducing the power consumption of the array substrate and improving the overall performance. On the other hand, the included angle between the first side wall 211 and the substrate 1 is greater than or equal to 5° and less than or equal to 20°, which not only ensures that the active layer 3 will not be easily broken at the corner position, but also ensures that the size of the crystal grain 34 included in the active layer 3 is larger, and the mobility of the carrier of the formed thin film transistor is larger, thereby reducing the power consumption of the array substrate and improving the overall performance.

[0085] In the example embodiment, the material of the substrate 1 can include inorganic materials, for example, the inorganic materials can be glass, quartz or metal, etc. The material of the substrate 1 can also include organic materials, for example, the organic materials can be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate, etc. The substrate 1 can be formed by multiple layers of materials, for example, the substrate 1 can include multiple layers of base material, and the material of the base material can be any of the above materials. Of course, the substrate 1 can also be provided as a single layer, which can be any of the above materials.

[0086] The first insulating layer 2 is provided on one side of the substrate 1, and the thickness of the first insulating layer 2 can be greater than or equal to 100 nm and less than or equal to 1000 nm, for example, the thickness of the first insulating layer 2 can be 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, etc.

[0087] The first recessed portion 21 is provided on the first insulating layer 2, specifically, the first recessed portion 21 is provided on the side of the first insulating layer 2 away from the substrate 1. The first recessed portion 21 has at least one first side wall 211, for example, the first recessed portion 21 can have one first side wall 211, the first recessed portion 21 can also have two first side walls 211, and the two first side walls 211 can be oppositely arranged, or the two first side walls 211 can be adjacently arranged; the first recessed portion 21 can also have three or more first side walls 211.

[0088] The distance between the first side wall 211 and the substrate 1 increases as the distance between the first side wall 211 and the edge of the first recessed portion 21 decreases, that is, the closer to the edge of the first recessed portion 21, the thicker the thickness of the retained first insulating layer 2, so that the first recessed portion 21 forms a structure with an opening larger than the bottom.

[0089] The first insulating layer 2 has a first plane 22 away from the substrate 1, that is, the first plane 22 is the side of the first insulating layer 2 away from the substrate 1, and the first side wall 211 is smoothly connected to the first plane 22, for example, the first side wall 211 and the first plane 22 can be tangentially connected, so that the first side wall 211 and the first plane 22 are smoothly connected without forming a protruding or recessed structure, avoiding affecting the formation of subsequent film layers.

[0090] The active layer 3 is located at least on one side of at least one of the first side walls 211 facing away from the substrate 1; for example, the active layer 3 can be located only on one side of a part of the first side walls 211 facing away from the substrate 1; the active layer 3 can also be located on one side of all of the first side walls 211 facing away from the substrate 1; the active layer 3 can also be located on one side of all of the first side walls 211 facing away from the substrate 1, and the active layer 3 can also be provided on the bottom wall of the first recess 21 and on the first plane 22 of the first insulating layer 2 facing away from the substrate 1.

[0091] In the case where the first recess 21 has one first side wall 211, the active layer 3 is provided as one.

[0092] Referring to FIG. 1, in the case where the first recess 21 has two first side walls 211, the active layer 3 can also be provided as two, and the two active layers 3 are provided in a spaced manner, and the two active layers 3 are located one by one on at least one side of at least one of the two first side walls 211 facing away from the substrate 1. Of course, referring to FIGS. 11-14, in the case where the first side wall 211 is provided as two, one active layer 3 can also be provided, and the active layer 3 is located on at least one side of at least one of the two first side walls 211 facing away from the substrate 1, and the active layer 3 covers the bottom wall of the first recess 211, thereby connecting the active layers 3 on the two first side walls 211 into one.

[0093] In the case where the first recess 21 has three or more first side walls 211, the active layer 3 can also be provided as three or more, and of course, in the case where the first side wall 211 is provided as three or more, one active layer 3 can also be provided.

[0094] Hereinafter, the case where the first recess 21 has two first side walls 211 is taken as an example for description.

[0095] Referring to FIG. 2, when the active material layer 3a of the first side wall 211 is subjected to the excimer laser annealing process to melt and crystallize the amorphous silicon into polycrystalline silicon, the excimer laser emits laser light in a direction perpendicular to the substrate 1, and the laser energy E received by the active material layer 3a of the first side wall 211 is the component Ecosα of the laser energy E emitted by the excimer laser perpendicular to the first side wall 211, i.e. E1=Ecosα.

[0096] Referring to FIG. 3, when the laser energy received by the active material layer 3a is high, the active material layer 3a will be completely melted instantaneously, and a large number of crystal nuclei will be generated at the same time on the surface, middle and bottom layer of the active material layer 3a, and the excessive number of crystal nuclei will result in very small crystal grains 34.

[0097] Referring to FIG. 4, when the laser energy received by the active material layer 3a is moderate, the active material layer 3a is almost completely melted, leaving only very few residual crystals as nuclei, so the nucleation rate is extremely low; when the temperature drops, the nuclei begin to grow and quickly reach the top of the film, and the crystal grains 34 will mainly grow in the transverse direction and eventually obtain large crystal grains 34.

[0098] Referring to FIG. 5, when the laser energy received by the active material layer 3a is low, a large number of nuclei will be formed on the surface of the active material layer 3a, and eventually small crystal grains 34 will be formed.

[0099] Therefore, the active layer 3 is at least located on at least one side of the first side wall 211 away from the substrate substrate 1, so that the laser energy received by the active material layer 3a is moderate, so that the active layer 3 includes crystal grains 34 with a larger size, and the mobility of the carriers of the formed thin film transistor is larger, thereby reducing the power consumption of the array substrate and improving the overall performance.

[0100] Different thin film transistors of different display devices have different requirements for the active layer 3, such as the need to generate laser of different energies, which requires replacement of laser equipment, resulting in increased equipment cost; by arranging the active layer 3 on the first side wall 211 arranged at an angle, laser of different energies can be obtained, thereby reducing the equipment cost; and in general, the crystal nuclei are generated on the edge of the first side wall 211 away from the substrate substrate 1 and on the edge close to the substrate substrate 1, and the number of crystal nuclei generated on the first side wall 211 is small, so that the crystal nuclei can grow in a directional manner on the first side wall 211, and the crystal nuclei can grow larger along the first side wall 211 to form large crystal grains 34; and the number of crystal nuclei generated on the plane is larger, so that the crystal nuclei will collide during growth on the plane, and cannot form large crystal grains 34.

[0101] In the example embodiment, the angle a between the first side wall 211 and the substrate substrate 1 is greater than or equal to 5° and less than or equal to 20°, for example, the angle a between the first side wall 211 and the substrate substrate 1 can be 7°, 9°, 10°, 12°, 14°, 15°, 17°, 19°, etc.

[0102] If the angle between the first side wall 211 and the substrate substrate 1 is too large, the first side wall 211 is relatively steep, and the subsequently formed active material layer 3a is heated and crystallized to form the active layer 3 after the ELA (Excimer Laser Annealing) process. The active layer 3 is prone to breakage at the corner position.

[0103] If the angle between the first side wall 211 and the substrate substrate 1 is too small, the laser energy received by the active material layer 3a is high, i.e., high energy, resulting in that the crystal grains 34 included in the formed active layer 3 have a smaller size.

[0104] The above numerical range not only ensures that the active layer 3 is not prone to breakage at the corner position, but also ensures that the size of the crystal grain 34 included in the active layer 3 is large, thereby making the mobility of the carriers of the thin film transistor formed larger, reducing the power consumption of the array substrate, and improving the overall performance.

[0105] Of course, in some other example embodiments of the present disclosure, the included angle a between the first side wall 211 and the substrate substrate 1 can be greater than or equal to 20° and less than or equal to 40°, for example, the included angle a between the first side wall 211 and the substrate substrate 1 can be 23°, 25°, 27°, 29°, 30°, 32°, 34°, 35°, 37°, 39°, etc.

[0106] Moreover, a slower solidification rate is easy to obtain a large-size crystal grain 34, that is, a slower solidification rate is conducive to the growth of the crystal grain 34 and more likely to obtain a large-size crystal grain 34. The solidification rate is closely related to heat transfer, and there are mainly three ways of heat transfer: heat conduction through the first insulating layer 2, heat radiation, and heat convection in the N2 atmosphere. Heat loss by heat radiation and heat convection is very small, and heat loss is mainly in the form of heat conduction from the first insulating layer 2 to the substrate substrate 1.

[0107] The solidification rate is closely related to the heat flux density τ, and the heat flux density τ is the energy flow per unit area per unit time, therefore, the greater the heat flux density τ, the greater the solidification rate; the smaller the heat flux density τ, the smaller the solidification rate.

[0108] According to the calculation formula of the heat flux density τ: τ=k*dT / dx, in the formula, k can be the thermal conductivity of the first insulating layer 2, and dT / dx is the temperature gradient, that is, the temperature slope of the first insulating layer 2 at the boundary of the active material layer 3a and the first insulating layer 2.

[0109] From the above formula, if you want to reduce heat loss and obtain a lower solidification rate, you can set the thermal conductivity k of the first insulating layer 2 to be smaller; specifically, the thermal conductivity of the first insulating layer 2 is greater than or equal to 1 W / (m·K) and less than or equal to 3 W / (m·K), for example, the thermal conductivity of the first insulating layer 2 can be 1.2, 1.5, 1.7, 2, 2.3, 2.5, 2.8, etc., and the unit is W / (m·K).

[0110] If the thermal conductivity of the first insulating layer 2 is too small, it makes the selection of the material of the first insulating layer 2 more difficult, increasing the cost.

[0111] If the thermal conductivity of the first insulating layer 2 is too large, it results in a faster solidification rate, which is not conducive to the growth of the crystal grain 34 and cannot obtain a large-size crystal grain 34.

[0112] The above numerical range not only ensures a slow solidification rate and a large-size crystal grain 34, but also makes the material of the first insulating layer 2 easy to select and does not increase the cost.

[0113] The thickness of the first insulating layer 2 is greater than or equal to 1000 angstroms and less than or equal to 6000 angstroms, for example, the thickness of the first insulating layer 2 can be 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, etc. The material of the first insulating layer 2 can be SiO.

[0114] In the present example embodiment, referring to FIG. 2, the width K1 of the first side wall 211 is greater than or equal to 0.5 μm and less than or equal to 10 μm, for example, the width K1 of the first side wall 211 can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, 9.5 μm, etc.

[0115] If the width K1 of the first side wall 211 is too small, the width of the active layer 3 formed thereby is too small, which cannot meet the minimum size requirement of the thin film transistor.

[0116] If the width K1 of the first side wall 211 is too large, the thin film transistor occupies a large space, which is not conducive to improving the aperture ratio, reducing the energy consumption, and controlling the formation of a large-size crystal grain 34.

[0117] The above numerical range not only ensures that the minimum size requirement of the thin film transistor can be met, but also the thin film transistor occupies a small space, which is conducive to improving the aperture ratio, reducing the energy consumption, and controlling the formation of a large-size crystal grain 34.

[0118] It should be noted that the width K1 is the size between the opening edge of the first recessed portion 21 and the bottom wall edge of the first recessed portion 21.

[0119] Referring to FIG. 6, the first side wall 211 can be recessed toward the side close to the substrate substrate 1. Specifically, the first side wall 211 can include a first portion 2111 and a second portion 2112; the first portion 2111 is connected to the first plane 22 of the first insulating layer 2 away from the substrate substrate 1, and the second portion 2112 is connected to the side of the first portion 2111 away from the first plane 22; the first portion 2111 can be arc-shaped and protrude toward the side away from the substrate substrate 1, so that the first plane 22 of the first insulating layer 2 away from the substrate substrate 1 and the second portion 2112 are smoothly connected; the second portion 2112 can be arc-shaped and recessed toward the side close to the substrate substrate 1, and the width of the second portion 2112 is greater than the width of the first portion 2111, so that the first side wall 211 can be recessed toward the side close to the substrate substrate 1 in general.

[0120] Of course, in some other example embodiments of the present disclosure, the first side wall 211 can also protrude toward the side away from the substrate substrate 1. Referring to FIG. 7, specifically, the first side wall 211 can include a first portion 2111 and a second portion 2112; the first portion 2111 is connected to the first plane 22 of the first insulating layer 2 away from the substrate substrate 1, and the second portion 2112 is connected to the side of the first portion 2111 away from the first plane 22; the first portion 2111 can be arc-shaped and protrude toward the side away from the substrate substrate 1, so that the first plane 22 of the first insulating layer 2 away from the substrate substrate 1 and the second portion 2112 are smoothly connected; the second portion 2112 can be arc-shaped and recessed toward the side close to the substrate substrate 1, and the width of the first portion 2111 is greater than the width of the second portion 2112, so that the first side wall 211 can protrude toward the side away from the substrate substrate 1 in general.

[0121] In addition, the first side wall 211 can include more portions, that is, the first side wall 211 can include the first portion 2111, the second portion 2112, and a third portion, and so on.

[0122] It should be noted that the first side wall 211 can be recessed toward the side close to the substrate substrate 1, or the first side wall 211 can protrude toward the side away from the substrate substrate 1; not only the entire first side wall 211 can be recessed toward the side close to the substrate substrate 1 or protrude toward the side away from the substrate substrate 1; but also most of the first side wall 211 can be recessed toward the side close to the substrate substrate 1 or protrude toward the side away from the substrate substrate 1.

[0123] Referring to FIG. 8, the part of the active layer 3 located on the side of the first side wall 211 away from the substrate substrate 1 is not formed with the grain boundary 35, and is formed with the sub-grain boundary 36; the part of the active layer 3 located on the side of the first plane 22 away from the substrate substrate 1 is formed with the grain boundary 35; and the part of the active layer 3 located on the side of the bottom wall of the first recessed portion 21 away from the substrate substrate 1 is formed with the grain boundary 35.

[0124] The active layer 3 forms a grain boundary column 37, a projection of which on the substrate substrate 1 at least partially overlaps with a projection of a connecting line of the first side wall 211 and the first plane 22 on the substrate substrate 1, that is, the active layer 3 forms the grain boundary column 37 at the connecting position of the first side wall 211 and the first plane 22, and the grain boundary column 37 extends along the connecting line of the first side wall 211 and the first plane 22.

[0125] Moreover, the projection of the grain boundary column 37 on the substrate substrate 1 at least partially overlaps with a projection of a connecting line of the first side wall 211 and the bottom wall of the first recess 21 on the substrate substrate 1, that is, the active layer 3 also forms the grain boundary column 37 at the connecting position of the first side wall 211 and the bottom wall of the first recess 21, and the grain boundary column 37 extends along the connecting line of the first side wall 211 and the bottom wall of the first recess 21.

[0126] In other words, the active layer 3 forms the grain boundary column 37 at the connecting position of the first side wall 211 and the plane, and the grain boundary column 37 extends along the connecting line of the first side wall 211 and the plane.

[0127] Of course, in some other example embodiments of the present disclosure, when the active layer 3 is not arranged on the side of the first plane 22 facing away from the substrate substrate 1, the grain boundary column 37 is located at the edge of the active layer 3 closest to the first plane 22; when the active layer 3 is not arranged on the side of the bottom wall of the first recess 21 facing away from the substrate substrate 1, the grain boundary column 37 is located at the edge of the active layer 3 closest to the bottom wall of the first recess 21.

[0128] Referring to FIG. 1, the active layer 3 can include a first conductive connection portion 31, a channel portion 32 and a second conductive connection portion 33 connected in sequence, that is, the first conductive connection portion 31 and the second conductive connection portion 33 are connected to opposite ends of the channel portion 32. Moreover, the second conductive connection portion 33 is closer to the bottom wall of the first recess 21 than the first conductive connection portion 31, that is, the second conductive connection portion 33 is connected to one end of the channel portion 32 closest to the bottom wall of the first recess 21, and the first conductive connection portion 31 is connected to one end of the channel portion 32 facing away from the bottom wall of the first recess 21.

[0129] The channel portion 32 is located on at least one side of the first sidewall 211 away from the substrate substrate 1. Specifically, the channel portion 32 can be located on a portion of the first sidewall 211 away from the substrate substrate 1, that is, the channel portion 32 only covers a portion of the first sidewall 211, without covering the first sidewall 211 completely; so that the channel portion 32 includes grains 34, the size of the grains 34 is microns, that is, the channel portion 32 includes large grains 34; specifically, the size of the grains 34 is greater than or equal to 1 μm and less than or equal to 4 μm, for example, the size of the grains 34 can be 1.3 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, 2.7 μm, 3 μm, 3.3 μm, 3.5 μm, 3.8 μm, etc.; so that the mobility of the carriers of the thin film transistor formed is large, the power consumption of the array substrate is reduced, and the overall performance is improved.

[0130] In this case, the first conductive connection portion 31 and the second conductive connection portion 33 can be located only on one side of the first sidewall 211 away from the substrate substrate 1; or a part of the first conductive connection portion 31 and a part of the second conductive connection portion 33 can be located on one side of the first sidewall 211 away from the substrate substrate 1, another part of the first conductive connection portion 31 is located on the first plane 22 of the first insulating layer 2 away from the substrate substrate 1, and another part of the second conductive connection portion 33 can be located on the bottom wall of the first recessed portion 21; of course, the first conductive connection portion 31 can be located only on one side of the first sidewall 211 away from the substrate substrate 1, and the second conductive connection portion 33 can be located only on the bottom wall of the first recessed portion 21; or the first conductive connection portion 31 can be located only on the first plane 22 of the first insulating layer 2 away from the substrate substrate 1, and the second conductive connection portion 33 can be located only on one side of the first sidewall 211 away from the substrate substrate 1.

[0131] It should be noted that the above describes the setting positions of the first conductive connection portion 31 and the second conductive connection portion 33 by way of example, but is not exhaustive; and the setting positions of the first conductive connection portion 31 and the second conductive connection portion 33 can also be combined in more ways, which will not be described one by one here.

[0132] Of course, in some other example embodiments of the present disclosure, the channel portion 32 can be located on one side of the entire first sidewall 211 away from the substrate substrate 1, that is, the channel portion 32 completely covers the first sidewall 211; for the same reason, the channel portion 32 includes grains 34, the size of the grains 34 is microns, that is, the channel portion 32 includes large grains 34; so that the mobility of the carriers of the thin film transistor formed is large, the power consumption of the array substrate is reduced, and the overall performance is improved.

[0133] In this case, the first conductive connection part 31 can be located on the first plane 22 of the first insulating layer 2 away from the substrate base plate 1, and the second conductive connection part 33 can be located on the bottom wall of the first recessed part 21.

[0134] Furthermore, since the active layer 3 is not formed with the grain boundary 35 on the portion of the first side wall 211 away from the substrate base plate 1, the sub-grain boundary 36 is formed; therefore, the channel part 32 is not formed with the grain boundary 35, and the channel part 32 is formed with the sub-grain boundary 36. The grain boundary 35 is the cause of the roughness of the polycrystalline silicon material, and the grain boundary 35 has a star-shaped protrusion, which can cause undulation and is the main defect of carrier trapping, and is the most important factor affecting the mobility; the sub-grain boundary 36 does not cause obvious undulation and does not significantly affect the mobility. Referring to FIG. 8, the white part of the upper surface is the grain boundary 35, and the gap that is not white is the sub-grain boundary 36. It can be clearly seen that the slope is very smooth, and the grain boundary 35 is not formed, only the sub-grain boundary 36 is formed, and the flat area next to it has many undulations of the grain boundary 35. Therefore, the channel part 32 is not formed with the grain boundary 35, so that the mobility of the carrier of the thin film transistor formed is larger, and the power consumption of the array substrate is reduced and the overall performance is improved.

[0135] The first conductive connection part 31 and the second conductive connection part 33 are conductors formed by doping the polycrystalline silicon formed by crystallization, so even if the grain boundary 35 is formed in the first conductive connection part 31 and the second conductive connection part 33, it will not affect the conductivity of the first conductive connection part 31 and the second conductive connection part 33.

[0136] The array substrate can further include a planarization layer group 11, which is arranged on the side of the active layer 3 away from the substrate base plate 1, fills the first recessed part 21, and has a flat surface away from the substrate base plate 1.

[0137] It should be noted that the planarization layer group 11 fills the first recessed part 21, which can be directly filled by the planarization layer group 11 or indirectly filled by the planarization layer group 11.

[0138] The structure of the thin film transistor and the position of the planarization layer group 11 will be described below.

[0139] Referring to FIG. 1, the first conductive connection part 31 can be a source connection part, the second conductive connection part 33 can be a drain connection part, and the array substrate can further include a gate insulating layer group 4, a gate layer 5, a second insulating layer group 6, and a first conductive layer 7.

[0140] The gate insulating layer group 4 is arranged on the side of the active layer 3 away from the substrate substrate 1, and a first via hole 41 is arranged on the gate insulating layer group 4. Specifically, the gate insulating layer group 4 can include at least one inorganic insulating layer 42 and a filling insulating layer 43. For example, the gate insulating layer group 4 can include one inorganic insulating layer 42 and one filling insulating layer 43. The gate insulating layer group 4 can also include two or more inorganic insulating layers 42 and one filling insulating layer 43. The material of the inorganic insulating layer 42 can be silicon nitride, silicon oxide, silicon oxynitride, etc. In the case of including two or more inorganic insulating layers 42, the materials of the adjacent two inorganic insulating layers 42 are different. The material of the filling insulating layer 43 can be silicate, phosphorus-doped silicate, siloxane, organosiloxane, etc. The filling insulating layer 43 is isolated from the active layer 3 by the inorganic insulating layer 42, so as to avoid affecting the active layer 3.

[0141] A first sub-via hole 422 is arranged on the inorganic insulating layer 42, and a second sub-via hole 431 is arranged on the filling insulating layer 43. The second sub-via hole 431 is in communication with the first sub-via hole 422 and is included in the first via hole 41. That is, the communicated second sub-via hole 431 and the first sub-via hole 422 form the first via hole 41.

[0142] The inorganic insulating layer 42 is arranged on the side of the active layer 3 away from the substrate substrate 1. The thickness of the inorganic insulating layer 42 is greater than or equal to 80 nm and less than or equal to 200 nm. The thickness of the inorganic insulating layer 42 is relatively thin, so that after the inorganic insulating layer 42 covers the first insulating layer 2 and the active layer 3, a second recessed portion 421 is formed at the position of the first recessed portion 21. That is, the second recessed portion 421 is arranged on the inorganic insulating layer 42. The orthographic projection of the second recessed portion 421 on the substrate substrate 1 is located within the orthographic projection of the first recessed portion 21 on the substrate substrate 1. For example, the edge line of the orthographic projection of the second recessed portion 421 on the substrate substrate 1 can coincide with the edge line of the orthographic projection of the first recessed portion 21 on the substrate substrate 1. Alternatively, the orthographic projection of the first recessed portion 21 on the substrate substrate 1 can cover and be larger than the orthographic projection of the second recessed portion 421 on the substrate substrate 1. In the case of including two or more inorganic insulating layers 42, the two or more inorganic insulating layers 42 are arranged in sequence.

[0143] The filling insulating layer 43 is arranged on the side of the inorganic insulating layer 42 away from the substrate substrate 1. The filling insulating layer 43 fills the second recessed portion 421, so that the side of the gate insulating layer group 4 away from the substrate substrate 1 is a plane. This provides a relatively flat base plane for subsequent formation of the gate electrode layer 5, so as to avoid fracture of the gate electrode layer 5 due to discontinuity. In this case, the gate insulating layer group 4 is a planarization layer group 11.

[0144] A gate layer 5 is disposed on a side of the gate insulating layer group 4 away from the substrate base plate 1, and the gate layer 5 can include a gate 51 and a gate line (not shown in the figure), the gate 51 being connected to the gate line, and the gate 51 being disposed opposite to the channel portion 32, i.e. the orthographic projection of the gate 51 on the substrate base plate 1 at least partially overlaps the orthographic projection of the channel portion 32 on the substrate base plate 1. In this case, the gate layer 5 is substantially parallel to the substrate base plate 1. In addition, the gate layer 5 can also include other traces.

[0145] A second insulating layer group 6 is disposed on a side of the gate layer 5 away from the substrate base plate 1, and the second insulating layer group 6 can include at least one inorganic layer 62, for example, the second insulating layer group 6 can include one inorganic layer 62, and the second insulating layer group 6 can also include two or more inorganic layers 62, and a second via hole 61 is disposed on the second insulating layer group 6, and the second via hole 61 is connected to the first via hole 41.

[0146] A first conductive layer 7 is disposed on a side of the second insulating layer away from the substrate base plate 1, and the first conductive layer 7 can include a data line, a source electrode 71 and a drain electrode 72, the data line being connected to the source electrode 71, the source electrode 71 being connected to the source connection portion through the first via hole 41 and the second via hole 61, and the drain electrode 72 being connected to the drain connection portion through the first via hole 41 and the second via hole 61.

[0147] Please continue to refer to FIG. 1, in this case, in the third direction Z, the minimum thickness H1 of the gate insulating layer group 4 between the drain connection portion and the gate 51 is greater than the maximum thickness H2 of the gate insulating layer group 4 between the source connection portion and the gate 51, i.e. the minimum thickness H1 of the gate insulating layer group 4 between the second conductive connection portion 33 and the gate 51 is greater than the maximum thickness H2 of the gate insulating layer group 4 between the first conductive connection portion 31 and the gate 51, so that the distance between the drain connection portion and the gate 51 is greater than the distance between the source connection portion and the gate 51, which can alleviate the degradation of the characteristics of the thin film transistor and the short channel effect caused by the excessive electric field at one end of the drain connection portion. The third direction Z is perpendicular to the substrate base plate 1.

[0148] In this case, the gate 51 can be provided as two, and the two gates 51 are respectively disposed opposite to the two channel portions 32; the drain electrode 72 can be provided as two, and the two drain electrodes 72 are respectively connected to the two second conductive connection portions 33.

[0149] In addition, in some other example embodiments of the present disclosure, the gate 51 can be provided as one, and the one gate 51 is disposed opposite to the two channel portions 32; the drain electrode 72 can be provided as one, and the one drain electrode 72 is connected to the two second conductive connection portions 33.

[0150] Of course, in some other example embodiments of the present disclosure, referring to FIG. 9, the gate insulating layer group 4 can include only at least one inorganic insulating layer 42, for example, the gate insulating layer group 4 can include one inorganic insulating layer 42, and the gate insulating layer group 4 can also include two or more inorganic insulating layers 42; in this case, the inorganic insulating layer 42 is provided with a second recessed portion 421, specifically, the inorganic insulating layer 42 is provided with a second recessed portion 421 on the side away from the substrate 1. The second recessed portion 421 has at least one second side wall 4211, for example, in the case where the first recessed portion 21 has one first side wall 211, the second recessed portion 421 can have one second side wall 4211, and in the case where the first recessed portion 21 has two first side walls 211, the second recessed portion 421 can also have two second side walls 4211, and the two second side walls 4211 are oppositely arranged. The gate electrode 51 is arranged on at least part of the side of the second side wall 4211 away from the substrate 1, for example, the gate electrode 51 can be arranged on part of the side of the second side wall 4211 away from the substrate 1, or the gate electrode 51 can be arranged on the entire side of the second side wall 4211 away from the substrate 1. In this way, the gate electrode 51 is arranged to be inclined with the second side wall 4211.

[0151] In the case where the second recessed portion 421 has two second side walls 4211, the gate electrode 51 can also be provided in two, and the two gate electrodes 51 are arranged one-to-one corresponding to the two second side walls 4211; of course, in the case where the second side wall 4211 is provided in two, one gate electrode 51 can also be provided.

[0152] The second recessed portion 421 is formed due to the inorganic insulating layer 42 conformally covering the first insulating layer 2, so the distance between the second side wall 4211 and the substrate 1 increases as the distance from the edge of the second recessed portion 421 decreases, so that the second recessed portion 421 forms a structure with an opening larger than the bottom. Moreover, the included angle between the second side wall 4211 and the substrate 1 is greater than or equal to 5° and less than or equal to 20°, for example, the included angle between the second side wall 4211 and the substrate 1 can be 7°, 9°, 10°, 12°, 14°, 15°, 17°, 19°, etc. The inorganic insulating layer 42 has a certain filling effect on the first recessed portion 21, so the included angle between the second side wall 4211 and the substrate 1 is less than or equal to the included angle between the first side wall 211 and the substrate 1.

[0153] In this case, the second recessed portion 421 can be filled by the second insulating layer group 6, the first recessed portion 21 can be indirectly filled by the second insulating layer group 6, the second insulating layer group 6 is the planarization layer group 11, specifically, the second insulating layer group 6 can include at least one inorganic layer 62 and a filling layer 63, for example, the second insulating layer group 6 can include one inorganic layer 62 and one filling layer 63, the second insulating layer group 6 can include two or more inorganic layers 62 and one filling layer 63. The material of the inorganic layer 62 can be silicon nitride, silicon oxide, silicon oxynitride, etc., and in the case of including two or more inorganic layers 62, the materials of the adjacent two inorganic layers 62 are different. The material of the filling layer 63 can be silicate, phosphorus-doped silicate, siloxane, organosiloxane, etc., and organosiloxane is also known as organic silicone rubber or silicone rubber. The filling layer 63 can be isolated from the gate layer 5 by the inorganic layer 62 to avoid affecting the gate layer 5.

[0154] The third sub-via hole 622 is arranged on the inorganic layer 62, and the fourth sub-via hole 631 is arranged on the filling layer 63. The third sub-via hole 622 and the fourth sub-via hole 631 are in communication and are included in the second via hole 61, that is, the third sub-via hole 622 and the fourth sub-via hole 631 in communication form the second via hole 61.

[0155] The inorganic layer 62 is arranged on the side of the gate layer 5 away from the substrate 1. The thickness of the inorganic layer 62 is greater than or equal to 200 nm and less than or equal to 600 nm. The inorganic layer 62 is relatively thin, so that after the inorganic layer 62 covers the gate layer 5, a third recessed portion 621 is formed at the position of the second recessed portion 421, that is, the third recessed portion 621 is arranged on the inorganic layer 62. The orthographic projection of the third recessed portion 621 on the substrate 1 is located within the orthographic projection of the second recessed portion 421 on the substrate 1, for example, the edge line of the orthographic projection of the third recessed portion 621 on the substrate 1 can coincide with the edge line of the orthographic projection of the second recessed portion 421 on the substrate 1, or the orthographic projection of the second recessed portion 421 on the substrate 1 can cover and be larger than the orthographic projection of the third recessed portion 621 on the substrate 1. In the case of including two or more inorganic layers 62, the two or more inorganic layers 62 are arranged in sequence.

[0156] The filling layer 63 is arranged on the side of the inorganic layer 62 away from the substrate 1, and the filling layer 63 fills the third recessed portion 621, so that the side of the second insulating layer group 6 away from the substrate 1 is a plane, thereby providing a relatively flat base plane for the subsequent formation of the first conductive layer 7, and avoiding the fracture of the first conductive layer 7 due to the difference.

[0157] The gate 51 can be provided as two, and the two gates 51 are arranged opposite to the two channel portions 32 one by one; the drain 72 can be provided as two, and the two drains 72 are connected to the two second conductive connection portions 33 one by one.

[0158] In addition, in some other example embodiments of the present disclosure, the gate 51 can be provided as one, and one gate 51 is provided opposite to the two channel portions 32; the drain 72 can be provided as one, and one drain 72 is connected to the two second conductive connection portions 33.

[0159] The above-described top-gate thin film transistor is described in detail, of course, the gate layer 5 in the above-described thin film transistor can be provided as two layers, so that the thin film transistor forms a double-gate top-gate thin film transistor. The bottom-gate thin film transistor is described below.

[0160] Referring to FIG. 10, the first conductive connection portion 31 can be a drain connection portion, the second conductive connection portion 33 can be a source connection portion, and the array substrate can further include a gate layer 5, a second insulating layer group 6, and a first conductive layer 7.

[0161] The buffer layer 10 is provided on one side of the substrate 1, which plays a role of blocking water vapor and impurity ions in the substrate 1 (especially organic material) and plays a role of adding hydrogen ions to the subsequently formed active layer 3. The buffer layer 10 is made of an insulating material, which can include silicon nitride, silicon oxide, or silicon oxynitride. Depending on the type of the substrate 1 or the process conditions, the buffer layer 10 can be omitted.

[0162] The gate layer 5 is provided on the side of the buffer layer 10 away from the substrate 1, which can include a gate 51 and a gate line. The gate 51 is connected to the gate line, and the gate 51 is provided opposite to the channel portion 32, that is, the orthographic projection of the gate 51 on the substrate 1 at least partially overlaps the orthographic projection of the channel portion 32 on the substrate 1. In this case, the gate layer 5 is substantially parallel to the substrate 1. In addition, the gate layer 5 can also include other traces.

[0163] The first insulating layer 2 and the active layer 3 are sequentially stacked on the side of the gate layer 5 away from the substrate 1; in this structure, the crystal grain 34 included in the channel portion is a large crystal grain, specifically, the size of the crystal grain 34 is greater than or equal to 1 μm and less than or equal to 2 μm, for example, the size of the crystal grain 34 can be 1.3 μm, 1.5 μm, 1.8 μm, etc. The specific structures of the first insulating layer 2 and the active layer 3 have been described in detail above, and thus will not be described here.

[0164] The second insulating layer group 6 is provided on the side of the active layer 3 away from the substrate 1, and the second via hole 61 is provided on the second insulating layer group 6.

[0165] Specifically, the second insulating layer group 6 can include at least one inorganic layer 62 and one filling layer 63. For example, the second insulating layer group 6 can include one inorganic layer 62 and one filling layer 63. The second insulating layer group 6 can include two or more inorganic layers 62 and one filling layer 63. The material of the inorganic layer 62 can be silicon nitride, silicon oxide, silicon oxynitride, etc. In the case of including two or more inorganic layers 62, the materials of the adjacent two inorganic layers 62 are different. The material of the filling layer 63 can be silicate, phosphorus-doped silicate, siloxane, organosiloxane, etc. The organosiloxane is also known as organic silicone or silicone rubber. The inorganic layer 62 can isolate the filling layer 63 from the active layer 3, so as to avoid the influence of the filling layer 63 on the active layer 3.

[0166] The inorganic layer 62 is arranged on the side of the active layer 3 away from the substrate 1. The thickness of the inorganic layer 62 is greater than or equal to 200 nm and less than or equal to 600 nm. The inorganic layer 62 is relatively thin, so that after the inorganic layer 62 covers the first insulating layer 2, a third recess 621 is formed at the position of the first recess 21, that is, the third recess 621 is arranged on the inorganic layer 62. The orthographic projection of the third recess 621 on the substrate 1 is located within the orthographic projection of the first recess 21 on the substrate 1. For example, the edge line of the orthographic projection of the third recess 621 on the substrate 1 can coincide with the edge line of the orthographic projection of the first recess 21 on the substrate 1. Alternatively, the orthographic projection of the first recess 21 on the substrate 1 can cover and be larger than the orthographic projection of the third recess 621 on the substrate 1. In the case of including two or more inorganic layers 62, the two or more inorganic layers 62 are sequentially stacked.

[0167] The filling layer 63 is arranged on the side of the inorganic layer 62 away from the substrate 1. The filling layer 63 fills the third recess 621, so that the side of the second insulating layer group 6 away from the substrate 1 is a plane. This provides a relatively flat base plane for the subsequent formation of the first conductive layer 7, so as to avoid the breakage of the first conductive layer 7 due to the difference in height. The second insulating layer group 6 directly fills the first recess 21, and the second insulating layer group 6 is a planarization layer group 11.

[0168] The side of the second insulating layer group 6 away from the substrate 1 is provided with the first conductive layer 7. The first conductive layer 7 can include a data line, a source electrode 71 and a drain electrode 72. The data line is connected with the source electrode 71. The source electrode 71 is connected with the source connection part through the second via hole 61. The drain electrode 72 is connected with the drain connection part through the second via hole 61.

[0169] Please continue to refer to FIG. 10, in this case, in the third direction Z, the minimum thickness H3 of the first insulating layer 2 between the drain connecting portion and the gate 51 is greater than the maximum thickness H4 of the first insulating layer 2 between the source connecting portion and the gate 51, i.e. the minimum distance H3 between the drain connecting portion and the gate 51 is greater than the maximum distance H4 between the source connecting portion and the gate 51, which can alleviate the degradation of the thin film transistor characteristics and the short channel effect caused by the excessive electric field at one end of the drain connecting portion.

[0170] In the present example embodiment, the gate 51 can be provided as one, and one gate 51 is provided opposite to the two channel portions 32; the source 71 can be provided as two, and the two sources 71 are connected to the two first conductive connecting portions 31 one by one.

[0171] In addition, in some other example embodiments of the present disclosure, the gate 51 can be provided as two, and the two gates 51 are provided opposite to the two channel portions 32 one by one; the source 71 can be provided as one, and one source 71 is connected to the two first conductive connecting portions 31.

[0172] Of course, the gate layer 5 in the above-mentioned bottom-gate thin film transistor can be provided as two layers, so that the thin film transistor forms a double-gate bottom-gate thin film transistor.

[0173] The following describes a vertical thin film transistor.

[0174] Referring to FIGS. 11-14, the array substrate can further include a first conductor portion 8, a second conductor portion 9, a gate insulating layer group 4, and a gate layer 5.

[0175] A buffer layer 10 is provided on one side of the substrate 1, and the buffer layer 10 functions to block water vapor and impurity ions in the substrate 1 (especially organic materials). The buffer layer 10 can be made of an insulating material, and can include silicon nitride, silicon oxide, or silicon oxynitride. Depending on the type of the substrate 1 or the process conditions, the buffer layer 10 can be omitted.

[0176] The first conductor portion 8 is provided on one side of the substrate 1, specifically, on the side of the buffer layer 10 away from the substrate 1. The first conductor portion 8 can include a source 71 and a first trace 81, and the first trace 81 can include a data line connected to the source 71.

[0177] In the case where the first recessed portion 21 has one first sidewall 211, the source 71 of the first conductor portion 8 can be provided as one; in the case where the first recessed portion 21 has two first sidewalls 211, the source 71 of the first conductor portion 8 can be provided as one, and one source 71 is connected with one second conductive connection portion 33; the source 71 of the first conductor portion 8 can be provided as two, and two sources 71 are connected with one second conductive connection portion 33.

[0178] Of course, in the case where the second conductive connection portion 33 is provided as two, the source 71 of the first conductor portion 8 can be provided as one, and one source 71 is connected with two second conductive connection portions 33; the source 71 of the first conductor portion 8 can be provided as two, and two sources 71 are connected with two second conductive connection portions 33 one by one. The first conductor portion is arranged substantially parallel to the substrate 1.

[0179] Of course, in some other example embodiments of the present disclosure, the first wire 81 can further include other wires, and the first conductor portion 8 can include the drain 72 and the first wire 81.

[0180] The first insulating layer 2 and the active layer 3 are arranged in sequence on the side of the first conductor portion 8 away from the substrate 1, and the active layer 3 can include two channel portions 32, two first conductive connection portions 31 and one second conductive connection portion 33, and the two channel portions 32 are connected through the second conductive connection portion 33. The specific structure of the first insulating layer 2 and the active layer 3 has been described in detail above, and thus will not be described here again.

[0181] The bottom wall of the first recessed portion 21 penetrates to the first conductor portion 8, specifically, in the case where the source 71 of the first conductor portion 8 is provided as one, a via hole can be provided at the bottom of the first recessed portion 21 of the first insulating layer 2; in the case where the first conductor portion 8 is provided as two, two via holes can be provided at the bottom of the first recessed portion 21 of the first insulating layer 2.

[0182] At least part of the first conductor portion 8 is connected with the second conductive connection portion 33, specifically, the source 71 of the first conductor portion 8 is connected with the second conductive connection portion 33, and the first wire 81 of the first conductor portion 8 can be connected with the second conductive connection portion 33 or can not be connected with the second conductive connection portion 33; since the source 71 of the first conductor portion 8 is not covered by the first insulating layer 2, the second conductive connection portion 33 is connected with the source 71 of the first conductor portion 8, and the second conductive connection portion 33 can be a source connection portion.

[0183] Of course, in some other example embodiments of the present disclosure, in the case where the first conductor part 8 can include the drain 72 and the first trace 81, the second conductive connection part 33 can be a drain connection part; in the case where the first recess part 21 has two first side walls 211, the drain 72 of the first conductor part 8 can be provided as one, and one drain 72 is connected with one second conductive connection part 33; the drain 72 of the first conductor part 8 can be provided as two, and two drains 72 are connected with one second conductive connection part 33.

[0184] Of course, in the case where the second conductive connection part 33 is provided as two, the drain 72 of the first conductor part 8 can be provided as one, and one drain 72 is connected with two second conductive connection parts 33; the drain 72 of the first conductor part 8 can be provided as two, and two drains 72 are connected with two second conductive connection parts 33 one by one.

[0185] The second conductor part 9 is provided on the side of the first insulating layer 2 away from the substrate substrate 1, and at least part of the second conductor part 9 is connected with the first conductive connection part 31, specifically, the drain of the second conductor part 9 is connected with the first conductive connection part 31, and the second trace of the second conductor part 9 can be connected with the first conductive connection part 31 or can not be connected with the first conductive connection part 31.

[0186] Referring to FIGS. 11-14, the second conductor part 9 is provided on the first plane 22 of the side of the first insulating layer 2 away from the substrate substrate 1, that is, the second conductor part 9 is not provided in the first recess part 21. Referring to FIGS. 11 and 12, the material of the second conductor part 9 can be metal, in which case the second conductor part 9 is formed by a different patterning process than the active layer 3, and therefore at least part of the first conductive connection part 31 is located on the side of the second conductor part 9 away from the substrate substrate 1, for example, part of the first conductive connection part 31 can be located on the side of the second conductor part 9 away from the substrate substrate 1, or all of the first conductive connection part 31 can be located on the side of the second conductor part 9 away from the substrate substrate 1, so that the first conductive connection part 31 is overlapped with the second conductor part 9, thereby ensuring that the second conductor part 9 is connected with the first conductive connection part 31.

[0187] Furthermore, the thickness of the overlapped part of the second conductor part 9 and the first conductive connection part 31 is greater than or equal to 500 angstroms and less than or equal to 1000 angstroms, for example, the thickness of the overlapped part of the second conductor part 9 and the first conductive connection part 31 can be 550 angstroms, 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, 800 angstroms, 850 angstroms, 900 angstroms, 950 angstroms, etc.

[0188] If the thickness of the overlap part between the second conductor part 9 and the first conductive connection part 31 is too thick, it is difficult for the first conductive connection part 31 of the active layer 3 to climb up to the side of the second conductor part 9 away from the substrate 1, and a large gap is generated between the second conductor part 9 and the first insulating layer 2, which causes the first conductive connection part 31 to be prone to breakage.

[0189] If the thickness of the overlap part between the second conductor part 9 and the first conductive connection part 31 is too thin, the second conductor part 9 is prone to deformation during the annealing process of forming the active layer 3, which increases the connection resistance between the second conductor part 9 and the first conductive connection part 31 and cannot guarantee the connection effect of the second conductor part 9 and the first conductive connection part 31.

[0190] The above numerical range sets the thickness of the overlap part between the second conductor part 9 and the first conductive connection part 31 to be relatively thin, which not only enables the first conductive connection part 31 of the active layer 3 to climb up to the side of the second conductor part 9 away from the substrate 1, but also avoids the first conductive connection part 31 from being prone to breakage, and does not increase the connection resistance between the second conductor part 9 and the first conductive connection part 31, so as to guarantee the connection effect of the second conductor part 9 and the first conductive connection part 31.

[0191] In addition, in some other example embodiments of the present disclosure, referring to FIGS. 13 and 14, the material of the second conductor part 9 is doped low-temperature polycrystalline silicon or doped low-temperature polycrystalline oxide (LTPO), which includes a doped low-temperature polycrystalline silicon film layer and an oxide film layer. The oxide film layer can be IGZO (Indium Gallium Zinc Oxide), which can further reduce power consumption.

[0192] In this case, the second conductor part 9 and the active layer 3 are formed by the same patterning process, so that the second conductor part 9 and the first conductive connection part 31 are originally connected together, and therefore, there is no overlap or need for overlap between the second conductor part 9 and the first conductive connection part 31.

[0193] The second conductor part 9 can include a drain 72 and a second trace 91, in which case the first conductive connection part 31 is a drain connection part. Of course, in some other example embodiments of the present disclosure, the second conductor part 9 can include a source 71 and a second trace 91, in which case the first conductive connection part 31 is a source connection part.

[0194] In the case where the first recessed part 21 has one first sidewall 211, the second conductor part 9 can be provided as one; in the case where the first recessed part 21 has two first sidewalls 211, the second conductor part 9 can be provided as two.

[0195] The gate insulating layer group 4 is provided on the side of the second conductor 9 away from the substrate 1. Referring to FIGS. 11-14, the gate insulating layer group 4 can include at least one inorganic insulating layer 42. For example, the gate insulating layer group 4 can include one inorganic insulating layer 42. The gate insulating layer group 4 can also include two or more inorganic insulating layers 42. In this case, the second recessed portion 421 is provided on the inorganic insulating layer 42. Specifically, the second recessed portion 421 is provided on the side of the inorganic insulating layer 42 away from the substrate 1. The second recessed portion 421 has at least one second side wall 4211. For example, when the first recessed portion 21 has one first side wall 211, the second recessed portion 421 can have one second side wall 4211. When the first recessed portion 21 has two first side walls 211, the second recessed portion 421 can also have two second side walls 4211, and the two second side walls 4211 are oppositely arranged.

[0196] The gate layer 5 is provided on the side of the gate insulating layer group 4 away from the substrate 1. The gate layer 5 can include a gate 51 and a gate line. The gate 51 is connected to the gate line. The gate 51 is arranged opposite to the channel portion 32, i.e., the orthographic projection of the gate 51 on the substrate 1 at least partially overlaps the orthographic projection of the channel portion 32 on the substrate 1.

[0197] The gate 51 is provided on the side of at least part of the second side wall 4211 away from the substrate 1. For example, the gate 51 can be provided on the side of part of the second side wall 4211 away from the substrate 1. Alternatively, the gate 51 can be provided on the side of all of the second side wall 4211 away from the substrate 1. In this way, the gate 51 is arranged in an inclined manner with the second side wall 4211.

[0198] When the second recessed portion 421 has two second side walls 4211, the gate 51 can also be provided in two. The two gates 51 are arranged one-to-one corresponding to the two second side walls 4211. The two gates 51 are arranged one-to-one opposite to the two channel portions 32. Of course, when the second side wall 4211 is provided in two, one gate 51 can also be provided. The one gate 51 is arranged opposite to the two channel portions 32.

[0199] The second recess 421 is formed by the inorganic insulating layer 42 conformally covering the first insulating layer 2, and thus the distance between the second sidewall 4211 and the substrate 1 increases as the distance from the edge of the second recess 421 decreases, so that the second recess 421 forms a structure with an opening larger than a bottom. Moreover, the included angle between the second sidewall 4211 and the substrate 1 is greater than or equal to 5° and less than or equal to 20°, for example, the included angle between the second sidewall 4211 and the substrate 1 can be 7°, 9°, 10°, 12°, 14°, 15°, 17°, 19°, and the like. The inorganic insulating layer 42 has a certain filling effect on the first recess 21, and thus the included angle between the second sidewall 4211 and the substrate 1 is less than or equal to the included angle between the first sidewall 211 and the substrate 1.

[0200] In this case, the second insulating layer group 6 is arranged on the side of the gate layer 5 away from the substrate 1, and the second insulating layer group 6 can fill the second recess 421 and indirectly fill the first recess 21, and the second insulating layer group 6 is a planarization layer group 11.

[0201] Specifically, the second insulating layer group 6 can include at least one inorganic layer 62 and a filling layer 63, for example, the second insulating layer group 6 can include one inorganic layer 62 and one filling layer 63, and the second insulating layer group 6 can include two or more inorganic layers 62 and one filling layer 63. The material of the inorganic layer 62 can be silicon nitride, silicon oxide, silicon oxynitride, or the like, and in the case of including two or more inorganic layers 62, the materials of the two adjacent inorganic layers 62 are different. The material of the filling layer 63 can be silicate, phosphorus-doped silicate, siloxane, organosiloxane, or the like, and organosiloxane is also known as organic silicone rubber or silicone rubber. The inorganic layer 62 can isolate the filling layer 63 from the gate layer 5, so as to avoid the influence of the filling layer 63 on the gate layer 5.

[0202] The inorganic layer 62 is arranged on the side of the gate layer 5 away from the substrate 1, and the thickness of the inorganic layer 62 is greater than or equal to 200 nm and less than or equal to 600 nm. The inorganic layer 62 is relatively thin, so that after the inorganic layer 62 covers the gate layer 5, a third recess 621 is formed at the position of the second recess 421, that is, the third recess 621 is arranged on the inorganic layer 62. The orthographic projection of the third recess 621 on the substrate 1 is located within the orthographic projection of the second recess 421 on the substrate 1, for example, the edge line of the orthographic projection of the third recess 621 on the substrate 1 can coincide with the edge line of the orthographic projection of the second recess 421 on the substrate 1, or the orthographic projection of the second recess 421 on the substrate 1 can cover and be larger than the orthographic projection of the third recess 621 on the substrate 1. In the case of including two or more inorganic layers 62, the two or more inorganic layers 62 are sequentially stacked.

[0203] The filling layer 63 is arranged on the side of the inorganic layer 62 away from the substrate 1, and fills the third recessed portion 621, so that the side of the second insulating layer group 6 away from the substrate 1 is flat, and a relatively flat base plane is provided for the subsequently formed film layer, so as to avoid the film layer formed subsequently from being broken due to the difference in height.

[0204] Of course, in some other example embodiments of the present disclosure, referring to FIG. 15, the gate insulating layer group 4 can include at least one inorganic insulating layer 42 and a filling insulating layer 43. For example, the gate insulating layer group 4 can include one inorganic insulating layer 42 and one filling insulating layer 43, or the gate insulating layer group 4 can include two or more inorganic insulating layers 42 and one filling insulating layer 43. The material of the inorganic insulating layer 42 can be silicon nitride, silicon oxide, silicon oxynitride, etc. In the case of including two or more inorganic insulating layers 42, the materials of the two adjacent inorganic insulating layers 42 are different. The material of the filling insulating layer 43 can be silicate, phosphorus-doped silicate, siloxane, organosiloxane, etc. The organosiloxane is also called organic silicone rubber or silicone rubber. The filling insulating layer 43 can be isolated from the active layer 3 by the inorganic insulating layer 42, so as to avoid the filling insulating layer 43 from affecting the active layer 3.

[0205] The inorganic insulating layer 42 is arranged on the side of the active layer 3 away from the substrate 1, and the thickness of the inorganic insulating layer 42 is greater than or equal to 80 nm and less than or equal to 200 nm. The inorganic insulating layer 42 is relatively thin, so that after the inorganic insulating layer 42 covers the first insulating layer 2 and the active layer 3, a second recessed portion 421 is formed at the position of the first recessed portion 21, that is, the second recessed portion 421 is arranged on the inorganic insulating layer 42. The orthographic projection of the second recessed portion 421 on the substrate 1 is located within the orthographic projection of the first recessed portion 21 on the substrate 1. For example, the edge line of the orthographic projection of the second recessed portion 421 on the substrate 1 can coincide with the edge line of the orthographic projection of the first recessed portion 21 on the substrate 1, or the orthographic projection of the first recessed portion 21 on the substrate 1 can cover and be larger than the orthographic projection of the second recessed portion 421 on the substrate 1. In the case of including two or more inorganic insulating layers 42, the two or more inorganic insulating layers 42 are sequentially stacked.

[0206] The filling insulating layer 43 is arranged on the side of the inorganic insulating layer 42 away from the substrate 1, and fills the second recessed portion 421, so that the side of the gate insulating layer group 4 away from the substrate 1 is flat, and a relatively flat base plane is provided for the subsequently formed gate layer 5, so as to avoid the gate layer 5 from being broken due to the difference in height. In this case, the gate insulating layer group 4 is a planarization layer group 11.

[0207] A gate layer 5 is arranged on the side of the gate insulating layer group away from the substrate base plate 1, the gate layer 5 can include a gate 51 and a gate line, the gate 51 is connected to the gate line, the gate 51 is arranged opposite to the channel portion 32, that is, the orthographic projection of the gate 51 on the substrate base plate 1 at least partially overlaps the orthographic projection of the channel portion 32 on the substrate base plate 1. In this case, the gate layer 5 is arranged substantially parallel to the substrate base plate 1. In addition, the gate layer 5 can also include other lines.

[0208] A second insulating layer group 6 is arranged on the side of the gate layer 5 away from the substrate base plate 1, the second insulating layer group 6 can include at least one inorganic layer 62, for example, the second insulating layer group 6 can include one inorganic layer 62, the second insulating layer group 6 can also include two or more inorganic layers 62.

[0209] In the above example embodiment, the active layer 3 can be provided with lines, thereby reducing the pressure of too dense metal lines and layout.

[0210] The preparation method of the array substrate will be illustrated below.

[0211] Referring to FIG. 16, a first insulating material layer is formed on one side of the substrate base plate 1, and the first insulating material layer is subjected to a patterning process to form a first insulating layer 2, the first insulating layer 2 is formed with a first recessed portion 21, the first recessed portion 21 has at least one first side wall 211, the distance between the first side wall 211 and the substrate base plate 1 increases as the distance from the edge of the first recessed portion 21 decreases, the included angle between the first side wall 211 and the substrate base plate 1 is greater than or equal to 5° and less than or equal to 20°, the specific structure of the first insulating layer 2 has been described in detail above, and will not be described here.

[0212] Referring to FIG. 2, an active material layer 3a is formed on the side of the first insulating layer 2 away from the substrate base plate 1, the material of the active material layer 3a can be amorphous silicon, the thickness of the active material layer 3a is greater than or equal to 10 nm and less than or equal to 300 nm, for example, the thickness of the active material layer 3a can be 30 nm, 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 170 nm, 200 nm, 230 nm, 250 nm, 280 nm, etc.

[0213] Referring to FIG. 17, the active material layer 3a is subjected to excimer laser annealing and patterning to form a transition layer 3b, the transition layer 3b is at least located on the side of at least part of the first side wall 211 away from the substrate base plate 1.

[0214] ​​​​​​​Excimer laser annealing is a technology that converts amorphous silicon into polycrystalline silicon thin film by heating the active material layer 3a of amorphous silicon with excimer laser. It has the technical advantages of low processing temperature and short processing time. Solid phase crystallization is a traditional annealing method that uses an annealing furnace to heat. It generally has a high heating temperature and a long annealing time. Metal-induced crystallization is a method that reduces the crystallization temperature by using metal-induced nucleation. However, it has the problem of metal contamination and cannot be used for large-scale production at present.

[0215] The size of the crystal grain 34 of the polycrystalline silicon formed by using excimer laser annealing technology on the amorphous silicon arranged on the first plane 22 is about 300 nm, and the field effect mobility is 80-160 cm 2 / V·S. The size of the crystal grain 34 of the polycrystalline silicon formed by using excimer laser annealing technology on the amorphous silicon arranged on the first sidewall 211 is micron level, which greatly improves the mobility of the thin film transistor.

[0216] Referring to FIG. 18, a gate insulating layer group 4 is formed on the side of the transition layer 3b away from the substrate 1. Specifically, at least one inorganic insulating layer 42 is formed on the side of the transition layer 3b away from the substrate 1. For example, one inorganic insulating layer 42 can be deposited on the side of the transition layer 3b away from the substrate 1, or two or more inorganic insulating layers 42 can be sequentially deposited on the side of the transition layer 3b away from the substrate 1. The second recessed portion 421 is formed on the inorganic insulating layer 42, and the orthographic projection of the second recessed portion 421 on the substrate 1 is located within the orthographic projection of the first recessed portion 21 on the substrate 1.

[0217] A filling insulating layer 43 is formed on the side of the inorganic insulating layer 42 away from the substrate 1 by a SOG (Spin-On-Glass) process. The filling insulating layer 43 fills the second recessed portion 421, so that the side of the gate insulating layer group 4 away from the substrate 1 is a plane. Moreover, the filling insulating layer 43 has good compatibility with the thin film transistor and has no significant effect on the thin film transistor.

[0218] Referring to FIG. 19, a gate material layer is formed on the side of the gate insulating layer group 4 away from the substrate 1, and the gate material layer is patterned to form a gate electrode 51.

[0219] Referring to FIG. 1, the transition layer 3b is doped with the gate electrode 51 as a shield to form a first conductive connection portion 31, a channel portion 32, and a second conductive connection portion 33 connected in sequence in the active layer 3. A second insulating layer group 6 is formed on the side of the gate electrode 51 away from the substrate 1. A first conductive material layer is formed on the side of the second insulating layer group 6 away from the substrate 1, and the first conductive material layer is patterned to form a source electrode 71 and a drain electrode 72. The source electrode 71 is connected to the first conductive connection portion 31, and the drain electrode 72 is connected to the second conductive connection portion 33.

[0220] Of course, in some other example embodiments of the present disclosure, referring to FIG. 9, forming the gate insulating layer group 4 on the side of the active layer 3 away from the substrate 1 can include: forming at least one inorganic insulating layer 42 on the side of the active layer 3 away from the substrate 1, for example, a layer of inorganic insulating layer 42 can be formed by deposition on the side of the active layer 3 away from the substrate 1, or two or more layers of inorganic insulating layer 42 can be sequentially formed on the side of the active layer 3 away from the substrate 1; the second recess 421 is formed on the inorganic insulating layer 42, and the orthographic projection of the second recess 421 on the substrate 1 is located within the orthographic projection of the first recess 21 on the substrate 1.

[0221] In this case, forming the second insulating layer group 6 on the side of the gate 51 away from the substrate 1 can include: forming at least one inorganic layer 62 on the side of the gate 51 away from the substrate 1, for example, a layer of inorganic layer 62 can be formed on the side of the gate 51 away from the substrate 1, or two or more layers of inorganic layer 62 can be sequentially formed on the side of the gate 51 away from the substrate 1; the second recess 421 is formed on the inorganic layer 62, and the orthographic projection of the second recess 421 on the substrate 1 is located within the orthographic projection of the first recess 21 on the substrate 1; a filling layer 63 is formed on the side of the inorganic layer 62 away from the substrate 1, and the filling layer 63 fills the second recess 421, so that the side of the second insulating layer group 6 away from the substrate 1 is a plane.

[0222] The filling layer 63 is also formed by the SOG (Spin-On-Glass) process, and the filling layer 63 has good compatibility with the thin film transistor and has no significant effect on the thin film transistor.

[0223] Referring to FIG. 10, for the bottom-gate type thin film transistor, before forming the first insulating material layer, the preparation method further includes: forming a gate material layer on one side of the substrate 1, and patterning the gate material layer to form a gate electrode layer 5;

[0224] After forming the active layer 3, the preparation method can further include: forming a second insulating layer group 6 on the side of the active layer 3 away from the substrate 1; specifically, at least one inorganic layer 62 is formed on the side of the active layer 3 away from the substrate 1, for example, a layer of inorganic layer 62 can be formed by deposition on the side of the active layer 3 away from the substrate 1, or two or more layers of inorganic layer 62 can be sequentially formed by deposition on the side of the active layer 3 away from the substrate 1; the second recess 421 is formed on the inorganic layer 62, and the orthographic projection of the second recess 421 on the substrate 1 is located within the orthographic projection of the first recess 21 on the substrate 1.

[0225] A filling layer 63 is formed on the side of the inorganic layer 62 away from the substrate 1, and the filling layer 63 fills the second recessed portion 421, so that the side of the second insulating layer group 6 away from the substrate 1 is planar.

[0226] A first conductive material layer is formed on the side of the second insulating layer group 6 away from the substrate 1, and the first conductive material layer is subjected to a patterning process to form a source electrode 71 and a drain electrode 72, the source electrode 71 being connected to the second conductive connection portion 33, and the drain electrode 72 being connected to the first conductive connection portion 31.

[0227] Referring to FIG. 20, for the quasi-vertical thin film transistor, before the first insulating material layer is formed, the preparation method can further include: sequentially depositing a buffer layer 10 and a first conductor material layer on the side of the substrate 1, and subjecting the first conductor material layer to a patterning process to form a first conductor portion 8, the thickness of the first conductor material layer being greater than or equal to 5 nm and less than or equal to 100 nm, so that the thickness of the formed first conductor portion 8 is greater than or equal to 5 nm and less than or equal to 100 nm, for example, the thickness of the first conductor material layer can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, etc., and the thickness of the first conductor portion 8 can also be the above-mentioned values. Of course, the first conductor material layer can also be directly deposited on the side of the substrate 1.

[0228] Referring to FIG. 21, a first insulating material layer is formed on the side of the first conductor portion 8 away from the substrate 1, and the first insulating material layer is subjected to a patterning process to form a first recessed portion 21, and the bottom wall of the first recessed portion 21 penetrates at least part of the first conductor portion 8. Then, the transition layer 3b is prepared, and the preparation method of the transition layer 3b has been described in detail above, which will not be described here.

[0229] After the transition layer 3b is formed, the preparation method can further include: referring to FIG. 22, forming a gate insulating layer group 4 on the side of the transition layer 3b away from the substrate 1; forming a gate material layer on the side of the gate insulating layer group 4 away from the substrate 1, and subjecting the gate material layer to a patterning process to form a gate electrode layer 5, and the transition layer 3b is doped with the gate electrode layer 5 as a shield to form a first conductive connection portion 31, a channel portion 32 and a second conductive connection portion 33 connected in sequence, and the second conductive connection portion 33 is connected to at least part of the first conductor portion 8; referring to FIG. 11, forming a second insulating layer group 6 on the side of the gate electrode layer 5 away from the substrate 1.

[0230] Referring to FIG. 23, in some other example embodiments of the present disclosure, after the first insulating layer 2 is formed, the preparation method further includes: forming a second conductor material layer on the side of the first insulating layer 2 away from the substrate base plate 1, and patterning the second conductor material layer to form a second conductor part 9, the second conductor part 9 being connected with the first conductive connection part 31.

[0231] The doping concentration of the active layer 3 is greater than or equal to 5E11 ion / cm2and less than or equal to 5E15 ions / cm2, for example, the doping concentration of the active layer 3 can be 5E12 ion / cm2, 5E13 ion / cm2, 5E14 ion / cm2, etc. The doping material can include B (boron), P (phosphorus), F (fluorine), H (hydrogen), Ar (argon) plasma, etc. To ensure that the first conductive connection part 31 and the second conductive connection part 33 of the active layer 3 are normally overlapped and communicated with the first conductor part 8 and the second conductor part 9.

[0232] Based on the same inventive concept, the example embodiments of the present disclosure provide a display device, which can include the array substrate of any one of the above. The specific structure of the array substrate has been described in detail above, and thus will not be described here again.

[0233] The display device can be a liquid crystal display panel, an OLED (Organic Electroluminescence Display) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro-LED (micro-Light Emitting Diode) display panel, a mini-LED (mini-Light Emitting Diode) display panel, etc.

[0234] The specific type of the display device is not particularly limited, and any type of display device commonly used in the art can be used, for example, a mobile device such as a mobile phone, a wearable device such as a watch, a VR device, etc. A person skilled in the art can select a corresponding display device according to the specific use of the display device, and thus will not be described here again.

[0235] It should be noted that the display device includes other necessary components and components in addition to the array substrate. For example, a display device includes a housing, a circuit board, a power line, etc. A person skilled in the art can supplement a corresponding display device according to the specific use requirements of the display device, and thus will not be described here again.

[0236] Compared with the prior art, the display device provided by the example embodiments of the present application has the same beneficial effects as the array substrate provided by the example embodiments described above, and thus will not be described herein.

[0237] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the present disclosure cover any and all variations of the present disclosure that come within the scope of the following claims and their equivalents. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the disclosure indicated by the following claims.

Claims

1. An array substrate, wherein, include: Substrate; A first insulating layer is disposed on one side of the substrate. A first recess is provided on the first insulating layer. The first recess has at least one first sidewall. The distance between the first sidewall and the substrate increases as the distance to the edge of the first recess decreases. The included angle between the first sidewall and the substrate is greater than or equal to 5° and less than or equal to 20°. An active layer is located at least partially on the side of the first sidewall that faces away from the substrate.

2. The array substrate according to claim 1, wherein, The thermal conductivity of the first insulating layer is greater than or equal to 1 W / (m·K) and less than or equal to 3 W / (m·K).

3. The array substrate according to claim 1, wherein, The width of the first sidewall is greater than or equal to 0.5 μm and less than or equal to 10 μm, and the width is the dimension from the opening edge of the first recess to the bottom wall edge of the first recess.

4. The array substrate according to claim 1, wherein, The first sidewall is recessed toward the side closer to the substrate or protrudes toward the side away from the substrate.

5. The array substrate according to claim 1, wherein, The first insulating layer has a first plane facing away from the substrate, and the first sidewall is smoothly connected to the first plane; the portion of the active layer located on the side of the first sidewall facing away from the substrate does not form a grain boundary, but forms a subgrain boundary; the portion of the active layer located on the side of the first plane facing away from the substrate forms a grain boundary; and / or, the portion of the active layer located on the bottom wall of the first recess facing away from the substrate forms a grain boundary.

6. The array substrate according to claim 5, wherein, The active layer forms a grain boundary array, and the orthographic projection of the grain boundary array on the substrate at least partially overlaps with the orthographic projection of the connection line between the first sidewall and the first plane on the substrate. And / or, the orthographic projection of the grain boundary array on the substrate at least partially overlaps with the orthographic projection of the connecting line between the first sidewall and the bottom wall of the first recess on the substrate.

7. The array substrate according to claim 5, wherein, The active layer includes a first conductive connection portion, a channel portion, and a second conductive connection portion connected in sequence. The second conductive connection portion is closer to the bottom wall of the first recess relative to the first conductive connection portion. The channel portion is located on at least a portion of the first sidewall facing away from the substrate. The channel portion includes grains with a size at the micrometer level.

8. The array substrate according to claim 7, wherein, The array substrate further includes: A planarization layer group is disposed on the side of the active layer away from the substrate. The planarization layer group fills the first recessed portion, and the side of the planarization layer group away from the substrate is a plane.

9. The array substrate according to claim 8, wherein, The first conductive connection portion is a source connection portion, the second conductive connection portion is a drain connection portion, and the array substrate further includes: A gate insulating layer group is disposed on the side of the active layer opposite to the substrate, and a first via is provided on the gate insulating layer group; A gate layer is disposed on the side of the gate insulating layer group opposite to the substrate, and the gate layer includes a gate. A second insulating layer group is disposed on the side of the gate layer opposite to the substrate, and a second via is disposed on the second insulating layer group to communicate with the first via. A first conductive layer is disposed on the side of the second insulating layer opposite to the substrate. The first conductive layer includes a source and a drain. The source is connected to the source connection portion through the first via and the second via. The drain is connected to the drain connection portion through the first via and the second via.

10. The array substrate according to claim 9, wherein, The first sidewalls are configured as two opposite sides; the active layers are configured as two spaced apart, and the two active layers are located at least on the side of the two first sidewalls facing away from the substrate, or the active layers are located on the side of the two first sidewalls facing away from the substrate and cover the bottom wall of the first recess. The gate is configured as two, with each gate corresponding to one of the two channels; or, the gate is configured as one, with each gate corresponding to one of the two channels. The drain is configured as two, and the two drains are connected to the two second conductive connection portions in a one-to-one correspondence; or, the drain is configured as one, and the one drain is connected to the two second conductive connection portions.

11. The array substrate according to claim 8, wherein, The array substrate further includes: A first conductor portion is disposed on one side of the substrate, a first insulating layer is disposed on the side of the first conductor portion away from the substrate, the bottom wall of the first recessed portion extends through the first conductor portion, and at least a portion of the first conductor portion is connected to the second conductive connection portion. The second conductor portion is disposed on the side of the first insulating layer away from the substrate, and at least a portion of the second conductor portion is connected to the first conductive connection portion; A gate insulating layer group is disposed on the side of the second conductor portion and the active layer away from the substrate. A gate layer is disposed on the side of the gate insulating layer group opposite to the substrate, and the gate layer includes a gate. The second insulating layer group is disposed on the side of the gate layer opposite to the substrate.

12. The array substrate according to claim 11, wherein, The first conductor portion includes a source electrode and a first trace, the second conductive connection portion is a source electrode connection portion, the second conductor portion includes a drain electrode and a second trace, and the first conductive connection portion is a drain electrode connection portion; or, the first conductor portion includes a drain electrode and a first trace, the second conductive connection portion is a drain electrode connection portion, the second conductor portion includes a source electrode and a second trace, and the first conductive connection portion is a source electrode connection portion.

13. The array substrate according to claim 11, wherein, The second conductor portion is made of metal, at least a portion of the first conductive connection portion is located on the side of the second conductor portion away from the substrate, and the thickness of the overlap portion between the second conductor portion and the first conductive connection portion is greater than or equal to 500 angstroms and less than or equal to 1000 angstroms; or, the second conductor portion is made of doped low-temperature polycrystalline silicon or doped low-temperature polycrystalline oxide.

14. The array substrate according to claim 12, wherein, The first sidewalls are configured as two opposite sides; the active layers are configured as two spaced apart, and the two active layers are located at least on the side of the two first sidewalls facing away from the substrate, or the active layers are located at least on the side of the two first sidewalls facing away from the substrate and cover the bottom wall of the first recess. The gate is configured as two, with each gate corresponding to one of the two channels; or, the gate is configured as one, with each gate corresponding to one of the two channels. The first conductor portion has two sources or drains, and each of the two sources or drains is connected to one of the two second conductive connections; or, the first conductor portion has one source or drain, and each of the two sources or drains is connected to one of the two second conductive connections.

15. The array substrate according to any one of claims 9 to 14, wherein, The gate insulating layer group includes: At least one inorganic insulating layer is disposed on the side of the active layer away from the substrate. A second recess is provided on the inorganic insulating layer, and the orthographic projection of the second recess on the substrate is located within the orthographic projection of the first recess on the substrate.

16. The array substrate according to claim 15, wherein, The gate insulating layer group further includes: A filling insulating layer is disposed on the side of the inorganic insulating layer away from the substrate. The filling insulating layer fills the second recess so that the side of the gate insulating layer group away from the substrate is a plane. The gate insulating layer group is the planarization layer group.

17. The array substrate according to claim 16, wherein, In the third direction, the minimum thickness of the gate insulating layer group between the drain connection and the gate is greater than the maximum thickness of the gate insulating layer group between the source connection and the gate, and the third direction is perpendicular to the substrate.

18. The array substrate according to claim 15, wherein, The second recess has at least one second sidewall, the distance between the second sidewall and the substrate increases as the distance to the edge of the second recess decreases, and the included angle between the second sidewall and the substrate is greater than or equal to 5° and less than or equal to 20°. The gate is disposed on at least a portion of the second sidewall on the side opposite to the substrate. The second insulating layer group includes: At least one inorganic layer is disposed on the side of the gate layer away from the substrate, and a third recess is provided on the inorganic layer, wherein the orthographic projection of the third recess on the substrate is located within the orthographic projection of the second recess on the substrate. A filler layer is disposed on the side of the inorganic layer away from the substrate. The filler layer fills the third recess so that the side of the second insulating layer group away from the substrate is planar. The second insulating layer group is the planarization layer group.

19. The array substrate according to claim 8, wherein, The first conductive connection portion is a drain connection portion, the second conductive connection portion is a source connection portion, and the array substrate further includes: A gate layer is disposed on one side of the substrate, the gate layer includes a gate, and the first insulating layer is disposed on the side of the gate layer opposite to the substrate. A second insulating layer group is disposed on the side of the active layer away from the substrate, and a second via is provided on the second insulating layer group; A first conductive layer is disposed on the side of the second insulating layer group away from the substrate. The first conductive layer includes a source and a drain. The source is connected to the source connection portion through the second via, and the drain is connected to the drain connection portion through the second via.

20. The array substrate according to claim 19, wherein, The second insulating layer group includes: At least one inorganic layer is disposed on the side of the active layer away from the substrate, and a third recess is provided on the inorganic layer, wherein the orthographic projection of the third recess on the substrate is located within the orthographic projection of the first recess on the substrate. A filler layer is disposed on the side of the inorganic layer away from the substrate. The filler layer fills the third recess so that the side of the second insulating layer group away from the substrate is planar. The second insulating layer group is the planarization layer group.

21. The array substrate according to claim 19, wherein, In the third direction, the minimum thickness of the first insulating layer between the drain connection and the gate is greater than the maximum thickness of the first insulating layer between the source connection and the gate, and the third direction is perpendicular to the substrate.

22. The array substrate according to claim 19, wherein, The first sidewalls are configured as two opposite sides; the active layers are configured as two spaced apart, and the two active layers are located at least on the side of the two first sidewalls facing away from the substrate, or the active layers are located at least on the side of the two first sidewalls facing away from the substrate and cover the bottom wall of the first recess. The gate is configured as two, with each gate corresponding to one of the two channels; or, the gate is configured as one, with each gate corresponding to one of the two channels. The source electrode is configured as two, and the two source electrodes are connected to the two first conductive connection portions in a one-to-one correspondence; or, the source electrode is configured as one, and the one source electrode is connected to the two first conductive connection portions.

23. A display device, wherein, include: The array substrate according to any one of claims 1 to 22.

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