Pixel driving circuit and driving method therefor, and display apparatus

Abstract

A pixel driving circuit and a driving method therefor, and a display apparatus. The pixel driving circuit comprises: a driving control sub-circuit, a reset sub-circuit, a driving sub-circuit and a light-emission control sub-circuit, wherein the light-emission control sub-circuit is configured to provide a signal of a first power supply line (VDD) to a second node (N2) and a signal of a third node (N3) to a fifth node (N5) under the control of signals of a first light-emission signal line (EM1) and second light-emission signal line (EM2). The display apparatus comprises a first control unit, wherein the first control unit is electrically connected to each of a first light-emission signal line (EM1) and a second light-emission signal line (EM2), and is configured to provide signals to the first light-emission signal line (EM1) and the second light-emission signal line (EM2), part of a time period within which the first control unit provides an effective level signal to the first light-emission signal line (EM1) not overlapping a time period within which the first control unit provides an effective level signal to the second light-emission signal line (EM2).

Description

Pixel driving circuit and its driving method, display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a pixel driving circuit and its driving method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a pixel driving circuit disposed in a display device, comprising: a driving control sub-circuit, a reset sub-circuit, a driving sub-circuit, and a light emission control sub-circuit;

[0006] The reset sub-circuit is electrically connected to at least one reset signal line, a first initial signal line, a second initial signal line, a reference signal line, a second node, a fourth node, and a fifth node, respectively, and is configured to provide the reference signal line to the second node, the first initial signal line to the fourth node, and the second initial signal line to the fifth node under the control of the signal of at least one reset signal line.

[0007] The drive control sub-circuit is electrically connected to at least two scan signal lines, a data signal line, a first power line, a first node, a second node, a third node, and a fourth node, respectively, and is configured to provide the data signal line to the second node and the third or fourth node to the first node under the control of the signals of at least two scan signal lines and the first power line.

[0008] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node.

[0009] The light-emitting control sub-circuit is electrically connected to the first light-emitting signal line, the second light-emitting signal line, the first power supply line, the second node, the third node, and the fifth node, respectively. It is configured to provide the first power supply line signal to the second node and the third node signal to the fifth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line.

[0010] The display device includes: a first control unit, which is electrically connected to a first light-emitting signal line and a second light-emitting signal line respectively, and is configured to provide signals to the first light-emitting signal line and the second light-emitting signal line, wherein the time period during which the first control unit provides an effective level signal to the first light-emitting signal line does not overlap with the time period during which it provides an effective level signal to the second light-emitting signal line.

[0011] In an exemplary embodiment, the driving sub-circuit includes a third transistor, and the light-emitting control sub-circuit includes a fifth transistor and a sixth transistor;

[0012] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0013] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node.

[0014] The control electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0015] In an exemplary embodiment, the display device includes: a multi-row pixel driving circuit, wherein the second light-emitting signal line connected to the i-th row pixel driving circuit and the first light-emitting signal line connected to the (i+1)-th row pixel driving circuit are the same signal line.

[0016] In an exemplary embodiment, the start time of the period during which the first control unit provides an effective level signal to the first light-emitting signal line is earlier than the start time of the period during which the first control unit provides an effective level signal to the second light-emitting signal line, and the end time of the period during which the first control unit provides an effective level signal to the first light-emitting signal line is earlier than the end time of the period during which the first control unit provides an effective level signal to the second light-emitting signal line.

[0017] In an exemplary embodiment, at least one reset signal line includes: a first reset signal line, and the reset sub-circuit includes: a first transistor, a seventh transistor, and a ninth transistor;

[0018] The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the fourth node.

[0019] The control electrode of the seventh transistor is electrically connected to the first reset signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fifth node.

[0020] The control electrode of the ninth transistor is electrically connected to the first reset signal line, the first electrode of the ninth transistor is electrically connected to the reference signal line, and the second electrode of the ninth transistor is electrically connected to the second node.

[0021] The display device further includes: a second control unit, which is electrically connected to the first reset signal line and configured to provide a signal to the first reset signal line;

[0022] The time period during which the second control unit provides a valid level signal to the first reset signal line at least partially overlaps with at least one of the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line and to the second light-emitting signal line.

[0023] In an exemplary embodiment, at least one reset signal line includes: a first reset signal line and a second reset signal line;

[0024] The reset sub-circuit is configured to provide a signal of the first initial signal line to the fourth node under the control of the signal of the first reset signal line, provide a signal of the second initial signal line to the fifth node under the control of the signal of the second reset signal line, and provide a signal of the reference signal line to the second node.

[0025] The display device further includes: a second control unit, which is electrically connected to the first reset signal line and the second reset signal line respectively, and is configured to provide signals to the first reset signal line and the second reset signal line;

[0026] The time period during which the second control unit provides an effective level signal to the first reset signal line does not overlap with the time period during which the second control unit provides an effective level signal to the second reset signal line, and the end time of the time period during which the second control unit provides an effective level signal to the second reset signal line is earlier than the start time of the time period during which the second control unit provides an effective level signal to the first reset signal line.

[0027] At least one of the time periods during which the second control unit provides a valid level signal to the first reset signal line and the time periods during which the second control unit provides a valid level signal to the second reset signal line overlaps at least partially with at least one of the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line and the time periods during which the first control unit provides an invalid level signal to the second light-emitting signal line.

[0028] In an exemplary embodiment, the reset sub-circuit includes: a first transistor, a seventh transistor, and a ninth transistor;

[0029] The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the fourth node.

[0030] The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fifth node.

[0031] The control electrode of the ninth transistor is electrically connected to the second reset signal line, the first electrode of the ninth transistor is electrically connected to the reference signal line, and the second electrode of the ninth transistor is electrically connected to the second node.

[0032] In an exemplary embodiment, at least two scan signal lines include: a first scan signal line and a third scan signal line;

[0033] The drive control sub-circuit is configured to provide a data signal line signal to the second node and a third node signal to the fourth node under the control of the signal of the first scan signal line, and to provide a fourth node signal to the first node under the control of the signal of the third scan signal line.

[0034] The display device further includes: a third control unit and a fourth control unit, wherein the third control unit is electrically connected to the first scan signal line and is configured to provide a signal to the first scan signal line, and the fourth control unit is electrically connected to the third scan signal line and is configured to provide a signal to the third scan signal line;

[0035] The time period during which the third control unit provides an effective level signal to the first scan signal line overlaps at least partially with the time period during which the fourth control unit provides an effective level signal to the third scan signal line.

[0036] At least one of the time periods during which the third control unit provides a valid level signal to the first scan signal line and the time periods during which the fourth control unit provides a valid level signal to the third scan signal line at least partially overlaps with at least one of the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line and the time periods during which the first control unit provides an invalid level signal to the second light-emitting signal line.

[0037] In an exemplary embodiment, the drive control sub-circuit includes: a capacitor, a second transistor, a fourth transistor, and an eighth transistor, wherein the capacitor includes: a first plate and a second plate;

[0038] The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node.

[0039] The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node.

[0040] The control electrode of the eighth transistor is electrically connected to the third scan signal line, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0041] The first plate of the capacitor is electrically connected to the first power line, and the second plate of the capacitor is electrically connected to the first node.

[0042] In an exemplary embodiment, at least two scan signal lines include: a first scan signal line, a second scan signal line, and a third scan signal line;

[0043] The drive control sub-circuit is configured to provide a data signal line signal to the second node under the control of the signal of the first scan signal line, provide a signal of the third node to the fourth node under the control of the signal of the second scan signal line, and provide a signal of the fourth node to the first node under the control of the signal of the third scan signal line.

[0044] The display device further includes: a third control unit, a fourth control unit, and a fifth control unit. The third control unit is electrically connected to the first scan signal line and is configured to provide a signal to the first scan signal line. The fourth control unit is electrically connected to the third scan signal line and is configured to provide a signal to the third scan signal line. The fifth control unit is electrically connected to the second scan signal line and is configured to provide a signal to the second scan signal line.

[0045] The time period during which the fifth control unit provides an effective level signal to the second scan signal line includes: a first time period and a second time period, wherein the end time of the first time period is earlier than the start time of the second time period;

[0046] The time period during which the third control unit provides an effective level signal to the first scan signal line overlaps at least partially with the second time period, but does not overlap with the first time period;

[0047] At least one of the first time period and the second time period overlaps at least partially with the time period during which the fourth control unit provides an effective level signal to the third scan signal line;

[0048] The time period during which the fourth control unit provides an effective level signal to the third scan signal line at least partially overlaps with at least one of the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line and to the second light-emitting signal line.

[0049] In an exemplary embodiment, the drive control sub-circuit includes: a capacitor, a second transistor, a fourth transistor, and an eighth transistor, wherein the capacitor includes: a first plate and a second plate;

[0050] The control electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node.

[0051] The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node.

[0052] The control electrode of the eighth transistor is electrically connected to the third scan signal line, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0053] Secondly, this disclosure also provides a display device, including: a plurality of sub-pixels, at least one sub-pixel including: the aforementioned pixel driving circuit.

[0054] In an exemplary embodiment, it further includes: a plurality of first light-emitting signal lines and a plurality of second light-emitting signal lines, wherein at least one of the first light-emitting signal lines and the second light-emitting signal lines extends at least partially along a first direction;

[0055] The first light-emitting signal line connected to the pixel driving circuit of the j-th row sub-pixel and the second light-emitting signal line connected to the pixel driving circuit of the (j-1)-th row sub-pixel are the same signal line, 1≤j≤N, where N is the total number of rows of sub-pixels.

[0056] In an exemplary embodiment, it further includes: a plurality of first reset signal lines, wherein the first reset signal lines extend at least partially along a first direction;

[0057] The pixel driving circuit of the j-th row sub-pixel includes two first reset signal lines. The first first reset signal line connected to the pixel driving circuit of the j-th row sub-pixel is the same signal line as the second first reset signal line connected to the pixel driving circuit of the (j-1)-th row sub-pixel. The second first reset signal line connected to the pixel driving circuit of the j-th row sub-pixel is the same signal line as the first first reset signal line connected to the pixel driving circuit of the (j+1)-th row sub-pixel.

[0058] In an exemplary embodiment, it further includes: multiple first scan signal lines, multiple third scan signal lines, multiple first initial signal lines, multiple second initial signal lines, and multiple reference signal lines;

[0059] At least one of the first scan signal line, the third scan signal line, the first initial signal line, the second initial signal line, and the reference signal line extends at least partially along the first direction;

[0060] The first light-emitting signal line connected to the pixel driving circuit of the j-th sub-pixel, the first first reset signal line connected to the pixel driving circuit of the j-th sub-pixel, the first scan signal line connected to the pixel driving circuit of the j-th sub-pixel, the second light-emitting signal line connected to the pixel driving circuit of the j-th sub-pixel, and the second first reset signal line connected to the pixel driving circuit of the j-th sub-pixel are arranged sequentially along the second direction, and the first direction intersects the second direction;

[0061] The orthographic projection of the reference signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate at least partially overlaps with the first reset signal line connected to the pixel driving circuit of the j-th sub-pixel. The orthographic projection of the second initial signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate at least partially overlaps with the orthographic projection of the first light emission signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate. The orthographic projection of the third scan signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate is located between the orthographic projection of the first scan signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate and the orthographic projection of the first reset signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate. The orthographic projection of the second initial signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate is located on the side of the orthographic projection of the second reset signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate that is away from the orthographic projection of the second light emission signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate.

[0062] In an exemplary embodiment, at least one pixel driving circuit includes: a first transistor to a ninth transistor, and at least one transistor includes: an active pattern;

[0063] The active patterns of the first transistor, the second transistor, the third transistor, the fourth transistor, the sixth transistor, and the seventh transistor located in the same sub-pixel are integrated into one structure, and the active patterns of the fifth transistor and the ninth transistor located in the same sub-pixel are integrated into one structure.

[0064] The active patterns of the fifth transistor in the pixel driving circuit of the j-th row sub-pixel and the active patterns of the sixth transistor in the pixel driving circuit of the (j-1)-th row sub-pixel are arranged along the first direction. The active patterns of the ninth transistor in the pixel driving circuit of the j-th row sub-pixel, the active patterns of the first transistor in the pixel driving circuit of the j-th row sub-pixel, and the active patterns of the seventh transistor in the pixel driving circuit of the (j-1)-th row sub-pixel are arranged along the first direction.

[0065] In an exemplary embodiment, at least one transistor further includes: a first electrode and a second electrode, the active pattern includes a first region and a second region, the second electrode of the fifth transistor and the second electrode of the ninth transistor are integrally structured and extend along a second direction;

[0066] The first region of the active pattern of the third transistor is the same as the second region of the active pattern of the fourth transistor, and the second region of the active pattern of the fifth transistor is the same as the second region of the active pattern of the ninth transistor.

[0067] The second terminal of the fifth transistor is connected to the first region of the active pattern of the third transistor and the second region of the active pattern of the fifth transistor, respectively.

[0068] The orthographic projection of the second electrode of the fifth transistor in the pixel driving circuit of the j-th column sub-pixel on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the reference signal line connected to the pixel driving circuit of the j-th row sub-pixel, the second initial signal line connected to the (j-1)-th row sub-pixel, the third scan signal line connected to the pixel driving circuit of the j-th row sub-pixel, and the first scan signal line connected to the pixel driving circuit of the j-th row sub-pixel.

[0069] In an exemplary embodiment, it further includes: a plurality of initial connection lines, a plurality of first power lines and a plurality of data signal lines, wherein at least one of the first power lines, data signal lines and initial connection lines extends at least partially along a second direction, and the first direction intersects the second direction;

[0070] At least one initial connection line is electrically connected to at least one first initial signal line.

[0071] In an exemplary embodiment, the system further includes: a substrate and a driving structure layer disposed on the substrate, the driving structure layer being provided with a pixel driving circuit, the pixel driving circuit including: at least one N-type transistor, at least one P-type transistor and a capacitor, the capacitor including a first electrode plate and a second electrode plate, the transistor including: an active pattern, a control electrode, a first electrode and a second electrode, and the third scan signal line including a first sub-signal line and a second sub-signal line.

[0072] The driving structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are sequentially stacked on the substrate;

[0073] The first semiconductor layer includes at least: an active pattern of at least one P-type transistor;

[0074] The first conductive layer includes at least: a first scan signal line, a first light emission signal line, a second light emission signal line, a first reset signal line, a first electrode of a capacitor located in at least one pixel driving circuit, and a control electrode of at least one P-type transistor;

[0075] The second conductive layer includes at least: a first sub-signal line of the third scan signal line, a second initial signal line, and a second plate of a capacitor located in the pixel driving circuit of at least one sub-pixel;

[0076] The second semiconductor layer includes at least: an active pattern of at least one N-type transistor;

[0077] The third conductive layer includes at least: a second sub-signal line of the third scan signal line, a first initial signal line, and a reference signal line;

[0078] The fourth conductive layer includes at least: an initial connection line located at the first and second poles of at least one transistor in at least one pixel driving circuit.

[0079] Thirdly, this disclosure also provides a method for driving a pixel driving circuit, configured to drive the aforementioned pixel driving circuit, the method comprising:

[0080] Under the control of at least one reset signal line, the reset sub-circuit provides a reference signal line signal to the second node, a first initial signal line signal to the fourth node, and a second initial signal line signal to the fifth node.

[0081] Under the control of at least two scan signal lines and the first power supply line, the drive control sub-circuit provides the data signal line to the second node and the signal of the third or fourth node to the first node;

[0082] The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes;

[0083] Under the control of the signals from the first and second light-emitting signal lines, the light-emitting control sub-circuit provides the first power line signal to the second node and the third node signal to the fifth node.

[0084] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0085] Overview of the attached figures

[0086] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0087] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0088] Figure 2 is a timing diagram of the signals of the first and second light-emitting signal lines;

[0089] Figure 3 shows the equivalent circuit diagram of the driver sub-circuit and the light-emitting control sub-circuit;

[0090] Figure 4 is an equivalent circuit diagram of the reset sub-circuit;

[0091] Figure 5 shows another equivalent circuit diagram of the reset sub-circuit;

[0092] Figure 6 is an equivalent circuit diagram of the drive control sub-circuit;

[0093] Figure 7 shows another equivalent circuit diagram of the drive control sub-circuit;

[0094] Figure 8 is an equivalent circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0095] Figure 9 is an equivalent circuit diagram of the pixel driving circuit provided in the embodiment of this disclosure.

[0096] Figure 10 is an equivalent circuit diagram of the pixel driving circuit provided in the embodiment of this disclosure.

[0097] Figure 11 is an equivalent circuit diagram of the pixel driving circuit provided in the embodiment of this disclosure;

[0098] Figure 12 is a timing diagram of the pixel driving circuit provided in Figure 8;

[0099] Figure 13 is a timing diagram of the pixel driving circuit provided in Figure 9;

[0100] Figure 14 is a timing diagram of the pixel driving circuit provided in Figure 10;

[0101] Figure 15 is a timing diagram of the pixel driving circuit provided in Figure 11;

[0102] Figure 16 is a schematic diagram of the structure of the display device provided in an embodiment of this disclosure;

[0103] Figure 17 is a schematic diagram of a portion of the film layers in Figure 16;

[0104] Figure 18 is a schematic diagram of a portion of the film layers in Figure 16;

[0105] Figure 19 is a schematic diagram of the light-shielding layer pattern formed in Figure 16;

[0106] Figure 20 is a schematic diagram of the pattern of the first semiconductor layer in Figure 16;

[0107] Figure 21 is a schematic diagram after the first semiconductor layer pattern is formed in Figure 16;

[0108] Figure 22 is a schematic diagram of the first conductive layer pattern in Figure 16;

[0109] Figure 23 is a schematic diagram after the first conductive layer pattern is formed in Figure 16;

[0110] Figure 24 is a schematic diagram of the second conductive layer pattern in Figure 16;

[0111] Figure 25 is a schematic diagram after the second conductive layer pattern is formed in Figure 16;

[0112] Figure 26 is a schematic diagram of the second semiconductor layer pattern in Figure 16;

[0113] Figure 27 is a schematic diagram after the second semiconductor layer pattern is formed in Figure 16;

[0114] Figure 28 is a schematic diagram of the third conductive layer pattern in Figure 16;

[0115] Figure 29 is a schematic diagram after the third conductive layer pattern is formed in Figure 16;

[0116] Figure 30 is a schematic diagram after the sixth insulating layer pattern is formed in Figure 16;

[0117] Figure 31 is a schematic diagram of the fourth conductive layer pattern in Figure 16;

[0118] Figure 32 is a schematic diagram after the fourth conductive layer pattern is formed in Figure 16;

[0119] Figure 33 is a schematic diagram after the first planarization layer pattern is formed in Figure 16;

[0120] Figure 34 is a schematic diagram of the fifth conductive layer pattern in Figure 16;

[0121] Figure 35 is a schematic diagram of the fifth conductive layer pattern formed in Figure 16.

[0122] Detailed Explanation

[0123] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0124] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0125] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0126] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0127] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0128] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0129] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0130] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0131] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0132] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0133] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0134] Display products include pixel driving circuits and light-emitting devices. The pixel driving circuit drives the light-emitting devices to emit light, thereby realizing the display. When the level of at least one signal in the pixel driving circuit changes, charge leakage occurs, which in turn makes the signals of some nodes in the pixel driving circuit unstable, affecting the reliability of the pixel driving circuit and reducing the display effect of the display substrate.

[0135] Therefore, this disclosure provides a pixel driving circuit.

[0136] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. As shown in Figure 1, the pixel driving circuit provided in this embodiment of the disclosure is disposed in a display device and may include: a driving control sub-circuit, a reset sub-circuit, a driving sub-circuit, and a light emission control sub-circuit.

[0137] As shown in Figure 1, the reset sub-circuit is electrically connected to at least one reset signal line, a first initial signal line INIT1, a second initial signal line INIT2, a reference signal line REF, a second node N2, a fourth node N4, and a fifth node N5, respectively. It is configured to provide the reference signal line REF to the second node N2, the first initial signal line INIT1 to the fourth node N4, and the second initial signal line INIT2 to the fifth node N5 under the control of the signal from at least one reset signal line. The drive control sub-circuit is electrically connected to at least two scan signal lines, a data signal line Data, a first power supply line VDD, a first node N1, a second node N2, a third node N3, and a fourth node N4, respectively. It is configured to provide the reference signal line REF to the second node N2, the first initial signal line INIT1 to the fourth node N4, and the second initial signal line INIT2 to the fifth node N5, respectively, under the control of the signal from at least one reset signal line. Under the control of the signal D, a data signal line Data is provided to the second node N2, and a signal from the third node N3 or the fourth node N4 is provided to the first node N1; a driving sub-circuit is electrically connected to the first node N1, the second node N2, and the third node N3 respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals from the first node N1 and the second node N2; a light emission control sub-circuit is electrically connected to the first light emission signal line EM1, the second light emission signal line EM2, the first power supply line VDD, the second node N2, the third node N3, and the fifth node N5 respectively, and is configured to provide a signal from the first power supply line VDD to the second node N2 under the control of the signals from the first light emission signal line EM1 and the second light emission signal line EM2, and provide a signal from the third node N3 to the fifth node N5.

[0138] Figure 2 is a timing diagram of the signals of the first light-emitting signal line and the second light-emitting signal line. As shown in Figure 2, the display device includes: a first control unit, which is electrically connected to the first light-emitting signal line EM1 and the second light-emitting signal line EM2 respectively, and is configured to provide signals to the first light-emitting signal line EM1 and the second light-emitting signal line EM2. The time period during which the first control unit provides an effective level signal to the first light-emitting signal line EM1 does not overlap with the time period during which it provides an effective level signal to the second light-emitting signal line EM2.

[0139] In an exemplary embodiment, the display device includes: a multi-row pixel driving circuit, wherein the second light-emitting signal line connected to the i-th row pixel driving circuit and the first light-emitting signal line connected to the (i+1)-th row pixel driving circuit are the same signal line.

[0140] In an exemplary embodiment, as shown in FIG1, at least one reset signal line may include: a first reset signal line Reset1, or may include: a first reset signal line Reset1 and a second reset signal line Reset2.

[0141] In an exemplary embodiment, as shown in FIG1, at least one scan signal line may include: a first scan signal line Gate1 and a third scan signal line Gate3, or may include: a first scan signal line Gate1, a second scan signal line Gate2 and a third scan signal line Gate3.

[0142] As shown in Figure 1, the light-emitting element EL is electrically connected to the fourth node N4 and the second power line VSS.

[0143] In an exemplary embodiment, the voltage value of the signal on the first initial signal line INIT1 is constant and is a DC signal. The voltage value of the signal on the first initial signal line INIT1 can be -3V. A DC signal can be one in which neither the magnitude nor the direction of the signal changes with time.

[0144] In an exemplary embodiment, the voltage value of the signal on the second initial signal line INIT2 is constant and is a DC signal; the voltage value of the signal on the second initial signal line INIT2 can be 0V.

[0145] In an exemplary embodiment, the voltage value of the reference signal line REF is constant and is a DC signal; the voltage value of the reference signal line REF can be 5V.

[0146] In an exemplary embodiment, the light-emitting element EL can be electrically connected to the fifth node N5 and the second power line VSS, respectively.

[0147] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the second power line VSS continuously provides a low-level signal.

[0148] In an exemplary embodiment, the light-emitting element EL can be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). Exemplarily, the anode of the organic light-emitting diode is electrically connected to a fourth node N4, and the cathode of the organic light-emitting diode is electrically connected to a second power line VSS.

[0149] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0150] This disclosure ensures that the time period during which the first control unit provides an effective level signal to the first light-emitting signal line does not overlap with the time period during which it provides an effective level signal to the second light-emitting signal line. This disperses the charge discharge that occurs when the signal level changes, ensures the stability of the node signals in the pixel driving circuit, improves the reliability of the pixel driving circuit, and guarantees the display effect of the display substrate.

[0151] In an exemplary embodiment, Figure 3 is an equivalent circuit diagram of the driving sub-circuit and the light-emitting control sub-circuit. As shown in Figure 3, the driving sub-circuit includes a third transistor T3, and the light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5.

[0152] In an exemplary embodiment, the third transistor T3 may be referred to as the driving transistor. The third transistor T3 can determine the magnitude of the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode.

[0153] In an exemplary embodiment, the fifth transistor T5 can be referred to as the first light-emitting transistor, and the sixth transistor T6 can be referred to as the second light-emitting transistor. When the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are both valid level signals, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device EL to emit light by forming a driving current path between the first power line VDD and the second power line VSS.

[0154] Figure 3 shows an exemplary structure of the driver sub-circuit. It will be readily understood by those skilled in the art that the implementation of the driver sub-circuit is not limited to this.

[0155] Figure 3 also shows an exemplary structure of the light-emitting control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the light-emitting control sub-circuit is not limited to this.

[0156] In an exemplary embodiment, as shown in FIG2, the start time of the time period during which the first control unit provides an effective level signal to the first light-emitting signal line EM1 is earlier than the start time of the time period during which the first control unit provides an effective level signal to the second light-emitting signal line EM2, and the end time of the time period during which the first control unit provides an effective level signal to the first light-emitting signal line EM1 is earlier than the end time of the time period during which the first control unit provides an effective level signal to the second light-emitting signal line EM2.

[0157] In an exemplary embodiment, FIG4 is an equivalent circuit diagram of a reset sub-circuit. FIG4 is illustrated with an example of at least one reset signal line including a first reset signal line Reset1. As shown in FIG4, when at least one reset signal line includes the first reset signal line Reset1, the reset sub-circuit may include a first transistor T1, a seventh transistor T7, and a ninth transistor T9. As shown in FIG4, the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the seventh transistor T7 is electrically connected to the first reset signal line Reset1, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5; the control electrode of the ninth transistor T9 is electrically connected to the first reset signal line Reset1, the first electrode of the ninth transistor T9 is electrically connected to the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2.

[0158] In an exemplary embodiment, when at least one reset signal line includes a first reset signal line Reset1, the display device further includes a second control unit, which is electrically connected to the first reset signal line Reset1 and configured to provide a signal to the first reset signal line Reset1; at least one of the time periods during which the second control unit provides an effective level signal to the first reset signal line Reset1 and the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line EM1 and the second light-emitting signal line EM2 overlaps at least partially.

[0159] In an exemplary embodiment, at least one reset signal line includes: a first reset signal line Reset1 and a second reset signal line Reset2. The reset sub-circuit is configured to provide a signal of a first initial signal line INIT1 to the fourth node N4 under the control of the signal of the first reset signal line Reset1, provide a signal of a second initial signal line INIT2 to the fifth node N5 under the control of the signal of the second reset signal line Reset2, and provide a signal of a reference signal line REF to the second node N2.

[0160] In an exemplary embodiment, FIG5 is another equivalent circuit diagram of the reset sub-circuit. FIG5 is illustrated with an example of at least one reset signal line including: a first reset signal line Reset1 and a second reset signal line Reset2. When at least one reset signal line includes: a first reset signal line Reset1 and a second reset signal line Reset2, the reset sub-circuit may include: a first transistor T1, a seventh transistor T7, and a ninth transistor T9. Specifically, the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Reset2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5; the control electrode of the ninth transistor T9 is electrically connected to the second reset signal line Reset2, the first electrode of the ninth transistor T9 is electrically connected to the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2.

[0161] In an exemplary embodiment, when at least one reset signal line includes a first reset signal line Reset1 and a second reset signal line Reset2, the display device further includes a second control unit. The second control unit is electrically connected to the first reset signal line Reset1 and the second reset signal line Reset2, respectively, and is configured to provide signals to the first reset signal line Reset1 and the second reset signal line Reset2. The time period during which the second control unit provides a valid level signal to the first reset signal line Reset1 does not overlap with the time period during which the second control unit provides a valid level signal to the second reset signal line Reset2, and the end time of the time period during which the second control unit provides a valid level signal to the second reset signal line Reset2 is earlier than the start time of the time period during which the second control unit provides a valid level signal to the first reset signal line Reset1. At least one of the time periods during which the second control unit provides a valid level signal to the first reset signal line Reset1 and the second control unit provides a valid level signal to the second reset signal line Reset2 at least partially overlaps with at least one of the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line EM1 and the second light-emitting signal line EM2.

[0162] Figures 4 and 5 also illustrate two exemplary structures of the reset sub-circuit. It will be readily understood by those skilled in the art that the implementation of the reset sub-circuit is not limited to these.

[0163] In an exemplary embodiment, when at least two scan signal lines include a first scan signal line Gate1 and a third scan signal line Gate3, the drive control sub-circuit is configured to provide a data signal line Data to the second node N2 and a signal of the third node N3 to the fourth node N4 under the control of the signal of the first scan signal line Gate1, and to provide a signal of the fourth node N4 to the first node N1 under the control of the signal of the third scan signal line Gate3.

[0164] In an exemplary embodiment, FIG6 is an equivalent circuit diagram of a drive control sub-circuit. FIG6 is illustrated using at least two scan signal lines, including a first scan signal line Gate1 and a third scan signal line Gate3. When at least two scan signal lines include a first scan signal line Gate1 and a third scan signal line Gate3, the drive control sub-circuit may include a capacitor C, a second transistor T2, a fourth transistor T4, and an eighth transistor T8. The capacitor C includes a first plate and a second plate. Specifically, the control electrode of the second transistor T2 is electrically connected to the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the eighth transistor T8 is electrically connected to the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the first plate of capacitor C is electrically connected to the first power supply line VDD, and the second plate of capacitor C is electrically connected to the first node N1.

[0165] In an exemplary embodiment, when at least two scan signal lines include a first scan signal line Gate1 and a third scan signal line Gate3, the display device further includes a third control unit and a fourth control unit. The third control unit is electrically connected to the first scan signal line Gate1 and configured to provide a signal to the first scan signal line Gate1. The fourth control unit is electrically connected to the third scan signal line Gate3 and configured to provide a signal to the third scan signal line Gate3. Specifically, the time period during which the third control unit provides a valid level signal to the first scan signal line Gate1 at least partially overlaps with the time period during which the fourth control unit provides a valid level signal to the third scan signal line Gate3. At least one of the time periods during which the third control unit provides a valid level signal to the first scan signal line Gate1 and the fourth control unit provides a valid level signal to the third scan signal line Gate3 at least partially overlaps with at least one of the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line EM1 and the second light-emitting signal line EM2 at least partially overlaps with the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line EM1 and the second light-emitting signal line EM2 at least partially overlaps with the time periods during which the third control unit provides an invalid level signal to the first light-emitting signal line EM1 at least partially overlaps with the time periods during which the first control unit provides an invalid level signal to the second light-emitting signal line EM2 at least partially overlaps with the time periods during which the third control unit provides an invalid level signal to the first light-emitting signal line EM1 at least partially overlaps with the time periods during which the fourth ...

[0166] In an exemplary embodiment, when at least two scan signal lines include a first scan signal line Gate1, a second scan signal line Gate2, and a third scan signal line Gate3, the drive control sub-circuit is configured to provide a data signal line Data to the second node N2 under the control of the signal of the first scan signal line Gate1, provide a signal of the third node N3 to the fourth node N4 under the control of the signal of the second scan signal line Gate2, and provide a signal of the fourth node N4 to the first node N1 under the control of the signal of the third scan signal line Gate3.

[0167] In an exemplary embodiment, FIG7 is another equivalent circuit diagram of the drive control sub-circuit. FIG7 is illustrated with an example of at least two scan signal lines including: a first scan signal line Gate1, a second scan signal line Gate2, and a third scan signal line Gate3. When at least two scan signal lines include: a first scan signal line Gate1, a second scan signal line Gate2, and a third scan signal line Gate3, the drive control sub-circuit may include: a capacitor C, a second transistor T2, a fourth transistor T4, and an eighth transistor T8, wherein the capacitor C includes: a first plate and a second plate. The control electrode of the second transistor T2 is electrically connected to the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the second scan signal line Gate2, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the eighth transistor T8 is electrically connected to the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the first plate of capacitor C is electrically connected to the first power supply line VDD, and the second plate of capacitor C is electrically connected to the first node N1.

[0168] In an exemplary embodiment, when at least two scan signal lines include a first scan signal line Gate1, a second scan signal line Gate2, and a third scan signal line Gate3, the display device further includes a third control unit, a fourth control unit, and a fifth control unit. The third control unit is electrically connected to the first scan signal line Gate1 and is configured to provide a signal to the first scan signal line Gate1. The fourth control unit is electrically connected to the third scan signal line Gate3 and is configured to provide a signal to the third scan signal line Gate3. The fifth control unit is electrically connected to the second scan signal line Gate2 and is configured to provide a signal to the second scan signal line Gate2. The time periods during which the fifth control unit provides a valid level signal to the second scan signal line Gate2 include: a first time period and a second time period, wherein the end time of the first time period is earlier than the start time of the second time period; the time period during which the third control unit provides a valid level signal to the first scan signal line Gate1 at least partially overlaps with the second time period and does not overlap with the first time period; at least one of the first time period and the second time period at least partially overlaps with the time period during which the fourth control unit provides a valid level signal to the third scan signal line Gate3; and the time period during which the fourth control unit provides a valid level signal to the third scan signal line Gate3 at least partially overlaps with at least one of the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line EM1 and the second light-emitting signal line EM2.

[0169] In an exemplary embodiment, the transistor type of the eighth transistor T8 is different from that of at least one of the second transistor T2 and the fourth transistor T4. Exemplarily, the eighth transistor T8 can be an N-type transistor, and the second transistor T2 and the fourth transistor T4 can be P-type transistors; this disclosure does not impose any limitations on this.

[0170] Figures 6 and 7 illustrate two exemplary structures of the drive control subcircuit. It will be readily understood by those skilled in the art that the implementation of the drive control subcircuit is not limited to these examples.

[0171] Figure 8 is an equivalent circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure. Figure 8 is illustrated using at least one reset signal line including a first reset signal line Reset1, and at least one scan signal line including a first scan signal line Gate1 and a third scan signal line Gate3 as an example. As shown in Figure 8, the driving sub-circuit includes a third transistor T3, the light emission control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the reset sub-circuit includes a first transistor T1, a seventh transistor T7 and a ninth transistor T9, and the driving control sub-circuit includes a capacitor C, a second transistor T2, a fourth transistor T4 and an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first terminal of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second terminal of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal line Gate1, the first terminal of the second transistor T2 is electrically connected to the fourth node N4, and the second terminal of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first terminal of the fourth transistor T4 is electrically connected to the data signal line Data, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first light emission signal line EM1, the first terminal of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the fifth transistor T5... The second electrode of transistor 5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the first reset signal line Reset1, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5; the control electrode of the eighth transistor T8 is electrically connected to the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected to the first reset signal line Reset1, the first electrode of the ninth transistor T9 is electrically connected to the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2; the first plate of capacitor C is electrically connected to the first power supply line VDD, and the second plate of capacitor C is electrically connected to the first node N1.

[0172] Figure 9 is an equivalent circuit diagram of the pixel driving circuit provided in this embodiment of the present disclosure. Figure 9 is illustrated using an example of at least one reset signal line including a first reset signal line Reset1 and a second reset signal line Reset2, and at least one scan signal line including a first scan signal line Gate1 and a third scan signal line Gate3. As shown in Figure 9, the driving sub-circuit includes a third transistor T3, the light emission control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the reset sub-circuit includes a first transistor T1, a seventh transistor T7 and a ninth transistor T9, and the driving control sub-circuit includes a capacitor C, a second transistor T2, a fourth transistor T4 and an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first terminal of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second terminal of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal line Gate1, the first terminal of the second transistor T2 is electrically connected to the fourth node N4, and the second terminal of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first terminal of the fourth transistor T4 is electrically connected to the data signal line Data, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first light emission signal line EM1, the first terminal of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the fifth transistor T5... The second electrode of transistor 5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Reset2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5; the control electrode of the eighth transistor T8 is electrically connected to the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected to the second reset signal line Reset2, the first electrode of the ninth transistor T9 is electrically connected to the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2; the first plate of capacitor C is electrically connected to the first power supply line VDD, and the second plate of capacitor C is electrically connected to the first node N1.

[0173] Figure 10 is an equivalent circuit diagram of the pixel driving circuit provided in the embodiments of this disclosure. Figure 10 is illustrated using an example of at least one reset signal line including a first reset signal line Reset1, and at least one scan signal line including a first scan signal line Gate1, a second scan signal line Gate2, and a third scan signal line Gate3. As shown in Figure 10, the driving sub-circuit includes a third transistor T3, the light emission control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the reset sub-circuit includes a first transistor T1, a seventh transistor T7, and a ninth transistor T9, and the driving control sub-circuit includes a capacitor C, a second transistor T2, a fourth transistor T4, and an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the second scan signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first light emission signal line EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the fifth transistor T5... The second electrode of transistor 5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the first reset signal line Reset1, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5; the control electrode of the eighth transistor T8 is electrically connected to the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected to the first reset signal line Reset1, the first electrode of the ninth transistor T9 is electrically connected to the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2; the first plate of capacitor C is electrically connected to the first power supply line VDD, and the second plate of capacitor C is electrically connected to the first node N1.

[0174] Figure 11 is an equivalent circuit diagram of the pixel driving circuit provided in the embodiments of this disclosure. Figure 11 is illustrated using an example of at least one reset signal line including: a first reset signal line Reset1 and a second reset signal line Reset2, and at least one scan signal line including: a first scan signal line Gate1, a second scan signal line Gate2, and a third scan signal line Gate3. As shown in Figure 11, the driving sub-circuit includes: a third transistor T3, the light emission control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6, the reset sub-circuit includes: a first transistor T1, a seventh transistor T7, and a ninth transistor T9, and the driving control sub-circuit includes: a capacitor C, a second transistor T2, a fourth transistor T4, and an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the second scan signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first light emission signal line EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the fifth transistor T5... The second electrode of transistor 5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Reset2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5; the control electrode of the eighth transistor T8 is electrically connected to the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected to the second reset signal line Reset2, the first electrode of the ninth transistor T9 is electrically connected to the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2; the first plate of capacitor C is electrically connected to the first power supply line VDD, and the second plate of capacitor C is electrically connected to the first node N1.

[0175] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0176] In an exemplary embodiment, the pixel driving circuit provided in this disclosure includes a ninth transistor, which can reset the first electrode of the third transistor, improve the variable refresh rate of the display device, and prevent the display device from producing image retention.

[0177] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 in the pixel driving circuit provided in this disclosure are controlled by different light-emitting signal lines, which can more flexibly adjust the signal of the second node N2.

[0178] In an exemplary embodiment, the signal of the first reset signal line connected to the pixel driving circuit may be the same as the signal of the first scan signal line connected to at least the pixel driving circuit in the row preceding the pixel driving circuit, and this disclosure does not limit it in any way.

[0179] In an exemplary embodiment, the signal of the second reset signal line connected to the pixel driving circuit can be the same as the signal of the first scan signal line connected to at least the first two rows of the pixel driving circuit. This disclosure does not limit this in any way.

[0180] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 can be either P-type or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the ninth transistor T9 may include both P-type and N-type transistors. For example, the eighth transistor T8 can be an N-type transistor, while the first transistor T1 to the seventh transistor T7 and the ninth transistor T9 are P-type transistors.

[0181] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0182] In an exemplary embodiment, some of the transistors in the first transistor T1 to the ninth transistor T9 can be oxide transistors, and some transistors can be low-temperature polysilicon transistors. Oxide transistors can reduce leakage current, improve the performance of the pixel driving circuit, and reduce the power consumption of the pixel driving circuit.

[0183] Figure 12 is a timing diagram of the pixel driving circuit provided in Figure 8. Figure 8 illustrates the operation using P-type transistors T1 to T7 and T9, and N-type transistor T8. As shown in Figure 12, the operation of the pixel driving circuit provided in Figure 8 may include:

[0184] In the first stage S11, also known as the initialization stage, the signal on the first reset signal line Reset1 is low, while the signals on the first scan signal line Gate1, the third scan signal line Gate3, the first light emission signal line EM1, and the second light emission signal line EM2 are high. The first transistor T1, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0185] The first transistor T1 and the eighth transistor T8 are turned on. The signal of the first initial signal line INIT1 is written to the first node N1 through the fourth node N4, initializing (resetting) the first node N1 and the fourth node N4, clearing their internal pre-stored voltages, and completing the initialization. The seventh transistor T7 is turned on. The signal of the second initial signal line INIT2 is written to the fifth node N5, initializing (resetting) the anode of the light-emitting element EL, clearing its internal pre-stored voltages, and completing the initialization. The ninth transistor T9 is turned on. The signal of the reference signal line REF is written to the second node N2, initializing (resetting) the second node N2, clearing its internal pre-stored voltages, and completing the initialization.

[0186] The second stage, S12, is called the threshold compensation and data writing stage. The first scan signal line Gate1 is at a low level, while the first reset signal line Reset1, the third scan signal line Gate3, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are at a high level. The data signal line Data outputs the data voltage. The second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on, while the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned off.

[0187] The second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on. The data voltage output from the data signal line Data is supplied to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fourth node N4, and the turned-on eighth transistor T8. The difference between the data voltage output from the data signal line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output from the data signal line Data and Vth is the threshold voltage of the third transistor T3.

[0188] In the third stage S13, the signals of the third scan signal line Gate3 and the first light-emitting signal line EM1 are low-level signals, while the signals of the first scan signal line Gate1, the first reset signal line Reset1, and the second light-emitting signal line EM2 are high-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0189] When the fifth transistor T5 is turned on, the signal of the first power line VDD is written into the second node N2.

[0190] In the fourth stage, S14, known as the light-emitting stage, the signals of the first light-emitting signal line EM1, the second light-emitting signal line EM2, and the third scan signal line Gate3 are low-level signals, while the signals of the first reset signal line Reset1 and the first scan signal line Gate1 are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0191] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power line VDD provides a driving voltage to the first terminal of the light-emitting element EL through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, driving the light-emitting element L to emit light.

[0192] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor T3 is: I = K*(Vgs - Vth). 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0193] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device EL, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0194] Figure 13 is a timing diagram of the pixel driving circuit provided in Figure 9. Figure 9 illustrates the operation using P-type transistors T1 to T7 and T9, and N-type transistor T8 as an example. As shown in Figure 13, the operation of the pixel driving circuit provided in Figure 9 may include:

[0195] In the first stage S21, also known as the first initialization stage, the signal on the second reset signal line Reset2 is low, while the signals on the first reset signal line Reset1, the first scan signal line Gate1, the third scan signal line Gate3, the first light emission signal line EM1, and the second light emission signal line EM2 are high. The seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0196] When the seventh transistor T7 is turned on, the signal on the second initial signal line INIT2 is written to the fifth node N5, initializing (resetting) the anode of the light-emitting element EL, clearing its internal pre-stored voltage, and completing the initialization. When the ninth transistor T9 is turned on, the signal on the reference signal line REF is written to the second node N2, initializing (resetting) the second node N2, clearing its internal pre-stored voltage, and completing the initialization.

[0197] In the second stage S22, also known as the second initialization stage, the signal of the first reset signal line Reset1 is a low-level signal, while the signals of the second reset signal line Reset2, the first scan signal line Gate1, the third scan signal line Gate3, the first light emission signal line EM1, and the second light emission signal line EM2 are high-level signals. The first transistor T1 and the eighth transistor T8 are turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned off.

[0198] The first transistor T1 and the eighth transistor T8 are turned on. The signal of the first initial signal line INIT1 is written to the first node N1 through the fourth node N4, which initializes (resets) the first node N1 and the fourth node N4, clears the pre-stored voltage inside them, and completes the initialization.

[0199] The third stage, S23, is called the threshold compensation and data writing stage. The first scan signal line Gate1 is a low-level signal, while the first reset signal line Reset1, the second reset signal line Reset2, the third scan signal line Gate3, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. The data signal line Data outputs the data voltage. The second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on, while the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned off.

[0200] The second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on. The data voltage output from the data signal line Data is supplied to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fourth node N4, and the turned-on eighth transistor T8. The difference between the data voltage output from the data signal line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output from the data signal line Data and Vth is the threshold voltage of the third transistor T3.

[0201] In the fourth stage S24, the signals of the third scan signal line Gate3 and the first light-emitting signal line EM1 are low-level signals, while the signals of the first scan signal line Gate1, the first reset signal line Reset1, the second reset signal line Reset2, and the second light-emitting signal line EM2 are high-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0202] When the fifth transistor T5 is turned on, the signal of the first power line VDD is written into the second node N2.

[0203] In the fifth stage, S25, also known as the light-emitting stage, the signals of the first light-emitting signal line EM1, the second light-emitting signal line EM2, and the third scan signal line Gate3 are low-level signals, while the signals of the first reset signal line Reset1, the second reset signal line Reset2, and the first scan signal line Gate1 are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0204] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power line VDD provides a driving voltage to the first terminal of the light-emitting element EL through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, driving the light-emitting element L to emit light.

[0205] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor T3 is: I = K*(Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0206] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device EL, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0207] Figure 14 is a timing diagram of the pixel driving circuit provided in Figure 10. Figure 10 illustrates the operation using P-type transistors T1 to T7 and T9, and N-type transistor T8 as an example. As shown in Figure 14, the operation of the pixel driving circuit provided in Figure 10 may include:

[0208] In the first stage S31, also known as the initialization stage, the signals of the first reset signal line Reset1 and the second scan signal line Gate2 are low-level signals, while the signals of the first scan signal line Gate1, the third scan signal line Gate3, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. The first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, while the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0209] The first transistor T1 and the eighth transistor T8 are turned on. The signal of the first initial signal line INIT1 is written to the first node N1 through the fourth node N4, initializing (resetting) the first node N1 and the fourth node N4, clearing their internal pre-stored voltages, and completing the initialization. The first transistor T1 and the second transistor T2 are turned on. The signal of the first initial signal line INIT1 is written to the third node N3 through the fourth node N4, initializing (resetting) the third node N3 and the fourth node N4, clearing their internal pre-stored voltages, and completing the initialization. The seventh transistor T7 is turned on. The signal of the second initial signal line INIT2 is written to the fifth node N5, initializing (resetting) the anode of the light-emitting element EL, clearing its internal pre-stored voltages, and completing the initialization. The ninth transistor T9 is turned on. The signal of the reference signal line REF is written to the second node N2, initializing (resetting) the second node N2, clearing its internal pre-stored voltages, and completing the initialization.

[0210] The second stage, S32, is called the initialization stage. The signals of the first reset signal line Reset1, the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, the first light emission signal line EM1, and the second light emission signal line EM2 are all high-level signals. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are disconnected.

[0211] The third stage, S33, is called the threshold compensation and data writing stage. The signals on the first scan signal line Gate1 and the second scan signal line Gate2 are low-level signals, while the signals on the first reset signal line Reset1, the third scan signal line Gate3, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. The data signal line Data outputs the data voltage. The second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on, while the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned off.

[0212] The second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on. The data voltage output from the data signal line Data is supplied to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fourth node N4, and the turned-on eighth transistor T8. The difference between the data voltage output from the data signal line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output from the data signal line Data and Vth is the threshold voltage of the third transistor T3.

[0213] In the fourth stage S34, the signals of the third scan signal line Gate3 and the first light-emitting signal line EM1 are low-level signals, while the signals of the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, and the second light-emitting signal line EM2 are high-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0214] When the fifth transistor T5 is turned on, the signal of the first power line VDD is written into the second node N2.

[0215] In the fifth stage, S35, also known as the light-emitting stage, the signals of the first light-emitting signal line EM1, the second light-emitting signal line EM2, and the third scan signal line Gate3 are low-level signals, while the signals of the first reset signal line Reset1, the first scan signal line Gate1, and the second scan signal line Gate2 are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0216] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power line VDD provides a driving voltage to the first terminal of the light-emitting element EL through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, driving the light-emitting element L to emit light.

[0217] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor T3 is: I = K*(Vgs - Vth). 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0218] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device EL, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0219] Figure 15 is a timing diagram of the pixel driving circuit shown in Figure 11. Figure 11 illustrates the operation using P-type transistors T1 to T7 and T9, and N-type transistor T8 as an example. As shown in Figure 15, the operation of the pixel driving circuit shown in Figure 11 can include:

[0220] In the first stage S41, also known as the first initialization stage, the signals of the second reset signal line Reset2 and the second scan signal line Gate2 are low-level signals, while the signals of the first reset signal line Reset1, the first scan signal line Gate1, the third scan signal line Gate3, the first light emission signal line EM1, and the second light emission signal line EM2 are high-level signals. The second transistor T2, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, while the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0221] When the seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fifth node N5, initializing (resetting) the anode of the light-emitting element EL, clearing its internal pre-stored voltage, and completing the initialization. When the ninth transistor T9 is turned on, the signal of the reference signal line REF is written to the second node N2, initializing (resetting) the second node N2, clearing its internal pre-stored voltage, and completing the initialization. The second transistor T2 and the eighth transistor T8 are turned on, connecting the third node N3, the fourth node N4, and the first node N1. The second node N2 charges the signal of the first node N1, making the voltage value of the signal of the first node N1 Vref+Vth. At this time, the third transistor T3 is in a weak bias state, which is beneficial to the hysteresis recovery of the third transistor and can recover the threshold voltage drift caused by the third transistor being in a bias state in the previous display frame.

[0222] In the second stage S42, also known as the second initialization stage, the signal on the first reset signal line Reset1 is low, while the signals on the second reset signal line Reset2, the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, the first light emission signal line EM1, and the second light emission signal line EM2 are high. The first transistor T1 and the eighth transistor T8 are turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned off.

[0223] The first transistor T1 and the eighth transistor T8 are turned on. The signal of the first initial signal line INIT1 is written to the first node N1 through the fourth node N4, which initializes (resets) the first node N1 and the fourth node N4, clears the pre-stored voltage inside them, and completes the initialization.

[0224] The third stage, S43, is called the threshold compensation and data writing stage. The signals on the first scan signal line Gate1 and the second scan signal line Gate2 are low-level signals, while the signals on the first reset signal line Reset1, the second reset signal line Reset2, the third scan signal line Gate3, the first light emission signal line EM1, and the second light emission signal line EM2 are high-level signals. The data signal line Data outputs the data voltage. The second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on, while the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned off.

[0225] The second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on. The data voltage output from the data signal line Data is supplied to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fourth node N4, and the turned-on eighth transistor T8. The difference between the data voltage output from the data signal line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output from the data signal line Data and Vth is the threshold voltage of the third transistor T3.

[0226] In the fourth stage (S44), the signals of the third scan signal line Gate3 and the first light-emitting signal line EM1 are low-level signals, while the signals of the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2, and the second light-emitting signal line EM2 are high-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0227] When the fifth transistor T5 is turned on, the signal of the first power line VDD is written into the second node N2.

[0228] In the fifth stage, S45, also known as the light-emitting stage, the signals of the first light-emitting signal line EM1, the second light-emitting signal line EM2, and the third scan signal line Gate3 are low-level signals, while the signals of the first reset signal line Reset1, the second reset signal line Reset2, the first scan signal line Gate1, and the second scan signal line Gate2 are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0229] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power line VDD provides a driving voltage to the first terminal of the light-emitting element EL through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, driving the light-emitting element L to emit light.

[0230] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor T3 is: I = K*(Vgs - Vth). 2 =K*[(Vdd-Vd+|Vth|)-Vth]2 =K*(Vdd-Vd) 2

[0231] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device EL, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0232] In the exemplary embodiment, in the pixel driving circuit provided in FIG10 and FIG11, the second transistor T4 is driven through the first scan signal line Gate1, and the fourth transistor T4 is driven through the second scan signal line Gate2, thereby realizing the separate driving of the second transistor T2 and the fourth transistor T4, realizing the weak bias voltage reset of the driving transistor, and improving the bias voltage state of the driving transistor.

[0233] This disclosure also provides a display device, including: a substrate and a plurality of sub-pixels disposed on the substrate, wherein at least one sub-pixel includes: a pixel driving circuit.

[0234] Figure 16 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure, Figure 17 is a schematic diagram of a portion of the film layer in Figure 16 (first), and Figure 18 is a schematic diagram of a portion of the film layer in Figure 16 (second). As shown in Figures 16 to 18, the display device provided in the embodiment of this disclosure further includes: a plurality of first light-emitting signal lines EM1 and a plurality of second light-emitting signal lines EM2, wherein at least one of the first light-emitting signal lines EM1 and the second light-emitting signal lines EM2 extends at least partially along a first direction D1. Figures 16 to 18 are illustrated using the pixel driving circuit provided in Figure 8 as an example.

[0235] The first light-emitting signal line EM1(j) connected to the pixel driving circuit of the j-th row sub-pixel and the second light-emitting signal line EM2(j-1) connected to the pixel driving circuit of the (j-1)-th row sub-pixel are the same signal line, 1≤j≤N, where N is the total number of rows of sub-pixels.

[0236] In an exemplary embodiment, as shown in Figures 16 to 18, the display device further includes: a plurality of first reset signal lines Reset1, wherein the first reset signal lines Reset1 extend at least partially along a first direction D1. The first reset signal lines connected to the pixel driving circuit of the j-th row sub-pixel include two lines. The first first reset signal line Reset1(j) connected to the pixel driving circuit of the j-th row sub-pixel is the same signal line as the second first reset signal line Reset1(j-1) connected to the pixel driving circuit of the (j-1)-th row sub-pixel. The second first reset signal line Reset1(j) connected to the pixel driving circuit of the j-th row sub-pixel is the same signal line as the first first reset signal line Reset1(j+1) connected to the pixel driving circuit of the (j+1)-th row sub-pixel.

[0237] In an exemplary embodiment, as shown in Figures 16 to 18, the display device further includes: a plurality of first scan signal lines Gate1, a plurality of third scan signal lines Gate3, a plurality of first initial signal lines INIT1, a plurality of second initial signal lines INIT2, and a plurality of reference signal lines REF. At least one of the first scan signal lines Gate1, Gate3, INIT1, INIT2, and REF extends at least partially along a first direction D1.

[0238] In an exemplary embodiment, as shown in Figures 16 to 18, the first light-emitting signal line EM1(j) connected to the pixel driving circuit of the j-th row sub-pixel, the first first reset signal line Reset1(j) connected to the pixel driving circuit of the j-th row sub-pixel, the first scan signal line Gate1(j) connected to the pixel driving circuit of the j-th row sub-pixel, the second light-emitting signal line EM2(j) connected to the pixel driving circuit of the j-th row sub-pixel, and the second first reset signal line Reset1(j) connected to the pixel driving circuit of the j-th row sub-pixel are arranged sequentially along the second direction D2, and the first direction D1 intersects the second direction D2.

[0239] In an exemplary embodiment, as shown in Figures 16 to 18, the orthographic projection of the reference signal line REF(j) connected to the pixel driving circuit of the j-th row sub-pixel on the substrate at least partially overlaps with the first reset signal line Reset1(j) connected to the pixel driving circuit of the j-th row sub-pixel. The orthographic projection of the second initial signal line INIT2(j) connected to the pixel driving circuit of the j-th row sub-pixel on the substrate at least partially overlaps with the orthographic projection of the first light emission signal line EM1(j) connected to the pixel driving circuit of the j-th row sub-pixel on the substrate. The third scan signal line Gate3(j) connected to the pixel driving circuit of the j-th row sub-pixel on the substrate at least partially overlaps with the first light emission signal line EM1 ... The orthographic projection is located between the orthographic projection of the first scan signal line Gate1(j) connected to the pixel driving circuit of the j-th sub-pixel on the substrate and the orthographic projection of the first reset signal line Reset1(j) connected to the pixel driving circuit of the j-th sub-pixel on the substrate. The orthographic projection of the second initial signal line INIT2(j) connected to the pixel driving circuit of the j-th sub-pixel on the substrate is located on the side away from the orthographic projection of the second light emission signal line EM2(j) connected to the pixel driving circuit of the j-th sub-pixel on the substrate.

[0240] In an exemplary embodiment, as shown in FIG16, at least one pixel driving circuit includes: a first transistor T1 to a ninth transistor T9, and at least one transistor includes: an active pattern.

[0241] The active patterns T11 of the first transistor, T21 of the second transistor, T31 of the third transistor, T41 of the fourth transistor, T61 of the sixth transistor, and T71 of the seventh transistor, located in the same sub-pixel, are integrated into one structure. The active patterns T51 of the fifth transistor and T91 of the ninth transistor, located in the same sub-pixel, are also integrated into one structure.

[0242] The active pattern T51(j) of the fifth transistor in the pixel driving circuit of the j-th sub-pixel and the active pattern T61(j-1) of the sixth transistor in the pixel driving circuit of the (j-1)-th sub-pixel are arranged along the first direction D1. The active pattern T91(j) of the ninth transistor in the pixel driving circuit of the j-th sub-pixel, the active pattern T11(j) of the first transistor in the pixel driving circuit of the j-th sub-pixel and the active pattern T71(j-1) of the seventh transistor in the pixel driving circuit of the (j-1)-th sub-pixel are arranged along the first direction D1.

[0243] In an exemplary embodiment, as shown in Figures 16 to 19, at least one transistor further includes a first electrode and a second electrode, the active pattern includes a first region and a second region, the second electrode T54 of the fifth transistor and the second electrode T94 of the ninth transistor are integral structures and extend along the second direction D2.

[0244] In an exemplary embodiment, the first region of the active pattern of the third transistor is the same region as the second region of the active pattern of the fourth transistor, and the second region of the active pattern of the fifth transistor is the same region as the second region of the active pattern of the ninth transistor. The second terminal of the fifth transistor is connected to both the first region of the active pattern of the third transistor and the second region of the active pattern of the fifth transistor.

[0245] In an exemplary embodiment, the orthographic projection of the second pole T54(j) of the fifth transistor in the pixel driving circuit of the j-th column sub-pixel on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the reference signal line REF(j) connected to the pixel driving circuit of the j-th row sub-pixel, the second initial signal line INIT2(j-1) connected to the sub-pixel of the (j-1)-th row, the third scan signal line Gate3(j) connected to the pixel driving circuit of the j-th row sub-pixel, and the first scan signal line Gate1(j) connected to the pixel driving circuit of the j-th row sub-pixel.

[0246] In an exemplary embodiment, as shown in FIG16, the display device may further include: a plurality of initial connection lines INL, a plurality of first power lines VDD, and a plurality of data signal lines Data, wherein at least one of the first power lines VDD, data signal lines Data, and initial connection lines INL extends at least partially along a second direction D2. The at least one initial connection line INL is electrically connected to at least one first initial signal line INIT1.

[0247] In an exemplary embodiment, the display device further includes: a substrate and a driving structure layer disposed on the substrate, the driving structure layer being provided with a pixel driving circuit, the pixel driving circuit including: at least one N-type transistor, at least one P-type transistor and a capacitor, the capacitor including: a first electrode plate and a second electrode plate, the transistor including: an active pattern, a control electrode, a first electrode and a second electrode, and a third scan signal line including a first sub-signal line and a second sub-signal line.

[0248] The driving structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are sequentially stacked on the substrate.

[0249] The first semiconductor layer includes at least one active pattern of a P-type transistor.

[0250] The first conductive layer includes at least: a first scan signal line, a first light emission signal line, a second light emission signal line, a first reset signal line, a first electrode of a capacitor located in at least one pixel driving circuit, and a control electrode of at least one P-type transistor.

[0251] The second conductive layer includes at least: a first sub-signal line of the third scan signal line, a second initial signal line, and a second plate of a capacitor located in the pixel driving circuit of at least one sub-pixel.

[0252] The second semiconductor layer includes at least one active pattern of an N-type transistor.

[0253] The third conductive layer includes at least: a second sub-signal line of the third scan signal line, a first initial signal line, and a reference signal line.

[0254] The fourth conductive layer includes at least: an initial connection line and a first and second pole of at least one transistor located in at least one pixel driving circuit.

[0255] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. The rigid substrate may be, but is not limited to, one or more of glass and conductive foil. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0256] In an exemplary embodiment, the display device may further include a light-emitting structure layer.

[0257] In an exemplary embodiment, the light-emitting structure layer includes: an anode layer, a pixel definition layer, an organic structure layer, and a cathode layer sequentially stacked on a substrate. The anode layer includes: an anode of at least one light-emitting device; the organic structure layer includes: an organic light-emitting layer; and the cathode layer includes: a cathode of at least one light-emitting device.

[0258] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0259] Figures 19 to 35 illustrate the process using two pixel driving circuits as shown in Figure 16 as examples. The fabrication process of the display substrate provided in this disclosure may include:

[0260] (1) Forming a light-shielding layer pattern. In an exemplary embodiment, forming a light-shielding layer pattern includes: depositing a light-shielding film on a substrate, and patterning the light-shielding film through a patterning process to form a light-shielding layer pattern, as shown in FIG19. FIG19 is a schematic diagram of FIG16 after the light-shielding layer pattern is formed.

[0261] In an exemplary embodiment, as shown in FIG19, the light-shielding layer pattern may include: light-shielding portions SDL arranged in an array and spaced apart from each other, and the light-shielding layer pattern may also include: a first light-shielding connecting portion SL1 and a second light-shielding connecting portion SL2.

[0262] In an exemplary embodiment, the shape of the light-shielding part SHL can be square.

[0263] In an exemplary embodiment, the first light-shielding connector SL1 connects to adjacent light-shielding connectors SDL located in the same column. In an exemplary embodiment, the shape of the first light-shielding connector SL1 can be a strip structure extending along the second direction D2.

[0264] In an exemplary embodiment, the second light-shielding connector SL2 connects to an adjacent light-shielding connector SDL located in the same row. In an exemplary embodiment, the shape of the second light-shielding connector SL2 can be a strip-shaped structure extending along the first direction D1.

[0265] (2) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, and patterning the first semiconductor film by a patterning process to form a first insulating layer covering the substrate and a first semiconductor layer pattern disposed on the first insulating layer, as shown in Figures 20 and 21. Figure 20 is a schematic diagram of the first semiconductor layer pattern in Figure 16, and Figure 21 is a schematic diagram of the first semiconductor layer pattern after it has been formed in Figure 16.

[0266] In an exemplary embodiment, as shown in Figures 20 and 21, the first semiconductor layer pattern may include at least: an active pattern T11 of a first transistor, an active pattern T21 of a second transistor, an active pattern T31 of a third transistor, an active pattern T41 of a fourth transistor, an active pattern T51 of a fifth transistor, an active pattern T61 of a sixth transistor, an active pattern T71 of a seventh transistor, and an active pattern T91 of a ninth transistor located in at least one sub-pixel. In Figure 21, the active pattern T11(j) of the first transistor refers to the active pattern of the first transistor in the pixel driving circuit of the j-th row sub-pixel; the active pattern T21(j) of the second transistor refers to the active pattern of the second transistor in the pixel driving circuit of the j-th row sub-pixel; the active pattern T31(j) of the third transistor refers to the active pattern of the third transistor in the pixel driving circuit of the j-th row sub-pixel; the active pattern T41(j) of the fourth transistor refers to the active pattern of the fourth transistor in the pixel driving circuit of the j-th row sub-pixel; the active pattern T51(j) of the fifth transistor refers to the active pattern of the fifth transistor in the pixel driving circuit of the j-th row sub-pixel; the active pattern T61(j) of the sixth transistor refers to the active pattern of the sixth transistor in the pixel driving circuit of the j-th row sub-pixel; the active pattern T71(j) of the seventh transistor refers to the active pattern of the seventh transistor in the pixel driving circuit of the j-th row sub-pixel; and the active pattern T91(j) of the ninth transistor refers to the active pattern of the ninth transistor in the pixel driving circuit of the j-th row sub-pixel.

[0267] In an exemplary embodiment, the active patterns T11 of the first transistor, T21 of the second transistor, T31 of the third transistor, T41 of the fourth transistor, T51 of the fifth transistor, T61 of the sixth transistor, T71 of the seventh transistor, and T91 of the ninth transistor, which are adjacent sub-pixels located in the same row, are symmetrically arranged with respect to a virtual straight line extending along the second direction D2.

[0268] In an exemplary embodiment, the active patterns T11 of the first transistor, T21 of the second transistor, T31 of the third transistor, T41 of the fourth transistor, T61 of the sixth transistor, and T71 of the seventh transistor, all located in the same sub-pixel, are integrated into a single structure. The active patterns T51 of the fifth transistor and T91 of the ninth transistor, also located in the same sub-pixel, are integrated into a single structure. The integrated structure of the active patterns T11, T21, T31, T41 of the fourth transistor, T61 of the sixth transistor, and T71 of the seventh transistor, and the integrated structure of the active patterns T51 of the fifth transistor and T91 of the ninth transistor, located in the same sub-pixel, are separately configured.

[0269] In an exemplary embodiment, for the pixel driving circuit of the j-th row sub-pixel, in the first direction D1, the active pattern T41(j) of the fourth transistor can be located on the same side of the active pattern T31(j) of the third transistor, the active pattern T61(j) of the sixth transistor can be located on the same side of the active pattern T31(j) of the third transistor, and the active pattern T61(j) of the sixth transistor and the active pattern T41(j) of the fourth transistor can be located on different sides of the active pattern T31(j) of the third transistor of the sub-pixel. In the second direction D2, the active patterns T11(j) of the first transistor, T21(j) of the second transistor, T41(j) of the fourth transistor, T51(j) of the fifth transistor, and T91(j) of the ninth transistor are located on the side of the active pattern T31(j) of the third transistor in the pixel driving circuit of the j-th row sub-pixel, which is close to the pixel driving circuit of the (j-1)-th row sub-pixel. The active pattern T71(j) of the seventh transistor can be located on the side of the pixel driving circuit of the j-th row sub-pixel close to the pixel driving circuit of the (j+1)-th row sub-pixel.

[0270] In an exemplary embodiment, the active pattern T51(j) of the fifth transistor and the active pattern T91(j) of the ninth transistor in the pixel driving circuit of the j-th row sub-pixel are located on the side of the active pattern T41(j) of the fourth transistor in the pixel driving circuit of the j-th row sub-pixel that is close to the pixel driving circuit of the (j-1)-th row sub-pixel, and the active pattern T51(j) of the fifth transistor in the pixel driving circuit of the j-th row sub-pixel is located on the side of the active pattern T91(j) of the ninth transistor that is far away from the active pattern T31(j) of the third transistor.

[0271] In an exemplary embodiment, the active pattern T51(j) of the fifth transistor in the pixel driving circuit of the j-th row sub-pixel and the active pattern T61(j-1) of the sixth transistor in the pixel driving circuit of the (j-1)-th row sub-pixel are arranged along the first direction D1. The active pattern T91(j) of the ninth transistor in the pixel driving circuit of the j-th row sub-pixel, the active pattern T11(j) of the first transistor in the pixel driving circuit of the j-th row sub-pixel, and the active pattern T71(j-1) of the seventh transistor in the pixel driving circuit of the (j-1)-th row sub-pixel are arranged along the first direction D1.

[0272] In an exemplary embodiment, for at least one sub-pixel, the active pattern T31 of the third transistor can be shaped like an inverted "Ω". The active patterns T11 of the first transistor, T41 of the fourth transistor, T51 of the fifth transistor, T61 of the sixth transistor, T71 of the seventh transistor, and T91 of the ninth transistor can be shaped like an "I". The active pattern T21 of the second transistor can be shaped like a "┐".

[0273] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, for a pixel driving circuit of at least one sub-pixel, the second region T11_2 of the active pattern T11 of the first transistor can simultaneously serve as the first region T21-1 of the active pattern T21 of the second transistor; the first region T31_1 of the active pattern 13 of the third transistor can simultaneously serve as the second region T41_2 of the active pattern T41 of the fourth transistor; the second region T31_2 of the active pattern T31 of the third transistor can simultaneously serve as the second region T21-2 of the active pattern T21 of the second transistor and the first region T61_1 of the active pattern T61 of the sixth transistor; and the second region T61_2 of the active pattern T61 of the sixth transistor. The second region T71_2 of the active pattern T71 of the seventh transistor can be used as the second region T91_2 of the active pattern T51 of the fifth transistor. The first region T11-1 of the active pattern T11 of the first transistor, the first region T41_1 of the active pattern T41 of the fourth transistor, the first region T51_1 of the active pattern T51 of the fifth transistor, the first region T71_1 of the active pattern T71 of the seventh transistor, and the first region T91-1 of the active pattern T91 of the ninth transistor can be set individually.

[0274] In an exemplary embodiment, the first region T71_1 of the active pattern T71 of at least two adjacent sub-pixels of the seventh transistor located in the same row is the same region.

[0275] In an exemplary embodiment, the orthographic projection of the active pattern T31 of the third transistor in the pixel driving circuit of at least one sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the light-shielding portion onto the substrate.

[0276] (3) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; and patterning the second insulating film and the first conductive film using a patterning process to form a second insulating layer pattern and a first conductive layer pattern located on the second insulating layer, as shown in Figures 22 and 23. Figure 22 is a schematic diagram of the first conductive layer pattern in Figure 16, and Figure 23 is a schematic diagram of Figure 16 after the first conductive layer pattern has been formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0277] In an exemplary embodiment, as shown in Figures 22 and 23, the first conductive layer pattern may include: a first scan signal line Gate1, a first light-emitting signal line EM1, a second light-emitting signal line EM2, a first reset signal line Reset1, and a first electrode C1 of a capacitor located in at least one pixel driving circuit, a control electrode T11 of a first transistor, a control electrode T22 of a second transistor, a control electrode T32 of a third transistor, a control electrode T42 of a fourth transistor, a control electrode T52 of a fifth transistor, a control electrode T62 of a sixth transistor, a control electrode T72 of a seventh transistor, and a control electrode T92 of a ninth transistor. In Figure 22, Gate1(j) refers to the first scan signal line connected to the pixel driving circuit of the j-th row sub-pixel, EM1(j) refers to the first light-emitting signal line connected to the pixel driving circuit of the j-th row sub-pixel, EM2(j) refers to the second light-emitting signal line connected to the pixel driving circuit of the j-th row sub-pixel, and Reset1(j) refers to the first reset signal line connected to the pixel driving circuit of the j-th row sub-pixel.

[0278] In an exemplary embodiment, the first light-emitting signal line EM1(j) connected to the pixel driving circuit of the j-th row sub-pixel and the second light-emitting signal line EM2(j-1) connected to the pixel driving circuit of the (j-1)-th row sub-pixel are the same signal line.

[0279] In an exemplary embodiment, the first reset signal line Reset1(j) connected to the pixel driving circuit of the j-th row sub-pixel includes two lines. Specifically, the first first reset signal line Reset1(j) connected to the pixel driving circuit of the j-th row sub-pixel is the same signal line as the second first reset signal line Reset1(j-1) connected to the pixel driving circuit of the (j-1)-th row sub-pixel, and the second first reset signal line Reset1(j) connected to the pixel driving circuit of the j-th row sub-pixel is the same signal line as the first first reset signal line Reset1(j+1) connected to the pixel driving circuit of the (j+1)-th row sub-pixel.

[0280] In an exemplary embodiment, the first light-emitting signal line EM1(j) (which is also the second light-emitting signal line EM2(j-1) connected to the pixel driving circuit of the (j-1)th row of sub-pixels), the first first reset signal line Reset1(j) (which is also the second first reset signal line Reset1(j-1) connected to the pixel driving circuit of the (j-1)th row of sub-pixels), the first scan signal line Gate1(j) connected to the pixel driving circuit of the jth row of sub-pixels, the second light-emitting signal line EM2(j) (which is also the first light-emitting signal line EM1(j+1) connected to the pixel driving circuit of the (j+1)th row of sub-pixels), and the second first reset signal line Reset1(j) (which is also the first first reset signal line Reset1(j+1) connected to the pixel driving circuit of the jth row of sub-pixels) are arranged sequentially along the second direction D2.

[0281] In an exemplary embodiment, the first plate C1 of the capacitor of the pixel driving circuit of adjacent sub-pixels, the control electrode T11 of the first transistor, the control electrode T22 of the second transistor, the control electrode T32 of the third transistor, the control electrode T42 of the fourth transistor, the control electrode T52 of the fifth transistor, the control electrode T62 of the sixth transistor, the control electrode T72 of the seventh transistor, and the control electrode T92 of the ninth transistor are symmetrically arranged with respect to the virtual straight line extending along the second direction D2.

[0282] In an exemplary embodiment, for the pixel driving circuit of the j-th row sub-pixel, the shape of the first electrode C1(j) can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first electrode C1(j) on the substrate at least partially overlaps with the orthographic projection of the active pattern of the third transistor on the substrate. In an exemplary embodiment, the first electrode C1(j) can simultaneously serve as one electrode of a capacitor and the gate electrode T32(j) of the third transistor.

[0283] In an exemplary embodiment, the orthographic projection of the first plate of the capacitor onto the substrate at least partially overlaps with the orthographic projection of the light-shielding portion onto the substrate.

[0284] In an exemplary embodiment, the shape of the first scan signal line Gate1 can be a line shape extending along the first direction D1 of the main body portion. The first scan signal line Gate1(j) connected to the pixel driving circuit of the j-th row sub-pixel can be located on the side of the capacitor C1(j) in the pixel driving circuit of the j-th row sub-pixel (which is also the gate electrode T32(j) of the third transistor) close to the (j-1)-th row sub-pixel. The area where the first scan signal line Gate1(j) connected to the pixel driving circuit of the j-th row sub-pixel overlaps with the active pattern of the second transistor in the pixel driving circuit of the j-th row sub-pixel can serve as the gate electrode T22(j) of the second transistor, and the area where the first scan signal line Gate1(j) connected to the pixel driving circuit of the j-th row sub-pixel overlaps with the active pattern of the fourth transistor in the pixel driving circuit of the j-th row sub-pixel can serve as the gate electrode T42(j) of the fourth transistor.

[0285] In an exemplary embodiment, the shape of the first light-emitting signal line EM1 can be a line shape in which the main body extends along the first direction D1. The first light-emitting signal line EM1(j) connected to the pixel driving circuit of the j-th row sub-pixel (which is also the second light-emitting signal line EM2(j-1) connected to the pixel driving circuit of the (j-1)-th row sub-pixel) can be located on the side of the first scan signal line Gate1(j) connected to the pixel driving circuit of the j-th row sub-pixel away from the first plate C1(j) of the capacitor in the pixel driving circuit of the j-th row sub-pixel (which is also the gate electrode T32(j) of the third transistor). The area where the first light-emitting signal line EM1(j) (which is also the second light-emitting signal line EM2(j-1)) connected to the pixel driving circuit of the j-th sub-pixel overlaps with the active pattern of the fifth transistor in the pixel driving circuit of the j-th sub-pixel is used as the gate electrode T52(j) of the fifth transistor in the pixel driving circuit of the j-th sub-pixel. The area where the first light-emitting signal line EM1(j) (which is also the second light-emitting signal line EM2(j-1)) connected to the pixel driving circuit of the j-th sub-pixel overlaps with the active pattern of the sixth transistor in the pixel driving circuit of the (j-1)-th sub-pixel is used as the gate electrode T62(j-1) of the sixth transistor in the pixel driving circuit of the (j-1)-th sub-pixel.

[0286] In an exemplary embodiment, the shape of the second light-emitting signal line EM2 can be a line shape in which the main body extends along the first direction D1. The second light-emitting signal line EM2(j) connected to the pixel driving circuit of the j-th row sub-pixel (which is also the first light-emitting signal line EM1(j) connected to the pixel driving circuit of the (j+1)-th row sub-pixel) can be located on the side away from the first plate C1(j) of the capacitor in the pixel driving circuit of the j-th row sub-pixel (which is also the gate electrode T32(j) of the third transistor) away from the first scan signal line Gate1(j) connected to the pixel driving circuit of the j-th row sub-pixel. The area where the second light-emitting signal line EM2(j) (which is also the first light-emitting signal line EM1(j)) connected to the pixel driving circuit of the j-th sub-pixel overlaps with the active pattern of the fifth transistor of the pixel driving circuit of the j+1-th sub-pixel is used as the gate electrode T52(j+1) of the fifth transistor in the pixel driving circuit of the j+1-th sub-pixel. The area where the second light-emitting signal line EM2(j) (which is also the first light-emitting signal line EM1(j)) connected to the pixel driving circuit of the j-th sub-pixel overlaps with the active pattern of the sixth transistor of the pixel driving circuit of the j-th sub-pixel is used as the gate electrode T62(j) of the sixth transistor in the pixel driving circuit of the j-th sub-pixel.

[0287] In an exemplary embodiment, the shape of the first reset signal line Reset1 can be a line shape in which the main body extends along the first direction D1.

[0288] In an exemplary embodiment, the first first reset signal line Reset1(j) (which is also the second first reset signal line Reset1(j-1) connected to the pixel driving circuit of the j-th row sub-pixel) is located between the first light emission signal line EM1(j) (which is also the second light emission signal line EM2(j-1) connected to the pixel driving circuit of the j-th row sub-pixel) and the first scan signal line Gate1(j) connected to the pixel driving circuit of the j-th row sub-pixel. The area where the first first reset signal line Reset1(j) (which is also the second first reset signal line Reset1(j-1) connected to the pixel driving circuit of the j-th row sub-pixel) overlaps with the active pattern of the first transistor of the pixel driving circuit of the j-th row sub-pixel is considered as the image of the j-th row sub-pixel. The area where the gate electrode T12(j) of the first transistor in the pixel driving circuit overlaps with the active pattern of the ninth transistor in the pixel driving circuit of the j-th row sub-pixel (which is also the second first reset signal line Reset1(j-1) connected to the pixel driving circuit of the (j-1)-th row sub-pixel) is used as the gate electrode T92(j) of the ninth transistor in the pixel driving circuit of the j-th row sub-pixel. The area where the first first reset signal line Reset1(j) connected to the pixel driving circuit of the j-th row sub-pixel (which is also the second first reset signal line Reset1(j-1) connected to the pixel driving circuit of the (j-1)-th row sub-pixel) overlaps with the active pattern of the seventh transistor in the pixel driving circuit of the (j-1)-th row sub-pixel is used as the gate electrode T72(j-1) of the seventh transistor in the pixel driving circuit of the (j-1)-th row sub-pixel.

[0289] In an exemplary embodiment, the second first reset signal line Reset1(j) (which is also the first first reset signal line Reset1(j+1)) connected to the pixel driving circuit of the j-th row sub-pixel is located on the side away from the first plate C1(j) (which is also the gate electrode T32(j)) of the capacitor in the pixel driving circuit of the j-th row sub-pixel, where the second light emission signal line EM2(j) (which is also the first light emission signal line EM1(j+1)) connected to the pixel driving circuit of the j-th row sub-pixel is located. The area where the second first reset signal line Reset1(j) (which is also the first first reset signal line Reset1(j+1)) connected to the pixel driving circuit of the j-th row sub-pixel overlaps with the active pattern of the first transistor in the pixel driving circuit of the (j+1)-th row sub-pixel serves as the gate electrode T12(j+1) of the first transistor in the pixel driving circuit of the (j+1)-th row sub-pixel. The region where the active pattern of the ninth transistor of the pixel driving circuit of the (j+1)th row sub-pixel overlaps with that of the (j+1)th row sub-pixel is taken as the gate electrode T92(j+1) of the ninth transistor in the pixel driving circuit of the (j+1)th row sub-pixel. The region where the second first reset signal line Reset1(j) (which is also the first first reset signal line Reset1(j+1)) connected to the pixel driving circuit of the jth row sub-pixel overlaps with the active pattern of the seventh transistor of the pixel driving circuit of the jth row sub-pixel is taken as the gate electrode T72(j) of the seventh transistor in the pixel driving circuit of the jth row sub-pixel.

[0290] In an exemplary embodiment, the first scan signal line Gate1, the first reset signal line Reset1, the first light emission signal line EM1, and the second light emission signal line EM2 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0291] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel regions of the first transistor to the seventh transistor and the ninth transistor. The first semiconductor layer in the area not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first transistor to the seventh transistor and the ninth transistor are both conducted. The second region T11_2 of the active pattern T11 of the first transistor after conductor conversion (which is also the first region T21-1 of the active pattern T21 of the second transistor) is multiplexed as the second terminal T14 (also the first terminal T13 of the second transistor). The first region T31_1 of the active pattern T31 of the third transistor (which is also the second region T41_2 of the active pattern T41 of the fourth transistor) is multiplexed as the first terminal T33 of the third transistor (also the second terminal T44 of the fourth transistor). The second region T31_2 of the active pattern T31 of the third transistor (which is also the second region T21-2 of the active pattern T21 of the second transistor and the first region T61_1 of the active pattern T61 of the sixth transistor) is multiplexed as the second terminal T34 of the third transistor (also the second terminal T24 of the second transistor and the first terminal T63 of the sixth transistor).

[0292] In an exemplary embodiment, the gate electrode of the first transistor is disposed across the active pattern of the first transistor, the gate electrode of the second transistor is disposed across the active pattern of the second transistor, the gate electrode of the third transistor is disposed across the active pattern of the third transistor, the gate electrode of the fourth transistor is disposed across the active pattern of the fourth transistor, the gate electrode of the fifth transistor is disposed across the active pattern of the fifth transistor, the gate electrode of the sixth transistor is disposed across the active pattern of the sixth transistor, the gate electrode of the seventh transistor is disposed across the active pattern of the seventh transistor, and the gate electrode of the ninth transistor is disposed across the active pattern of the ninth transistor. That is, the extending direction of the gate electrode of at least one transistor is perpendicular to the extending direction of the active pattern.

[0293] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the third insulating film and the second conductive film using a patterning process to form a third insulating layer pattern and a second conductive layer pattern located on the second insulating layer, as shown in Figures 24 and 25. Figure 24 is a schematic diagram of the second conductive layer pattern in Figure 16, and Figure 25 is a schematic diagram of Figure 16 after the second conductive layer pattern has been formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0294] In an exemplary embodiment, as shown in Figures 24 and 25, the second conductive layer pattern may include: a first sub-signal line Gate3A of the third scan signal line, a second initial signal line INIT2, and a second plate C2 of a capacitor located in the pixel driving circuit of at least one sub-pixel, and a first control electrode T82A of the eighth transistor. Gate3A(j) refers to the first sub-signal line of the third scan signal line connected to the pixel driving circuit of the j-th row sub-pixel, and INIT2(j) refers to the second initial signal line connected to the pixel driving circuit of the j-th row sub-pixel. C2(j) refers to the second plate of the capacitor in the pixel driving circuit of the j-th row sub-pixel, and T82A(j) refers to the first control electrode of the eighth transistor in the pixel driving circuit of the j-th row sub-pixel.

[0295] In an exemplary embodiment, the second plate C2 of the capacitor of the pixel driving circuit of adjacent sub-pixels located in the same row and the first control electrode T82A of the eighth transistor are symmetrically arranged with respect to a virtual straight line extending along the second direction D2.

[0296] In an exemplary embodiment, the second plate C2 of the capacitor of the pixel driving circuit of adjacent sub-pixels located in the same row is electrically connected.

[0297] In an exemplary embodiment, the main outline of the second electrode C2 of the capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate. The second electrode can serve as the other electrode of the capacitor, and the first and second electrodes constitute the capacitor of the pixel driving circuit. The second electrode of the capacitor is provided with an opening V0, which can be rectangular in shape and located in the middle of the second electrode, forming a ring structure. The opening V0 exposes the third insulating layer covering the first electrode, and the orthographic projection of the first electrode on the substrate includes the orthographic projection of the opening on the substrate. In an exemplary embodiment, the opening exposes the first electrode, allowing the first electrode of the subsequently formed eighth transistor to be connected to the first electrode.

[0298] In an exemplary embodiment, the shape of the first sub-signal line Gate3A of the third scan signal line can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the first sub-signal line Gate3A(j) of the third scan signal line connected to the pixel driving circuit of the j-th row sub-pixel on the substrate is located between the orthographic projection of the first scan signal line connected to the pixel driving circuit of the j-th row sub-pixel on the substrate and the orthographic projection of the first first reset signal line (which is also the second first reset signal line connected to the pixel driving circuit of the (j-1)-th row sub-pixel) connected to the pixel driving circuit of the j-th row sub-pixel on the substrate. The region where the first sub-signal line Gate3A(j) of the third scan signal line connected to the pixel driving circuit of the j-th row sub-pixel overlaps with the active pattern of the eighth transistor in the pixel driving circuit of the j-th row sub-pixel formed subsequently serves as the first control electrode of the eighth transistor in the pixel driving circuit of the j-th row sub-pixel.

[0299] In an exemplary embodiment, the shape of the second initial signal line INIT2 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the second initial signal line INIT2(j) connected to the pixel driving circuit of the j-th row sub-pixel on the substrate is located on the side away from the orthographic projection of the second first reset signal line (also the first second reset signal line connected to the pixel driving circuit of the (j+1)-th row sub-pixel) connected to the pixel driving circuit of the j-th row sub-pixel on the substrate.

[0300] In an exemplary embodiment, the first sub-signal lines of the second initial signal line and the third scan signal line can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines. This disclosure does not limit the scope of the invention.

[0301] (5) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: on the substrate on which the aforementioned pattern is formed, including: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate, and patterning the fourth insulating film and the second semiconductor film by a patterning process to form a fourth insulating layer pattern and a second semiconductor layer pattern located on a third insulating layer, as shown in Figures 26 and 27. Figure 26 is a schematic diagram of the second semiconductor layer pattern in Figure 16, and Figure 27 is a schematic diagram of the second semiconductor layer pattern after it is formed in Figure 16.

[0302] In an exemplary embodiment, as shown in Figures 26 and 27, the second semiconductor layer may include an active pattern T81 of the eighth transistor in the pixel driving circuit of at least one sub-pixel. T81(j) refers to the active pattern of the eighth transistor in the pixel driving circuit of the j-th row sub-pixel.

[0303] In an exemplary embodiment, as shown in Figures 26 and 27, the active pattern T81 of the eighth transistor includes a first active portion A1 and a second active portion A2. The first active portion A1 is a line shape extending along the second direction D2, and the second active portion A2 is a line shape extending along the first direction D1. The first active portion A1 and the second active portion A2 are arranged at right angles.

[0304] In an exemplary embodiment, the orthographic projection of the first active portion of the active pattern T81(j) of the eighth transistor in the pixel driving circuit of the j-th sub-pixel on the substrate at least partially overlaps with the orthographic projection of the first sub-signal line of the third scan signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate, and the orthographic projection of the second active portion of the active pattern T81(j) of the eighth transistor in the pixel driving circuit of the j-th sub-pixel on the substrate at least partially overlaps with the orthographic projection of the first scan signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate.

[0305] In an exemplary embodiment, the active pattern T11 of the eighth transistor is disposed across the first control electrode of the eighth transistor.

[0306] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the fifth insulating film and the third conductive film using a patterning process to form a fifth insulating layer pattern and a third conductive layer pattern located on the fifth insulating layer, as shown in Figures 28 and 29. Figure 28 is a schematic diagram of the third conductive layer pattern in Figure 16, and Figure 29 is a schematic diagram of Figure 16 after the third conductive layer pattern has been formed. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0307] In an exemplary embodiment, as shown in Figures 28 and 29, the third conductive layer pattern may include: a second sub-signal line Gate3B of the third scan signal line, a first initial signal line INIT1, a reference signal line REF, and a first control electrode T82B of the eighth transistor located in the pixel driving circuit of at least one sub-pixel. Gate3B(j) refers to the second sub-signal line of the third scan signal line connected to the pixel driving circuit of the j-th row sub-pixel, INIT1(j) refers to the first initial signal line connected to the pixel driving circuit of the j-th row sub-pixel, REF(j) refers to the reference signal line connected to the pixel driving circuit of the j-th row sub-pixel, and T82B(j) refers to the second control electrode of the eighth transistor in the pixel driving circuit of the j-th row sub-pixel.

[0308] In an exemplary embodiment, the second control electrode T82B of the eighth transistor of the pixel driving circuit of adjacent sub-pixels located in the same row is symmetrically arranged with respect to the virtual straight line extending along the second direction D2.

[0309] In an exemplary embodiment, the shape of the second sub-signal line Gate3B of the third scan signal line can be a line shape in which the main body extends along the first direction D1. The orthogonal projection of the second sub-signal line Gate3B(j) of the third scan signal line connected to the pixel driving circuit of the j-th row sub-pixel on the substrate at least partially overlaps with the first sub-signal line of the third scan signal line connected to the pixel driving circuit of the j-th row sub-pixel. The region where the second sub-signal line Gate3B(j) of the third scan signal line connected to the pixel driving circuit of the j-th row sub-pixel overlaps with the active pattern of the eighth transistor in the pixel driving circuit of the j-th row sub-pixel serves as the second control electrode of the eighth transistor in the pixel driving circuit of the j-th row sub-pixel.

[0310] In an exemplary embodiment, the shape of the first initial signal line INIT1 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the second initial signal line INIT2(j) connected to the pixel driving circuit of the j-th row sub-pixel on the substrate at least partially overlaps with the orthographic projection of the first light-emitting signal line (which is also the second light-emitting signal line connected to the pixel driving circuit of the (j-1)-th row sub-pixel) connected to the pixel driving circuit of the j-th row sub-pixel on the substrate.

[0311] In an exemplary embodiment, the reference signal line REF can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the reference signal line REF(j) connected to the pixel driving circuit of the j-th row sub-pixel on the substrate at least partially overlaps with the orthographic projection of the first first reset signal line (which is also the second first reset signal line connected to the pixel driving circuit of the (j-1)-th row sub-pixel) connected to the pixel driving circuit of the j-th row sub-pixel on the substrate.

[0312] In an exemplary embodiment, the second sub-signal lines of the first initial signal line, the reference signal line, and the third scan signal line can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0313] (7) Forming a sixth insulating layer pattern includes: depositing a sixth insulating film on a substrate on which the aforementioned pattern has been formed, and patterning the sixth insulating film by a patterning process to form a sixth insulating layer pattern covering the aforementioned pattern. The sixth insulating layer has multiple via patterns, as shown in Figure 30. Figure 30 is a schematic diagram of the formation of the sixth insulating layer pattern in Figure 16.

[0314] In an exemplary embodiment, as shown in FIG30, the plurality of vias in the sixth insulating layer include at least: a first via V1 to a sixteenth via V16 located in the pixel driving circuit of at least one sub-pixel.

[0315] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the orthographic projection range of the first region of the active pattern of the first transistor onto the substrate. The fifth, fourth, third, second, and first insulating layers within the first via V1 are etched away, exposing the surface of the first region of the active layer of the first transistor. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active layer of the first transistor through the via.

[0316] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the orthographic projection range of the first region of the active pattern of the first transistor onto the substrate. The fifth, fourth, third, second, and first insulating layers within the first via V1 are etched away, exposing the surface of the first region of the active layer of the first transistor. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active layer of the first transistor through the via.

[0317] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the second region of the active pattern of the first transistor (which is also the first region of the active pattern of the second transistor) onto the substrate. The fifth, fourth, third, second, and first insulating layers within the second via V2 are etched away, exposing the surface of the second region of the active pattern of the first transistor (which is also the first region of the active pattern of the second transistor). The second via V2 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor and the second electrode of the eighth transistor) to be connected to the second region of the active pattern of the first transistor (which is also the first region of the active pattern of the second transistor) through the via.

[0318] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the orthographic projection of the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor) onto the substrate. The fifth, fourth, third, second, and first insulating layers within the third via V3 are etched away, exposing the surface of the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor). The third via V3 is configured to allow the second electrode of the subsequently formed fifth transistor (which is also the second electrode of the ninth transistor) to be connected to the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor) through the via.

[0319] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the orthographic projection range of the first region of the active pattern of the fourth transistor onto the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the fourth via V4 are etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The fourth via V4 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the first region of the active pattern of the fourth transistor through the via.

[0320] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is located within the orthographic projection of the first region of the active pattern of the fifth transistor onto the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the active pattern of the fifth transistor. The fifth via V5 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the first region of the active pattern of the fifth transistor through the via.

[0321] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate lies within the orthographic projection of the second region of the active pattern of the fifth transistor (which is also the second region of the active pattern of the ninth transistor) onto the substrate. The fifth, fourth, third, second, and first insulating layers within the sixth via V6 are etched away, exposing the surface of the second region of the active pattern of the fifth transistor (which is also the second region of the active pattern of the ninth transistor). The sixth via V6 is configured to allow the second electrode of the subsequently formed fifth transistor (which is also the second electrode of the ninth transistor) to be connected to the second region of the active pattern of the fifth transistor (which is also the second region of the active pattern of the ninth transistor) through the via.

[0322] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) onto the substrate. The fifth, fourth, third, second, and first insulating layers within the seventh via V7 are etched away, exposing the surface of the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor). The seventh via V7 is configured to allow the second electrode of the subsequently formed sixth transistor (which is also the second electrode of the seventh transistor) to be connected to the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) through the via.

[0323] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the orthographic projection of the first region of the active pattern of the seventh transistor onto the substrate. The fifth, fourth, third, second, and first insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the active pattern of the seventh transistor. The eighth via V8 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the first region of the active pattern of the seventh transistor through the via.

[0324] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the orthographic projection of the first region of the active pattern of the ninth transistor onto the substrate. The fifth, fourth, third, second, and first insulating layers within the ninth via V9 are etched away, exposing the surface of the first region of the active pattern of the ninth transistor. The ninth via V9 is configured to allow the first electrode of the subsequently formed ninth transistor to be connected to the first region of the active pattern of the ninth transistor through the via.

[0325] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the first plate of the capacitor onto the substrate. The fifth, fourth, third, and second insulating layers within the tenth via V10 are etched away, exposing the surface of the first plate of the capacitor. The tenth via V10 is configured to allow the first electrode of the subsequently formed eighth transistor to be connected to the first plate of the capacitor through the via.

[0326] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is located within the range of the orthographic projection of the second plate of the capacitor onto the substrate. The fifth, fourth, and third insulating layers within the eleventh via V11 are etched away, exposing the surface of the second plate of the capacitor. The eleventh via V11 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the second plate of the capacitor through the via.

[0327] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is within the range of the orthographic projection of the second initial signal line onto the substrate. The fifth and fourth insulating layers within the twelfth via V12 are etched away, exposing the surface of the second initial signal line. The twelfth via V12 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the second initial signal line through the via.

[0328] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is within the orthographic projection of the first region of the active pattern of the eighth transistor onto the substrate. The fifth insulating layer within the thirteenth via V13 is etched away, exposing the surface of the first region of the active pattern of the eighth transistor. The thirteenth via V13 is configured to allow the first electrode of the subsequently formed eighth transistor to be connected to the first region of the active pattern of the eighth transistor through the via.

[0329] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate is within the orthographic projection of the second region of the active pattern of the eighth transistor onto the substrate. The fifth insulating layer within the fourteenth via V14 is etched away, exposing the surface of the second region of the active pattern of the eighth transistor. The fourteenth via V14 is configured to allow the second terminal of the subsequently formed first transistor (which is also the first terminal of the second transistor and the second terminal of the eighth transistor) to be connected to the second region of the active pattern of the eighth transistor through the via.

[0330] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is within the range of the orthographic projection of the first initial signal line on the substrate, exposing the surface of the first initial signal line. The fifteenth via V15 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first initial signal line through the via.

[0331] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is within the range of the orthographic projection of the reference signal line on the substrate, exposing the surface of the reference signal line. The sixteenth via V16 is configured to allow the first electrode of the subsequently formed ninth transistor to be connected to the reference signal line through the via.

[0332] In an exemplary embodiment, at least one pixel driving circuit shares the same via as the eighth via in one of the adjacent pixel driving circuits located in the same row.

[0333] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film by a patterning process to form a fourth conductive layer pattern, as shown in Figures 31 and 32. Figure 31 is a schematic diagram of the fourth conductive layer pattern in Figure 16, and Figure 32 is a schematic diagram of the fourth conductive layer pattern after it is formed in Figure 16.

[0334] In an exemplary embodiment, as shown in Figures 31 and 32, the fourth conductive layer pattern may include: an initial connection line INL located at the first pole T13 and the second pole T14 of a first transistor, the first pole T23 of a second transistor, the first pole T43 of a fourth transistor, the first pole T53 of a fifth transistor, the second pole T64 of a sixth transistor, the first pole T73 and the second pole T74 of a seventh transistor, the first pole T83 and the second pole T84 of an eighth transistor, and the first pole T93 and the second pole T94 of a ninth transistor.

[0335] In an exemplary embodiment, the first electrode T13 of the first transistor is separately disposed and is block-shaped, extending at least partially along the second direction D2. The first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor through a first via and is electrically connected to the first initial signal line through a fifteenth via.

[0336] In an exemplary embodiment, the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, and the second electrode T84 of the eighth transistor are integral structures, and their shapes are lines extending along the first direction D1. The second electrode T14 of the first transistor (which is also the first electrode T23 of the second transistor and the second electrode T84 of the eighth transistor) is connected to the second region of the active pattern of the first transistor (which is also the first region of the active pattern of the second transistor) through a second via, and is connected to the second region of the active pattern of the eighth transistor through a fourteenth via.

[0337] In an exemplary embodiment, the first electrode T43 of the fourth transistor is separately disposed and is shaped as a line extending along the second direction D2. The first electrode T43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor through a fourth via V4.

[0338] In an exemplary embodiment, the first electrode T53 of the fifth transistor is separately provided and is shaped as a broken line extending at least partially along the first direction D1. The first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through a fifth via and is electrically connected to the second plate of the capacitor through an eleventh via.

[0339] In an exemplary embodiment, the second electrode T54 of the fifth transistor and the second electrode T94 of the ninth transistor are integrally formed and are shaped as a line extending along the second direction D2. The second electrode T54 of the fifth transistor (which is also the second electrode T94 of the ninth transistor) is connected to the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor) through a third via, and is connected to the second region of the active pattern of the fifth transistor (which is also the second region of the active pattern of the ninth transistor) through a sixth via.

[0340] In an exemplary embodiment, the orthographic projection of the integral structure of the second pole T54(j) of the fifth transistor and the second pole T94(j) of the ninth transistor in the pixel driving circuit of the j-th column sub-pixel on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the reference signal line connected to the pixel driving circuit of the j-th row sub-pixel, the second initial signal line connected to the (j-1)-th row sub-pixel, the third scan signal line connected to the pixel driving circuit of the j-th row sub-pixel, and the first scan signal line connected to the pixel driving circuit of the j-th row sub-pixel.

[0341] In an exemplary embodiment, the second electrode T64 of the sixth transistor (which is also the second electrode T74 of the seventh transistor) is shaped as a line extending along the second direction D2, and the second electrode T64 of the sixth transistor (which is also the second electrode T74 of the seventh transistor) is connected to the second region of the active layer of the sixth transistor (which is also the second region of the active layer of the sixth transistor) through a seventh via.

[0342] In an exemplary embodiment, the initial connection line INL can be a line shape in which the main body extends along the second direction D2. The initial connection line INL can be located between at least two adjacent sub-pixels. The initial connection line INL and the first electrode T73 of the seventh transistor of the pixel driving circuit of at least one sub-pixel are integrally structured. The first electrode T73 of the seventh transistor extends at least partially along the first direction D1, is connected to the first region of the active pattern of the seventh transistor through an eighth via, and is connected to the second initial signal line through a twelfth via.

[0343] In an exemplary embodiment, the first electrode T83 of the eighth transistor is separately provided and is shaped as a broken line extending at least partially along the second direction D2. The first electrode T83 of the eighth transistor is connected to the first plate of the capacitor through the tenth via and is electrically connected to the first region of the active pattern of the eighth transistor through the thirteenth via.

[0344] In an exemplary embodiment, the first electrode T93 of the ninth transistor is separately provided and is shaped as a broken line extending at least partially along the first direction D1. The first electrode T93 of the ninth transistor is connected to the first region of the active pattern of the ninth transistor through the ninth via and is electrically connected to the reference signal line through the sixteenth via.

[0345] (9) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: depositing a seventh insulating film on a substrate on which the aforementioned pattern is formed, patterning the seventh insulating film using a patterning process to form a seventh insulating layer, coating the first planarization film on the seventh insulating layer, and patterning the first planarization film using a patterning process to form a first planarization layer pattern covering the aforementioned pattern. The first planarization layer has a plurality of via patterns, as shown in FIG33, which is a schematic diagram of FIG16 after the formation of the first planarization layer pattern.

[0346] In an exemplary embodiment, as shown in FIG33, the plurality of via patterns on the first planarization layer include seventeenth via V17 to nineteenth via V19.

[0347] In an exemplary embodiment, as shown in FIG33, the orthogonal projection of the seventeenth via V17 on the substrate is within the range of the orthogonal projection of the first electrode of the fourth transistor on the substrate. The seventh insulating layer in the seventeenth via V17 is etched away, exposing the surface of the first electrode of the fourth transistor. The seventeenth via V17 is configured to allow subsequently formed data signal lines to be connected to the first electrode of the fourth transistor through the via.

[0348] In an exemplary embodiment, as shown in FIG33, the orthographic projection of the eighteenth via V18 on the substrate is within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate. The seventh insulating layer in the eighteenth via V18 is etched away, exposing the surface of the first electrode of the fifth transistor. The eighteenth via V18 is configured to allow the subsequently formed first power line to be connected to the first electrode of the fifth transistor through the via.

[0349] In an exemplary embodiment, as shown in FIG33, the orthogonal projection of the nineteenth via V19 on the substrate is located within the range of the orthogonal projection of the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) on the substrate. The seventh insulating layer in the nineteenth via V19 is etched away, exposing the surface of the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor). The nineteenth via V19 is configured to allow the subsequently formed anode connection electrode to be connected to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) through the via.

[0350] (10) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film by a patterning process to form a fifth conductive layer pattern, as shown in Figures 34 and 35. Figure 34 is a schematic diagram of the fifth conductive layer pattern in Figure 16, and Figure 35 is a schematic diagram of the fifth conductive layer pattern after it is formed in Figure 16.

[0351] In an exemplary embodiment, as shown in Figures 34 and 35, the fifth conductive layer pattern may include at least: a data signal line Data, a first power supply line VDD, and an anode connection electrode AL.

[0352] In an exemplary embodiment, the pixel driving circuit is interconnected with the first signal line VDD connected to one of the adjacent pixel driving circuits in the same row, and a plurality of annular regions R are provided between the two adjacent first signal lines VDD, and at least one anode connection electrode AL is located in at least one annular region.

[0353] In an exemplary embodiment, the data signal line Data is shaped like a line whose main body extends at least partially along the second direction D2, and is electrically connected to the first electrode of the fourth transistor through the seventeenth via.

[0354] In an exemplary embodiment, the data signal line VDD is shaped like a line whose main body extends at least partially along the second direction D2, and is electrically connected to the first electrode of the fifth transistor through the eighteenth via.

[0355] In an exemplary embodiment, the anode connection electrode AL is a strip shape that extends at least partially along the second direction D2, and is electrically connected to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) through the nineteenth via.

[0356] (11) Forming a light-emitting structure layer. In an exemplary embodiment, forming a light-emitting structure layer includes: coating a second planarization film on a substrate on which the aforementioned pattern is formed; patterning the second planarization film to form a second planarization layer pattern; depositing an anode film on the substrate on which the aforementioned pattern is formed; patterning the anode film using a patterning process to form an anode layer pattern; depositing a pixel definition film on the substrate on which the aforementioned pattern is formed; patterning the pixel definition film using a patterning process to form a pixel definition layer pattern exposing the anode layer pattern; coating an organic light-emitting material on the substrate on which the pixel definition layer pattern is formed; patterning the organic light-emitting material using a patterning process to form an organic structure layer pattern; and depositing a cathode film on the substrate on which the organic material layer pattern is formed; patterning the cathode film using a patterning process to form a cathode layer.

[0357] In an exemplary embodiment, the organic structure layer may include: an organic light-emitting layer of a light-emitting element.

[0358] In an exemplary embodiment, the cathode layer may include the cathodes of a plurality of light-emitting elements.

[0359] In an exemplary embodiment, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0360] In one exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0361] In an exemplary embodiment, at least one of the first to fifth conductive layers may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the first conductive layer may include molybdenum.

[0362] In an exemplary embodiment, the anode layer may be made of a transparent conductive material, such as any one or more of indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO).

[0363] In an exemplary embodiment, the cathode layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or the aforementioned conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0364] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0365] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of organic materials.

[0366] The display substrate described in this embodiment can be used in display products of any resolution.

[0367] This disclosure also provides a method for driving a pixel driving circuit. The method for driving a pixel driving circuit may include the following steps:

[0368] Under the control of at least one reset signal line, the reset sub-circuit provides a reference signal line signal to the second node, a first initial signal line signal to the fourth node, and a second initial signal line signal to the fifth node.

[0369] Under the control of at least two scan signal lines and the first power supply line, the drive control sub-circuit provides the data signal line to the second node and the signal of the third or fourth node to the first node;

[0370] The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes;

[0371] Under the control of the signals from the first and second light-emitting signal lines, the light-emitting control sub-circuit provides the first power line signal to the second node and the third node signal to the fifth node.

[0372] The pixel driving circuit is the same as the pixel driving circuit provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0373] This disclosure also provides a display device, including a display substrate.

[0374] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0375] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0376] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0377] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0378] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel driving circuit, disposed in a display device, comprising: Drive control subcircuit, reset subcircuit, drive subcircuit and light emission control subcircuit; The reset sub-circuit is electrically connected to at least one reset signal line, a first initial signal line, a second initial signal line, a reference signal line, a second node, a fourth node, and a fifth node, respectively, and is configured to provide the reference signal line to the second node, the first initial signal line to the fourth node, and the second initial signal line to the fifth node under the control of the signal of at least one reset signal line. The drive control sub-circuit is electrically connected to at least two scan signal lines, a data signal line, a first power line, a first node, a second node, a third node, and a fourth node, respectively, and is configured to provide the data signal line to the second node and the third or fourth node to the first node under the control of the signals of at least two scan signal lines and the first power line. The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node. The light-emitting control sub-circuit is electrically connected to the first light-emitting signal line, the second light-emitting signal line, the first power supply line, the second node, the third node, and the fifth node, respectively. It is configured to provide the first power supply line signal to the second node and the third node signal to the fifth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line. The display device includes: a first control unit, which is electrically connected to a first light-emitting signal line and a second light-emitting signal line respectively, and is configured to provide signals to the first light-emitting signal line and the second light-emitting signal line, wherein the time period during which the first control unit provides an effective level signal to the first light-emitting signal line does not overlap with the time period during which it provides an effective level signal to the second light-emitting signal line.

2. The pixel driving circuit according to claim 1, wherein, The driving sub-circuit includes a third transistor, and the light-emitting control sub-circuit includes a fifth transistor and a sixth transistor; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fifth node.

3. The pixel driving circuit according to claim 2, wherein, The display device includes: a multi-row pixel driving circuit, wherein the second light-emitting signal line connected to the i-th row pixel driving circuit and the first light-emitting signal line connected to the (i+1)-th row pixel driving circuit are the same signal line.

4. The pixel driving circuit according to claim 1, wherein, The start time of the period during which the first control unit provides an effective level signal to the first light-emitting signal line is earlier than the start time of the period during which the first control unit provides an effective level signal to the second light-emitting signal line, and the end time of the period during which the first control unit provides an effective level signal to the first light-emitting signal line is earlier than the end time of the period during which the first control unit provides an effective level signal to the second light-emitting signal line.

5. The pixel driving circuit according to claim 1, wherein, At least one reset signal line includes: a first reset signal line, and the reset sub-circuit includes: a first transistor, a seventh transistor, and a ninth transistor; The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the fourth node. The control electrode of the seventh transistor is electrically connected to the first reset signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fifth node. The control electrode of the ninth transistor is electrically connected to the first reset signal line, the first electrode of the ninth transistor is electrically connected to the reference signal line, and the second electrode of the ninth transistor is electrically connected to the second node. The display device further includes: a second control unit, which is electrically connected to the first reset signal line and configured to provide a signal to the first reset signal line; The time period during which the second control unit provides a valid level signal to the first reset signal line overlaps at least partially with at least one of the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line and to the second light-emitting signal line.

6. The pixel driving circuit according to claim 1, wherein, At least one reset signal line includes: a first reset signal line and a second reset signal line; The reset sub-circuit is configured to provide a signal of the first initial signal line to the fourth node under the control of the signal of the first reset signal line, provide a signal of the second initial signal line to the fifth node under the control of the signal of the second reset signal line, and provide a signal of the reference signal line to the second node. The display device further includes: a second control unit, which is electrically connected to the first reset signal line and the second reset signal line respectively, and is configured to provide signals to the first reset signal line and the second reset signal line; The time period during which the second control unit provides an effective level signal to the first reset signal line does not overlap with the time period during which the second control unit provides an effective level signal to the second reset signal line, and the end time of the time period during which the second control unit provides an effective level signal to the second reset signal line is earlier than the start time of the time period during which the second control unit provides an effective level signal to the first reset signal line. At least one of the time periods during which the second control unit provides a valid level signal to the first reset signal line and the time periods during which the second control unit provides a valid level signal to the second reset signal line overlaps at least partially with at least one of the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line and the time periods during which the first control unit provides an invalid level signal to the second light-emitting signal line.

7. The pixel driving circuit according to claim 6, wherein, The reset sub-circuit includes: a first transistor, a seventh transistor, and a ninth transistor; The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the fourth node. The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fifth node. The control electrode of the ninth transistor is electrically connected to the second reset signal line, the first electrode of the ninth transistor is electrically connected to the reference signal line, and the second electrode of the ninth transistor is electrically connected to the second node.

8. The pixel driving circuit according to claim 1, wherein, At least two scan signal lines include: a first scan signal line and a third scan signal line; The drive control sub-circuit is configured to provide a data signal line signal to the second node and a third node signal to the fourth node under the control of the signal of the first scan signal line, and to provide a fourth node signal to the first node under the control of the signal of the third scan signal line. The display device further includes: a third control unit and a fourth control unit, wherein the third control unit is electrically connected to the first scan signal line and is configured to provide a signal to the first scan signal line, and the fourth control unit is electrically connected to the third scan signal line and is configured to provide a signal to the third scan signal line; The time period during which the third control unit provides an effective level signal to the first scan signal line overlaps at least partially with the time period during which the fourth control unit provides an effective level signal to the third scan signal line. At least one of the time periods during which the third control unit provides an effective level signal to the first scan signal line and the time periods during which the fourth control unit provides an effective level signal to the third scan signal line overlaps at least partially with at least one of the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line and the time periods during which it provides an invalid level signal to the second light-emitting signal line.

9. The pixel driving circuit according to claim 8, wherein, The drive control sub-circuit includes: a capacitor, a second transistor, a fourth transistor, and an eighth transistor. The capacitor includes: a first plate and a second plate. The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node. The control electrode of the eighth transistor is electrically connected to the third scan signal line, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the fourth node. The first plate of the capacitor is electrically connected to the first power line, and the second plate of the capacitor is electrically connected to the first node.

10. The pixel driving circuit according to claim 1, wherein, At least two scan signal lines include: a first scan signal line, a second scan signal line, and a third scan signal line; The drive control sub-circuit is configured to provide a data signal line signal to the second node under the control of the signal of the first scan signal line, provide a signal of the third node to the fourth node under the control of the signal of the second scan signal line, and provide a signal of the fourth node to the first node under the control of the signal of the third scan signal line. The display device further includes: a third control unit, a fourth control unit, and a fifth control unit. The third control unit is electrically connected to the first scan signal line and is configured to provide a signal to the first scan signal line. The fourth control unit is electrically connected to the third scan signal line and is configured to provide a signal to the third scan signal line. The fifth control unit is electrically connected to the second scan signal line and is configured to provide a signal to the second scan signal line. The time period during which the fifth control unit provides an effective level signal to the second scan signal line includes: a first time period and a second time period, wherein the end time of the first time period is earlier than the start time of the second time period; The time period during which the third control unit provides an effective level signal to the first scan signal line overlaps at least partially with the second time period, but does not overlap with the first time period; At least one of the first time period and the second time period overlaps at least partially with the time period during which the fourth control unit provides an effective level signal to the third scan signal line; The time period during which the fourth control unit provides an effective level signal to the third scan signal line at least partially overlaps with at least one of the time periods during which the first control unit provides an invalid level signal to the first light-emitting signal line and to the second light-emitting signal line.

11. The pixel driving circuit according to claim 10, wherein, The drive control sub-circuit includes: a capacitor, a second transistor, a fourth transistor, and an eighth transistor. The capacitor includes: a first plate and a second plate. The control electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node. The control electrode of the eighth transistor is electrically connected to the third scan signal line, and the first electrode of the eighth transistor is electrically connected to the first node. Then, the second terminal of the eighth transistor is electrically connected to the fourth node.

12. A display device, comprising: A plurality of sub-pixels, at least one sub-pixel comprising: a pixel driving circuit as described in any one of claims 1 to 11.

13. The display device according to claim 12, further comprising: Multiple first light-emitting signal lines and multiple second light-emitting signal lines, wherein at least one of the first light-emitting signal lines and the second light-emitting signal lines extends at least partially along a first direction; The first light-emitting signal line connected to the pixel driving circuit of the j-th row sub-pixel and the second light-emitting signal line connected to the pixel driving circuit of the (j-1)-th row sub-pixel are the same signal line, 1≤j≤N, where N is the total number of rows of sub-pixels.

14. The display device according to claim 13, further comprising: Multiple first reset signal lines, each first reset signal line extending at least partially along a first direction; The pixel driving circuit of the j-th row sub-pixel includes two first reset signal lines. The first first reset signal line connected to the pixel driving circuit of the j-th row sub-pixel is the same signal line as the second first reset signal line connected to the pixel driving circuit of the (j-1)-th row sub-pixel. The second first reset signal line connected to the pixel driving circuit of the j-th row sub-pixel is the same signal line as the first first reset signal line connected to the pixel driving circuit of the (j+1)-th row sub-pixel.

15. The display device according to claim 14, further comprising: Multiple first scan signal lines, multiple third scan signal lines, multiple first initial signal lines, multiple second initial signal lines, and multiple reference signal lines; At least one of the first scan signal line, the third scan signal line, the first initial signal line, the second initial signal line, and the reference signal line extends at least partially along the first direction; The first light-emitting signal line connected to the pixel driving circuit of the j-th sub-pixel, the first first reset signal line connected to the pixel driving circuit of the j-th sub-pixel, the first scan signal line connected to the pixel driving circuit of the j-th sub-pixel, the second light-emitting signal line connected to the pixel driving circuit of the j-th sub-pixel, and the second first reset signal line connected to the pixel driving circuit of the j-th sub-pixel are arranged sequentially along the second direction, and the first direction intersects the second direction; The orthographic projection of the reference signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate at least partially overlaps with the first reset signal line connected to the pixel driving circuit of the j-th sub-pixel. The orthographic projection of the second initial signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate at least partially overlaps with the orthographic projection of the first light emission signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate. The orthographic projection of the third scan signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate is located between the orthographic projection of the first scan signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate and the orthographic projection of the first reset signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate. The orthographic projection of the second initial signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate is located on the side of the orthographic projection of the second reset signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate that is away from the orthographic projection of the second light emission signal line connected to the pixel driving circuit of the j-th sub-pixel on the substrate.

16. The display device according to claim 15, wherein, At least one pixel driving circuit includes: a first transistor to a ninth transistor, and at least one transistor includes: an active pattern; The active patterns of the first transistor, the second transistor, the third transistor, the fourth transistor, the sixth transistor, and the seventh transistor located in the same sub-pixel are integrated into one structure, and the active patterns of the fifth transistor and the ninth transistor located in the same sub-pixel are integrated into one structure. The active pattern of the fifth transistor in the pixel driving circuit of the j-th row sub-pixel and the active pattern of the sixth transistor in the pixel driving circuit of the (j-1)-th row sub-pixel are arranged along the first direction. The active patterns of the nine transistors, the active patterns of the first transistor in the pixel driving circuit of the j-th row of sub-pixels, and the active patterns of the seventh transistor in the pixel driving circuit of the (j-1)-th row of sub-pixels are arranged along the first direction.

17. The display device according to claim 16, wherein, At least one transistor further includes: a first electrode and a second electrode, the active pattern includes a first region and a second region, the second electrode of the fifth transistor and the second electrode of the ninth transistor are integrally structured and extend along a second direction; The first region of the active pattern of the third transistor is the same as the second region of the active pattern of the fourth transistor, and the second region of the active pattern of the fifth transistor is the same as the second region of the active pattern of the ninth transistor. The second terminal of the fifth transistor is connected to the first region of the active pattern of the third transistor and the second region of the active pattern of the fifth transistor, respectively. The orthographic projection of the second electrode of the fifth transistor in the pixel driving circuit of the j-th column sub-pixel on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the reference signal line connected to the pixel driving circuit of the j-th row sub-pixel, the second initial signal line connected to the (j-1)-th row sub-pixel, the third scan signal line connected to the pixel driving circuit of the j-th row sub-pixel, and the first scan signal line connected to the pixel driving circuit of the j-th row sub-pixel.

18. The display device according to claim 15, further comprising: Multiple initial connection lines, multiple first power lines, and multiple data signal lines, wherein at least one of the first power lines, data signal lines, and initial connection lines extends at least partially along a second direction, and the first direction intersects the second direction; At least one initial connection line is electrically connected to at least one first initial signal line.

19. The display device according to claim 18, further comprising: The substrate and the driving structure layer disposed on the substrate, the driving structure layer being provided with a pixel driving circuit, the pixel driving circuit including: at least one N-type transistor, at least one P-type transistor and a capacitor, the capacitor including a first plate and a second plate, the transistor including: an active pattern, a control electrode, a first electrode and a second electrode, the third scan signal line including a first sub-signal line and a second sub-signal line; The driving structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are sequentially stacked on the substrate; The first semiconductor layer includes at least: an active pattern of at least one P-type transistor; The first conductive layer includes at least: a first scan signal line, a first light emission signal line, a second light emission signal line, a first reset signal line, a first electrode of a capacitor located in at least one pixel driving circuit, and a control electrode of at least one P-type transistor; The second conductive layer includes at least: a first sub-signal line of the third scan signal line, a second initial signal line, and a second plate of a capacitor located in the pixel driving circuit of at least one sub-pixel; The second semiconductor layer includes at least: an active pattern of at least one N-type transistor; The third conductive layer includes at least: a second sub-signal line of the third scan signal line, a first initial signal line, and a reference signal line; The fourth conductive layer includes at least: an initial connection line located at the first and second poles of at least one transistor in at least one pixel driving circuit.

20. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as claimed in any one of claims 1 to 11, the method comprising: Under the control of at least one reset signal line, the reset sub-circuit provides a reference signal line signal to the second node, a first initial signal line signal to the fourth node, and a second initial signal line signal to the fifth node. Under the control of at least two scan signal lines and the first power supply line, the drive control sub-circuit provides the data signal line to the second node and the signal of the third or fourth node to the first node; The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes; Under the control of the signals from the first and second light-emitting signal lines, the light-emitting control sub-circuit provides the first power line signal to the second node and the third node signal to the fifth node.

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