Display substrate and display

Abstract

A display substrate and a display. The display substrate comprises a base and a plurality of sub-pixels arranged on the base, wherein at least some of the sub-pixels each comprise a pixel driving circuit, an anode (90) and an anode connecting electrode (83), and in the same sub-pixel, the pixel driving circuit is electrically connected to the anode (90) by means of the anode connecting electrode (83); in a direction perpendicular to a plane where the display substrate is located, the anode (90) is located on the side of the pixel driving circuit away from the base; and pixel driving circuits of at least some of the sub-pixels form a plurality of rows and a plurality of columns, and among a plurality of anodes (90) electrically connected to one row of pixel driving circuits, the overlapping area of at least one anode (90) with a row of pixel driving circuits adjacent thereto is greater than the overlapping area thereof with the row of pixel driving circuits electrically connected thereto.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible display devices with OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the embodiments of the present disclosure provide a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, at least part of the sub-pixels comprising a pixel driving circuit, an anode, and an anode connection electrode, in the same sub-pixel, the pixel driving circuit is electrically connected to the anode through the anode connection electrode; in a direction perpendicular to a plane where the display substrate is located, the anode is located on a side of the pixel driving circuit away from the substrate.

[0006] The pixel driving circuit of the at least part of the sub-pixels forms a plurality of rows and a plurality of columns, among the plurality of anodes electrically connected to a row of pixel driving circuits, at least one anode has an overlapping area with the pixel driving circuits of an adjacent row, which is greater than the overlapping area with the row of pixel driving circuits electrically connected thereto.

[0007] In an exemplary embodiment, among the plurality of anodes electrically connected to a row of pixel driving circuits, at least one anode has an overlapping area with the pixel driving circuits of an adjacent row, which is greater than the overlapping area with the row of pixel driving circuits electrically connected thereto, which can increase the length dimension of the anode connection electrode electrically connected to the at least one anode.

[0008] In an example embodiment, the at least part of the sub-pixels include first type sub-pixels and second type sub-pixels, a length dimension of an anode connecting electrode in the second type sub-pixels is greater than a length dimension of an anode connecting electrode in the first type sub-pixels; among a plurality of anodes electrically connected with a row of pixel driving circuits, a normal projection of the anode of the second type sub-pixel on the substrate at least partially overlaps with a normal projection of a pixel driving circuit of an adjacent row on the substrate, and an overlapping area of the anode of the second type sub-pixel with the pixel driving circuit of the adjacent row is greater than an overlapping area of the anode of the second type sub-pixel with the row of pixel driving circuits.

[0009] In an example embodiment, the anode includes an anode main part and an anode connecting part, in a same sub-pixel, the anode connecting part is electrically connected with the anode main part and a corresponding anode connecting electrode;

[0010] Among a plurality of anodes electrically connected with a row of pixel driving circuits, a normal projection of the anode main part of the second type sub-pixel on the substrate is located within a range of a normal projection of a pixel driving circuit of an adjacent row on the substrate.

[0011] In an example embodiment, among a plurality of anodes electrically connected with a row of pixel driving circuits, a normal projection of the anode of the first type sub-pixel on the substrate at least partially overlaps with a normal projection of the row of pixel driving circuits on the substrate.

[0012] In an example embodiment, among a plurality of anodes electrically connected with a row of pixel driving circuits, an overlapping area of the anode of the first type sub-pixel with the row of pixel driving circuits on the substrate is greater than an overlapping area of the anode of the first type sub-pixel with a pixel driving circuit of an adjacent row on the substrate.

[0013] In an example embodiment, in a direction perpendicular to a plane where a display substrate is located, the display substrate includes a driving circuit layer and an anode conductive layer, the anode connecting electrode is located in a conductive layer that is most adjacent to the anode conductive layer in the driving circuit layer, and the plurality of anodes are located in the anode conductive layer.

[0014] In an example embodiment, in a direction perpendicular to a plane where a display substrate is located, the driving circuit layer includes a fifth conductive layer and a sixth conductive layer, the sixth conductive layer is a conductive layer that is most adjacent to the anode conductive layer in the driving circuit layer, the fifth conductive layer is located between the substrate and the sixth conductive layer, and the sixth conductive layer is located between the fifth conductive layer and the anode conductive layer.

[0015] The fifth conductive layer comprises a first power supply connection line, the plurality of sub-pixels comprises a plurality of types, the plurality of types of sub-pixels at least comprises a second sub-pixel, and a normal projection of the first power supply connection line on the substrate at least partially overlaps with a normal projection of an anode of at least one second sub-pixel on the substrate.

[0016] In an example embodiment, the second type of sub-pixel comprises the second sub-pixel, the first power supply connection line comprises a first protruding portion, and among a plurality of anodes electrically connected with a row of pixel driving circuits, a normal projection of the anode of the second sub-pixel on the substrate at least partially overlaps with a normal projection of the first protruding portion in the pixel driving circuit of the adjacent row on the substrate.

[0017] In an example embodiment, the plurality of types of sub-pixels further comprises a first sub-pixel and a third sub-pixel, the first type of sub-pixel comprises the first sub-pixel and the third sub-pixel, the pixel driving circuits of the at least part of the sub-pixels are arranged in an array, and in the same row of pixel driving circuits, the pixel driving circuits of the first type of sub-pixel and the pixel driving circuits of the second type of sub-pixel are alternately arranged along the row direction, and in the row direction, the pixel driving circuit of the second sub-pixel is located between the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the third sub-pixel; a normal projection of the first power supply connection line and the pixel driving circuits of two adjacent sub-pixels in a row of pixel driving circuits on the substrate at least partially overlaps;

[0018] The first power supply connection line further comprises a connection body portion and two second protruding portions, and in the same first power supply connection line, the two second protruding portions are symmetric with respect to a middle line of the first power supply connection line extending in the column direction in the row direction; in the column direction, the first protruding portion is located on one side of the connection body portion, and the two second protruding portions are located on the other side of the connection body portion;

[0019] A normal projection of the anode of the first type of sub-pixel on the substrate at least partially overlaps with a normal projection of two adjacent second protruding portions in adjacent two first power supply connection lines on the substrate.

[0020] In an example embodiment, the sixth conductive layer further comprises a first power supply line, the first power supply line comprises a first power supply block and two first power supply connection structures, and in the same row of pixel driving circuits, a normal projection of the anode of the second type of sub-pixel, one of the first power supply blocks, and the first protruding portion in the corresponding first power supply connection line on the substrate at least partially overlaps; a normal projection of the anode of the first type of sub-pixel, two adjacent second protruding portions in adjacent two first power supply connection lines, and two adjacent first power supply connection structures in adjacent two first power supply lines on the substrate at least partially overlaps;

[0021] In the same pixel driving circuit, two adjacent first power supply blocks are connected to each other through the first power supply connection structure.

[0022] In an exemplary embodiment, the sixth conductive layer further comprises a plurality of data signal lines extending in the column direction and arranged at intervals in the row direction, and the data signal lines are electrically connected to at least part of the pixel driving circuits in one column of pixel driving circuits.

[0023] In the row direction, the first power supply line is located between two adjacent data signal lines, and two data signal lines are arranged between two adjacent first power supply lines; the orthogonal projection of the anode of the first type of sub-pixel on the substrate at least partially overlaps the orthogonal projection of the two data signal lines between the two adjacent first power supply lines on the substrate.

[0024] Among the two data signal lines and the two first power supply connection structures that overlap with the orthogonal projection of the anode of the same first type of sub-pixel on the substrate, one of the first power supply connection structures is located on one side of the two data signal lines, and the other first power supply connection structure is located on the other side of the two data signal lines.

[0025] In an exemplary embodiment, the fifth conductive layer further comprises a plurality of first data connection lines extending in the row direction and arranged at intervals in the column direction, and the sixth conductive layer further comprises a plurality of second data connection lines extending in the column direction and arranged at intervals in the row direction, and in the row direction, the second data connection line is located between two adjacent data signal lines; in the column direction, the distance interval between two adjacent first data connection lines is consistent with the size of one pixel driving circuit.

[0026] The plurality of data signal lines comprises a plurality of first type of data signal lines and a plurality of second type of data signal lines, and in the row direction, the first type of data signal line is located on the side of the second type of data signal line away from the first middle line, and the first middle line is the middle line of the display substrate extending in the column direction.

[0027] The first data connection line is electrically connected to one of the second data connection lines and one of the first type of data signal lines, and is configured to transmit the data signal of one of the second data connection lines to the first type of data signal line electrically connected thereto; among the first type of data signal line and the second data connection line electrically connected to the same first data connection line, in the row direction, the distance between the first type of data signal line and the first middle line is greater than the distance between the second data connection line and the first middle line.

[0028] In an exemplary embodiment, the normal projection of the anode of the first type of sub-pixel on the substrate also at least partially overlaps with the normal projection of one of the second data connection lines on the substrate.

[0029] Among the two data signal lines, the two first power supply connection structures and the second data connection line which overlap with the normal projection of the anode of the same first type of sub-pixel on the substrate, in the row direction, the two data signal lines are symmetrical relative to the second data connection line, and the two first power supply connection structures are symmetrical relative to the second data connection line.

[0030] In an exemplary embodiment, the display substrate includes a display area and a first frame area in a plane parallel to the display substrate, the first frame area is located on one side of the display area in the column direction, and the at least partially conductive layer in the drive circuit layer is provided with a bending mark in the first frame area.

[0031] In an exemplary embodiment, the drive circuit layer further includes a first conductive layer, a second conductive layer and a third conductive layer in a direction perpendicular to the plane in which the display substrate is located, the first conductive layer is located between the substrate and the second conductive layer, the second conductive layer is located between the first conductive layer and the third conductive layer, the third conductive layer is located between the second conductive layer and the fifth conductive layer, and the bending mark is located in at least one of the first conductive layer, the second conductive layer and the third conductive layer.

[0032] In an exemplary embodiment, the first frame area is provided with a bending area, and the bending mark is located in the bending area.

[0033] In an exemplary embodiment, the minimum distance between the bending mark and the adjacent signal line is 5 microns to 20 microns.

[0034] In an exemplary embodiment, the shape of the bending mark is cross-shaped or T-shaped.

[0035] In an exemplary embodiment, the plurality of sub-pixels includes a plurality of types, the plurality of types of sub-pixels at least include first sub-pixels, second sub-pixels and third sub-pixels, at least a part of the first sub-pixels, the second sub-pixels and the third sub-pixels are the first type of sub-pixels, and another part is the second type of sub-pixels.

[0036] In an exemplary embodiment, one of the first sub-pixels, the second sub-pixels and the third sub-pixels is the second type of sub-pixel, and the other two are the first type of sub-pixel.

[0037] In an exemplary embodiment, the anodes of the plurality of second-type sub-pixels electrically connected with the i-th row of pixel driving circuits at least partially overlap the orthographic projections of the i-1-th row of pixel driving circuits on the substrate; or the anodes of the plurality of second-type sub-pixels electrically connected with the i-th row of pixel driving circuits at least partially overlap the orthographic projections of the i+1-th row of pixel driving circuits on the substrate; i is a positive integer greater than 1.

[0038] The anodes of the plurality of first-type sub-pixels electrically connected with the i-th row of pixel driving circuits at least partially overlap the orthographic projections of the i-th row of pixel driving circuits on the substrate.

[0039] In an exemplary embodiment, the first-type sub-pixels include the first sub-pixels and the third sub-pixels, and the second-type sub-pixels include the second sub-pixels; the plurality of anodes form first anode columns and second anode columns arranged alternately along the row direction, in the same first anode column, the anodes of the first sub-pixels and the anodes of the third sub-pixels are arranged alternately along the column direction, and in the same second anode column, the anodes of the plurality of second sub-pixels are arranged spacedly along the column direction; the plurality of anodes form first anode rows and second anode rows arranged alternately along the column direction, in the same first anode row, the anodes of the first sub-pixels and the anodes of the third sub-pixels are arranged alternately along the row direction, and in the same second anode row, the anodes of the plurality of second sub-pixels are arranged spacedly along the row direction.

[0040] In an exemplary embodiment, the first-type sub-pixels include the first sub-pixels and the second sub-pixels, and the second-type sub-pixels include the third sub-pixels; or, the first-type sub-pixels include the second sub-pixels and the third sub-pixels, and the second-type sub-pixels include the first sub-pixels.

[0041] In an exemplary embodiment, the length dimension of the anode connecting electrode of the second-type sub-pixel is 5 microns to 15 microns.

[0042] In a second aspect, the embodiments of the present disclosure further provide a display device including the display substrate according to any one of the above embodiments.

[0043] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0044] The accompanying drawings are included to provide a further understanding of the technical scheme of the present disclosure and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical scheme of the present disclosure, and do not constitute a limitation on the technical scheme of the present disclosure. The shape and size of each component in the drawings do not reflect the true proportion, and the purpose is only to schematically illustrate the present disclosure.

[0045] FIG. 1 is a structural schematic diagram of a display device;

[0046] FIG. 2 is a structural schematic diagram of a display substrate;

[0047] FIG. 3 is a plan structural schematic diagram of a first frame region in a display substrate;

[0048] FIG. 4 is a structural schematic diagram of a display substrate;

[0049] FIG. 5a is a plan structural schematic diagram of a display region in a display substrate;

[0050] FIG. 5b is a cross-sectional structural schematic diagram of a display region in a display substrate;

[0051] FIG. 6 is an equivalent circuit schematic diagram of a pixel driving circuit;

[0052] FIG. 7a is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0053] FIG. 7b is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0054] FIG. 7c is a plan structural schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0055] FIG. 7d is a plan structural schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0056] FIG. 7e is a plan structural schematic diagram of a first frame region in a display substrate provided by an exemplary embodiment of the present disclosure;

[0057] FIG. 8 is an equivalent circuit schematic diagram of a pixel driving circuit provided by an exemplary embodiment of the present disclosure;

[0058] FIG. 9 is a schematic diagram of a display substrate after forming a shielding layer pattern provided by an exemplary embodiment of the present disclosure;

[0059] FIG. 10a is a schematic diagram of a display substrate after forming a first semiconductor layer pattern provided by an exemplary embodiment of the present disclosure;

[0060] FIG. 10b is a schematic diagram of a first semiconductor layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0061] FIG. 10c is a schematic diagram of a display substrate after forming a first semiconductor layer pattern provided by an exemplary embodiment of the present disclosure;

[0062] FIG. 11a is a schematic diagram of a display substrate after forming a first conductive layer pattern provided by an exemplary embodiment of the present disclosure;

[0063] FIG. 11b shows a schematic view of a first conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0064] FIG. 12a shows a schematic view of a display substrate after forming a second conductive layer pattern according to an example embodiment of the present disclosure;

[0065] FIG. 12b shows a schematic view of a second conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0066] FIG. 12c shows a schematic view of a display substrate after forming a second conductive layer pattern according to an example embodiment of the present disclosure;

[0067] FIG. 13a shows a schematic view of a display substrate after forming a second semiconductor layer pattern according to an example embodiment of the present disclosure;

[0068] FIG. 13b shows a schematic view of a second semiconductor layer in a display substrate according to an example embodiment of the present disclosure;

[0069] FIG. 14a shows a schematic view of a display substrate after forming a third conductive layer pattern according to an example embodiment of the present disclosure;

[0070] FIG. 14b shows a schematic view of a third conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0071] FIG. 15 shows a schematic view of a display substrate after forming a sixth insulating layer pattern according to an example embodiment of the present disclosure;

[0072] FIG. 16a shows a schematic view of a display substrate after forming a fourth conductive layer pattern according to an example embodiment of the present disclosure;

[0073] FIG. 16b shows a schematic view of a fourth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0074] FIG. 16c shows a schematic view of a display substrate after forming a fourth conductive layer pattern according to an example embodiment of the present disclosure;

[0075] FIG. 17 shows a schematic view of forming a first planarization layer pattern according to an example embodiment of the present disclosure;

[0076] FIG. 18a shows a schematic view of a display substrate after forming a fifth conductive layer pattern according to an example embodiment of the present disclosure;

[0077] FIG. 18b shows a schematic view of a fifth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0078] FIG. 19a shows a schematic diagram of a display substrate after forming a second planarization layer pattern according to an example embodiment of the present disclosure;

[0079] FIG. 19b shows a schematic diagram of a display substrate after forming a second planarization layer pattern according to an example embodiment of the present disclosure;

[0080] FIG. 20a shows a schematic diagram of a display substrate after forming a sixth conductive layer pattern according to an example embodiment of the present disclosure;

[0081] FIG. 20b shows a schematic diagram of a sixth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0082] FIG. 20c shows a schematic diagram of a display substrate after forming a sixth conductive layer pattern according to an example embodiment of the present disclosure;

[0083] FIG. 21 shows a schematic diagram of a display substrate after forming a third planarization layer pattern according to an example embodiment of the present disclosure;

[0084] FIG. 22a shows a schematic diagram of a display substrate after forming an anode conductive layer pattern according to an example embodiment of the present disclosure;

[0085] FIG. 22b shows a schematic diagram of an anode conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0086] FIG. 22c shows a schematic diagram of a display substrate after forming an anode conductive layer pattern according to an example embodiment of the present disclosure;

[0087] FIG. 23a shows a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an example embodiment of the present disclosure;

[0088] FIG. 23b shows a schematic diagram of a pixel definition layer pattern in a display substrate according to an example embodiment of the present disclosure;

[0089] FIG. 23c shows a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0090] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. The embodiments can be implemented in various forms. It should be easily understood by those of ordinary skill in the art that the embodiments and the contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict unless otherwise specified. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed description of some known functions and known components will be omitted. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0091] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the thickness and interval of each film layer, the width and interval of each signal line, can be adjusted according to the actual situation. The drawings described in the present disclosure are only schematic diagrams of structures, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0092] In the present specification, ordinal numbers such as "first", "second", and "third" are set in order to avoid confusion of components, and are not intended to be limiting in terms of numbers.

[0093] In the present specification, words indicating directions or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain the positional relationship of components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the components is appropriately changed according to the direction of each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0094] In the present specification, unless explicitly specified and limited, the terms "mount", "connect", "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0095] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, a channel region refers to a region where current flows mainly.

[0096] In this specification, a first electrode can be a drain electrode and a second electrode can be a source electrode, or a first electrode can be a source electrode and a second electrode can be a drain electrode. In the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other. In this embodiment of the disclosure, a gate electrode can be referred to as a control electrode.

[0097] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. An element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of an element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element having another function.

[0098] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0099] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0100] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon. There can be some small deformation due to a tolerance, a rounded corner, a curved side, or the like.

[0101] In this embodiment of the disclosure, "approximately" means that a limit is not strictly defined and a value within a range of a process and measurement error is allowed.

[0102] FIG. 1 shows a structural schematic diagram of a display device, a display substrate can include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array, the timing controller is connected with the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit respectively, the data signal driving circuit is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan signal driving circuit is connected with a plurality of scan signal lines (G1 to Gm) respectively, and the light emission signal driving circuit is connected with a plurality of light emission signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting device connected with the circuit unit, the circuit unit can include a pixel driving circuit, and the pixel driving circuit can be connected with a scan signal line, a light emission signal line, and a data signal line (which can be referred to as a data line) respectively. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data signal driving circuit to the data signal driving circuit, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driving circuit to the scan signal driving circuit, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can generate a data voltage to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data signal driving circuit can sample the gray value using the clock signal, and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan signal driving circuit can generate a scan signal to be provided to the scan signal lines G1, G2, G3, …, and Gm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driving circuit can sequentially provide the scan signal having an on-level pulse to the scan signal lines G1 to Gm. For example, the scan signal driving circuit can be configured in the form of a shift register, and can generate the scan signal in a manner of sequentially transferring the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emission signal driving circuit can generate an emission signal to be provided to the light emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emission signal driving circuit can sequentially provide the emission signal having an off-level pulse to the light emission signal lines E1 to Eo. For example, the light emission driver can be configured in the form of a shift register, and can generate the emission signal in a manner of sequentially transferring the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number.

[0103] FIG. 2 shows a structural schematic diagram of a display panel. As shown in FIG. 2, the display panel can include a display area AA and a frame area BB located at the periphery of the display area AA. In some examples, the periphery area BB can include a first frame (lower frame) B1 and a second frame (upper frame) B2 oppositely arranged in the second direction Y, and a third frame (left frame) B3 and a fourth frame (right frame) B4 oppositely arranged in the first direction X. The first frame B1 is in communication with the third frame B3 and the fourth frame B4, and the second frame B2 is in communication with the third frame B3 and the fourth frame B4. In some examples, the display area AA can include a first edge (lower edge) and a second edge (upper edge) oppositely arranged in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) oppositely arranged in the first direction X. The display area AA can include a plurality of sub-pixels Pxij arranged in a regular pattern, the sub-pixels can include a pixel driving circuit and a light emitting device, the first frame B1 can include a bonding circuit connecting a signal line to an external driving device, and the third frame B3 and the fourth frame B4 can include a gate driving circuit and a second power supply line VSS transmitting a voltage signal to the plurality of sub-pixels.

[0104] FIG. 3 shows a schematic diagram of a planar structure of the first bezel area B1, which can include, in a plane parallel to the display substrate, a first fan-out area a1, a bending area a2, a second fan-out area a3, and a binding area a4 arranged in sequence in a direction away from the display area AA; the binding area a4 can include a driving chip area a41 and a binding electrode area a42 arranged in sequence in a direction away from the bending area a2 from the second fan-out area a3. The first fan-out area a1 can include data fan-out lines, a first power line, and a second power line VSS, the data fan-out lines being located in a middle portion of the first fan-out area a1 and including a plurality of data connection lines configured to connect data lines of the display area AA in a fan-out manner, the first power line being configured to connect a high-voltage power line (VDD) of the display area AA, and the second power line being a low-voltage power line (VSS) located in the third bezel area B3 and the fourth bezel area B4. The bending area a2 can include a composite insulating layer provided with a groove and configured to bend the binding area a4 to a back surface of the display area AA (as shown in FIG. 4). The second fan-out area a3 includes a plurality of data connection lines led out in a fan-out manner. The driving chip area a41 can be provided with an integrated circuit (IC) 20 configured to be connected to the plurality of data connection lines. The binding electrode area a42 includes a plurality of bonding pads configured to be connected to a flexible printed circuit (FPC) 30 in a binding manner. In an example embodiment, the integrated circuit (IC) 20 can be connected to the driving chip area a41 in a binding manner, and the flexible printed circuit (FPC) 30 can be connected to the binding electrode area a42 in a binding manner. In an example embodiment, the integrated circuit 20 can generate a driving signal required for driving a sub-pixel and can provide the driving signal to the sub-pixel Pxij located in the display area AA. For example, the driving signal can be a data signal for controlling the luminance of the sub-pixel. In an example embodiment, the binding electrode area a42 can be provided with a pad (PAD) including a plurality of pins (PIN), and the flexible printed circuit 30 can be connected to the pad in a binding manner.

[0105] In an example embodiment, as shown in FIG. 4, the bending area a2 can invert the surface of the binding area a4, i.e., the surface of the binding area a4 facing upward can be converted to face downward through the bending of the bending area a2. In an example embodiment, when the bending area a2 is bent, the binding area a4 can overlap the display area AA in a display panel thickness direction.

[0106] In an example embodiment, for a large size display substrate, a plurality of data driving ICs (may be referred to as driving IC, i.e. driving integrated circuit) and a plurality of FPCs can be provided, the plurality of FPCs are respectively bound to the plurality of data driving ICs, for example, four data driving ICs can be provided and bound to four FPCs, the embodiments of the present disclosure are not limited to four ICs and four FPCs, for example, two data driving ICs and two FPCs can be provided; for a small size display substrate, one data driving IC or two data driving ICs can be provided. In the embodiments of the present disclosure, the number of data driving ICs and FPCs can be set according to the size of the display substrate and the need of function, which is not limited herein.

[0107] FIG. 5a is a schematic diagram of a planar structure of a display substrate. As shown in FIG. 5a, the display substrate can include a plurality of pixel units P arranged in a matrix manner, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, and a third sub-pixel P3 emitting third color light, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light emitting device. The pixel driving circuit in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 is respectively connected with a scan signal line, a data signal line, and a light emitting signal line, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, and output a corresponding current to the light emitting device. The light emitting device in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 is respectively connected with the pixel driving circuit in the sub-pixel where the light emitting device is located, and is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit in the sub-pixel where the light emitting device is located.

[0108] In an example embodiment, the pixel unit P can include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an example embodiment, the shape of the sub-pixel in the pixel unit can be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner, which is not limited herein.

[0109] FIG. 5b is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in FIG. 5b, in a plane perpendicular to the display substrate, the display substrate can include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a spacer, which is not limited herein.

[0110] In the example embodiment, the substrate 101 can be a flexible substrate, or can be a rigid substrate. The driving circuit layer 102 of each sub-pixel can include a plurality of transistors and a storage capacitor constituting a pixel driving circuit. The light-emitting structure layer 103 can include an anode 301 connected to the drain electrode of the driving transistor 210 through a via, an organic light-emitting layer 302 connected to the anode 301, and a cathode 303 connected to the organic light-emitting layer 302, the organic light-emitting layer 302 emitting light of a corresponding color under the driving of the anode 301 and the cathode 303. The encapsulation layer 104 can include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together, the first encapsulation layer 401 and the third encapsulation layer 403 can be made of inorganic material, the second encapsulation layer 402 can be made of organic material, and the second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403, so as to prevent external water vapor from entering the light-emitting structure layer 103.

[0111] In the example embodiment, the organic light-emitting layer 302 can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked together. In the example embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0112] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. FIG. 6 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 6, the pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and can be connected with 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, emission signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS).

[0113] In an exemplary embodiment, the pixel driving circuit can include a first node N1, a second node N2 and a third node N3. The first node N1 is connected with the first electrode of the third transistor T3, the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5 respectively, the second node N2 is connected with the second electrode of the first transistor T1, the first electrode of the second transistor T2, the control electrode of the third transistor T3 and the second end of the storage capacitor C respectively, and the third node N3 is connected with the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 respectively.

[0114] In an exemplary embodiment, the first end of the storage capacitor C is connected with the first power supply line VDD, and the second end of the storage capacitor C is connected with the second node N2, i.e. the second end of the storage capacitor C is connected with the control electrode of the third transistor T3.

[0115] The control electrode of the first transistor T1 is connected with the second scan signal line S2, the first electrode of the first transistor T1 is connected with the initial signal line INIT, and the second electrode of the first transistor is connected with the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so as to initialize the charge amount of the control electrode of the third transistor T3.

[0116] The control electrode of the second transistor T2 is connected with the first scan signal line S1, the first electrode of the second transistor T2 is connected with the second node N2, and the second electrode of the second transistor T2 is connected with the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3.

[0117] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driver transistor, and the amount of a drive current flowing between the first power supply line VDD and the second power supply line VSS is determined in accordance with the potential difference between the control electrode and the first electrode of the third transistor T3.

[0118] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, a scan transistor, or the like, and the fourth transistor T4 inputs a data voltage of the data signal line D to the pixel driving circuit when an on-level scan signal is applied to the first scan signal line S1.

[0119] The control electrode of the fifth transistor T5 is connected to the emission signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the emission signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors. The fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a drive current path between the first power supply line VDD and the second power supply line VSS when an on-level emission signal is applied to the emission signal line E.

[0120] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. The seventh transistor T7 transmits an initialization voltage to the first electrode of the light emitting device to initialize the amount of charge accumulated in the first electrode of the light emitting device or release the amount of charge accumulated in the first electrode of the light emitting device when an on-level scan signal is applied to the first scan signal line S1.

[0121] In the example embodiment, the second electrode of the light emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low level signal, and the signal of the first power supply line VDD is a continuously provided high level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 can be S(n), and the second scan signal line S2 can be S(n-1). The second scan signal line S2 of the current display row and the first scan signal line S1 of the previous display row are the same signal line, which can reduce the signal lines of the display panel and achieve a narrow frame of the display panel.

[0122] In the example embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0123] In the example embodiment, the first scan signal line S1, the second scan signal line S2, the light emitting signal line E, and the initial signal line INIT extend along the horizontal direction, and the second power supply line VSS, the first power supply line VDD, and the data signal line D extend along the vertical direction.

[0124] In the example embodiment, the light emitting device can be an organic electroluminescence diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0125] With the development of OLED display technology and mobile communication technology, the power consumption requirement of the OLED display panel in a mobile device is increasingly small, that is, the power consumption of the OLED display panel needs to be reduced to support the long endurance of the mobile device (for example, a terminal such as a mobile phone), so reducing power consumption is one of the important issues of the OLED display panel. The OLED display panel is usually debugged by a Gamma module to adjust the signal voltage, brightness, gray scale, chroma, and power consumption of the OLED display panel. The Gamma module includes a voltage dividing unit, wherein the write black voltage VGMP (that is, the data write-in voltage corresponding to the low gray scale, which can be the voltage corresponding to the lowest gray scale) is the high voltage of the Gamma module, which controls the write black of the display panel. Therefore, the high and low of the black state voltage VGMP directly affects the power consumption of the OLED, and reducing the black state voltage VGMP can effectively reduce the power consumption of the OLED panel. The anode trace of the light emitting device is short and cannot form a large anode node capacitance. Such a pixel usually has a large write black voltage, resulting in large power consumption of the display panel.

[0126] The display substrate provided by the embodiment of the present disclosure can include a substrate and a plurality of sub-pixels arranged on the substrate, at least part of the sub-pixels including a pixel driving circuit, an anode and an anode connecting electrode, the pixel driving circuit being electrically connected to the anode through the anode connecting electrode in the same sub-pixel, and the anode being located on a side of the pixel driving circuit away from the substrate in a direction perpendicular to a plane in which the display substrate is located.

[0127] The pixel driving circuit of the at least part of the sub-pixels forms a plurality of rows and a plurality of columns, and among the plurality of anodes electrically connected to a row of the pixel driving circuits, an overlapping area of at least one anode and a pixel driving circuit of an adjacent row is greater than an overlapping area of the at least one anode and a row of the pixel driving circuits electrically connected thereto.

[0128] The display substrate provided by the embodiment of the present disclosure can include a substrate and a plurality of sub-pixels arranged on the substrate, at least part of the sub-pixels including a pixel driving circuit, an anode and an anode connecting electrode, the pixel driving circuit being electrically connected to the anode through the anode connecting electrode in the same sub-pixel, and the anode being located on a side of the pixel driving circuit away from the substrate in a direction perpendicular to a plane in which the display substrate is located.

[0129] As shown in FIGS. 7a and 7b, the display substrate provided by the embodiment of the present disclosure can include a substrate and a plurality of sub-pixels arranged on the substrate, at least part of the sub-pixels including a pixel driving circuit, an anode 90 and an anode connecting electrode 83, the pixel driving circuit being electrically connected to the anode 90 through the anode connecting electrode 83 in the same sub-pixel, and the anode 90 being located on a side of the pixel driving circuit away from the substrate in a direction perpendicular to a plane in which the display substrate is located.

[0130] The pixel driving circuit of the at least part of the sub-pixels forms a plurality of rows and a plurality of columns, and among the plurality of anodes 90 electrically connected to a row of the pixel driving circuits, an overlapping area of at least one anode 90 and a pixel driving circuit of an adjacent row is greater than an overlapping area of the at least one anode 90 and a row of the pixel driving circuits electrically connected thereto.

[0131] In the exemplary implementation, among the plurality of anodes 90 electrically connected to a row of the pixel driving circuits, an overlapping area of at least one anode 90 and a pixel driving circuit of an adjacent row is greater than an overlapping area of the at least one anode 90 and a row of the pixel driving circuits electrically connected thereto, which can increase a length dimension of the anode connecting electrode 83 electrically connected to the at least one anode 90.

[0132] In an example embodiment, the overlapping area of the at least one anode 90 and the pixel driving circuit of the adjacent row can be the overlapping area of the orthographic projection of the at least one anode 90 on the substrate and the orthographic projection of the pixel driving circuit of the adjacent row on the substrate; the overlapping area of the at least one anode 90 and the pixel driving circuit of the row to which the at least one anode 90 is electrically connected can be the overlapping area of the orthographic projection of the at least one anode 90 on the substrate and the orthographic projection of the pixel driving circuit of the row to which the at least one anode 90 is electrically connected on the substrate.

[0133] In an example embodiment, the at least part of the sub-pixels can include first-type sub-pixels PA1 and second-type sub-pixels PA2, and the length dimension L2 of the anode connecting electrode 83 in the second-type sub-pixels PA2 is greater than the length dimension L1 of the anode connecting electrode 83 in the first-type sub-pixels PA1.

[0134] In an example embodiment, among the plurality of anodes electrically connected to the row of pixel driving circuits, the anode 90 of the second-type sub-pixel PA2 at least partially overlaps the orthographic projection of the pixel driving circuit of the adjacent row on the substrate, and the overlapping area of the anode 90 of the second-type sub-pixel PA2 and the pixel driving circuit of the adjacent row is greater than the overlapping area of the anode 90 of the second-type sub-pixel PA2 and the pixel driving circuit of the row to which the anode 90 is electrically connected, and the length dimension of the anode connecting electrode 83 of the second-type sub-pixel PA2 can be increased.

[0135] In an example embodiment, the length dimension L1 of the anode connecting electrode 83 of the second-type sub-pixel PA2 can be 5 microns to 15 microns.

[0136] In the embodiments of the present disclosure, lengthening the anode connecting electrode 83 in the second-type sub-pixel PA2 can increase the parasitic capacitance between the anode connecting electrode 83 in the second-type sub-pixel PA2 and the nearby signal line, thereby reducing the black writing voltage and reducing the power consumption of the display substrate. In an example embodiment, the black writing voltage VGMP of the display substrate refers to the voltage of the display substrate in the non-emitting state (that is, the voltage of the gray scale value of 0, which can be referred to as the black state voltage). In the case of increasing the parasitic capacitance between the anode connecting electrode 83 and the nearby signal line, the sub-pixel can emit light only after the capacitor is fully charged, and the black state voltage VGMP can be correspondingly reduced.

[0137] In the example embodiment, the parasitic capacitance between the anode 90 and the nearby signal lines can be increased by increasing the area of the anode 90, which will reduce the transmittance of the display substrate and result in a decrease in display effect compared to increasing the length of the anode connecting electrode 83. The example embodiment increases the parasitic capacitance and reduces the power consumption of the display substrate without affecting the transmittance of the display substrate by increasing the length of the anode connecting electrode 83. In the example embodiment, at least some of the sub-pixels can include a light-emitting device, and the pixel driving circuit is configured to drive the corresponding light-emitting device to emit light. The light-emitting device includes the anode 90, and the anode connecting electrode 83 is electrically connected to the corresponding anode 90. That is, increasing the size of the anode connecting electrode 83 and increasing the area of the anode 90 can both increase the parasitic capacitance between the anode of the light-emitting device and the nearby signal lines.

[0138] In the example embodiment, the anode 90 can include an anode main body part 901 and an anode connecting part 902. In the same sub-pixel, the anode connecting part 902 is electrically connected to the anode main body part 901 and the corresponding anode connecting electrode 83.

[0139] In the example embodiment, among the plurality of anodes 90 electrically connected to the pixel driving circuit of one row, the anode main body part 901 of the second type of sub-pixel PA2 has a footprint on the substrate within the footprint of the pixel driving circuit of the adjacent row on the substrate.

[0140] In the example embodiment, among the plurality of anodes 90 electrically connected to the pixel driving circuit of one row, the anode 90 of the first type of sub-pixel PA1 has a footprint on the substrate at least partially overlapping the footprint of the pixel driving circuit of the row on the substrate.

[0141] In the example embodiment, among the plurality of anodes 90 electrically connected to the pixel driving circuit of one row, the anode 90 of the first type of sub-pixel PA1 has a footprint on the substrate at least partially overlapping the footprint of the pixel driving circuit of the row on the substrate.

[0142] In the example embodiment, in the direction perpendicular to the plane of the display substrate, the display substrate can include a driving circuit layer and an anode conductive layer. The anode connecting electrode 83 can be located in the conductive layer closest to the anode conductive layer in the driving circuit layer, and the plurality of anodes 90 can be located in the anode conductive layer.

[0143] In the example embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer can include a fifth conductive layer and a sixth conductive layer. The sixth conductive layer is the conductive layer in the driving circuit layer closest to the anode conductive layer. The fifth conductive layer is located between the substrate and the sixth conductive layer, and the sixth conductive layer is located between the fifth conductive layer and the anode conductive layer.

[0144] The fifth conductive layer can include a first power supply connection line 73 (as shown in FIGS. 7a, 7b, 18a and 18b), the plurality of sub-pixels can include a plurality of types, and the plurality of types of sub-pixels can include at least the second sub-pixel P2. The orthogonal projection of the first power supply connection line 73 on the substrate at least partially overlaps the orthogonal projection of the anode 92 of the at least one second sub-pixel P2 on the substrate.

[0145] In an example embodiment, the second type of sub-pixel PA2 can include the second sub-pixel P2, the first power supply connection line 73 can include a first protruding portion 731, and among the plurality of anodes 90 electrically connected with the pixel driving circuit of one row of pixels, the orthogonal projection of the anode 92 of the second sub-pixel P2 on the substrate at least partially overlaps the orthogonal projection of the first protruding portion 731 in the pixel driving circuit of the adjacent row of pixels on the substrate. The first power supply connection line 73 can shield the signal of the data signal line 81, reduce the coupling of the voltage jump of the data signal line 81 to the anode 92 of the second sub-pixel P2, and thus reduce the interference to the anode 92 of the second sub-pixel P2.

[0146] In an example embodiment, the orthogonal projection of the anode 92 of the second sub-pixel P2 on the substrate can be located within the range of the orthogonal projection of the first protruding portion 731 in the pixel driving circuit of the adjacent row of pixels on the substrate. In the first aspect, the first protruding portion 731 can well shield the signal of the wiring in the film layer near the substrate side of the anode 92 of the second sub-pixel P2; in the second aspect, the flatness of the anode 92 of the second sub-pixel P2 can be improved; and in the third aspect, in the case where the second sub-pixel P2 is a sub-pixel emitting green light, the sub-pixel emitting green light is more sensitive and is prone to have uneven pictures (such as prone to have color deviation, horizontal lines, vertical lines, etc.). In the case where the flatness of the anode 92 of the second sub-pixel P2 is improved and the interference signal is shielded, the defect of the uneven picture of the second sub-pixel P2 is improved, and the display effect is improved to some extent.

[0147] In an example embodiment, the plurality of sub-pixels can further include a first sub-pixel P1 and a third sub-pixel P3, the first type of sub-pixel PA1 can include the first sub-pixel P1 and the third sub-pixel P3, the pixel driving circuit of at least part of the sub-pixels is arranged in an array, in the same row of pixel driving circuits, the pixel driving circuit of the first type of sub-pixel PA1 and the pixel driving circuit of the second type of sub-pixel PA2 are arranged alternately along the row direction X, and in the row direction X, the pixel driving circuit of the second sub-pixel P2 can be located between the pixel driving circuit of the first sub-pixel P1 and the pixel driving circuit of the third sub-pixel P3; the orthogonal projection of the first power supply connection line 73 and the pixel driving circuit of the adjacent two sub-pixels in one row of pixel driving circuits on the substrate at least partially overlaps.

[0148] The first power connection line 73 can further include a connection main body part 730 and two second protruding parts 732. In the same first power connection line 73, the two second protruding parts 732 are symmetric to the middle line W1-W1 of the first power connection line 73 extending in the column direction Y (as shown in FIG. 18b) in the row direction X; in the column direction Y, the first protruding part 731 can be located on one side of the connection main body part 730, and the two second protruding parts 732 can be located on the other side of the connection main body part 730.

[0149] The first protruding part 731 of the first power connection line 73 can be located on one side of the connection main body part 730 in the column direction Y, and the two second protruding parts 732 can be located on the other side of the connection main body part 730.

[0150] In the exemplary embodiments, the first sub-pixel P1 can be a sub-pixel emitting red light, the second sub-pixel P2 can be a sub-pixel emitting green light, and the third sub-pixel P3 can be a sub-pixel emitting blue light. In actual products, the first sub-pixel P1 and the third sub-pixel P3 are less likely to have high write voltage, and the problem of high power consumption is not serious, or even does not exist. The second sub-pixel P2 has high efficiency and is prone to have high power consumption. Therefore, in some exemplary embodiments, the second type of sub-pixel PA2 can include the second sub-pixel P2, and the first type of sub-pixel PA1 can include the first sub-pixel P1 and the third sub-pixel P3, that is, by increasing the length of the anode connecting electrode 83, the power consumption of the second sub-pixel P2 is reduced as much as possible.

[0151] In the exemplary embodiments, as shown in FIGS. 7a and 20b, the sixth conductive layer can further include a first power line 82, and the first power line 82 can include a first power block 821 and two first power connection structures 822. In the same row of pixel driving circuits, the anode 92 of the second type of sub-pixel PA2, one of the first power blocks 821, and the first protruding part 731 in the corresponding first power connection line 73 at least partially overlap in the projection on the substrate; the anode 91 of the first type of sub-pixel PA1, the two second protruding parts 732 adjacent to each other in the two adjacent first power connection lines 73, and the two first power connection structures 822 adjacent to each other in the two adjacent first power lines 82 at least partially overlap in the projection on the substrate.

[0152] In the same column of pixel driving circuits, the two first power blocks 821 adjacent to each other can be connected to each other through the first power connection structure 822, and the pixel driving circuits in the same column of pixel driving circuits can receive signals from the first power line 82, which are basically consistent, thereby improving the display uniformity.

[0153] In the example embodiment, the sixth conductive layer can further include a plurality of data signal lines 81 extending along the column direction Y and arranged at intervals along the row direction X, and the data signal lines 81 are electrically connected to at least part of the pixel driving circuits in one column of pixel driving circuits;

[0154] In the row direction X, the first power supply line 82 can be located between two adjacent data signal lines 81, and two data signal lines 81 are arranged between the two adjacent first power supply lines 82; the orthogonal projection of the anode 91 of the first-type sub-pixel PA1 on the substrate at least partially overlaps the orthogonal projection of the two data signal lines 81 between the two adjacent first power supply lines 82 on the substrate.

[0155] Of the two data signal lines 81 and the two first power supply connection structures 822 that overlap with the orthogonal projection of the anode 91 of the same first-type sub-pixel PA1 on the substrate, in the row direction X, one of the first power supply connection structures 822 is located on one side of the two data signal lines 81, and the other first power supply connection structure 822 is located on the other side of the two data signal lines 81, which can improve the symmetry of the anode 90 of the first-type sub-pixel PA and improve the display effect.

[0156] In the example embodiment, as shown in FIGS. 7a-7d, the fifth conductive layer can further include a plurality of first data connection lines 71 extending along the row direction X and arranged at intervals along the column direction Y, and the sixth conductive layer can further include a plurality of second data connection lines 84 extending along the column direction Y and arranged at intervals along the row direction X; in the row direction X, the second data connection line 84 can be located between two adjacent data signal lines 81; in the column direction Y, the distance interval between two adjacent first data connection lines 71 is consistent with the size of one pixel driving circuit.

[0157] The plurality of data signal lines 81 can include a plurality of first-type data signal lines 811 and a plurality of second-type data signal lines 812, and in the row direction X, the first-type data signal lines 811 are located on the same side of the first median line Q1-Q1, and the second-type data signal lines 812 are located on the side of the first median line Q1-Q1 away from the first-type data signal lines 811, and the first median line Q1-Q1 is a median line of the display substrate extending along the column direction Y.

[0158] The first data connection line 71 is electrically connected to one of the second data connection lines 84 and one of the first-type data signal lines 811, and is configured to transmit the data signal of the one of the second data connection lines 84 to the first-type data signal line 811 electrically connected thereto; of the first-type data signal lines 811 and the second data connection lines 84 electrically connected to the same first data connection line 71, in the row direction X, the distance between the first-type data signal line 811 and the first median line Q1-Q1 is greater than the distance between the second data connection line 84 and the first median line Q1-Q1.

[0159] In the example embodiment, the orthogonal projection of the anode of the first type of sub-pixel PA1 on the substrate can also at least partially overlap with the orthogonal projection of one of the second data connection lines 84 on the substrate;

[0160] Among the two data signal lines 81, the two first power connection structures 822 and the second data connection line 84 that overlap with the orthogonal projection of the anode of the same first type of sub-pixel PA1 on the substrate, in the row direction X, the two data signal lines 81 can be symmetrical relative to the second data connection line 84, and the two first power connection structures 822 can be symmetrical relative to the second data connection line 84, which can improve the symmetry of the anode 90 of the first type of sub-pixel PA, thereby improving the display effect.

[0161] In the example embodiment, the two data signal lines 81 are symmetrical relative to the second data connection line 84, which can be approximately symmetrical relative to the second data connection line 84; and the two first power connection structures 822 are symmetrical relative to the second data connection line 84, which can be approximately symmetrical relative to the second data connection line 84.

[0162] With the development of OLED display technology, consumers have higher and higher requirements for the display effect of display products, and extremely narrow frame has become a new trend of display product development, so the narrow frame or even frameless design is paid more and more attention in the design of OLED display products. As shown in FIG. 2 and FIG. 3, the narrow design of the lower frame (the first frame area B1) of the display device is more difficult; the FIAA (Fanout in AA, FIAA for short) or FIP (Fanout In Panel, FIP for short) technology is adopted in the embodiments of the present disclosure, as shown in FIG. 7c and FIG. 7d, the data fanout line (i.e. the first data connection line 71 and the second data connection line 84) is located in the display area (Fanout in AA, FIAA for short) structure, for example, as shown in FIG. 7c and FIG. 7d, one end of at least part of the second data connection line 84 is located in the display area of the display substrate, and is connected with the plurality of first data signal lines 811 in the display area AA through at least part of the first data connection line 71 (one first data connection line 71 and one second data connection line 84 and one first data signal line 811 are electrically connected, that is, one second data connection line 84 and one first data signal line 811 can be electrically connected one by one through the first data connection line 71), and the other end of at least part of the second data connection line 84 extends to the first frame area B1 and is connected with the integrated circuit located in the first frame area B1. Since the fan-shaped diagonal line does not need to be arranged in the first frame area B1, the width of the fanout area is reduced, and the width of the lower frame (i.e. the first frame area B1) of the display substrate is effectively reduced.

[0163] In an example embodiment, as shown in FIG. 7c and FIG. 7e, in a plane parallel to the display substrate, the display substrate can include a display area AA and a first frame area B1, and in the column direction Y, the first frame area B1 can be located on one side of the display area AA, and at least part of the conductive layer in the driving circuit layer is provided with a bending mark M1 in the first frame area B1.

[0164] In an example embodiment, in a direction perpendicular to the plane in which the display substrate is located, the driving circuit layer further includes a first conductive layer, a second conductive layer and a third conductive layer, the first conductive layer is located between the substrate and the second conductive layer, the second conductive layer is located between the first conductive layer and the third conductive layer, and the third conductive layer is located between the second conductive layer and the fifth conductive layer, and the bending mark can be located in at least one of the first conductive layer, the second conductive layer and the third conductive layer. For example, the bending mark M1 can be located in any one of the first conductive layer, the second conductive layer and the third conductive layer.

[0165] In an example embodiment, the material of the bending mark M1 can be metal, for example, the material of the bending mark M1 can be molybdenum.

[0166] In the example embodiment, the bending mark M1 can be arranged in one or more of the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer. Due to the design of the narrow frame of the display substrate, in the first frame area B1, the fourth conductive layer can not be provided with an insulating layer on the side away from the substrate. In the case where the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer are not provided with an insulating layer on the side away from the substrate, the bending mark M1 is not protected by the insulating layer (i.e., not protected by the inorganic layer) on the side away from the substrate, and the bending mark M1 is prone to corrosion. The packaging of the edge of the display substrate on the side close to the first frame area B1 can have a risk of signal loss (i.e., the bending mark M1 is prone to corrosion or wear). After the bending mark M1 is corroded, it is usually difficult to distinguish. In addition, the bending mark M1 can be arranged in the first semiconductor layer, and one or more of the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer need to be used as a substrate reflector. Since the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer are prone to corrosion due to the lack of protection of the insulating layer, the bending mark M1 in the first semiconductor layer also has a risk of signal loss (i.e., the bending mark M1 is prone to corrosion or wear). Therefore, the example embodiment of the present disclosure uses one or more of the first conductive layer, the second conductive layer, and the third conductive layer as the bending mark. Since the third conductive layer in the first frame area B1 is provided with an insulating layer on the side away from the substrate, in the case of a narrow frame, there is no risk of signal loss, and the corrosion resistance of the bending mark M1 can be improved.

[0167] In the example embodiment, the first frame area B1 is provided with a bending area a2, and the bending mark M1 can be located in the bending area a2.

[0168] In the example embodiment, the minimum distance L3 between the bending mark M1 and the adjacent signal line can be 5 microns to 20 microns, i.e., the bending mark M1 is provided with a clearance area of 5 microns to 20 microns adjacent to the signal line, which can prevent the bending mark M1 and the adjacent signal line from being separated.

[0169] In the example embodiment, the shape of the bending mark M1 is a cross or a T shape. The shape of the bending mark M1 is not limited thereto and can be well distinguished.

[0170] In the exemplary embodiments, in the structure in which the bending mark M1 is T-shaped: the size H1 of the bending mark M1 along the row direction X can be 120 microns to 170 microns, for example, the size H1 of the bending mark M1 along the row direction X can be 150 microns; the size H1 of the bending mark M1 along the column direction Y can be 80 microns to 120 microns, for example, the size H2 of the bending mark M1 along the column direction Y can be 100 microns; the bending mark M1 can include a first structure part M11 extending along the row direction X and a second structure part M12 extending along the column direction Y, the second structure part M12 is connected to the middle part of the first structure part M11 at one end close to the display area AA, the size H3 of the first structure part M11 along the column direction Y can be 20 microns to 80 microns, for example, the size H1 of the first structure part M11 along the column direction Y can be 50 microns; the size H4 of the second structure part M12 along the row direction X can be 20 microns to 80 microns, for example, the size H4 of the second structure part M12 along the row direction X can be 50 microns.

[0171] In the exemplary embodiments, as shown in FIG. 7e, in the column direction Y, at least one blocking dam C1 can be arranged on the side of the bending area a2 away from the display area AA, for example, the number of the blocking dam C1 can be four, the blocking dam C1 can extend along the row direction X, and a cutting line can be arranged on the side of the blocking dam C1 away from the bending area a2, so that the crack generated when cutting along the cutting line can not extend to the bending area a2. In the exemplary embodiments, the blocking dam C1 can be a groove of the insulating layer, a plurality of insulating layers can be arranged in the first bezel area B1 in the direction perpendicular to the plane where the display substrate is located, the insulating layer closest to the substrate side at the position corresponding to the blocking dam C1 cannot be etched through, and the insulating layer away from the substrate side can be etched through to form the blocking dam C1.

[0172] In the exemplary embodiments, as shown in FIG. 7c and FIG. 7e, in the row direction X, the third bezel area B3 and the fourth bezel area B4 can be arranged on both sides of the display area AA, the gate drive circuit GOA can be arranged in the third bezel area B3 and the fourth bezel area B4, in the first bezel area B1, on the side of the bending area a2 close to the display area AA, at least one of the first conductive layer, the second conductive layer, and the third conductive layer can be arranged in the direction perpendicular to the plane where the display substrate is located, and at least one of the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, and the anode conductive layer can be arranged in the direction perpendicular to the plane where the display substrate is located, at least one of the first conductive layer to the third conductive layer can be arranged to be electrically connected to the plurality of signal lines SL, one end of at least part of the signal lines SL is electrically connected to the gate drive circuit GOA, and the other end is electrically connected to the bonding electrode area a42, for example, electrically connected to the plurality of bonding pads of the bonding electrode area a42.

[0173] In an example embodiment, as shown in FIG. 7e, in the first bezel area B1, the bending area a2 is close to one side of the display area AA, at least one of the fourth conductive layer to the sixth conductive layer and the anode conductive layer is provided with the second power supply line VSS, and the second power supply line VSS can be formed by a multi-layer structure of the anode conductive layer and at least one of the fourth conductive layer to the sixth conductive layer, which can reduce the impedance of the second power supply line VSS and improve the display effect of the display substrate.

[0174] In an example embodiment, as shown in FIG. 7a, the plurality of sub-pixels can include multiple types, and the multiple types of sub-pixels can include at least first sub-pixels P1, second sub-pixels P2 and third sub-pixels P3. At least part of the first sub-pixels P1, the second sub-pixels P2 and the third sub-pixels P3 are first type sub-pixels PA1, and the other part are second type sub-pixels PA2.

[0175] In an example embodiment, one of the first sub-pixels P1, the second sub-pixels P2 and the third sub-pixels P3 is the second type sub-pixel PA2, and the other two are the first type sub-pixel PA1. Alternatively, one of the first sub-pixels P1, the second sub-pixels P2 and the third sub-pixels P3 can be the first type sub-pixel PA1, and the other two can be the second type sub-pixel PA2.

[0176] In an example embodiment, as shown in FIG. 7a, the anodes of the plurality of second type sub-pixels PA2 electrically connected with the pixel driving circuit of the i-th row at least partially overlap the orthographic projection of the pixel driving circuit of the i-1-th row on the substrate; or the anodes of the plurality of second type sub-pixels PA2 electrically connected with the pixel driving circuit of the i-th row at least partially overlap the orthographic projection of the pixel driving circuit of the i+1-th row on the substrate; i is a positive integer greater than 1.

[0177] The anodes of the plurality of first type sub-pixels PA1 electrically connected with the pixel driving circuit of the i-th row at least partially overlap the orthographic projection of the pixel driving circuit of the i-th row on the substrate.

[0178] In the example embodiment, the first type of sub-pixel PA1 can include the first sub-pixel P1 and the third sub-pixel P3, and the second type of sub-pixel PA2 can include the second sub-pixel P2; as shown in FIG. 7a and FIG. 22c, the plurality of anodes form first anode columns R1 and second anode columns R2 arranged alternately along the row direction X, in the same first anode column R1, the anodes of the first sub-pixel P1 and the third sub-pixel P3 are arranged alternately along the column direction Y, and in the same second anode column R2, the anodes of the plurality of second sub-pixels P2 are arranged alternately along the column direction Y; the plurality of anodes form first anode rows K1 and second anode rows K2 arranged alternately along the column direction Y, in the same first anode row K1, the anodes of the first sub-pixel P1 and the third sub-pixel P3 are arranged alternately along the row direction X, and in the same second anode row K2, the anodes of the plurality of second sub-pixels P2 are arranged alternately along the row direction X.

[0179] In the example embodiment, the first type of sub-pixel PA1 can include the first sub-pixel P1 and the second sub-pixel P2, and the second type of sub-pixel PA2 can include the third sub-pixel P3; or, the first type of sub-pixel PA1 includes the second sub-pixel P2 and the third sub-pixel P3, and the second type of sub-pixel PA2 includes the first sub-pixel P1.

[0180] In an example embodiment, the pixel driving circuit can be 8T1C, 7T1C, 6T1C, etc. as shown in FIG. 8, which is an equivalent circuit diagram of the pixel driving circuit in one sub-pixel corresponding to the display substrate in FIGS. 7a and 7b. The pixel driving circuit shown in FIG. 8 is an 8T1C structure. As shown in FIG. 8, the pixel driving circuit can include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and can be connected with eleven signal lines (data signal line DL, first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, emission signal line EML, first initial signal line Vinit1, second initial signal line Vinit2, third initial signal line Vinit3, first power line VDD and second power line VSS). The first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit, the second power line VSS can be configured to provide a constant second voltage signal to the pixel driving circuit, and the first voltage signal is greater than the second voltage signal. The first scan signal line S1 can be configured to provide a first scan signal to the pixel driving circuit, the second scan signal line S2 can be configured to provide a second scan signal to the pixel driving circuit, the third scan signal line S3 can be configured to provide a third scan signal to the pixel driving circuit, the fourth scan signal line S4 can be configured to provide a fourth scan signal to the pixel driving circuit, the data signal line DL can be configured to provide a data signal to the pixel driving circuit, and the emission control line EML can be configured to provide an emission control signal to the pixel circuit. In an actual layout structure, different signal lines, transfer lines between different signal lines, and the storage capacitor C can be realized by different metals such as polysilicon, titanium aluminum titanium, and molybdenum metal wiring. Among them, the first scan signal line S1 to the fourth scan signal line S4 and the emission signal line EML can be signal lines extending in the row direction X in the display area AA, the data signal line and the first power line VDD can be signal lines extending in the column direction Y in the display area AA, the signals of the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can be provided to the display area AA by the fourth frame area B4 and the third frame area B3, and the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 are signal lines extending in the row direction X in the display area AA (or are signal lines extending in the column direction Y, or are in a grid structure), and the signals of the first scan signal line S1 to the fourth scan signal line S4 and the emission signal line EML can be provided by the gate drive circuit GOA located in the third frame area B3 and the fourth frame area B4; the second power line VSS can form a signal loop by evaporating the cathode.

[0181] As shown in FIG. 8, the first electrode of the first transistor T1 is connected with the first initial signal line Vinit1, the second electrode of the first transistor T1 is connected with the third node N3, and the control electrode of the first transistor T1 is connected with the first scan signal line S1; the first electrode of the second transistor T2 is connected with the first node N1, the second electrode of the second transistor T2 is connected with the third node N3, and the control electrode of the second transistor T2 is connected with the fourth scan signal line S4; the first electrode of the third transistor T3 is connected with the second node N2, the second electrode of the third transistor T3 is connected with the third node N3, and the control electrode of the third transistor T3 is connected with the first node N1; the first electrode of the fourth transistor T4 is connected with the data signal line DL, the second electrode of the fourth transistor T4 is connected with the second node N2, and the control electrode of the fourth transistor T4 is connected with the second scan signal line S2; the first electrode of the fifth transistor T5 is connected with the first power supply line VDD, the second electrode of the fifth transistor T5 is connected with the second node N2, and the control electrode of the fifth transistor T5 is connected with the light-emitting signal line EML; the first electrode of the sixth transistor T6 is connected with the third node N3, the second electrode of the sixth transistor T6 is connected with the fourth node N4, and the control electrode of the sixth transistor T6 is connected with the light-emitting signal line EML; the first electrode of the seventh transistor T7 is connected with the second initial signal line Vinit2, the second electrode of the seventh transistor T7 is connected with the fourth node N4, and the control electrode of the seventh transistor T7 is connected with the third scan signal line S3; the first electrode of the eighth transistor T8 is connected with the third initial signal line Vinit3, the second electrode of the eighth transistor T8 is connected with the second node N2, and the control electrode of the eighth transistor T8 is connected with the third scan signal line S3; the first plate of the storage capacitor C is connected with the first node N1, and the second plate of the storage capacitor C is connected with the first power supply line VDD. The fourth node in the pixel driving circuit shown in FIG. 8 is connected with the anode of the light-emitting device (for example, the light-emitting device can be a light-emitting diode EL). In the embodiment of the present disclosure, the length of the anode connecting electrode 83 in the second type of sub-pixel PA2 is increased, mainly to increase the parasitic capacitance of the fourth node N4.

[0182] In the example embodiment, the first transistor T1, the third transistor T3 to the eighth transistor T8 are low temperature poly-silicon transistors (may be referred to as low temperature poly-silicon thin film transistors), and the second transistor T2 is an oxide transistor (may be referred to as an oxide thin film transistor). The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. By integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate to form a low temperature poly-oxide (LTPS+Oxide) display substrate, the advantages of both can be utilized to achieve low frequency driving, reduce power consumption, and improve display quality.

[0183] In the example embodiment, the row direction X can be referred to as the first direction, and the column direction Y can be referred to as the second direction.

[0184] The preparation process of the display substrate is exemplarily described below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials or transparent conductive materials, and includes coating organic materials, mask exposure and development, etc. for organic materials. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material made on a substrate (or substrate) by deposition, coating or other processes. If the "thin film" does not need to be patterned during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are disposed in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the example embodiment of the present disclosure, "the orthographic projection of B is located within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0185] In the example embodiment, taking 2 sub-pixels (1 sub-pixel row and 2 sub-pixel columns) in the display area (AA) as an example, the preparation process of one kind of display substrate can include the following operations.

[0186] (101) A substrate is prepared on a glass carrier. In an exemplary embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a bonding layer, a second flexible material layer, and a second inorganic material layer. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the like, and the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), and the like, for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also referred to as barrier layers, and the material of the bonding layer can be amorphous silicon (a-si). In an exemplary embodiment, taking the laminated structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the preparation process can include: first coating a layer of polyimide on the glass carrier, and after curing to form a film, a first flexible material (PI1) layer is formed; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and after curing to form a film, a second flexible material (PI2) layer is formed; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, and the preparation of the substrate is completed.

[0187] (102) A shielding layer pattern is formed. In an exemplary embodiment, forming the shielding layer pattern can include: depositing a conductive film of the shielding layer on the substrate, patterning the conductive film of the shielding layer by a patterning process, and forming the shielding layer pattern on the substrate, as shown in FIG. 9, which is a planar structure diagram of the shielding layer pattern in two sub-pixels.

[0188] In the example embodiment, the shielding layer pattern of at least part of the sub-pixels can include a first shielding structure 11, a second shielding structure 12, a third shielding structure 13, and a shielding block 14. The shielding block 14 can be in a rectangular shape, and the corners of the rectangular shape can be chamfered. The first shielding structure 11 can be in a strip shape extending along the first direction X, the first shielding structure 11 is arranged on one side of the shielding block 14 in the first direction X and connected with the shielding block 14. The second shielding structure 12 can be in a zigzag shape extending along the second direction Y, the second shielding structure 12 is arranged on one side of the shielding block 14 in the opposite direction of the second direction Y and connected with the shielding block 14. The third shielding structure 13 can be in a zigzag shape or a strip shape extending along the second direction Y, the third shielding structure 13 is arranged on one side of the shielding block 14 in the second direction Y and connected with the shielding block 14.

[0189] In the example embodiment, the second shielding structure 12 is provided with a first spacer structure DP1 and a second spacer structure DP2, and the areas corresponding to the first spacer structure DP1 and the second spacer structure DP2 in the subsequently formed film layer structure are provided with vias. The first spacer structure DP1 and the second spacer structure DP2 can improve the local flatness, for example, the flatness of the via position.

[0190] In the example embodiment, in at least part of the sub-pixels, the first shielding structure 11 of one of the sub-pixels is connected with the shielding block 14 of the adjacent sub-pixel in the first direction X, so that at least part of the shielding layers in one sub-pixel row are connected as a whole to form an interconnected whole structure.

[0191] In the example embodiment, in at least part of the sub-pixels, the second shielding structure 12 of one of the sub-pixels is connected with the third shielding structure 13 of the adjacent sub-pixel in the second direction Y, so that at least part of the shielding layers in one sub-pixel column are connected as a whole to form an interconnected whole structure.

[0192] In the example embodiment, the shielding layers in the sub-pixel rows and the sub-pixel columns are connected as a whole to form a grid-shaped structure, which can ensure that the shielding layers in the display substrate have the same potential, and is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0193] In exemplary embodiments, the shielding layer in the Nth column and the shielding layer in the N+1th column can be mirror symmetrical relative to the first center line, the shielding layer in the N+1th column and the shielding layer in the N+2th column can be mirror symmetrical relative to the second center line, the shielding layer in the N+2th column and the shielding layer in the N+3th column can be mirror symmetrical relative to the third center line, and the first center line, the second center line and the third center line can be straight lines extending along the second direction Y between adjacent sub-pixel columns, for example, the first center line can be a straight line extending along the second direction Y between the Nth column and the N+1th column of sub-pixels, the second center line can be a straight line extending along the second direction Y between the N+1th column and the N+2th column of sub-pixels, and the third center line can be a straight line extending along the second direction Y between the N+2th column and the N+3th column of sub-pixels.

[0194] In exemplary embodiments, the shielding layers in the plurality of sub-pixel rows can have the same shape.

[0195] In some exemplary embodiments, the shielding layer pattern can not be provided, i.e., the first semiconductor layer pattern described below can be formed directly on the substrate.

[0196] (103) forming a first semiconductor layer pattern. In exemplary embodiments, forming the first semiconductor layer pattern can include: sequentially depositing a first insulating thin film and a first semiconductor thin film on the substrate on which the aforementioned pattern is formed or on the substrate, patterning the first semiconductor thin film through a patterning process, forming a first insulating layer covering the shielding layer pattern or provided on the substrate, and a first semiconductor layer pattern provided on the first insulating layer, as shown in FIGS. 10a to 10c, FIG. 10a is a planar structural diagram of two sub-pixels after forming the first semiconductor layer, FIG. 10b is a planar schematic diagram of the first semiconductor layer in FIG. 10a, and FIG. 10c is a planar structural diagram of four sub-pixels after forming the first semiconductor layer.

[0197] In exemplary embodiments, the first semiconductor layer pattern of at least part of the sub-pixels can include an active layer 21 of the first transistor T1, an active layer 23 of the third transistor T3 to an active layer 28 of the eighth transistor T8, and the active layer 23 of the third transistor T3 to the active layer 27 of the seventh transistor T7 can be an integrated structure connected to each other.

[0198] In the exemplary embodiments, in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the same side of the active layer 23 of the third transistor T3, the active layer 21 of the first transistor T1 and the active layer 26 of the sixth transistor T6 are located on the other side of the active layer 23 of the third transistor T3, and the active layer 28 of the eighth transistor T8 is located between the active layer 25 of the fifth transistor T5 and the active layer 27 of the seventh transistor T7; in the second direction Y, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on both sides of the active layer 23 of the third transistor T3, and the active layer 25 of the fifth transistor T5, the active layer 26 of the sixth transistor T6, the active layer 27 of the seventh transistor T7, and the active layer 28 of the eighth transistor T8 are located on the same side of the active layer 23 of the third transistor T3, the active layer 27 of the seventh transistor T7 is located on the side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3, the active layer 28 of the eighth transistor T8 is located on the side of the active layer 23 of the third transistor T3 away from the active layer 24 of the fourth transistor T4, and the active layer 21 of the first transistor T1 is located on the side of the active layer 23 of the third transistor T3 away from the active layer 26 of the sixth transistor T6.

[0199] In the exemplary embodiments, taking the sub-pixel in the Mth row and the Nth column as an example: in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N+1th column, and the active layer 21 of the first transistor T1 and the active layer 26 of the sixth transistor T6 are located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N-1th column; in the second direction Y, the active layer 24 of the fourth transistor T4 is located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the M+1th row, the active layer 25 of the fifth transistor T5, the active layer 26 of the sixth transistor T6, the active layer 27 of the seventh transistor T7, and the active layer 28 of the eighth transistor T8 are located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the M-1th row, the active layer 27 of the seventh transistor T7 is located on the side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3, the active layer 28 of the eighth transistor T8 is located on the side of the active layer 23 of the third transistor T3 away from the active layer 24 of the fourth transistor T4, and the active layer 21 of the first transistor T1 is located on the side of the active layer 23 of the third transistor T3 away from the active layer 26 of the sixth transistor T6.

[0200] In the example embodiment, the active layer 23 of the third transistor T3 can be in the shape of an "Ω", the active layers 21 of the first transistor T1, 24 of the fourth transistor T4, 26 of the sixth transistor T6 and 28 of the eighth transistor T8 can be in the shape of an "I", the active layer 25 of the fifth transistor T5 can be in the shape of a "Z", and the active layer 27 of the seventh transistor T7 can be in the shape of an "L".

[0201] In the example embodiment, the active layer of at least part of the transistor can include a first region, a second region and a channel region between the first region and the second region. In the example embodiment, the first region 23-1 of the active layer 23 of the third transistor T3 can serve as the second region 24-2 of the active layer 24 of the fourth transistor T4 and the second region 25-2 of the active layer 25 of the fifth transistor T5, the second region 23-2 of the active layer 23 of the third transistor T3 can serve as the first region 26-1 of the active layer 26 of the sixth transistor T6, the second region 26-2 of the active layer 26 of the sixth transistor T6 can serve as the second region 27-2 of the active layer 27 of the seventh transistor T7, and the first region 21-1 and the second region 21-2 of the active layer 21 of the first transistor T1, the first region 24-1 of the active layer 24 of the fourth transistor T4, the first region 25-1 of the active layer 25 of the fifth transistor T5, the first region 27-1 of the active layer 27 of the seventh transistor T7, the first region 28-1 and the second region 28-2 of the active layer 28 of the eighth transistor T8 can be separately provided.

[0202] In the example embodiment, the orthographic projection of the active layer 23 of the third transistor T3 on the substrate can at least partially overlap with the orthographic projection of the shielding block 14 on the substrate. In the example embodiment, the orthographic projection of the channel region of the active layer 23 of the third transistor T3 on the substrate is within the range of the orthographic projection of the shielding block 14 on the substrate.

[0203] In the example embodiment, as shown in FIG. 10c, the first region 25-1 of the active layer 25 of the fifth transistor T5 of the Nth column and the first region 25-1 of the active layer 25 of the fifth transistor T5 of the N-1th column are connected to each other, and the first region 25-1 of the active layer 25 of the fifth transistor T5 of the N+1th column and the first region 25-1 of the active layer 25 of the fifth transistor T5 of the N+2th column are connected to each other. In the example embodiment, since the first region of the active layer of the fifth transistor T5 in the sub-pixel is connected to the first power supply line formed subsequently, by forming the first regions of the active layers of the fifth transistors T5 of adjacent sub-pixels into an integrated structure connected to each other, it can be ensured that the first electrodes of the fifth transistors T5 of adjacent sub-pixels have substantially the same potential, which is conducive to improving the uniformity of the panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0204] In the example embodiment, the first semiconductor layer of the Nth column and the first semiconductor layer of the N+1th column can be mirror symmetrical relative to the first center line, the first semiconductor layer of the N+1th column and the first semiconductor layer of the N+2th column can be mirror symmetrical relative to the second center line, and the first semiconductor layer of the N+2th column and the first semiconductor layer of the N+3th column can be mirror symmetrical relative to the third center line.

[0205] In the example embodiment, the first semiconductor layer can be polycrystalline silicon (p-Si), i.e., the first transistor T1, the third transistor T3 to the eighth transistor T8 can be LTPS thin film transistors. In the example embodiment, the patterning of the first semiconductor thin film through the patterning process can include: first forming an amorphous silicon (a-si) thin film on the first insulating thin film, performing dehydrogenation treatment on the amorphous silicon thin film, performing crystallization treatment on the amorphous silicon thin film after the dehydrogenation treatment, and forming a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form a first semiconductor layer pattern.

[0206] (104) Forming a first conductive layer pattern. In the example embodiment, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the first conductive thin film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 11a and 11b, FIG. 11a is a schematic diagram of the planar structure of two sub-pixels after the formation of the first conductive layer, and FIG. 11b is a planar schematic diagram of the first conductive layer in FIG. 11a. In the example embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0207] In the example embodiment, the first conductive layer pattern can at least include: a first scan signal line 31, a second scan signal line 32, a first plate 33 of a storage capacitor, a light-emitting control line 34, and a third scan signal line 35. The main body portion of the second scan signal line 32 can extend along the first direction X, the first scan signal line 31, the light-emitting control line 34, and the third scan signal line 35 can be polyline structures or strip-shaped structures extending along the first direction X, and the first scan signal line 31, the second scan signal line 32, the first plate 33 of the storage capacitor, the light-emitting control line 34, and the third scan signal line 35 can be arranged along the second direction Y in the same sub-pixel.

[0208] In the exemplary embodiments, in the second direction Y, the second scan signal line 32 and the light emission control line 34 can be located on both sides of the first plate 33 of the storage capacitor, the first scan signal line 31 is located on the side of the second scan signal line 32 away from the first plate 33 of the storage capacitor, and the third scan signal line 35 is located on the side of the light emission control line 34 away from the first plate 33 of the storage capacitor. For example, in the second direction, the first scan signal line 31, the second scan signal line 32, the first plate 33 of the storage capacitor, the light emission control line 34, and the third scan signal line 35 are arranged in sequence.

[0209] For example, taking the Mth row and the Nth column sub-pixel as an example, in the second direction Y, the second scan signal line 32 can be located on the side of the first plate 33 of the storage capacitor in the sub-pixel close to the (M-1)th row sub-pixel; the light emission control line 34 can be located on the side of the first plate 33 of the storage capacitor in the sub-pixel close to the (M+1)th row sub-pixel; the first scan signal line 31 can be located on the side of the second scan signal line 32 close to the (M-1)th row sub-pixel; and the third scan signal line 35 can be located on the side of the light emission control line 34 close to the (M+1)th row sub-pixel.

[0210] In the exemplary embodiments, the first plate 33 can be located between the light emission control line 34 and the second scan signal line 32, the shape of the first plate 33 can be a rectangle, the corners of the rectangle can be chamfered, and the orthographic projection of the first plate 33 on the substrate and the orthographic projection of the active layer of the third transistor T3 on the substrate have an overlapping area. In the exemplary embodiments, the first plate 33 can serve as one plate of the storage capacitor and the control electrode of the third transistor T3.

[0211] In the exemplary embodiments, the area where the light emission control line 34 (i.e., the light emission signal line EML in FIG. 8) overlaps with the active layer of the fifth transistor T5 can serve as the control electrode of the fifth transistor T5, the area where the light emission control line 34 overlaps with the active layer of the sixth transistor T6 can serve as the control electrode of the sixth transistor T6, the area where the first scan signal line 31 (i.e., the first scan signal line S1 in FIG. 8) overlaps with the active layer of the first transistor T1 can serve as the control electrode of the first transistor T1, the area where the second scan signal line 32 (i.e., the second scan signal line S2 in FIG. 8) overlaps with the active layer of the fourth transistor T4 can serve as the control electrode of the fourth transistor T4, the area where the third scan signal line 35 (i.e., the third scan signal line S3 in FIG. 8) overlaps with the active layer of the seventh transistor T7 can serve as the control electrode of the seventh transistor T7, and the area where the third scan signal line 35 overlaps with the active layer of the eighth transistor T8 can serve as the control electrode of the eighth transistor T8.

[0212] In the example embodiment, the third pad structure DP3 is arranged on the first scan signal line 31, and the third pad structure DP3 at least partially overlaps the orthographic projection of the first pad structure DP3 on the base; the fourth pad structure DP4 is arranged on the second scan signal line 32, and the fourth pad structure DP4 at least partially overlaps the orthographic projection of the second pad structure DP2 on the base. In the subsequently formed film layer structure, the regions corresponding to the third pad structure DP3 and the fourth pad structure DP4 are provided with vias, and the third pad structure DP3 and the fourth pad structure DP4 can improve the local flatness, for example, the flatness of the via positions.

[0213] In the example embodiment, after the first conductive layer pattern is formed, the semiconductor layer can be subjected to a conductorization treatment by using the first conductive layer as a shield, and the semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1, the third transistor T3, and the eighth transistor T8, and the semiconductor layer in the region not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the active layer 21 of the first transistor T1, the active layer 23 of the third transistor T3, and the active layer 28 of the eighth transistor T8 are all conductorized.

[0214] (105) Forming a second conductive layer pattern. In the example embodiment, forming the second conductive layer pattern can include: sequentially depositing a third insulating film and a second conductive film on the base on which the aforementioned pattern is formed, patterning the second conductive film by using a patterning process, forming a third insulating layer covering the first conductive layer, and forming a second conductive layer pattern on the third insulating layer, as shown in FIGS. 12a to 12c, FIG. 12a is a planar structural diagram of two sub-pixels after the second conductive layer is formed, FIG. 12b is a planar schematic diagram of the second conductive layer in FIG. 12a, and FIG. 12c is a planar structural diagram of four sub-pixels after the second conductive layer is formed. In the example embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0215] In the example embodiment, the second conductive layer pattern at least includes: a first initial signal line 41, a first shielding line 42, and a second plate 43 of a storage capacitor, the main body part of the first initial signal line 41 (i.e., the first initial signal line Vinit1 in FIG. 8) and the first shielding line 42 can extend along the first direction X. The second plate 43 of the storage capacitor serves as the other plate of the storage capacitor. In the second direction Y, the first shielding line 42 is located between the first initial signal line 41 and the second plate 43 of the storage capacitor, for example, in the same sub-pixel, the first initial signal line 41, the first shielding line 42, and the second plate 43 of the storage capacitor (i.e., the storage capacitor C in FIG. 8) can be arranged in sequence along the second direction Y.

[0216] In the example embodiment, the first shielding line 42 is configured to serve as a shielding layer of the second transistor T2, shielding the channel of the second transistor T2 and ensuring the electrical performance of the oxide transistor T2. In the example embodiment, the signal of the first shielding line 42 can be the same as the signal of the fourth scan signal line 51 formed later, that is, the first shielding line 42 is connected in parallel with the fourth scan signal line 51 formed later, both of which are connected to the same signal source, so that the first shielding line 42 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the second transistor T2, forming a double-gate structure of the second transistor T2.

[0217] In the example embodiment, the second plate 43 can have a rectangular shape, and the corners of the rectangular shape can be chamfered. The second plate 43 has an overlapping area with the first plate 33 in the orthographic projection on the substrate, and the first plate 33 and the second plate 43 form a storage capacitor of the pixel driving circuit. The second plate 43 is provided with an opening 44, which can be located in the middle of the second plate 43. The opening 44 can be rectangular, so that the second plate 43 forms a ring structure. The opening 44 exposes the third insulating layer covering the first plate 33, and the orthographic projection of the first plate 33 on the substrate contains the orthographic projection of the opening 44 on the substrate. In the example embodiment, the opening 44 is configured to accommodate the thirteenth via formed later, and the ninth via is located in the opening 44 and exposes the first plate 33, so that the first electrode of the second transistor T2 formed later is connected to the first plate 33.

[0218] In the example embodiment, as shown in FIG. 12c, the second plate 43 of the Nth column and the second plate 43 of the N-1th column are connected to each other, and the second plate 43 of the N+1th column and the second plate 43 of the N+2th column are connected to each other. In the example embodiment, since the second plate 43 in the sub-pixel is connected to the first power line formed later, by forming the second plates 43 of adjacent sub-pixels into an integrated structure connected to each other, it can be ensured that the second plates 43 of adjacent sub-pixels have substantially the same potential, which is conducive to improving the uniformity of the panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0219] (106) Forming a second semiconductor layer pattern. In the example embodiment, forming the second semiconductor layer pattern can include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film by a patterning process, forming a fourth insulating layer covering the substrate, and forming a second semiconductor layer pattern on the fourth insulating layer, as shown in FIGS. 13a and 13b, FIG. 13a is a plan view of two sub-pixels after forming the second semiconductor layer, and FIG. 13b is a plan view of the second semiconductor layer in FIG. 13a.

[0220] In an example embodiment, the second semiconductor layer pattern in at least part of the sub-pixel comprises at least an active layer 22 of a second transistor T2.

[0221] In an example embodiment, the active layer 22 of the second transistor T2 can be in an "L" shape, and a first region 22-1 and a second region 22-2 of the active layer 22 of the second transistor T2 can be separately provided.

[0222] In an example embodiment, the second semiconductor layer of the Nth column and the second semiconductor layer of the N+1th column can be mirror-symmetrical relative to a first center line, the second semiconductor layer of the N+1th column and the second semiconductor layer of the N+2th column can be mirror-symmetrical relative to a second center line, and the second semiconductor layer of the N+2th column and the second semiconductor layer of the N+3th column can be mirror-symmetrical relative to a third center line.

[0223] In an example embodiment, the shape of the second semiconductor layer in the plurality of sub-pixel rows can be the same.

[0224] In an example embodiment, in a first direction X, the active layer 21 of the first transistor T1 and the active layer 22 of the second transistor T2 are located on the same side of the active layer 23 of the third transistor T3 in a plane in which the display substrate is located; in a second direction Y, the active layer 22 of the second transistor T2 is located on a side of the active layer 23 of the third transistor T3 away from the active layer 26 of the sixth transistor T6, for example, in the second direction Y, the active layer 22 of the second transistor T2 can be located between the active layer 21 of the first transistor T1 and the active layer 26 of the sixth transistor T6.

[0225] In an example embodiment, taking the sub-pixel of the Mth row and the Nth column as an example: in the first direction X, the active layer 21 of the first transistor T1, the active layer 22 of the second transistor T2, and the active layer 26 of the sixth transistor T6 are located on a side of the active layer 23 of the third transistor T3 away from the sub-pixel of the N-1th column; in the second direction Y, the active layer 22 of the second transistor T2 is located on a side of the active layer 23 of the third transistor T3 away from the sub-pixel of the M+1th row.

[0226] In an example embodiment, the second semiconductor layer can employ an oxide, i.e., the second transistor T2 is an oxide thin film transistor. In an example embodiment, the oxide can be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride oxide (InGaZnON), zinc oxide (ZnO), zinc nitride oxide (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfur oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the second semiconductor thin film can employ indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon. Since the leakage current of the IGZO TFT is relatively small, the second transistor T2 employs an N-type transistor, which can avoid the leakage of the first node N1 during the light emitting stage.

[0227] (107) Forming a third conductive layer pattern. In an example embodiment, forming the third conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a fifth insulating thin film and a third conductive thin film, patterning the third conductive thin film by using a patterning process, forming a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIGS. 14a and 14b, FIG. 14a is a plan view of the two sub-pixels after the third conductive layer is formed, and FIG. 14b is a plan view of the third conductive layer in FIG. 14a. In an example embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0228] In an example embodiment, the third conductive layer pattern at least includes: a fourth scan signal line 51, a third initial signal line 52 (i.e., the third initial signal line Vinit3 in FIG. 8), and a second initial signal line 53. The fourth scan signal line 51, the third initial signal line 52, and the second initial signal line 53 can be in the shape of a polyline or a strip extending along the first direction X, and can be arranged in the second direction Y in the same sub-pixel row.

[0229] In an example embodiment, the region where the fourth scan signal line 51 (i.e., the fourth scan signal line S4 in FIG. 8) overlaps with the active layer 22 of the second transistor T2 serves as the control electrode of the second transistor T2.

[0230] In the example embodiment, the fourth scan signal line 51 and the first shielding line 42 at least partially overlap in the orthographic projection on the substrate; the signal of the first shielding line 42 and the fourth scan signal line 51 can be the same, that is, both are connected in parallel and connected to the same signal source, so that the first shielding line 42 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the second transistor T2, forming a double-gate structure of the second transistor T2. In the example embodiment, in one row of sub-pixels, the second initial signal line 53 can be located in the sub-pixels of the adjacent row, and the second initial signal line 53 can at least partially overlap with the first scan signal line 31 in the orthographic projection on the substrate in the sub-pixels of the adjacent row, saving space of the display substrate. Taking the Mth row of sub-pixels as an example: the second initial signal line 53 of the Mth row of sub-pixels can be located in the M+1th row of sub-pixels, and at least partially overlap with the first scan signal line 31 in the orthographic projection on the substrate in the M+1th row of sub-pixels.

[0231] (108) Forming a sixth insulating layer pattern. In the example embodiment, forming the sixth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a sixth insulating thin film, and patterning the sixth insulating thin film by a patterning process to form a sixth insulating layer covering the third conductive layer, the sixth insulating layer being provided with a plurality of vias, as shown in FIG. 15, which is a planar structure diagram of two sub-pixels after the sixth insulating layer is formed.

[0232] In the example embodiment, the plurality of vias in at least part of the sub-pixels at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0233] In the example embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the active layer 21 of the first transistor T1 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the first via V1 are etched away, exposing the surface of the first region 21-1 of the active layer 21 of the first transistor T1. The first via V1 is configured to allow the first electrode of the first transistor T1 formed subsequently to be connected to the active layer 21 of the first transistor T1 through the via.

[0234] In the example embodiment, the second via V2 is located within the range of the orthogonal projection of the active layer 21 of the first transistor T1 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region 21-2 of the active layer 21 of the first transistor T1. The second via V2 is configured to enable the second electrode of the subsequently formed first transistor T1 to connect with the active layer 21 of the first transistor T1 through the via.

[0235] In the example embodiment, the third via V3 is located within the range of the orthogonal projection of the active layer 22 of the second transistor T2 on the substrate, the sixth insulating layer and the fifth insulating layer within the third via V3 are etched away, exposing the surface of the first region 22-1 of the active layer 22 of the second transistor T2. The third via V3 is configured to enable the first electrode of the subsequently formed second transistor T2 to connect with the active layer 22 of the second transistor T2 through the via.

[0236] In the example embodiment, the fourth via V4 is located within the range of the orthogonal projection of the active layer 22 of the second transistor T2 on the substrate, the sixth insulating layer and the fifth insulating layer within the fourth via V4 are etched away, exposing the surface of the second region 22-2 of the active layer 22 of the second transistor T2. The fourth via V4 is configured to enable the second electrode of the subsequently formed second transistor T2 to connect with the active layer 22 of the second transistor T2 through the via.

[0237] In the example embodiment, the fifth via V5 is located within the range of the orthogonal projection of the active layer 24 of the fourth transistor T4 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the fourth via V4 are etched away, exposing the first region 24-1 of the active layer 24 of the fourth transistor T4. The fifth via V5 is configured to enable the first electrode of the subsequently formed fourth transistor T4 to connect with the active layer 24 of the fourth transistor T4 through the via.

[0238] In the example embodiment, the sixth via V6 is located within the range of the orthogonal projection of the active layer 25 of the fifth transistor T5 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the first region 25-1 of the active layer 25 of the fifth transistor T5. The sixth via V6 is configured to enable the first electrode of the subsequently formed fifth transistor T5 to connect with the active layer 25 of the fifth transistor T5 through the via.

[0239] In an example embodiment, the seventh via V7 has a footprint on the substrate within a footprint of the active layer 25 of the fifth transistor T5 on the substrate, the sixth, fifth, fourth, third and second insulating layers within the seventh via V7 are etched away, exposing a surface of the second region 25-2 of the active layer 25 of the fifth transistor T5 (also the first region of the active layer 23 of the third transistor T3, the second region 24-2 of the active layer 24 of the fourth transistor T4). The seventh via V7 is configured to allow a second electrode of the fifth transistor T5 to be formed subsequently to be connected to the active layer 25 of the fifth transistor T5 through the via, and to allow a first electrode of the third transistor T3 to be formed subsequently to be connected to the active layer 23 of the third transistor T3 through the via, and to allow a second electrode of the fourth transistor T4 to be formed subsequently to be connected to the active layer 24 of the fourth transistor T4 through the via.

[0240] In an example embodiment, the eighth via V8 has a footprint on the substrate within a footprint of the active layer 26 of the sixth transistor T6 on the substrate, the sixth, fifth, fourth, third and second insulating layers within the sixth via V6 are etched away, exposing a surface of the first region 26-1 of the active layer 26 of the sixth transistor T6 (also the second region of the active layer 23 of the third transistor T3, the second region of the active layer 27 of the seventh transistor T7). The eighth via V8 is configured to allow a first electrode of the sixth transistor T6 to be formed subsequently to be connected to the active layer 26 of the sixth transistor T6 through the via, and to allow a second electrode of the third transistor T3 to be formed subsequently to be connected to the active layer 23 of the third transistor T3 through the via, and to allow a second electrode of the seventh transistor T7 to be formed subsequently to be connected to the active layer 27 of the seventh transistor T7 through the via.

[0241] In an example embodiment, the ninth via V9 has a footprint on the substrate within a footprint of the active layer 26 of the sixth transistor T6 on the substrate, the sixth, fifth, fourth, third and second insulating layers within the ninth via V9 are etched away, exposing a surface of the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7). The ninth via V9 is configured to allow a second electrode of the sixth transistor T6 to be formed subsequently to be connected to the active layer 26 of the sixth transistor T6 through the via, and to allow a second electrode of the seventh transistor T7 to be formed subsequently to be connected to the active layer 27 of the seventh transistor T7 through the via.

[0242] In the example embodiment, the tenth via V10 is located within the range of the orthogonal projection of the active layer 27 of the seventh transistor T7 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via V10 are etched to expose the surface of the first region 27-1 of the active layer 27 of the seventh transistor T7. The tenth via V10 is configured to connect the first electrode of the seventh transistor T7 to be formed subsequently to the active layer 27 of the seventh transistor T7 through the via.

[0243] In the example embodiment, the eleventh via V11 is located within the range of the orthogonal projection of the active layer 28 of the eighth transistor T8 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the eleventh via V11 are etched to expose the surface of the first region 28-1 of the active layer 28 of the eighth transistor T8. The eleventh via V11 is configured to connect the first electrode of the eighth transistor T8 to be formed subsequently to the active layer 28 of the eighth transistor T8 through the via.

[0244] In the example embodiment, the twelfth via V12 is located within the range of the orthogonal projection of the active layer 28 of the eighth transistor T8 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the twelfth via V12 are etched to expose the surface of the second region 28-2 of the active layer 28 of the eighth transistor T8. The twelfth via V12 is configured to connect the second electrode of the eighth transistor T8 to be formed subsequently to the active layer 28 of the eighth transistor T8 through the via.

[0245] In the example embodiment, the thirteenth via V13 is located within the range of the orthogonal projection of the opening 44 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer within the thirteenth via V13 are etched to expose the surface of the first electrode plate 33. The thirteenth via V13 is configured to connect the first electrode of the second transistor T2 to be formed subsequently to the first electrode plate 33 through the via.

[0246] In the example embodiment, the fourteenth via V14 is located within the range of the orthogonal projection of the second electrode plate 43 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer within the fourteenth via V14 are etched to expose the surface of the second electrode plate 43. The fourteenth via V14 is configured to connect the fifth connection electrode to be formed subsequently to the second electrode plate 43 through the via. In the example embodiment, the fourteenth via V14 as the power supply via can include multiple, and the multiple fourteenth vias V14 can be arranged in sequence along the second direction Y or the first direction X to increase the connection reliability of the first power supply connection line to the second electrode plate 43.

[0247] In the exemplary embodiment, the orthogonal projection of the fifteenth via V15 on the substrate is within the range of the orthogonal projection of the first initial signal line 41 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer in the fifteenth via V15 are etched away, exposing the surface of the first initial signal line 41. The fifteenth via V15 is configured to connect the first electrode of the first transistor T1 formed subsequently with the first initial signal line 41 through the via.

[0248] In the exemplary embodiment, the orthogonal projection of the sixteenth via V16 on the substrate is within the range of the orthogonal projection of the third initial signal line 52 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer in the sixteenth via V16 are etched away, exposing the surface of the third initial signal line 52. The sixteenth via V16 is configured to connect the eighth connecting electrode 68 formed subsequently with the third initial signal line 52 through the via.

[0249] In the exemplary embodiment, the orthogonal projection of the seventeenth via V17 on the substrate is within the range of the orthogonal projection of the second initial signal line 53 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer in the seventeenth via V17 are etched away, exposing the surface of the second initial signal line 53. The seventeenth via V17 is configured to connect the ninth connecting electrode 69 formed subsequently with the second initial signal line 53 through the via.

[0250] (109) Forming a fourth conductive layer pattern. In the exemplary embodiment, forming the fourth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fourth conductive thin film, patterning the fourth conductive thin film by using a patterning process, forming a fourth conductive layer disposed on the sixth insulating layer, as shown in FIGS. 16a to 16c, FIG. 16a is a planar structure diagram of two sub-pixels after forming the fourth conductive layer, FIG. 16b is a planar schematic diagram of the fourth conductive layer in FIG. 16a, and FIG. 16c is a planar structure diagram of four sub-pixels after forming the second conductive layer. In the exemplary embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0251] In the exemplary embodiment, the fourth conductive layer at least includes: a first connecting electrode 61, a second connecting electrode 62, a third connecting electrode 63, a fourth connecting electrode 64, a fifth connecting electrode 65, a sixth connecting electrode 66, a seventh connecting electrode 67, an eighth connecting electrode 68, and a ninth connecting electrode 69.

[0252] In the example embodiment, the first connection electrode 61 can be in a bar shape or a broken line extending along the second direction Y, the first connection electrode 61 is connected to the first region 21-1 of the active layer 21 of the first transistor T1 through the first via V1, and is connected to the first initial signal line 41 in the fifteenth via V15 in a sub-pixel row. In the example embodiment, the first connection electrode 61 can be a first electrode of the first transistor T1, and the first connection electrode 61 is configured to be connected to the first initial signal line 45 and the active layer 21 of the first transistor T1.

[0253] In the example embodiment, the main body part of the second connection electrode 62 extends along the second direction Y, the first end of the second connection electrode 62 is connected to the second region 21-2 of the active layer 21 of the first transistor T1 through the second via V2, the second end of the second connection electrode 62 is connected to the second region 22-2 of the active layer 22 of the second transistor T2 through the fourth via V4, and is connected to the first region 26-1 of the active layer 26 of the sixth transistor T6 (also the second region 23-2 of the active layer 23 of the third transistor T3) through the eighth via V8, so that the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 have the same potential. In the example embodiment, the second connection electrode 62 can be a second electrode of the first transistor T1, a second electrode of the third transistor T3 and a first electrode of the sixth transistor T6.

[0254] In the example embodiment, one end of the third connection electrode 63 is connected to the first region 22-1 of the active layer 22 of the second transistor T2 through the third via V3, and the other end of the third connection electrode 63 is connected to the first electrode plate 33 through the thirteenth via V13. In the example embodiment, the third connection electrode 63 can be a first electrode of the second transistor T2.

[0255] In the example embodiment, the fourth connection electrode 64 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 through the fifth via V5. In the example embodiment, the fourth connection electrode 64 can be a first electrode of the fourth transistor T4, and is configured to be electrically connected to a data signal line formed subsequently.

[0256] In the example embodiment, the fifth connection electrode 65 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 through the sixth via V6, and is connected to the second electrode plate 43 through the fourteenth via V14. In the example embodiment, the fifth connection electrode 65 can be a first electrode of the fifth transistor T5, and is configured to be connected to a first power connection line formed subsequently.

[0257] In the example embodiment, the sixth connection electrode 66 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7) through the ninth via V9. In the example embodiment, the sixth connection electrode 66 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the sixth connection electrode 66 is configured to be connected to the anode connection electrode of the light emitting element formed subsequently.

[0258] In the example embodiment, the seventh connection electrode 67 is connected at one end to the second region 25-2 of the active layer 25 of the fifth transistor T5 (also the second region 24-2 of the active layer 24 of the fourth transistor T4 and the first region 23-1 of the active layer 23 of the third transistor T3) through the seventh via V7, and connected at the other end to the second region 28-2 of the active layer 28 of the eighth transistor T8 through the twelfth via V12. In the example embodiment, the seventh connection electrode 67 can serve as the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8.

[0259] In the example embodiment, the eighth connection electrode 68 can be connected at one end to the first region 28-1 of the active layer 28 of the eighth transistor T8 through the eleventh via V11, and connected at the other end to the third initial signal line 52 through the sixteenth via V16. In the example embodiment, the eighth connection electrode 68 can serve as the first electrode of the eighth transistor T8.

[0260] In the example embodiment, the ninth connection electrode 69 can be in the shape of a broken line or a strip extending along the second direction Y in the body portion, and the ninth connection electrode 69 is connected at one end to the first region 27-1 of the active layer 27 of the seventh transistor T7 through the tenth via V10, and connected at the other end to the second initial signal line 53 through the seventeenth via V17, so that the initial voltage can be written to the seventh transistor T7. In the example embodiment, since the ninth connection electrode 69 is connected to the first region 27-1 of the active layer 27 of all the seventh transistors T7 in one sub-pixel row, the first electrodes of all the seventh transistors T7 in one sub-pixel row can have the same potential, which is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate. In the example embodiment, the ninth connection electrode 69 can serve as the first electrode of the seventh transistor T7.

[0261] In the example embodiment, as shown in FIG. 16c, the fifth connection electrode 65 in the Nth column and the fifth connection electrode 65 in the N-1th column are connected to each other, and the fifth connection electrode 65 in the N+1th column and the fifth connection electrode 65 in the N+2th column are connected to each other. In the example embodiment, since the fifth connection electrode 65 in the sub-pixel is connected to the first power supply line formed subsequently, by forming the fifth connection electrodes 65 of adjacent sub-pixels into an integrated structure connected to each other, on the one hand, the fifth connection electrodes 65 of adjacent sub-pixels can have substantially the same potential, which is conducive to improving the uniformity of panel display, avoiding display defects of the display substrate, ensuring the display effect of the display substrate, and on the other hand, the space of the display substrate can be saved.

[0262] In the example embodiment, as shown in FIG. 16c, the eighth connection electrode 68 in the Nth column and the eighth connection electrode 68 in the N-1th column are connected to each other, and the eighth connection electrode 68 in the N+1th column and the eighth connection electrode 68 in the N+2th column are connected to each other. In the example embodiment, since the eighth connection electrode 68 in the sub-pixel is connected to the third initial signal line 52, by forming the eighth connection electrodes 68 of adjacent sub-pixels into an integrated structure connected to each other, on the one hand, the eighth connection electrodes 68 of adjacent sub-pixels can have substantially the same potential, which is conducive to improving the uniformity of panel display, avoiding display defects of the display substrate, ensuring the display effect of the display substrate, and on the other hand, the space of the display substrate can be saved.

[0263] (110) forming a seventh insulating layer and a first planar layer pattern. In the example embodiment, forming the seventh insulating layer and the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, first depositing a seventh insulating film, then coating a first planar film, and patterning the first planar film and the seventh insulating film by using a patterning process, to form the seventh insulating layer covering the fourth conductive layer pattern and the first planar layer disposed on the seventh insulating layer, and the seventh insulating layer and the first planar layer are provided with a plurality of vias, as shown in FIG. 17, which is a planar structure diagram of two sub-pixels after the first planar layer is formed.

[0264] In the example embodiment, the plurality of vias in each sub-pixel can at least include: an eighteenth via V18, a nineteenth via V19, and a twentieth via V20.

[0265] In the example embodiment, the orthogonal projection of the eighteenth via V18 on the substrate is within the range of the orthogonal projection of the sixth connection electrode 66 on the substrate, and the first planar layer and the seventh insulating layer in the eighteenth via V18 are etched away to expose the surface of the fifth connection electrode 65. The eighteenth via V18 is configured to allow the anode connection electrode of the light-emitting element formed subsequently to be electrically connected to the sixth connection electrode 66 through the via.

[0266] In the exemplary embodiment, the normal projection of the nineteenth via V19 on the substrate is within the range of the normal projection of the fifth connection electrode 65 on the substrate, the first planar layer and the seventh insulating layer in the nineteenth via V19 are etched away, exposing the surface of the fifth connection electrode 65. The nineteenth via V19 is configured to enable the first power connection line formed subsequently to connect with the fifth connection electrode 65 through the via.

[0267] In the exemplary embodiment, the normal projection of the twentieth via V20 on the substrate is within the range of the normal projection of the fourth connection electrode 64 on the substrate, the first planar layer and the seventh insulating layer in the twentieth via V20 are etched away, exposing the surface of the fourth connection electrode 64. The twentieth via V20 is configured to enable the data signal line formed subsequently to connect with the fourth connection electrode 64 through the via.

[0268] (111) forming a fifth conductive layer pattern. In the exemplary embodiment, forming the fifth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fifth conductive thin film, patterning the fifth conductive thin film by using a patterning process, forming a fifth conductive layer disposed on the first planar layer, as shown in FIGS. 18a and 18b, FIG. 18a is a planar structure diagram of two sub-pixels after the fifth conductive layer is formed, and FIG. 18b is a planar schematic diagram of the fifth conductive layer in FIG. 18a. In the exemplary embodiment, the fifth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0269] In the exemplary embodiment, the fifth conductive layer at least includes: a first data connection line 71, a data line connection electrode 72, a first power connection line 73, and a first anode connection electrode 74.

[0270] In the exemplary embodiment, the first data connection line 71 can be a polyline shape with a main body portion extending along the first direction X, and the first data connection line 71 is configured to be electrically connected with the data signal line formed subsequently. In the exemplary embodiment, the first data connection line 71 can be provided with a first electrode connection block 711 (as shown in FIG. 19b), and the first electrode connection block 711 at the position electrically connected with the second data connection line 84 is electrically connected with the second data connection line (second electrode connection block) through a via, and no via is provided at the position not electrically connected with the second data connection line. In the embodiment of the present disclosure, the first electrode connection block 711 in the first data connection line 71 in the plurality of sub-pixels can be arranged in the same manner (including a plurality of first electrode connection blocks 711 not connected with the second data connection line and first electrode connection blocks 711 connected with the second data connection line), which can improve the display uniformity of the display substrate. In the exemplary embodiment, the first data connection line 71 can not be provided with the first electrode connection block 711 at the position not electrically connected with the second data connection line 84, which can save the space of the display substrate and improve the transmittance.

[0271] In the example embodiment, the first data connection line 71 has an orthographic projection on the substrate 10 that at least partially overlaps the orthographic projection of the first initial signal line 41 on the substrate 10, and the signal interference between the first data connection line 71 and the first initial signal line 41 is small, and the orthographic projection of the first data connection line 71 and the first initial signal line 41 on the substrate 10 overlaps, which can save the space of the display substrate.

[0272] In the example embodiment, the data line connection electrode 72 can be electrically connected to the fourth connection electrode 64 through the twentieth via V20, and the data line connection electrode 72 is configured to be electrically connected to the subsequently formed data signal line.

[0273] In the example embodiment, the first power connection line 73 can be a polyline extending along the first direction X, and the first power connection line 73 can be connected to the fifth connection electrode 65 through the nineteenth via V19. Since the fifth connection electrode 65 is connected to the second plate 43 through the via, the connection between the first power connection line 73 and the second plate 43 is achieved, and the power signal is written to the second plate 43. Since the fifth connection electrode 65 is connected to the first area 25-1 of the active layer 25 of the fifth transistor T5 through the via, the connection between the first power line 73 and the first electrode of the fifth transistor T5 is achieved, and the power signal is written to the fifth transistor T5.

[0274] In the example embodiment, the first anode connection electrode 74 can be connected to the sixth connection electrode 66 through the eighteenth via V18. Since the sixth connection electrode 66 is connected to the second area 26-2 of the active layer 26 of the sixth transistor T6 (also the second area 27-2 of the active layer 27 of the seventh transistor T7) through the via, the connection between the first anode connection electrode 74 and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 is achieved.

[0275] In the example embodiment, the first power connection line 73 can include a connection main body 730, a first protruding portion 731, and two second protruding portions 732. In the same first power connection line 73, the first protruding portion 731 can be located between the two second protruding portions 732 in the first direction X, and the first protruding portion 731 and the second protruding portion 732 are located on both sides of the connection main body 730 of the first power connection line 73 in the second direction Y.

[0276] In the example embodiment, by arranging the second protruding part 732 on the first power connection line 73, the second protruding part 732 between two adjacent data signal lines 81 can be made flush with the first protruding part 731, so that the height and flatness of the anode of the sub-pixel are kept consistent, that is, the anode of the sub-pixel is kept in the same horizontal plane as much as possible, and the symmetry of the anode is increased. For example, the orthographic projection of the third anode formed subsequently on the substrate at least partially overlaps with the orthographic projection of the two second protruding parts 732 in the same first power connection line 73 on the substrate.

[0277] (112) The second flat layer pattern. In the example embodiment, forming the second flat layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a second flat film, patterning the second flat film by using a patterning process, forming a second flat layer covering the fifth conductive layer pattern, and the second flat layer being provided with a plurality of vias, as shown in FIGS. 19a and 19b. FIG. 19a is a planar structure diagram of two sub-pixels after the second flat layer is formed, and FIG. 19b is a planar structure diagram of sixteen sub-pixels after the second flat layer is formed.

[0278] In the example embodiment, the plurality of vias can at least include: a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, and a switching via Vm.

[0279] In the example embodiment, the orthographic projection of the twenty-first via V21 on the substrate is within the range of the orthographic projection of the data line connection electrode 72 on the substrate, the second flat layer in the twenty-first via V21 is etched away, and the surface of the data line connection electrode 72 is exposed. The twenty-first via V21 is configured to allow the data signal line formed subsequently to pass through the via and be connected to the data line connection electrode 72.

[0280] In the example embodiment, the orthographic projection of the twenty-second via V22 on the substrate is within the range of the orthographic projection of the first power connection line 73 on the substrate, the second flat layer in the twenty-second via V22 is etched away, and the surface of the first power connection line 73 is exposed. The twenty-second via V22 is configured to allow the first power line formed subsequently to pass through the via and be connected to the first power connection line 73.

[0281] In the example embodiment, the orthographic projection of the twenty-third via V23 on the substrate is within the range of the orthographic projection of the first anode connection electrode 74 on the substrate, and the twenty-third via V23 is configured to allow the second anode connection electrode formed subsequently to pass through the via and be connected to the first anode connection electrode 74.

[0282] In an example embodiment, the second twenty-fourth via V24 is configured to connect the first data connection line 71 and the data signal line to be formed later through the via.

[0283] In an example embodiment, the adapter via Vm is configured to connect the first data connection line 71 and the second data connection line to be formed later through the via.

[0284] In an example embodiment, as shown in FIG. 19b, not all of the sub-pixels are provided with the adapter via Vm and the second twenty-fourth via V24, and the corresponding adapter via Vm or the second twenty-fourth via V24 is provided at a position where the data signal needs to be transferred from the first data connection line 71 to the second data connection line.

[0285] (113) Forming a sixth conductive layer pattern. In an example embodiment, forming the sixth conductive layer can include: depositing a sixth conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the sixth conductive thin film by using a patterning process to form the sixth conductive layer disposed on the second planar layer, as shown in FIGS. 20a-20c, FIG. 20a is a planar structural diagram of two sub-pixels after the sixth conductive layer is formed, FIG. 20b is a planar schematic diagram of the sixth conductive layer in FIG. 20a, and FIG. 20c is a planar structural diagram of sixteen sub-pixels after the sixth conductive layer is formed. The sixth conductive layer can be referred to as a third source-drain metal (SD3) layer.

[0286] In an example embodiment, the sixth conductive layer at least includes: a data signal line 81 (i.e., the data signal line DL in FIG. 8), a first power supply line 82 (i.e., the first power supply line VDD in FIG. 8), a second anode connection electrode 83, and a second data connection line 84. In an example embodiment, the first anode connection electrode 74 and the second anode connection electrode 83 (which can be the anode connection electrode 83 described above, or the second anode connection electrode 83 and the corresponding first anode connection electrode 74 constitute the anode connection electrode 83 described above) are anode connection electrodes of the light emitting element.

[0287] In the example embodiment, the data signal line 81 is in a zigzag shape with the main body portion extending along the second direction Y, and the data signal line 81 is connected to the data line connection electrode 72 through the twenty-first via V21. Since the data line connection electrode 72 is connected to the fourth connection electrode 64 through the via, and the fourth connection electrode 64 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 through the via, the data signal line 81 is connected to the first electrode of the fourth transistor T4, and the data signal is written into the fourth transistor T4.

[0288] In the example embodiment, the first power supply line 82 is in a zigzag shape with the main body portion extending along the second direction Y, and the first power supply line 82 is connected to the first power supply connection line 73 through the twenty-second via V22. Since the first power supply connection line 73 is connected to the fifth connection electrode 65 through the via, and the fifth connection electrode 65 is connected to the second plate 43 through the via, the first power supply line 82 is connected to the second plate 43, and the power supply signal is written into the second plate 43. Since the fifth connection electrode 65 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 through the via, the first power supply line 82 is connected to the first electrode of the fifth transistor T5, and the power supply signal is written into the fifth transistor T5.

[0289] In the example embodiment, the second anode connection electrode 83 is connected to the first anode connection electrode 74 through the twenty-third via V23. Since the sixth connection electrode 66 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7) through the via, the second anode connection electrode 83 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0290] In the example embodiment, the main body portion of the second data connection line 84 extends along the second direction Y, and the second data connection line 84 is connected to the first data connection line 71 through the relay via Vm. In the example embodiment, the second data connection line 84 is disposed between two adjacent columns of sub-pixels. In the example embodiment, a plurality of second data connection lines 84 are respectively connected to a plurality of first data connection lines 71.

[0291] In the example embodiment, as shown in FIG. 20c, a plurality of second electrode connection blocks 841 can be arranged on the second data connection line 84, and the second electrode connection block 841 at the position electrically connected with the first data connection line 71 is electrically connected with the first data connection line 71 (the first electrode connection block 711) by arranging a transition via hole Vm, and no via hole is arranged at the position not electrically connected with the first data connection line 71. In the embodiment of the present disclosure, the arrangement mode of the second electrode connection block 841 in the second data connection line 84 can be consistent in the plurality of sub-pixels (including the plurality of second electrode connection blocks 841 not connected with the first data connection line 71 and the plurality of second electrode connection blocks 841 connected with the first data connection line 71), which can improve the display uniformity of the display substrate; or no second electrode connection block 841 is arranged at the position not electrically connected with the first data connection line 71, which can save the space of the display substrate.

[0292] In the example embodiment, in the first direction X, the first power line 82 can be located between two data signal lines 81, the second data connection line 84 is arranged between the adjacent two data signal lines 81, and the second data connection line 84 is located between the adjacent two columns of sub-pixels, the data signal line 81 can be located between the second data connection line 84 and the first power line 82, the orthographic projection of the first protruding portion 731 on the substrate at least partially overlaps the orthographic projection of the adjacent two first power lines 82 on the substrate, and the orthographic projection of the first protruding portion 731 on the substrate covers at least a part of the orthographic projection of the channel of the transistor on the substrate. The first protruding portion 731 can shield the interference of the signal of the data signal line 81 on the channel of the transistor, thereby playing a role in protecting the channel of the transistor in the sub-pixel.

[0293] In the example embodiment, in the first direction X, the orthographic projection of the channels of the two first transistors T1 and the two second transistors T2 in the adjacent two columns of sub-pixels on the substrate is located within the range of the orthographic projection of the first protruding portion 731 on the substrate, which can avoid the interference of the signal of the data signal line 81 on the channels of the first transistor T1 and the second transistor T2, and can well protect the channels of the first transistor T1 and the second transistor T2.

[0294] So far, the driving circuit layer is prepared on the substrate, and the driving circuit layer is provided with the pixel driving circuit of the plurality of sub-pixels. FIGS. 9 to 20c show the planar structure schematic diagram of the pixel driving circuit of the sub-pixel in the display substrate. In the example embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer can include the shielding layer, the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer arranged on the substrate in sequence.

[0295] In the exemplary embodiments, the driving circuit layer can include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer, a first planar layer and a second planar layer in a direction perpendicular to the plane in which the display substrate is located, the first insulating layer is arranged between the shielding layer and the first semiconductor layer, the second insulating layer is arranged between the first semiconductor layer and the first conductive layer, the third insulating layer is arranged between the first conductive layer and the second conductive layer, the fourth insulating layer is arranged between the second conductive layer and the second semiconductor layer, the fifth insulating layer is arranged between the second semiconductor layer and the third conductive layer, the sixth insulating layer is arranged between the third conductive layer and the fourth conductive layer, the seventh insulating layer and the first planar layer are arranged between the fourth conductive layer and the fifth conductive layer, and the second planar layer is arranged between the fifth conductive layer and the sixth conductive layer.

[0296] In the exemplary embodiments, after the driving circuit layer is prepared, the light-emitting structure layer is prepared on the driving circuit layer, and the preparation process of the light-emitting structure layer can include the following operations. A third planar layer pattern is formed, and the third planar layer is provided with at least an anode via hole. An anode pattern (i.e., an anode conductive layer) is formed, and the anode is connected to the anode connecting electrode through the anode via hole. An anode pixel definition layer is formed, and the pixel definition layer is provided with a pixel opening, and the pixel opening exposes the anode. An organic light-emitting layer is formed by using a vapor deposition or inkjet printing process, and a cathode is formed on the organic light-emitting layer. An encapsulation layer is formed, and the encapsulation layer can include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer which are stacked, the first encapsulation layer and the third encapsulation layer can be made of inorganic materials, the second encapsulation layer can be made of an organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, so as to prevent external water vapor from entering the light-emitting structure layer. The step of forming the anode conductive layer is as follows:

[0297] (114) A third planar layer pattern is formed. In the exemplary embodiments, forming the third planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, a third planar film is coated, and the third planar film is patterned by using a patterning process to form a third planar layer covering the sixth conductive layer pattern, and the third planar layer is provided with a plurality of via holes, as shown in FIG. 21, which is a planar structure diagram of two sub-pixels after the third planar layer is formed.

[0298] In the exemplary embodiments, the plurality of via holes can at least include a twenty-fifth via hole V25.

[0299] In the example embodiment, the via of each sub-pixel includes at least the twenty-fifth via V25. The orthogonal projection of the twenty-fifth via V25 on the substrate is within the range of the orthogonal projection of the second anode connecting electrode 83 on the substrate, the third planar layer in the twenty-fifth via V25 is removed to expose the surface of the second anode connecting electrode 83, and the twenty-fifth via V25 is configured to allow the subsequently formed anode to be electrically connected to the second anode connecting electrode 83 through the via.

[0300] (115) Forming an anode conductive layer pattern. In the example embodiment, forming the anode conductive layer pattern can include: depositing an anode conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive thin film by using a patterning process to form the anode conductive layer pattern disposed on the planar layer, as shown in FIGS. 22a to and 22c, FIG. 22a is a schematic diagram of the planar structure of two sub-pixels after forming the anode conductive layer, FIG. 22b is a schematic diagram of the planar structure of the anode conductive layer in FIG. 22a, and FIG. 22c is a schematic diagram of the planar structure of sixteen sub-pixels after forming the anode conductive layer (FIG. 22c shows the pixel driving circuit and 27 anodes of the sixteen sub-pixels, wherein the sixteen anodes are respectively electrically connected to the sixteen pixel driving circuits, and the pixel driving circuit electrically connected to the other eleven anodes is not shown in FIG. 22c).

[0301] In the example embodiment, the anode conductive layer pattern can include at least a plurality of anodes 90, which can include: a first anode 91 of a red light emitting unit, a second anode 92 of a green light emitting unit, and a third anode 93 of a blue light emitting unit, the area where the first anode 91 is located can form a red light emitting unit that emits red light, the area where the second anode 92 is located can form a green light emitting unit that emits green light, and the area where the third anode 93 is located can form a blue light emitting unit that emits blue light.

[0302] In the example embodiment, the first anode 91, the second anode 92, and the third anode 93 can be respectively connected to the second anode connecting electrode 83 in the corresponding sub-pixel through the twenty-fifth via V25. Since the second anode connecting electrode 83 in the sub-pixel is electrically connected to the first anode connecting electrode 74 through the via, and the first anode connecting electrode 74 is electrically connected to the second electrode of the sixth transistor T6 (also the second electrode of the seventh transistor T7) through the via, the first anode 91, the second anode 92, and the third anode 93 can be respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 through the second anode connecting electrode 83, thereby realizing the driving of the light emitting device by the pixel driving circuit.

[0303] In an example embodiment, the anode 90 can include an anode body part 901 and an anode connecting part 902, the anode body part 901 can be a rectangular structure, and the anode connecting part 902 is connected to the anode body part 901 at one end and is electrically connected to the second anode connecting electrode 83 through the twenty-fifth via hole V25 at the other end. The anode connecting part 902 can be a strip structure extending along the first direction X or the second direction Y, and the anode connecting part 902 can be arranged to compensate for the difference in parasitic capacitance between the plurality of sub-pixels due to signal traces. By arranging the anode connecting part 902, the parasitic capacitances of the plurality of sub-pixels can be kept consistent, and the display uniformity of the display substrate can be improved. In an example embodiment, the anode connecting part 902 of the anode 90 located at the first protruding part 731 extends along the second direction Y, and the anode connecting part 902 of the anode 90 located at the second protruding part 732 extends along the first direction X. For example, the anode connecting part 902 of the first anode 91 and the anode connecting part 902 of the second anode 92 extend along the second direction Y, and the anode connecting part 902 of the third anode 93 extends along the first direction X.

[0304] In an example embodiment, the main body part 901 of the plurality of anodes 90 has an orthogonal projection on the substrate that overlaps the orthogonal projection of the first protruding part 731 on the substrate or overlaps the orthogonal projection of the second protruding part 732 on the substrate, which can make the anode height and flatness of the plurality of sub-pixels consistent. For example, the main body part 901 of the first anode 91 and the second anode 92 has an orthogonal projection on the substrate that overlaps the orthogonal projection of the first protruding part 731 on the substrate, and the main body part 901 of the third anode 93 has an orthogonal projection on the substrate that overlaps the orthogonal projection of the second protruding part 732 on the substrate.

[0305] In an example embodiment, as shown in FIG. 22c, the plurality of anodes 90 can form first anode columns and second anode columns arranged alternately along the first direction X, in the same first anode column, the first anode 91 and the third anode 93 can be arranged alternately along the second direction Y, and in the same second anode column, the plurality of second anodes 92 can be arranged alternately along the second direction Y; the plurality of anodes 90 can form first anode rows and second anode rows arranged alternately along the second direction Y, in the same first anode row, the first anode 91 and the third anode 93 can be arranged alternately along the first direction X, and in the same second anode row, the plurality of second anodes 92 can be arranged alternately along the first direction X.

[0306] (116) Forming a pixel definition layer pattern. In an example embodiment, forming the pixel definition layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a pixel definition layer thin film, patterning the pixel definition layer using a patterning process, and forming the pixel definition layer pattern disposed on the anode conductive layer, as shown in FIGS. 23a-23c, FIG. 23a is a schematic diagram of the planar structure of two sub-pixels after the pixel definition layer is formed, FIG. 23b is a schematic diagram of the planar structure of the pixel definition layer in FIG. 23a, and FIG. 23c is a schematic diagram of the planar structure of sixteen sub-pixels after the pixel definition layer is formed (FIG. 23c shows the pixel driving circuits of the sixteen sub-pixels and 27 pixel openings, of which the sixteen pixel openings correspond to the sixteen pixel driving circuits, and the pixel driving circuits of the other eleven pixel openings are not shown in FIG. 23c).

[0307] In an example embodiment, the pixel definition layer pattern can include a plurality of pixel openings K0 that expose the anode 90. In an example embodiment, the orthographic projection of the pixel openings K0 on the substrate is within the range of the orthographic projection of the anode 90 on the substrate. In an example embodiment, the pixel openings K0 can include a pixel opening K01 of the first sub-pixel, a pixel opening K02 of the second sub-pixel, and a pixel opening K03 of the third sub-pixel, the orthographic projection of the pixel opening K01 of the first sub-pixel on the substrate has an overlapping area with the orthographic projection of the first anode 91 on the substrate; the orthographic projection of the pixel opening K02 of the second sub-pixel on the substrate has an overlapping area with the orthographic projection of the second anode 92 on the substrate; and the orthographic projection of the pixel opening K03 of the third sub-pixel on the substrate has an overlapping area with the orthographic projection of the third anode 93 on the substrate.

[0308] In an example embodiment, as shown in FIG. 23c, the plurality of pixel openings K0 can form first pixel opening columns and second pixel opening columns arranged alternately along the first direction X, in the same first pixel opening column, the first pixel opening K01 and the third pixel opening K03 can be arranged alternately along the second direction Y, and in the same second pixel opening column, the plurality of second pixel openings K02 can be arranged alternately along the second direction Y; the plurality of pixel openings K0 can form first pixel opening rows and second pixel opening rows arranged alternately along the second direction Y, in the same first pixel opening row, the first pixel opening K01 and the third pixel opening K03 can be arranged alternately along the first direction X, and in the same second pixel opening row, the plurality of second pixel openings K02 can be arranged alternately along the first direction X.

[0309] In the example embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer and the seventh insulating layer can adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), which can be a single layer, a multi-layer or a composite layer. The first insulating layer can be referred to as a buffer layer for improving the water-oxygen resistance of the substrate, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be referred to as gate insulating (GI) layers, the sixth insulating layer can be referred to as an interlayer insulating (ILD) layer, and the seventh insulating layer can be referred to as a passivation (PVX) layer.

[0310] The structure and the preparation process thereof shown in the foregoing embodiments of the present disclosure are merely exemplary descriptions, and in the example embodiment, the corresponding structure can be changed, and the patterning process can be increased or reduced according to actual needs. The display substrate can be applied to other display devices having a pixel driving circuit, such as quantum dot display, which is not limited in the present disclosure.

[0311] The present disclosure also provides a display device including the display substrate of any of the foregoing embodiments. The display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator.

[0312] The display substrate and the display device provided by the embodiments of the present disclosure include a plurality of sub-pixels, at least part of the sub-pixels include a pixel driving circuit, an anode and an anode connection electrode, in the same sub-pixel, the pixel driving circuit is electrically connected to the anode through the anode connection electrode, the pixel driving circuit of at least part of the sub-pixels forms a plurality of rows and columns, among the plurality of anodes electrically connected to a row of pixel driving circuits, the overlapping area of at least one anode with the pixel driving circuit of the adjacent row is greater than the overlapping area of the anode with the row of pixel driving circuits electrically connected thereto, the length dimension of the anode connection electrode electrically connected to the at least one anode can be increased, and the write black voltage of the sub-pixel containing the at least one anode in the display substrate can be reduced, thereby reducing the power consumption of the display substrate and improving the endurance.

[0313] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0314] In the case of no conflict, the features in the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0315] Although the embodiments disclosed by the present disclosure are as above, the content is only the adopted embodiments for facilitating the understanding of the present disclosure, and is not used to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the implementation form and details without departing from the spirit and scope of the present disclosure disclosed, but the patent protection scope of the present disclosure still needs to be limited by the scope defined by the appended claims.

Claims

1. A display substrate, comprising: The substrate and a plurality of sub-pixels arranged on the substrate, at least part of the sub-pixels comprising a pixel drive circuit, an anode and an anode connecting electrode, in the same sub-pixel, the pixel drive circuit is electrically connected with the anode through the anode connecting electrode; in the direction perpendicular to the plane where the display substrate is located, the anode is located on the side of the pixel drive circuit away from the substrate; The pixel drive circuit of the at least part of the sub-pixels forms a plurality of rows and columns, among the plurality of anodes electrically connected with a row of pixel drive circuits, at least one anode has an overlapping area with the pixel drive circuits of the adjacent row, which is greater than the overlapping area with the row of pixel drive circuits electrically connected therewith. 2.The display substrate of claim 1, wherein, The at least part of the sub-pixels comprises a first type of sub-pixel and a second type of sub-pixel, the length dimension of the anode connecting electrode in the second type of sub-pixel is greater than the length dimension of the anode connecting electrode in the first type of sub-pixel; among the plurality of anodes electrically connected with a row of pixel drive circuits, the anode of the second type of sub-pixel and the pixel drive circuits of the adjacent row at least partially overlap in the orthographic projection on the substrate, and the overlapping area of the anode of the second type of sub-pixel and the pixel drive circuits of the adjacent row is greater than the overlapping area of the row of pixel drive circuits electrically connected therewith. 3.The display substrate of claim 2, wherein, The anode comprises an anode main body part and an anode connecting part, in the same sub-pixel, the anode connecting part is electrically connected with the anode main body part and the corresponding anode connecting electrode; Among the plurality of anodes electrically connected with a row of pixel drive circuits, the orthographic projection of the anode main body part of the second type of sub-pixel on the substrate is located within the orthographic projection of the pixel drive circuits of the adjacent row on the substrate. 4.The display substrate of claim 2, wherein, Among the plurality of anodes electrically connected with a row of pixel drive circuits, the orthographic projection of the anode of the first type of sub-pixel on the substrate at least partially overlaps with the orthographic projection of the row of pixel drive circuits on the substrate. 5.The display substrate of claim 4, wherein, Among the plurality of anodes electrically connected with a row of pixel drive circuits, the overlapping area of the anode of the first type of sub-pixel and the orthographic projection of the row of pixel drive circuits on the substrate is greater than the overlapping area of the orthographic projection of the pixel drive circuits of the adjacent row on the substrate. 6.The display substrate according to any one of claims 2 to 5, wherein In the direction perpendicular to the plane where the display substrate is located, the display substrate comprises a drive circuit layer and an anode conductive layer, the anode connecting electrode is located in the conductive layer closest to the anode conductive layer in the drive circuit layer, and the plurality of anodes are located in the anode conductive layer. 7.The display substrate of claim 6, wherein, In the direction perpendicular to the plane where the display substrate is located, the drive circuit layer comprises a fifth conductive layer and a sixth conductive layer, the sixth conductive layer is the conductive layer closest to the anode conductive layer in the drive circuit layer, the fifth conductive layer is located between the substrate and the sixth conductive layer, and the sixth conductive layer is located between the fifth conductive layer and the anode conductive layer; The fifth conductive layer comprises a first power supply connecting line, the plurality of sub-pixels comprise a plurality of types, the plurality of types of sub-pixels at least comprise a second sub-pixel, and the orthographic projection of the first power supply connecting line on the substrate at least partially overlaps with the orthographic projection of the anode of at least one second sub-pixel on the substrate. 8.The display substrate of claim 7, wherein, The second type of sub-pixel includes the second sub-pixel, and the first power supply connection line includes a first protruding portion. Among the plurality of anodes electrically connected with the pixel driving circuit in one row, the anode of the second sub-pixel and the first protruding portion in the pixel driving circuit of the adjacent row at least partially overlap in the orthographic projection on the substrate. 9.The display substrate of claim 8, wherein, The plurality of sub-pixels further include a first sub-pixel and a third sub-pixel, the first type of sub-pixel includes the first sub-pixel and the third sub-pixel, and the pixel driving circuit of at least part of the sub-pixels is arranged in an array. In the same row of pixel driving circuits, the pixel driving circuit of the first type of sub-pixel and the pixel driving circuit of the second type of sub-pixel are arranged alternately in the row direction. In the row direction, the pixel driving circuit of the second sub-pixel is located between the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the third sub-pixel. The first power supply connection line and the pixel driving circuit of the adjacent two sub-pixels in one row of pixel driving circuits at least partially overlap in the orthographic projection on the substrate. The first power supply connection line further includes a connection main body portion and two second protruding portions. In the same first power supply connection line, the two second protruding portions are symmetric with respect to the center line of the first power supply connection line extending in the column direction in the row direction. In the column direction, the first protruding portion is located on one side of the connection main body portion, and the two second protruding portions are located on the other side of the connection main body portion. The orthographic projection of the anode of the first type of sub-pixel on the substrate at least partially overlaps with the orthographic projection of the adjacent two second protruding portions in the two adjacent first power supply connection lines on the substrate. 10.The display substrate of claim 9, wherein, The sixth conductive layer further includes a first power supply line, and the first power supply line includes a first power supply block and two first power supply connection structures. In the same row of pixel driving circuits, the anode of the second type of sub-pixel, one of the first power supply blocks, and the first protruding portion in the corresponding first power supply connection line at least partially overlap in the orthographic projection on the substrate. The anode of the first type of sub-pixel, the adjacent two second protruding portions in the adjacent two first power supply connection lines, and the adjacent two first power supply connection structures in the adjacent two first power supply lines at least partially overlap in the orthographic projection on the substrate. In the same column of pixel driving circuits, the adjacent two first power supply blocks are connected to each other through the first power supply connection structure. 11.The display substrate of claim 10, wherein, The sixth conductive layer further includes a plurality of data signal lines. The plurality of data signal lines extend in the column direction and are arranged at intervals in the row direction. The data signal lines are electrically connected with at least part of the pixel driving circuits in one column of pixel driving circuits. In the row direction, the first power supply line is located between the adjacent two data signal lines, and two data signal lines are provided between the adjacent two first power supply lines. The orthographic projection of the anode of the first type of sub-pixel on the substrate at least partially overlaps with the orthographic projection of the two data signal lines between the adjacent two first power supply lines on the substrate. In the two data signal lines and the two first power connection structures which have overlap with the orthographic projection of the anode of the same first type sub-pixel on the substrate, one of the first power connection structures is located on one side of the two data signal lines in the row direction, and the other first power connection structure is located on the other side of the two data signal lines. 12.The display substrate of claim 11, wherein, The fifth conductive layer further comprises a plurality of first data connection lines extending in the row direction and arranged at intervals in the column direction, and the sixth conductive layer further comprises a plurality of second data connection lines extending in the column direction and arranged at intervals in the row direction, wherein the second data connection lines are located between adjacent two data signal lines in the row direction, and the distance interval between adjacent two first data connection lines in the column direction is consistent with the size of one pixel driving circuit. The plurality of data signal lines comprises a plurality of first type data signal lines and a plurality of second type data signal lines, and the first type data signal lines are located on the side away from the first middle line of the second type data signal lines on the same side of the first middle line in the row direction, and the first middle line is the middle line of the display substrate extending in the column direction. The first data connection line is electrically connected with one of the second data connection lines and one of the first type data signal lines, and is configured to transmit the data signal of one of the second data connection lines to the first type data signal line electrically connected therewith; and among the first type data signal lines and the second data connection lines electrically connected with the same first data connection line, the distance between the first type data signal line and the first middle line is greater than the distance between the second data connection line and the first middle line in the row direction. 13.The display substrate of claim 12, wherein, The orthographic projection of the anode of the first type sub-pixel on the substrate further at least partially overlaps with the orthographic projection of one of the second data connection lines on the substrate. Among the two data signal lines, the two first power connection structures and one second data connection line which have overlap with the orthographic projection of the anode of the same first type sub-pixel on the substrate, the two data signal lines are located on the same side of the first middle line in the row direction. The two first power connection structures are symmetrical with respect to the second data connection line.

14. The display substrate according to any one of claims 2 to 5, wherein, The plurality of sub-pixels comprises a plurality of types, and the plurality of types of sub-pixels at least include first sub-pixels, second sub-pixels and third sub-pixels, at least part of the first sub-pixels, the second sub-pixels and the third sub-pixels are the first type sub-pixels, and the other part are the second type sub-pixels. 15.The display substrate of claim 14, wherein, One of the first sub-pixels, the second sub-pixels and the third sub-pixels is the second type sub-pixel, and the other two are the first type sub-pixels. 16.The display substrate of claim 15, wherein, The orthographic projection of the anodes of the plurality of second type sub-pixels electrically connected with the i-th row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the pixel driving circuit of the i-1-th row on the substrate. Or, the orthographic projection of the anodes of the plurality of second type sub-pixels electrically connected with the i-th row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the pixel driving circuit of the i+1-th row on the substrate. i is a positive integer greater than 1. The anodes of the first type of sub-pixels electrically connected with the i-th row of pixel driving circuits at least partially overlap the projections of the pixel driving circuits on the substrate. 17.The display substrate of claim 15, wherein, The first type of sub-pixels includes the first sub-pixels and the third sub-pixels, and the second type of sub-pixels includes the second sub-pixels; the plurality of anodes form first anode columns and second anode columns arranged alternately along a row direction, in a same first anode column, the anodes of the first sub-pixels and the third sub-pixels are arranged alternately along a column direction, and in a same second anode column, the anodes of the plurality of second sub-pixels are arranged at intervals along the column direction. The plurality of anodes form first anode rows and second anode rows arranged alternately along a column direction, in a same first anode row, the anodes of the first sub-pixels and the third sub-pixels are arranged alternately along a row direction, and in a same second anode row, the anodes of the plurality of second sub-pixels are arranged at intervals along the row direction. 18.The display substrate of claim 15, wherein, The first type of sub-pixels includes the first sub-pixels and the second sub-pixels, and the second type of sub-pixels includes the third sub-pixels; or, the first type of sub-pixels includes the second sub-pixels and the third sub-pixels, and the second type of sub-pixels includes the first sub-pixels.

19. The display substrate according to any one of claims 2 to 5, wherein, The length of the anode connecting electrode of the second type of sub-pixels is 5-15 microns.

20. A display device comprising the display substrate according to any one of claims 1-19.

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