Memory and access method therefor, and electronic device

Abstract

A memory and an access method therefor, and an electronic device. The memory comprises at least one memory array, a plurality of common word lines, and a plurality of common bit lines. The memory array comprises a plurality of vertically stacked memory cell arrays and a plurality of vertical local bit lines. Each memory cell array comprises a plurality of local word lines extending in a second direction. The plurality of local word lines in a same memory cell array are divided into a plurality of word line groups, and different word line groups are connected to different common word lines. Each word line group comprises two local word lines connected to memory cells that are spaced one column apart from the word line group, each row of local bit lines corresponds to four common bit lines, and the common bit lines connected to the local bit lines connected to the memory cells connected to the local word lines in a same word line group are not adjacent.

Description

Memory and access method thereof, and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410822959.7, filed on June 24, 2024, and entitled "Memory and access method thereof, and electronic device", the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a memory and access method thereof, and electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of devices is increasingly shrinking, and the types and number of devices contained in a single chip are increasing, so that any slight difference in process production can affect the performance of the device.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] Embodiments of the present disclosure provide a memory, comprising:

[0008] at least one memory array, a plurality of common word lines, and a plurality of common bit lines;

[0009] The memory array comprises a plurality of layers of memory cell arrays stacked in a direction perpendicular to a substrate, and a plurality of local bit lines extending in a direction perpendicular to the substrate and arranged in a first direction and a second direction;

[0010] The memory cell array comprises: a plurality of memory cells arranged in the first direction and the second direction, a plurality of local word lines extending in the second direction corresponding to each column of memory cells arranged in the second direction, and the local word lines connecting the corresponding column of memory cells; and the local bit lines connect a plurality of memory cells at the same position of different layers, and the first direction and the second direction are parallel to the substrate and intersected;

[0011] The multiple local word lines of the same storage unit array are divided into multiple word line groups, each word line group is connected to a common word line, and different word line groups are connected to different common word lines; each word line group includes two local word lines, and the two local word lines in the same word line group are connected to the storage units in different columns, respectively.

[0012] Each row of local bit lines distributed along the first direction corresponds to four common bit lines, each local bit line is connected to a common bit line, and in the same row, every four continuously distributed local bit lines are connected to different common bit lines in the four common bit lines corresponding to the row of local bit lines, and the common bit lines connected by the local bit lines of the storage units connected by the local word lines of the same word line group are not adjacent.

[0013] In some embodiments, the memory includes multiple storage arrays spaced along the second direction, and adjacent storage units share the common word line, and in the multiple word line groups of the storage array, the word line group in which the local word lines connected to the storage units in the odd-numbered columns are connected to the same common word line as the word line group of one of the two storage arrays adjacent to the storage array, and the word line group in which the local word lines connected to the storage units in the even-numbered columns are connected to the same common word line as the word line group of the other of the two storage arrays adjacent to the storage array.

[0014] In some embodiments, the multiple columns of storage units connected by the word line groups connected to the same common word line and located in different storage arrays are in the same column.

[0015] In some embodiments, each local bit line is also connected to a second preset voltage terminal through a first gating subcircuit, the first gating subcircuit is connected to a first gating control line, and the first gating subcircuit is configured to electrically connect or disconnect the local bit line and the second preset voltage terminal under the control of the first gating control line.

[0016] In some embodiments, the multiple first gating subcircuits connected to the multiple common bit lines respectively connected to the local bit lines in the same column are connected to the same first gating control line.

[0017] The embodiments of the present disclosure provide an access method, applied to the above-mentioned memory, including:

[0018] In the data read / write phase, according to the word line group in which the local word line connected to the target storage unit to be operated is located, an activation signal is loaded on the common word line connected by the word line group, wherein the target storage unit includes two columns of storage units, and the two columns of storage units are connected to two local word lines of the same word line group, respectively.

[0019] In some embodiments, the method further comprises loading an off level signal on a first gate control line connected to a first gate subcircuit connected to a common bit line connected to two target local bit lines respectively connected to the target memory cells; the common bit line connected to the two target local bit lines is referred to as a target common bit line, and other common bit lines of a memory cell array where the target memory cells are located are referred to as non-target common bit lines; an on level signal is loaded on a first gate control line connected to a first gate subcircuit connected to a non-target common bit line.

[0020] In some embodiments, the method further comprises referring to a word line group where local word lines connected to memory cells in an odd column as an odd column word line group, referring to a word line group where local word lines connected to memory cells in an even column as an even column word line group, referring to a common bit line connected to local bit lines connected to memory cells in an odd column as an odd column common bit line, and referring to a common bit line connected to local bit lines connected to memory cells in an even column as an even column common bit line.

[0021] When the target memory cells are odd column memory cells, an off level signal is loaded on a first gate control line connected to a first gate subcircuit connected to the odd column common bit line, and an on level signal is loaded on a first gate control line connected to a first gate subcircuit connected to the even column common bit line.

[0022] When the target memory cells are even column memory cells, an off level signal is loaded on a first gate control line connected to a first gate subcircuit connected to the even column common bit line, and an on level signal is loaded on a first gate control line connected to a first gate subcircuit connected to the odd column common bit line.

[0023] The electronic device provided by the embodiments of the present disclosure includes the memory as described in any of the above embodiments.

[0024] In some embodiments, the electronic device further comprises a control circuit configured to access the memory according to the above access method.

[0025] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. Other advantages of the present application can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the following description.

[0026] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.

[0027] BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification, and are used to explain the technical solutions of the present application together with the embodiments of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0029] Fig. 1 is a schematic diagram of a logic circuit of a memory according to some embodiments;

[0030] Fig. 2 is a schematic diagram of a connection of a bit line and a common bit line according to some embodiments;

[0031] Fig. 3 is a schematic diagram of a connection of a bit line and a common bit line according to some other embodiments;

[0032] Fig. 4 is a schematic diagram of a timing of control signals according to some embodiments;

[0033] Fig. 5 is a schematic diagram of a timing of control signals according to some other embodiments;

[0034] Fig. 6 is a schematic diagram of a control circuit according to some embodiments;

[0035] Fig. 7 is a schematic diagram of a timing of the control circuit shown in Fig. 6.

[0036] Detailed description

[0037] The embodiments of the present application will be described in detail hereinafter with reference to the drawings. The features of the embodiments of the present application and the embodiments can be combined with each other as long as there is no conflict.

[0038] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs.

[0039] The embodiments of the present disclosure are not necessarily limited to the sizes shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the actual proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0040] The ordinal numbers "first", "second", "third", etc. in the present disclosure are set to avoid confusion of the components, and do not represent any order, number or importance.

[0041] In the present disclosure, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, can be a contact connection or an integrally connected connection, can be directly connected, or indirectly connected through an intermediate part, or the communication inside two elements. The specific meanings of the above terms in the present disclosure can be understood by the person skilled in the art according to the specific circumstances.

[0042] In the present disclosure, it can be that the first electrode is a drain electrode and the second electrode is a source electrode, or it can be that the first electrode is a source electrode and the second electrode is a drain electrode. In the case of using a transistor of opposite polarity or in the case of a change in the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be exchanged with each other.

[0043] In the present disclosure, "connection" includes a case where constituent elements are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can perform the transmission and reception of an electrical signal between the connected constituent elements. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0044] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0045] Fig. 1 is a schematic diagram of a logic circuit of a memory according to an example embodiment. As shown in Fig. 1, the memory can include a plurality of memory arrays located in different regions of a substrate, and the plurality of memory arrays can be arranged along a second direction Y. The memory array can include a plurality of layers of memory cell arrays 10 stacked in a direction perpendicular to the substrate, a plurality of local bit lines (LBL) extending in a direction perpendicular to the substrate. The memory cell array 10 can include a plurality of memory cells 11 arranged in a first direction X and a second direction Y, a plurality of local word lines (LWL) extending in the second direction Y. The memory cells 11 in the same column along the second direction Y in the same layer are connected to the same LWL. The memory cells 11 in different columns are connected to different LWLs. The plurality of memory cells 11 in the same position in different layers are connected to the same LBL. The plurality of LBLs are arranged in the first direction X and the second direction Y. The memory can further include a plurality of common word lines (CWL) and a plurality of common bit lines (CBL). The CBL can extend in the first direction X. The plurality of CBLs of the same memory cell array 10 can be spaced apart in the second direction Y.

[0046] The storage unit 11 can include a transistor and a capacitor, the transistor includes a gate electrode, a first electrode and a second electrode, the gate electrode of the transistor is connected to the LWL, the first electrode of the transistor is connected to the LBL, and the second electrode of the transistor is connected to the first end of the capacitor, and the second end of the capacitor is connected to the first preset voltage terminal V PL . The first preset voltage terminal V PL may be a fixed potential, such as a value between the voltage corresponding to the logic data "0" and the voltage corresponding to the logic data "1", such as "0" corresponding to the logic data "0" and VDD corresponding to the logic data "1", and V PL may be 1 / 2VDD.

[0047] The plurality of LWLs in the same storage unit array 10 can be divided into a plurality of groups, each group is called a word line group, each LWL belongs to only one word line group, each word line group can include two LWLs, and the two LWLs in the same word line group are separated by one LWL, the LWLs in the same word line group are connected to the same CWL, and the LWLs in different word line groups of the same storage unit array 10 are connected to different CWLs. For example, the storage unit array 10 includes N rows and 2M columns of storage units 11, that is, N*2M storage units 11, and includes 2M LWLs, the jth LWL is connected to the jth column of storage units 11, and j is 1 to 2M. The first LWL and the third LWL form the first word line group, and the LWLs in the word line group are connected to the first common word line CWL_0; the second LWL and the fourth LWL form the second word line group, and are connected to the second common word line CWL_1; the fifth LWL and the seventh LWL form the third word line group, and are connected to the third common word line CWL_2; the sixth LWL and the eighth LWL form the fourth word line group, and are connected to the fourth common word line CWL_3; and so on, the 2M-3th LWL and the 2M-1th LWL form the M-1th word line group, and are connected to the M-1th common word line CWL_M-2; and the 2M-2th LWL and the 2Mth LWL form the Mth word line group, and are connected to the Mth common word line CWL_M-1. The scheme provided in the embodiment can connect more storage units to each LWL compared to connecting four word lines of the same storage unit array 10 to the CWL, and is easier to wire.

[0048] Each CWL can be connected to two LWLs of two word line groups, and the two word line groups belong to the memory cell arrays 10 of the same layer of two adjacent memory arrays, and the memory cells 11 connected by the LWLs in the two word line groups are in the same column. For example, in the three adjacent memory arrays shown in FIG. 1, the k-1th memory array, the kth memory array and the k+1th memory array, the common word line CWL_0 is connected to the first LWL (connected to the first column of memory cells 11 of the kth memory array 10 of the rth layer) and the third LWL (connected to the third column of memory cells 11 of the kth memory array 10 of the rth layer) of the kth memory array, and the first LWL (connected to the first column of memory cells 11 of the k-1th memory array 10 of the rth layer) and the third LWL (connected to the third column of memory cells 11 of the k-1th memory array 10 of the rth layer) of the k-1th memory array.

[0049] The adjacent word line groups of the same memory cell array 10 are connected to the same CWL as the word line groups of different memory arrays. The word line group in which the LWLs connected to the memory cells of the odd-numbered columns are connected to the same common word line as the word line group of one of the two memory arrays adjacent to the memory array, and the word line group in which the LWLs connected to the memory cells of the even-numbered columns are connected to the same common word line as the word line group of the other of the two memory arrays adjacent to the memory array. For example, the word line group in which the LWLs connected to the memory cells 11 of the odd-numbered columns of the kth memory array is connected to the same common word line as the word line group in which the LWLs connected to the memory cells 11 of the odd-numbered columns of the (k-1)th memory array, and the word line group in which the LWLs connected to the memory cells 11 of the even-numbered columns of the kth memory array is connected to the same common word line as the word line group in which the LWLs connected to the memory cells 11 of the even-numbered columns of the (k+1)th memory array, or the word line group in which the LWLs connected to the memory cells 11 of the odd-numbered columns of the kth memory array is connected to the same common word line as the word line group in which the LWLs connected to the memory cells 11 of the odd-numbered columns of the (k+1)th memory array, and the word line group in which the LWLs connected to the memory cells 11 of the even-numbered columns of the kth memory array is connected to the same common word line as the word line group in which the LWLs connected to the memory cells 11 of the even-numbered columns of the (k-1)th memory array, where the adjacent word line groups are the word line groups in which there are adjacent LWLs among the LWLs included in the two word line groups. For example, the LWLs of the 1st, 3rd, …, (M-1)th word line groups of the kth memory array are connected to the same common word line as the LWLs of the corresponding 1st, 3rd, …, (M-1)th word line groups of the (k-1)th memory array, respectively, and the LWLs of the 2nd, 4th, …, Mth word line groups of the kth memory array are connected to the same common word line as the LWLs of the corresponding 2nd, 4th, …, Mth word line groups of the (k+1)th memory array, respectively. As shown in FIG. 1, the 1st word line group of the kth memory array (including the LWLs connected to the memory cells of the odd-numbered columns, i.e., the 1st LWL and the 3rd LWL) is connected to the same common word line CWL_0 as the 1st word line group of the (k-1)th memory array, and the 2nd word line group of the kth memory array (including the LWLs connected to the memory cells of the even-numbered columns, i.e., the 2nd LWL and the 4th LWL) is connected to the same common word line CWL_1 as the 2nd word line group of the (k+1)th memory array.

[0050] Each row of LBLs distributed along the first direction X corresponds to 4 CBLs, and each LBL is connected to one CBL. In the same row, every 4 consecutive LBLs are connected to different CBLs corresponding to the row. In the LBLs connected to the same common bit line, the interval between adjacent LBLs (here, referring to the interval between adjacent LBLs in a group of LBLs connected to the same common bit line) is 3 LBLs, and the CBLs connected by the LBLs connected by the memory cells 11 connected by the LWLs of the same word line group are not adjacent. For example, as shown in FIG. 2, the plurality of LBLs in the i+1th row correspond to 4 common bit lines CBL_i_0, CBL_i_1, CBL_i_2, CBL_i_3, i is 0 to N-1, wherein the LBLs in the 1st, 5th, … 2M-3th columns of the i+1th row are connected to the 1st common bit line CBL_i_0 corresponding to the row, the LBLs in the 2nd, 6th, … 2M-2th columns of the i+1th row are connected to the 2nd common bit line CBL_i_1 corresponding to the row, the LBLs in the 3rd, 7th, … 2M-1th columns of the i+1th row are connected to the 3rd common bit line CBL_i_2 corresponding to the row, and the LBLs in the 4th, 8th, … 2Mth columns of the i+1th row are connected to the 4th common bit line CBL_i_3 corresponding to the row. In other embodiments, the LBLs in the 1st, 5th, … 2M-3th columns of the i+1th row can be connected to the 4th common bit line CBL_i_3 corresponding to the row, the LBLs in the 2nd, 6th, … 2M-2th columns of the i+1th row can be connected to the 3rd common bit line CBL_i_2 corresponding to the row, the LBLs in the 3rd, 7th, … 2M-1th columns of the i+1th row can be connected to the 2nd common bit line CBL_i_1 corresponding to the row, and the LBLs in the 4th, 8th, … 2Mth columns of the i+1th row can be connected to the 1st common bit line CBL_i_0 corresponding to the row. The above connection mode is only an example, and other connection modes can be used, for example, the LBLs in the 1st, 5th, … 2M-3th columns of the i+1th row can be connected to the 3rd common bit line CBL_i_2 corresponding to the row, the LBLs in the 2nd, 6th, … 2M-2th columns of the i+1th row can be connected to the 2nd common bit line CBL_i_1 corresponding to the row, the LBLs in the 3rd, 7th, … 2M-1th columns of the i+1th row can be connected to the 1st common bit line CBL_i_0 corresponding to the row, and the LBLs in the 4th, 8th, … 2Mth columns of the i+1th row can be connected to the 4th common bit line CBL_i_3 corresponding to the row, and so on. It is ensured that the CBLs connected by the LBLs connected by the memory cells 11 connected by the LWLs of the same word line group are not adjacent, so that adjacent CBLs can be prevented from working at the same time.

[0051] Among the M common word lines connected by each memory cell array 10, only one common word line is activated at the same time. For example, as shown in FIG. 2, when the common word line CWL_0 is activated, the transistors of the first column of memory cells 11 and the third column of memory cells 11 connected by the first LWL and the third LWL are turned on, and the corresponding LBLs connected with the first column of memory cells 11 and the third column of memory cells 11 perform data reading or writing through charge sharing. At this time, the working LBLs are the LBLs connected with the first column of memory cells 11 and the third column of memory cells 11, which are non-adjacent LBLs, and the first column of LBLs and the third column of LBLs are separated by two memory cells 11, and the distance is very far, and the coupling between the first column of LBLs and the third column of LBLs is very small. In addition, the second column of LBLs can shield the first column of LBLs and the third column of LBLs, thereby further reducing the coupling between the first column of LBLs and the third column of LBLs. Thus, one common bit line can connect more LBLs, and the corresponding memory can use fewer common bit lines. In addition, since the common bit line is connected to the sense amplifier, the number of common bit lines is reduced, and the number of sense amplifiers connected to the common bit line is also reduced. At this time, among the four CBLs corresponding to the same row of LBLs, only two non-adjacent CBLs connected with the two columns of LBLs where the two activated LWLs are located are working, and the other two CBLs are not working, and can act as shielding lines between the working CBLs. The shielding lines can shield the adjacent CBLs and reduce the coupling capacitance between the adjacent CBLs, so that one CBL can connect more LBLs, and the corresponding memory can use fewer CBLs and fewer sense amplifiers. For example, when the common word line CWL_0 is activated, the LBLs connected with the first column of memory cells 11 and the third column of memory cells 11 perform data reading or writing through charge sharing. The LBL connected with the memory cell 11 in the first column of the i+1 row is connected to the common bit line CBL_i_0, and the LBL connected with the memory cell 11 in the third column of the i+1 row is connected to the common bit line CBL_i_2. At this time, CBL_i_1 and CBL_i_3 are not working, CBL_i_1 can act as a shielding line between CBL_i_0 and CBL_i_2, and CBL_i_3 can act as a shielding line between CBL_i_2 and another adjacent CBL (i.e., the CBL corresponding to the LBL of the adjacent row).

[0052] In some embodiments, as shown in FIG. 3, each of the CBLs can also be connected to a second preset voltage terminal VEQ through a first gating sub-circuit 21, the first gating sub-circuit 21 can also be connected to a first gating control line, and the first gating sub-circuit 21 is configured to be connected or disconnected between the CBL and the second preset voltage terminal VEQ (i.e., to make the CBL and the second preset voltage terminal VEQ electrically connected, or disconnected) under the control of the first gating control line. The scheme provided by the present embodiment can connect the non-target CBL to the preset voltage terminal through the first gating sub-circuit 21, so as to avoid the voltage change of the non-target LBL from interfering with the target LBL. However, the present embodiment is not limited thereto, and in other embodiments, the first gating sub-circuit 21 can be omitted.

[0053] In some embodiments, the voltage of the second preset voltage terminal VEQ can be a voltage between the voltage corresponding to the logic data "0" and the voltage corresponding to the logic data "1". For example, the voltage corresponding to the logic data "0" is 0, and the voltage corresponding to the logic data "1" is VDD, and the voltage of the second preset voltage terminal VEQ can be 1 / 2 VDD, etc.

[0054] In some embodiments, the four first gating sub-circuits 21 connected by the four CBLs corresponding to the LBLs in the same row are respectively connected to different first gating control lines, and the first gating sub-circuits 21 connected by the CBLs respectively connected to the LBLs in the same column are connected to the same first gating control line. For example, as shown in FIG. 3, the memory cell array includes N*2M LBLs, the LBL in the i-th row and the j-th column is LBL_i-1_j-1, i is 1 to N, and j is 1 to 2M, i.e., LBL_0_0 to LBL_N-1_2M-1. The first gating sub-circuits 21 connected by the CBLs respectively connected to the LBLs in the first column are all connected to the first first gating control line Ctrl_0, the first gating sub-circuits 21 connected by the CBLs respectively connected to the LBLs in the second column are all connected to the second first gating control line Ctrl_1, the first gating sub-circuits 21 connected by the CBLs respectively connected to the LBLs in the third column are all connected to the third first gating control line Ctrl_2, and the first gating sub-circuits 21 connected by the CBLs respectively connected to the LBLs in the fourth column are all connected to the fourth first gating control line Ctrl_3. The scheme provided by the present embodiment can control the CBLs connected to the LBLs in the same column at the same time, so as to facilitate the CBLs connected to the LBLs in the same column to be connected to the second preset voltage terminal VEQ at the same time when the LBLs are not working, thereby avoiding interfering with the working LBLs (i.e., the LBLs connected to the memory cells to be read and written). However, the present embodiment is not limited thereto, and the first gating sub-circuits 21 connected by the CBLs respectively connected to the LBLs in the same column can be connected to different first gating control lines.

[0055] In some embodiments, the first gating sub-circuit 21 can include a first transistor T1, a gate electrode of the first transistor T1 being connected to the first gating control line, a first electrode being connected to the CBL, and a second electrode being connected to a second preset voltage terminal VEQ. The structure of the first gating sub-circuit 21 described in the embodiment is only an example, and other circuits that can realize gating can be used, for example, a plurality of transistors can be included.

[0056] In some embodiments, the first gating sub-circuit 21 is an N-type transistor, but the embodiments of the present disclosure are not limited thereto, and the first gating sub-circuit 21 can be a P-type transistor.

[0057] When the CWL_m loads the activation signal, m is any value from 0 to M-1, at this time, the two columns of storage units 11 connected by the two word lines connected by the CWL_m are target storage units, the first gating sub-circuit 21 connected by the CBL connected by the two columns of LBLs (referred to as target LBLs, and the CBL connected by the target LBLs is referred to as a target CBL) connected by the two columns of target storage units loads a turn-off level signal on the first gating control line connected by the first gating sub-circuit 21 to turn off the two columns of target CBLs from the second preset voltage terminal VEQ, and other CBLs of the storage unit array 10 where the target storage units are located are referred to as non-target CBLs. A turn-on level signal is loaded on the first gating control line connected by the first gating sub-circuit 21 connected by the non-target CBL to connect the non-target CBL to the second preset voltage terminal VEQ, stabilize the voltage of the non-target CBL, avoid interfering with the target CBL, so that the CBL can be connected to more bit lines, and the corresponding memory can use fewer CBLs. In addition, since the CBL is connected to the sense amplifier, the number of CBLs is reduced, and the number of sense amplifiers connected by the CBLs can be reduced accordingly, so that the area occupied by the SA and the CBL can be reduced, the device density can be improved, or more space can be reserved for the peripheral circuit. For example, taking FIG. 3 as an example, when the common word line CWL_0 is activated, the target LBLs are the first column of LBLs and the third column of LBLs, at this time, the first gating control line Ctrl_0 connected by the first gating sub-circuit 21 connected by the CBL_i_0 connected by the first column of LBLs and the first gating control line Ctrl_2 connected by the first gating sub-circuit 21 connected by the CBL_i_2 connected by the third column of LBLs loads a turn-off level signal, the target CBL includes CBL_i_0 and CBL_i_2, i is 0 to N-1, the non-target CBL includes CBL_i_1 and CBL_i_3, i is 0 to N-1, and the first gating control line Ctrl_1 connected by the first gating sub-circuit 21 connected by the LBL connected by the non-target CBL and the first gating control line Ctrl_3 loads a turn-on level signal, so that CBL_i_1 and CBL_i_3, i is 0 to N-1, are in communication with the second preset voltage terminal VEQ. The scheme provided in the embodiment can connect more than 20 LBLs to one CBL, reduce the number of CBLs, and reduce the number of SAs.

[0058] The memory cell array 10 can be divided into a plurality of sub-arrays, every 4 columns of the memory cells 11 are continuously distributed as a sub-array, the 4 columns of memory cells 11 in each sub-array are connected to 4 LWLs, and the 4 LWLs are divided into two word line groups. The word line group in which the LWL connected to the memory cell 11 in the odd column is referred to as an odd column word line group, and the word line group in which the LWL connected to the memory cell 11 in the even column is referred to as an even column word line group. The CBL connected by the LBL connected to the memory cell 11 in the odd column is referred to as an odd column CBL, and the CBL connected by the LBL connected to the memory cell 11 in the even column is referred to as an even column CBL. The first control signal BLEQ_Odd is loaded on the first gating control line connected by the first gating sub-circuit 21 connected by the LBL connected to the odd column CBL, and the second control signal BLEQ_Even is loaded on the first gating control line connected by the first gating sub-circuit 21 connected by the LBL connected to the even column CBL.

[0059] When the signal CWL_Even loaded on the even column word line group is an activation signal, the second control signal BLEQ_Even loaded on the first gating control line connected by the first gating sub-circuit 21 connected by the LBL connected to the even column CBL is an off level signal, and the first control signal BLEQ_Odd loaded on the first gating control line connected by the first gating sub-circuit 21 connected by the LBL connected to the odd column CBL is an on level signal, as shown in FIG. 4.

[0060] When the signal CWL_Odd loaded on the odd column word line group is an activation signal, the first control signal BLEQ_Odd loaded on the first gating control line connected by the first gating sub-circuit 21 connected by the LBL connected to the odd column CBL is an off level signal, and the second control signal BLEQ_Even loaded on the first gating control line connected by the first gating sub-circuit 21 connected by the LBL connected to the even column CBL is an on level signal, as shown in FIG. 5.

[0061] In the above embodiment, the on level signal is taken as high level and the off level signal is taken as low level for example. However, the present embodiment is not limited thereto, and the on level signal can be low level and the off level signal can be high level.

[0062] The first control signal BLEQ_Odd and the second control signal BLEQ_Even can be generated under the control of a first enable signal BLEQ_Odd_en and a second enable signal BLEQ_Even_en, respectively. FIG. 6 is a schematic diagram of an enable circuit according to an exemplary embodiment. As shown in FIG. 6, the enable circuit can include a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5, a first inverter N1, a second inverter N2, a third inverter N3, a fourth inverter N4, a fifth inverter N5, a sixth inverter N6, a seventh inverter N7, and an eighth inverter N8. The second transistor T2 and the fourth transistor T4 can be N-type transistors, and the third transistor T3 and the fifth transistor T5 can be P-type transistors. The first electrode of the second transistor T2, the first electrode of the third transistor T3, the first electrode of the fourth transistor T4, and the first electrode of the fifth transistor T5 are connected to the first control terminal ACT. The second electrode of the second transistor T2 and the second electrode of the third transistor T3 are connected to a first node PG1. The second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5 are connected to a second node PG2. The second control terminal A0_Latch is connected to the input terminal of the first inverter N1, the gate electrode of the third transistor T3, and the gate electrode of the fourth transistor T4. The output terminal of the first inverter N1 is connected to the gate electrode of the second transistor T2. The second control terminal A0_Latch is connected to the input terminal of the second inverter N2. The output terminal of the second inverter N2 is connected to the gate electrode of the fifth transistor T5. The first node PG1 is connected to the input terminal of the third inverter N3. The output terminal of the third inverter N3 is connected to the input terminal of the fourth inverter N4 and the input terminal of the fifth inverter N5. The output terminal of the fourth inverter N4 is connected to the input terminal of the third inverter N3. The output terminal of the fifth inverter N5 outputs the first enable signal BLEQ_Odd_en. The second node PG2 is connected to the input terminal of the sixth inverter N6. The output terminal of the sixth inverter N6 is connected to the input terminal of the seventh inverter N7 and the input terminal of the eighth inverter N8. The output terminal of the seventh inverter N7 is connected to the input terminal of the sixth inverter N6. The output terminal of the eighth inverter N8 outputs the second enable signal BLEQ_Even_en.

[0063] Figure 7 is a timing diagram of the circuit shown in Figure 6. As shown in Figure 7, when the second control terminal A0_Latch loads a low-level signal, the second transistor T2 and the third transistor T3 are turned on, the signal of the first control terminal ACT is loaded to the output terminal of the fifth inverter N5, the first enable signal BLEQ_Odd_en is output, and the fourth transistor T4 and the fifth transistor T5 are turned off; when the second control terminal A0_Latch loads a high-level signal, the second transistor T2 and the third transistor T3 are turned off, the fourth transistor T4 and the fifth transistor T5 are turned on, the signal of the first control terminal ACT is loaded to the output terminal of the eighth inverter N8, the second enable signal BLEQ_Even_en is output. When the first enable signal BLEQ_Odd_en loads a high-level signal, the first control signal BLEQ_Odd is switched in level, from high level to low level, or from low level to high level; when the second enable signal BLEQ_Even_en loads a high-level signal, the second control signal BLEQ_Even is switched in level, from high level to low level, or from low level to high level. The signal of the second control terminal A0_Latch can indicate whether the odd-numbered column word line group or the even-numbered column word line group is activated. When the odd-numbered column word line group loads an activation signal, the second control terminal A0_Latch loads a low-level signal; when the even-numbered column word line group loads an activation signal, the second control terminal A0_Latch loads a high-level signal. When the odd-numbered column word line group loads an activation signal, BLEQ_Odd_en loads a high-level signal, the first control signal BLEQ_Odd is switched in level, i.e., BLEQ_Odd changes from high level to low level, the first gating sub-circuit 21 connected to the odd-numbered column CBL is turned off, the second control signal BLEQ_Even remains high level, the first gating sub-circuit 21 connected to the even-numbered column CBL is turned on, and the even-numbered column CBL is connected to the second preset voltage terminal VEQ.

[0064] When the even-numbered column word line group loads an activation signal, the second control terminal A0_Latch loads a high-level signal, BLEQ_Even_en loads a high-level signal, the second control signal BLEQ_Even is switched in level, i.e., BLEQ_Even changes from high level to low level, the first gating sub-circuit 21 connected to the even-numbered column CBL is turned off, the first control signal BLEQ_Odd remains high level, the first gating sub-circuit 21 connected to the odd-numbered column CBL is turned on, and the odd-numbered column CBL is connected to the second preset voltage terminal VEQ.

[0065] The embodiments of the present disclosure also provide an access method of the above-mentioned memory, which can include:

[0066] In a data read / write phase, according to local word lines to which two columns of target storage units to be operated are connected, an activation signal is loaded on a common word line connected to the word line group. The target storage units include two columns of storage units, and the two columns of storage units are connected to two local word lines of the same word line group.

[0067] The activation signal is a signal for turning on a transistor of a storage unit connected to a local word line connected to the common word line. The data read / write phase can include a data read phase and a data write phase.

[0068] In some embodiments, the method can further include: loading an off level signal on a first gating control line connected to a first gating subcircuit connected to a common bit line connected to two columns of target local bit lines respectively connected to the target storage units; the common bit line connected to the two columns of target local bit lines is referred to as a target common bit line, and other common bit lines of a storage unit array in which the target storage units are located are referred to as non-target common bit lines; and an on level signal is loaded on a first gating control line connected to a first gating subcircuit connected to the non-target common bit line. The scheme provided in this embodiment can stabilize the voltage of the non-target common bit line and reduce interference with the target common bit line.

[0069] In some embodiments, the method can further include: when the target storage units are odd column storage units, an off level signal is loaded on a first gating control line connected to a first gating subcircuit connected to the odd column common bit line, and an on level signal is loaded on a first gating control line connected to a first gating subcircuit connected to the even column common bit line.

[0070] When the target storage units are even column storage units, an off level signal is loaded on a first gating control line connected to a first gating subcircuit connected to the even column common bit line, and an on level signal is loaded on a first gating control line connected to a first gating subcircuit connected to the odd column common bit line.

[0071] The embodiments of the present disclosure further provide an electronic device including the memory of any of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0072] In some embodiments, the electronic device can further include a control circuit configured to access the memory according to any of the access methods described above. The control circuit can include a driver generating a control signal to the common word line, the above-mentioned enable circuit, and the like. The control circuit, together with a sense amplifier and the like, realizes access to the memory.

[0073] Although the present application has been described with reference to specific embodiments thereof, it will be apparent to one of ordinary skill in the art that a person can make modifications and variations to the described embodiments without departing from the spirit and scope of the application. Accordingly, the patent protection scope of the present application shall be defined only by the appended claims.

Claims

1. A memory, comprising: at least one memory array, a plurality of common word lines and a plurality of common bit lines; the memory array comprises a plurality of memory cell arrays stacked along a direction perpendicular to a substrate, a plurality of local bit lines extending along a direction perpendicular to the substrate and arrayed along a first direction and a second direction; the memory cell array comprises a plurality of memory cells arrayed along the first direction and the second direction, a plurality of local word lines extending along the second direction corresponding to each column of memory cells arrayed along the second direction, and the local word lines connecting the corresponding column of memory cells; the local bit lines connecting a plurality of memory cells at the same position of different layers, and the first direction and the second direction being parallel to the substrate and intersecting; a plurality of the local word lines of the same memory cell array are divided into a plurality of word line groups, each word line group connecting one common word line, and different word line groups connecting different common word lines; each word line group comprises two local word lines, and the two local word lines in the same word line group are connected to memory cells of different columns respectively; each row of local bit lines arrayed along the first direction corresponds to four common bit lines, each local bit line being connected to one common bit line, and among a plurality of local bit lines of the same row, every four continuously arrayed local bit lines are connected to different common bit lines of the four common bit lines corresponding to the row of local bit lines respectively, and the common bit lines connected by the local bit lines of the memory cells connected by the local word lines of the same word line group are not adjacent.

2. The memory of claim 1, wherein, the memory comprises a plurality of memory arrays spaced along the second direction, and adjacent memory cells share the common word lines, and among a plurality of word line groups of a memory array, the word line group in which the local word lines connected to the memory cells of odd columns are connected to the common word line of one of the two memory arrays adjacent to the memory array, and the word line group in which the local word lines connected to the memory cells of even columns are connected to the common word line of the other of the two memory arrays adjacent to the memory array.

3. The memory of claim 2, wherein, the memory cells connected by the word line groups connected to the same common word line and located in different memory arrays are in the same column.

4. The memory of claim 1, wherein, each common bit line is further connected to a second preset voltage terminal through a first gating sub-circuit, the first gating sub-circuit is connected to a first gating control line, and the first gating sub-circuit is configured to electrically connect or disconnect the common bit line and the second preset voltage terminal under the control of the first gating control line.

5. The memory of claim 4, wherein, the plurality of first gating sub-circuits connected by the plurality of common bit lines connected to the local bit lines of the same column are connected to the same first gating control line. 6.A method of accessing, applied to the memory of any one of claims 1 to 5, comprising: in a data read / write phase, loading an activation signal on a common word line connected by a word line group in which a local word line connected by a target memory cell to be operated is located, wherein the target memory cell comprises two columns of memory cells connected to two local word lines of the same word line group respectively.

7. The access method of claim 6, wherein, The memory is the memory as claimed in claim 4 or 5, and the method further comprises loading a turn-off level signal on a first gate control line connected to a first gate sub-circuit connected to a common bit line connected to two target local bit lines respectively connected to the target memory cells; the common bit line connected to the two target local bit lines respectively is referred to as a target common bit line, and other common bit lines of a memory cell array where the target memory cells are located are referred to as non-target common bit lines; a turn-on level signal is loaded on a first gate control line connected to a first gate sub-circuit connected to the non-target common bit lines.

8. The access method of claim 6, wherein, The memory is the memory as claimed in claim 4 or 5, and the method further comprises referring to a word line group where local word lines connected to memory cells in an odd column as an odd column word line group, referring to a word line group where local word lines connected to memory cells in an even column as an even column word line group, referring to a common bit line connected to local bit lines connected to memory cells in an odd column as an odd column common bit line, and referring to a common bit line connected to local bit lines connected to memory cells in an even column as an even column common bit line; When the target memory cells are memory cells in an odd column, a turn-off level signal is loaded on a first gate control line connected to a first gate sub-circuit connected to the odd column common bit lines, and a turn-on level signal is loaded on a first gate control line connected to a first gate sub-circuit connected to the even column common bit lines; When the target memory cells are memory cells in an even column, a turn-off level signal is loaded on a first gate control line connected to a first gate sub-circuit connected to the even column common bit lines, and a turn-on level signal is loaded on a first gate control line connected to a first gate sub-circuit connected to the odd column common bit lines.

9. An electronic device comprising the memory as claimed in any one of claims 1 to 5.

10. The electronic device of claim 9, wherein, The electronic device further comprises a control circuit configured to access the memory according to the access method as claimed in any one of claims 6 to 8.

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