Protection circuit and chip

Abstract

Embodiments of the present application provide a protection circuit and a chip. The protection circuit comprises: a protection module, used for turning off a first transistor when the voltage of a power supply input end is negative, turning off the first transistor and disconnecting the first transistor from the power supply input end when the absolute value of the negative voltage of the power supply input end is less than a voltage threshold of the first transistor, and connecting the power supply input end to a gate of the first transistor when the absolute value of the negative voltage of the power supply input end is greater than the voltage threshold of the first transistor and less than a voltage breakdown threshold; the first transistor, used for discharging the negative voltage to the power supply input end and disconnecting from the power supply input end when the absolute value of the negative voltage inputted from the power supply input end is greater than the voltage breakdown threshold; an ESD protector, used for discharging surge or ESD energy passing through the first transistor; and a power supply module, used for outputting a drive voltage to the first transistor so as to turn on the first transistor. In the present application, when an input voltage is negative, the protection module can protect the chip from being affected by the negative voltage.

Description

Protection circuit and chip

[0001] The present application claims priority to the Chinese patent application No. 202410820671.6 filed on June 24, 2024, entitled "Protection circuit and chip", the whole content of the above application is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of circuit, in particular to a protection circuit and chip. BACKGROUND

[0003] During the use of DC / DC or linear lithium battery charging chip, the input terminal may be connected incorrectly, negative surge or front-stage voltage stabilizing circuit failure may cause negative voltage input to the power module, resulting in damage to the power module and drop of the chip output voltage. In order to avoid human wiring errors, chip damage and chip power failure caused by surge and ESD at the chip end, it is necessary to add a protection circuit to the chip input port.

[0004] The current protection method mainly adds a circuit that can realize negative voltage protection effect and automatically restore operation when the input voltage is normal to the power input terminal, which can avoid damage to the chip under negative voltage condition.

[0005] However, in the current protection method, off-chip discrete devices are generally used to build, which increases the application cost, and only disconnects the connection of the input voltage terminal under negative voltage condition, which may cause electromagnetic field or voltage interference after the chip loses power supply, and may cause chip damage or logic error.

[0006] SUMMARY

[0007] Therefore, the embodiments of the present application provide a protection circuit and chip to at least partially solve the above problems.

[0008] According to a first aspect of the embodiments of the present application, a protection circuit is provided, comprising: a protection module, configured to turn off a first transistor when a voltage at a power input terminal is negative, turn off the first transistor when an absolute value of the negative voltage at the power input terminal is less than a voltage threshold of the first transistor, and disconnect the power input terminal; connect the power input terminal to a gate of the first transistor when the absolute value of the negative voltage at the power input terminal is greater than the voltage threshold of the first transistor and less than a voltage breakdown threshold; the first transistor, configured to discharge the negative voltage at the power input terminal when the absolute value of the negative voltage at the power input terminal is greater than the voltage breakdown threshold, and disconnect the power input terminal; an ESD protector, configured to discharge a surge or ESD energy passing through the first transistor; and a power supply module, configured to output a driving voltage to the first transistor when a voltage at the power input terminal is within a normal range, so as to turn on the first transistor.

[0009] In a possible implementation, the protection module comprises a first resistor, a second resistor, a second transistor and a third transistor; a first end of the first resistor is connected to the power input terminal, a source of the first transistor and a substrate of the first transistor; a second end of the first resistor is connected to a source of the second transistor; a drain of the second transistor and a substrate of the second transistor are connected to a source of the third transistor and a substrate of the third transistor; a gate of the second transistor is connected to a first end of the second resistor and a gate of the third transistor; a second end of the second resistor is grounded; the gate of the third transistor is connected to the first end of the second resistor; and a drain of the third transistor is connected to the power supply module and a gate of the first transistor.

[0010] In a possible implementation, the protection module further comprises a first zener diode, configured to protect the gate of the second transistor and the gate of the third transistor when a voltage value input to the second transistor and the third transistor exceeds a withstand voltage threshold of the second transistor and the third transistor; and a second zener diode, configured to protect the first transistor when the voltage value input to the power input terminal is greater than the voltage breakdown threshold.

[0011] In a possible implementation, a positive electrode of the first zener diode is connected to the drain of the second transistor, the substrate of the second transistor, the source of the third transistor and the substrate of the third transistor; a negative electrode of the first zener diode is connected to the gate of the second transistor, the gate of the third transistor, the first end of the second resistor and a positive electrode of the second zener diode; a negative electrode of the second zener diode is grounded and connected to a second end of the second resistor.

[0012] In a possible implementation, the protection module further includes a capacitor configured to protect the first transistor from breakdown when a negative ESD.

[0013] In a possible implementation, a first end of the first resistor is connected to the power input end, a source of the first transistor and a substrate of the first transistor, a second end of the first resistor is connected to a source of the second transistor, a drain of the second transistor and a substrate of the second transistor are connected to a source of the third transistor, a substrate of the third transistor and a first end of the capacitor, a gate of the second transistor is connected to a first end of the second resistor and a gate of the third transistor, the gate of the second transistor is connected to the first end of the second resistor, a second end of the capacitor and the gate of the third transistor, the gate of the third transistor is connected to the first end of the second resistor, and a drain of the third transistor is connected to the power supply module and a gate of the first transistor.

[0014] In a possible implementation, a capacitance of the capacitor satisfies the following relationship: V1=V0×[1-e^(-t / R2C)]

[0015] wherein C is used to represent the capacitance of the capacitor, V1 is used to represent a voltage difference between the gate of the second transistor and the input end, V0 is used to represent a voltage difference between the voltage coupled when the power input end is subjected to ESD and the input end, R2 is used to represent a resistance value of the second resistor, and t is used to represent a time value of the ESD current discharged by the first transistor.

[0016] In a possible implementation, the power supply module includes a charge pump configured to output a driving voltage to the first transistor, and a third resistor configured to limit a current output from the charge pump, so as to ensure that the first transistor is not turned on when an absolute value of a negative voltage input by the power input end is greater than a voltage threshold of the first transistor and less than a voltage breakdown threshold.

[0017] In a possible implementation, a resistance value of the third resistor is much greater than a sum of a resistance value of the first resistor, a turn-on impedance value of the second transistor and a turn-on impedance value of the third transistor.

[0018] In a possible implementation, the first transistor, the second transistor and the third transistor each include a parasitic diode.

[0019] According to a second aspect of the embodiment of the present application, a chip is provided, including the protection circuit according to any one of the first aspect of the embodiment.

[0020] From the above technical solutions, by setting the protection module, the chip internal voltage PMID and the later stage circuit can be protected from the influence of the negative input voltage. Since the protection circuit is set in the chip, the application cost is reduced. When the input voltage is in the normal range, the protection module is in the closed state, so it will not affect the normal operation of the circuit, and the effect of automatically switching the working mode according to the input voltage can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the present application. For those skilled in the art, other drawings can also be obtained from these drawings.

[0022] FIG. 1 is a schematic diagram of an off-chip discrete device including a negative voltage protection circuit;

[0023] FIG. 2 is a schematic diagram of a protection circuit provided by an embodiment of the present application;

[0024] FIG. 3 is a schematic diagram of another protection circuit provided by an embodiment of the present application;

[0025] FIG. 4 is a schematic diagram of a protection circuit including a first zener diode provided by an embodiment of the present application;

[0026] FIG. 5 is a circuit diagram of a protection circuit including a first zener diode provided by an embodiment of the present application;

[0027] FIG. 6 is a schematic diagram of a protection circuit including a capacitor provided by an embodiment of the present application;

[0028] FIG. 7 is a circuit diagram of a protection circuit including a capacitor provided by an embodiment of the present application;

[0029] FIG. 8 is a circuit diagram of a protection circuit including a charge pump provided by an embodiment of the present application;

[0030] FIG. 9 is a circuit diagram of a protection circuit including a parasitic diode provided by an embodiment of the present application;

[0031] FIG. 10 is a schematic diagram of a chip provided by an embodiment of the present application. DETAILED DESCRIPTION

[0032] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art shall fall within the scope of protection of the present application.

[0033] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this application and / or the appended claims, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0034] It should be understood that, although the terms first, second, third, etc. can be employed in this application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one piece of information from another piece of information of the same type. For example, the first information can also be called the second information without departing from the scope of the present application, and similarly, the second information can also be called the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon determination" or "in response to determining".

[0035] The following terms appearing in this text are explained: ESD: Electro-Static discharge, static discharge, equipment for electrostatic protection is collectively referred to as ESD protector.

[0036] Figure 1 is a schematic diagram of an off-chip discrete device including a negative voltage protection circuit. As shown in Figure 1, in order to protect the chip, a circuit capable of achieving negative voltage protection effect is installed at the power input end, which can automatically resume operation when the input voltage is normal. When the input end is connected incorrectly, negative surge or front stage voltage stabilizing circuit failure causes negative voltage input, the transistor Q is turned off, and the transistor Q is turned on again when the input voltage returns to normal, so that the circuit resumes operation.

[0037] However, during the period when the transistor Q is turned off, the voltage at the output end is pulled down, resulting in a decrease in the output voltage, which causes a power failure problem in the chip. Moreover, the off-chip discrete device increases the additional application cost. Therefore, the present application provides a protection circuit and a chip to at least partially solve the above problems.

[0038] Figure 2 is a schematic diagram of a protection circuit according to an embodiment of the present application. As shown in Figure 2, the protection circuit 100 comprises: a protection module 101, configured to turn off a first transistor 102 when a voltage input from a power input terminal is negative, turn off the first transistor 102 when an absolute value of the negative voltage input from the power input terminal is less than a voltage threshold of the first transistor 102, disconnect the first transistor 102 from the power input terminal, and connect the power input terminal and a gate of the first transistor 102 together when the absolute value of the voltage input from the power input terminal is greater than the voltage threshold of the first transistor 102 and less than a voltage breakdown threshold of the protection module 101. The first transistor 102 is configured to discharge a negative voltage input from the power input terminal and disconnect the first transistor 102 from the power input terminal when the absolute value of the negative voltage input from the power input terminal is greater than the voltage breakdown threshold. An ESD protector 103 is configured to discharge a surge or ESD energy passing through the first transistor 102. A power supply module 104 is configured to output a driving voltage to the first transistor 102 to turn on the first transistor 102 when a voltage input from the power input terminal is within a normal range.

[0039] When the absolute value of the negative voltage input from the power input terminal is less than the voltage threshold of the first transistor 102, the protection module 101 turns off the first transistor 102. When the absolute value of the negative voltage input from the power input terminal is greater than the voltage threshold of the first transistor 102, the protection module 101 connects the power input terminal and the gate of the first transistor 102 to turn off the first transistor 102, so that a chip internal voltage PMID and a subsequent circuit connected to the output terminal are not affected by the input negative voltage. When the absolute value of the negative voltage input from the power input terminal is greater than the voltage threshold of the first transistor 102 and less than the voltage breakdown threshold of the protection module 101, the protection module 101 turns off the first transistor 102 and disconnects the first transistor 102 from the power input terminal to protect the chip. At this time, the first transistor 102 is in an off state, and the chip internal voltage is not affected by the voltage input from the power input terminal. When the absolute value of the negative voltage input from the power input terminal is greater than the voltage breakdown threshold of the protection module 101, the protection module 101 starts to break down. At this time, the first transistor 102 is turned on, and the current passes through the ESD protector 103, and the first transistor 102 discharges the negative voltage or negative surge current to the power input terminal.

[0040] The ESD protector 103 can be an ESD static protection diode, when the protection circuit 100 is working normally, the ESD protector 103 is in the off state (high resistance state) and does not affect the normal work of the circuit. The first transistor 102 can be an NBL isolation tube including a source, a drain, a gate and a substrate. A transient diode (TVS) can be added in front of the input end of the protection circuit 100. When the two poles of the TVS are subjected to a reverse transient high-energy impact, the TVS changes the high impedance between the two poles to a low impedance at the order of 10 to the minus 12 power of seconds, absorbs a surge power of up to several kilowatts, and clamps the voltage between the two poles to a predetermined value, i.e. a negative voltage clamping voltage. Generally, the breakdown voltage (Off_BV) of the first transistor 102 in the off condition is greater than the negative voltage clamping voltage of the front-stage TVS. When the power input end encounters a negative surge voltage, the first transistor 102 and the ESD protector 103 can generate a negative surge current.

[0041] When the voltage input by the power input end is in the normal range, the power supply module 104 outputs a driving voltage for driving the first transistor 102 to work, for example, the driving voltage can be 5V, so that the first transistor 102 works in the deep linear region, and at this time the protection module 101 is in the off state.

[0042] The application can protect the internal voltage PMID and the rear-stage circuit of the chip from the influence of the input negative voltage by setting the protection module 101. Since the protection circuit 100 is arranged in the chip, the application cost is reduced. When the input voltage is in the normal range, the protection module 101 is in the off state, so it does not affect the normal operation of the circuit, and the effect of automatically switching the working mode according to the input voltage can be achieved.

[0043] Fig. 3 is a schematic diagram of another protection circuit according to an embodiment of the present application. As shown in Fig. 3, in the protection circuit 100, the protection module 101 can further include a first resistor 1011, a second resistor 1012, a second transistor 1013 and a third transistor 1014. The first end of the first resistor 1011 is connected to the power input end, the source of the first transistor 102 and the substrate of the first transistor 102. The second end of the first resistor 1011 is connected to the source of the second transistor 1013. The drain of the second transistor 1013 and the substrate of the second transistor 1013 are connected to the source of the third transistor 1014 and the substrate of the third transistor 1014. The gate of the second transistor 1013 is connected to the first end of the second resistor 1012 and the gate of the third transistor 1014. The second end of the second resistor 1012 is grounded. The gate of the third transistor 1014 is connected to the first end of the second resistor 1012. The drain of the third transistor 1014 is connected to the power supply module 104 and the gate of the first transistor 102.

[0044] The second transistor 1013 and the third transistor 1014 are the same NBL isolation tube as the first transistor 102. When a negative voltage or a negative surge is encountered at the power input port, the gate voltage of the second transistor 1013 is GND because the gate of the second transistor 1013 is terminated to GND through the second resistor 1012. When the absolute value of the negative voltage at the power input end is less than the threshold voltage of the NBL isolation tube, the second transistor 1013 and the third transistor 1014 are both closed together with the first transistor 102, so that the internal voltage PMID of the chip and the subsequent circuit connected to the output end are not affected by the negative voltage. When the absolute value of the negative voltage at the power input end is greater than the threshold voltage of the NBL isolation tube and less than the voltage breakdown threshold of the first transistor 102, the second transistor 1013 and the third transistor 1014 start to conduct, connecting the power input end and the gate of the first transistor 102 together, so that the voltage of the first transistor 102 is less than the threshold voltage, and the first transistor 102 is in the off state, so that the internal voltage of the chip is not affected by the negative voltage.

[0045] Taking the first transistor 102 with strong voltage discharge capability as an example, when a negative voltage is applied at the power input end, the voltage at the power input end will instantaneously become negative. The protection module 101 will close the first transistor 102, and the voltage at the power input end will continue to decrease until the first transistor 102 triggers the Off_BV state. At this time, the energy of the ESD protector 103 is discharged through the breakdown of the first transistor 102.

[0046] When the voltage at the power input end is in the normal range, the voltage difference between the gate of the second transistor 1013 and the gate of the third transistor 1014 and the power input end is less than the threshold voltage, so they are both in the closed state, and the protection module 101 does not work.

[0047] The application can make the protection module 101 not work when the voltage at the power input end is in a normal range, ensure normal operation of the circuit, and when negative voltage or negative surge is encountered at the power input end, the protection module 101 will close the first transistor 102, thereby avoiding the negative voltage or negative surge from flowing into the back-end circuit of the chip, and protecting the chip.

[0048] FIG. 4 is a schematic diagram of a protection circuit including a first zener diode according to an embodiment of the application. As shown in FIG. 4, in the protection circuit 100, the protection module 101 can further include: a first zener diode 1015, configured to protect the gate of the second transistor 1013 and the gate of the third transistor 1014 when the voltage value input to the second transistor 1013 and the third transistor 1014 exceeds the withstand voltage threshold of the second transistor 1013 and the third transistor 1014; and a second zener diode 1016, configured to protect the first transistor 102 when the absolute value of the voltage at the power input end is greater than the voltage breakdown threshold.

[0049] When the absolute value of the negative voltage at the power input end is greater than the voltage breakdown threshold of the protection module 101, the first zener diode 1015 and the second zener diode 1016 start to break down, a voltage difference ΔV=Izener*R1 is generated on the first resistor 1011, and the first transistor 102 is thus turned on. Therefore, by setting the first zener diode 1015 and the second zener diode 1016, the first transistor 102, the second transistor 1013 and the third transistor 1014 can be protected.

[0050] The application can protect the second transistor 1013 and the third transistor 1014 from being broken down when the absolute value of the input negative voltage is too large by setting the first zener diode 1015, and can protect the first transistor 102 by setting the second zener diode 1016. In order to improve safety, the number of the second zener diode 1016 can be adaptively adjusted to better protect the first transistor 102.

[0051] Specifically, FIG. 5 is a circuit diagram of a protection circuit including a first zener diode according to an embodiment of the application. In some embodiments, as shown in FIG. 5, the anode of the first zener diode 1015 in the protection module 101 is connected with the drain of the second transistor 1013, the substrate of the second transistor 1013, the source of the third transistor 1014, and the substrate of the third transistor 1014, the cathode of the first zener diode 1015 is connected with the gate of the second transistor 1013, the gate of the third transistor 1014, the first end of the second resistor 1012, and the anode of the second zener diode 1016, the cathode of the second zener diode 1016 is grounded and connected with the second end of the second resistor 1012.

[0052] A first Zener diode 1015 and at least one second Zener diode 1016 can be arranged in the protection module 101, and the first Zener diode 1015 and the second Zener diode 1016 are the same Zener diode. As shown in FIG. 5, two second Zener diodes 1016 are arranged in the protection module 101, and the voltage breakdown threshold of the protection module 101 is 3*Vzener, where Vzener is the breakdown voltage of the Zener diode. When the absolute value of the negative voltage at the power input end is greater than 3*Vzener, the first Zener diode 1015 and the second Zener diode 1016 start to break down, and a relatively large current flows from GND to the power input end through the first Zener diode 1015 and the second Zener diode 1016, thereby generating a voltage difference ΔV=Izener*R1 on the first resistor 1011, where R1 is the resistance value of the first resistor 1011. At this time, the voltage of the first transistor 102 is greater than the threshold voltage, and the first transistor 102 is turned on. The current flows through the ESD protector 103, and the first transistor 102 discharges the negative voltage or negative surge current to the power input port. In order to protect the first transistor 102 from being broken down, it is necessary to ensure that the Off_BV voltage of the first transistor 102 is greater than 3*Vzener.

[0053] FIG. 6 is a schematic diagram of a protection circuit including a capacitor according to an embodiment of the present application. As shown in FIG. 6, the protection module 101 in the protection circuit 100 can further include a capacitor 1017 for protecting the first transistor 102 from being broken down when the port encounters negative ESD.

[0054] When the voltage discharge capability of the first transistor 102 is weak, the capacitor 1017 can be arranged in the protection module 101. When the power input end encounters negative ESD, the voltage output by the power input end will instantaneously become negative. At this time, the first transistor 102 is in the on state, so the gate voltage of the second transistor 1013 is coupled to be low, so that the voltage of the second transistor 1013 is about equal to 0V. The second transistor 1013 and the third transistor 1014 are in the off state, so that the gate voltage of the first transistor 102 cannot be discharged to the power input end through the protection module 101, and the first transistor 102 is in the on state. The energy output by the ESD protector 103 is discharged through the channel of the first transistor 102, so as to prevent the first transistor 102 from being in the On_BV or Off_BV state.

[0055] The capacitor 1017 arranged in the protection module 101 can protect the first transistor 102 when the ESD discharge capability of the first transistor 102 is weak.

[0056] Specifically, FIG. 7 is a circuit diagram of a protection circuit including a capacitor according to an embodiment of the present application. As shown in FIG. 7, in the voltage protection circuit 100, a first end of a first resistor 1011 is connected to a power input end, a source of a first transistor 102, and a substrate of the first transistor 102, a second end of the first resistor 1011 is connected to a source of a second transistor 1013, a drain of the second transistor 1013, and a substrate of the second transistor 1013 are connected to a source of a third transistor 1014, a substrate of the third transistor 1014, and a first end of a capacitor 1017, a gate of the second transistor 1013 is connected to a first end of a second resistor 1012 and a gate of the third transistor 1014, the gate of the second transistor 1013 is connected to the first end of the second resistor 1012, a second end of the capacitor 1017, and the gate of the third transistor 1014, a gate of the third transistor 1014 is connected to the first end of the second resistor 1012, and a drain of the third transistor 1014 is connected to a power supply module 104 and a gate of the first transistor 102.

[0057] When the power input end encounters a negative ESD, the voltage output by the power input end will instantaneously become negative. Due to the existence of the parasitic capacitance of the first transistor 102, the gate voltage of the first transistor 102 will be coupled to a higher voltage Vgs=(Vin-Vdio)*Cgd / (Cgs+Cgd), where Vin is the voltage output by the power input end, Vdio is the forward voltage of the ESD protector 103, and Cgs and Cgd are the capacitance values of the parasitic capacitance of the first transistor 102. At this time, the first transistor 102 is in a conducting state. Since the voltage of the capacitor 1017 cannot change abruptly, the gate voltage of the second transistor 1013 will be coupled to be low, so that the voltage value of the second transistor 1013 is approximately equal to 0V, and thus the second transistor 1013 and the third transistor 1014 are in an off state.

[0058] In a feasible manner, the capacitance value of the capacitor 1017 can satisfy the following relationship: V1=V0*[1-e^(-t / R2C)]

[0059] Where C is used to represent the capacitance value of the capacitor 1017, V1 is used to represent the voltage difference between the gate of the second transistor 1013 and the input end, V0 is used to represent the voltage difference coupled when the power input end encounters a negative ESD, R2 is used to represent the resistance value of the second resistor 1012, and t is used to represent the time value of the first transistor 102 discharging a negative ESD current.

[0060] In order to ensure that the energy of the ESD protector 103 can be discharged from the channel of the first transistor 102, it is required to ensure that the protection module 101 cannot turn on the second transistor 1013 before the energy of the ESD protector 103 is discharged, so the value of R2*C is required to ensure that V1 is less than the voltage threshold of the first transistor 102 before the energy of the ESD protector 103 is discharged.

[0061] It is required to note that in order to prevent the first transistor 102 from being turned on under the negative surge condition and affecting the internal voltage of the chip, the value of R2*C cannot be too large, for example, R2 can be 50K, the energy discharge time t of the ESD protector 103 is about 200ns, and then the value of C is about 4pF. Controlling the value of R2*C within a reasonable range can prevent the protection module 101 from not being able to turn off the first transistor 102 in time when the voltage input at the power input end suddenly becomes negative, so that the internal voltage of the chip can be affected by the negative voltage input at the power input end.

[0062] The application determines the set value of the capacitor through the voltage of the second transistor 1013 when the ESD protector 103 discharges energy, which can ensure that the voltage of the second transistor 1013 is less than the voltage threshold of the first transistor 102 before the energy of the ESD protector 103 is discharged, so that the energy of the ESD protector 103 can be discharged from the first transistor 102.

[0063] FIG. 8 is a circuit diagram of a protection circuit including a charge pump according to an embodiment of the application. As shown in FIG. 8, the power supply module 104 in the protection circuit 100 can further include a charge pump 1041 for outputting a driving voltage to the first transistor 102. A third resistor 1042 is used to ensure that the first transistor 102 is not turned on when the absolute value of the negative voltage at the power input end is greater than the voltage threshold of the first transistor and less than the voltage breakdown threshold. The output end of the charge pump 1041 is connected with the first end of the third resistor 1013, and the second end of the third resistor 1042 is connected with the drain of the second transistor 1013 and the gate of the first transistor 102.

[0064] The charge pump 1041 (CP) is a switched capacitor voltage converter, which is a DC-DC converter that uses "flying" or "pumping" capacitors (rather than inductors or transformers) to store energy.

[0065] When the absolute value of the negative voltage inputted by the power input end is greater than the threshold voltage of the first transistor 102 and less than the voltage breakdown threshold of the protection module 101, the second transistor 1013 and the third transistor 1014 start to conduct, connecting the power input end and the gate of the first transistor 102 together, at this time, the voltage of the first transistor 102 is less than the threshold voltage, and the first transistor 102 is in the off state, so that the internal voltage of the chip is not affected by the negative voltage inputted by the power input end.

[0066] The power supply module 104 of the present application can play a role of voltage division by including the third resistor 1042, thereby ensuring that the first transistor 102 is in the off state when the absolute value of the negative voltage inputted by the power input end is greater than the threshold voltage of the first transistor 102 and less than the voltage breakdown threshold of the protection module 101.

[0067] In a feasible manner, the resistance value of the third resistor 1042 is greater than the sum of the resistance value of the first resistor 1011, the on-resistance value of the second transistor 1013 and the on-resistance value of the third transistor 1014.

[0068] When the absolute value of the negative voltage inputted by the power input end is greater than the threshold voltage of the first transistor 102 and less than the voltage breakdown threshold of the protection module 101, the voltage Vgs3 of the first transistor 102 is Vgs3=|Vin|*(R1+Rdson1+Rdson2) / (R3+R1+Rdson1+Rdson2), Vin is the voltage inputted by the power input end, Rdson1 and Rdson2 are the on-resistance of the second transistor 1013 and the third transistor 1014 respectively, R1 is the resistance value of the first resistor 1011, and R3 is the resistance value of the third resistor 1042. In order to ensure that the first transistor 102 will not conduct, it is necessary to make R1+Rdson1+Rdson2<<R3.

[0069] By setting the resistance value of the third resistor 1042 to be greater than the sum of the resistance value of the first resistor 1011, the on-resistance value of the second transistor 1013 and the on-resistance value of the third transistor 1014, the present application can ensure that the first transistor 102 will not conduct when the absolute value of the negative voltage inputted by the power input end is greater than the threshold voltage of the first transistor 102 and less than the voltage breakdown threshold of the protection module 101, thereby protecting the subsequent circuit of the chip.

[0070] FIG. 9 is a circuit diagram of a protection circuit including a parasitic diode according to an embodiment of the present application. As shown in FIG. 9, the first transistor 102, the second transistor 1013 and the third transistor 1014 all include a parasitic diode.

[0071] When the power input end encounters positive ESD or positive surge, the energy is discharged to GND through the parasitic diode of the first transistor 102 via the ESD protector 103, avoiding damage to the chip back-end circuit by high voltage.

[0072] The application can protect the loops of the first transistor 102, the second transistor 1013 and the third transistor 1014 by setting the parasitic diodes of the first transistor 102, the second transistor 1013 and the third transistor 1014, and improve the safety of the protection circuit 100.

[0073] FIG. 10 is a schematic diagram of a chip according to an embodiment of the application. As shown in FIG. 10, the application provides a chip 200, which comprises the protection circuit 100 of any one of the foregoing protection circuit embodiments.

[0074] It should be noted that the various embodiments described in the application and / or the technical features in the various embodiments can be combined with each other arbitrarily without conflict, and the technical solutions obtained after combination should also fall within the protection scope of the application.

[0075] It should be understood that the specific examples in the embodiments of the application are only to help those skilled in the art better understand the embodiments of the application, and not to limit the scope of the embodiments of the application, and those skilled in the art can make various improvements and modifications on the basis of the above embodiments, and these improvements or modifications all fall within the protection scope of the application.

[0076] The above is only a specific implementation of the application, but the protection scope of the application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the application, which should be covered within the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.

Claims

1. A protection circuit, characterized by, The application relates to an ESD protection device and a method for protecting a first transistor from ESD. The protection module is used for turning off the first transistor when the voltage of the power input end is negative, turning off the first transistor when the absolute value of the negative voltage of the power input end is smaller than the voltage threshold of the first transistor, and disconnecting the connection between the power input end and the first transistor when the absolute value of the negative voltage of the power input end is greater than the voltage threshold of the first transistor and smaller than a voltage breakdown threshold. The first transistor is used for discharging the negative voltage of the power input end when the absolute value of the negative voltage of the power input end is greater than the voltage breakdown threshold, and disconnecting the connection between the power input end and the first transistor. The ESD protector is used for discharging the surge or ESD energy through the first transistor. The power supply module is used for outputting a driving voltage to the first transistor when the voltage of the power input end is in a normal range, so that the first transistor is turned on.

2. The circuit of claim 1, wherein, The protection module comprises a first resistor, a second resistor, a second transistor and a third transistor. The first end of the first resistor is connected with the power input end, the source of the first transistor and the substrate of the first transistor, the second end of the first resistor is connected with the source of the second transistor, the drain of the second transistor and the substrate of the second transistor are connected with the source of the third transistor and the substrate of the third transistor, the gate of the second transistor is connected with the first end of the second resistor and the gate of the third transistor, the second end of the second resistor is grounded, the gate of the third transistor is connected with the first end of the second resistor, and the drain of the third transistor is connected with the power supply module and the gate of the first transistor.

3. The circuit of claim 2, wherein, The protection module further comprises: The first voltage stabilizing diode is used for protecting the gate of the second transistor and the gate of the third transistor when the voltage value input into the second transistor and the third transistor exceeds the bearing voltage threshold of the second transistor and the third transistor. The second voltage stabilizing diode and the first voltage stabilizing diode are used for protecting the first transistor when the voltage value input into the power input end is greater than the voltage breakdown threshold.

4. The circuit of claim 3, wherein, The anode of the first voltage stabilizing diode is connected with the drain of the second transistor, the substrate of the second transistor, the source of the third transistor and the substrate of the third transistor, the cathode of the first voltage stabilizing diode is connected with the gate of the second transistor, the gate of the third transistor, the first end of the second resistor and the anode of the second voltage stabilizing diode, the cathode of the second voltage stabilizing diode is grounded and connected with the second end of the second resistor.

5. The circuit of claim 4, wherein, The protection module further comprises: The capacitor is used for protecting the first transistor from being broken down when a negative ESD occurs.

6. The circuit of claim 5, wherein, The first end of the first resistor is connected to the power input end, the source of the first transistor and the substrate of the first transistor, the second end of the first resistor is connected to the source of the second transistor, the drain of the second transistor and the substrate of the second transistor are connected to the source of the third transistor, the substrate of the third transistor and the first end of the capacitor, the gate of the second transistor is connected to the first end of the second resistor and the gate of the third transistor, the gate of the second transistor is connected to the first end of the second resistor, the second end of the capacitor and the gate of the third transistor, the gate of the third transistor is connected to the first end of the second resistor, and the drain of the third transistor is connected to the power supply module and the gate of the first transistor.

7. The circuit of claim 6, wherein, The capacitance value of the capacitor satisfies the following relationship: V1=V0×[1-e^(-t / R2C)] Wherein, C is used to represent the capacitance value of the capacitor, V1 is used to represent the voltage difference between the gate of the second transistor and the input end, V0 is used to represent the voltage difference between the voltage coupled when the power input end is negative ESD and the input end, R2 is used to represent the resistance value of the second resistor, and t is used to represent the time value of the first transistor discharging negative ESD current.

8. The circuit of claim 2, wherein, The power supply module comprises: a charge pump for outputting a driving voltage to the first transistor; a third resistor for limiting the current from the charge pump, when the absolute value of the negative voltage of the power input end is greater than the voltage threshold of the first transistor and less than the voltage breakdown threshold, the first transistor is ensured not to be turned on; the output end of the charge pump is connected to the first end of the third resistor, and the second end of the third resistor is connected to the drain of the second transistor and the gate of the first transistor.

9. The circuit of claim 8, wherein, The resistance value of the third resistor is greater than the sum of the resistance value of the first resistor, the on-resistance value of the second transistor and the on-resistance value of the third transistor.

10. The circuit of any one of claims 1-9, wherein, The first transistor, the second transistor and the third transistor all include a parasitic diode.

11. A chip, characterized by The protection circuit comprises any one of claims 1-10. The protection circuit comprises any one of claims 1-10.

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