Semiconductor structure and manufacturing method therefor

Abstract

A semiconductor structure and a manufacturing method therefor. The method comprises: forming a stacked layer on a substrate; forming a plurality of lower electrodes in the stacked layer, wherein each lower electrode comprises a main body portion located in the stacked layer and an extension portion protruding from the stacked layer; etching the extension portion, such that the horizontal width of the extension portion is less than the horizontal width of the main body portion; sequentially forming a dielectric layer and a conductive film layer on the stacked layer, wherein the dielectric layer and the conductive film layer cover the extension portion; etching the conductive film layer to expose the stacked layer, and forming a plurality of conductive support layers; etching the stacked layer to expose the main body portion; forming a dielectric layer on the main body portion; and forming an upper electrode on the dielectric layer. The manufacturing method has a simple process.

Description

Semiconductor structure and manufacturing method thereof

[0001] The present application claims priority to the Chinese patent application No. 202410853846.3, filed on June 27, 2024, and entitled "Semiconductor structure and manufacturing method thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0003] Dynamic Random Access Memory (DRAM) is a kind of semiconductor memory widely used in computer systems. As one of the necessary structures in DRAM, the capacitor has the functions of voltage adjustment and filtering in the circuit, and is widely used in integrated circuits.

[0004] With the development of preparation process, the size of the capacitor hole is getting smaller and smaller, and the distance is also getting smaller and smaller, and the process difficulty of forming the capacitor structure also increases.

[0005] SUMMARY

[0006] According to a first aspect of embodiments of the present disclosure, a manufacturing method of a semiconductor structure is provided, comprising:

[0007] forming a stack on a substrate;

[0008] forming a plurality of lower electrodes in the stack, the lower electrodes comprising a main body part located in the stack and an extension part protruding from the stack;

[0009] etching the extension part so that the horizontal width of the extension part is smaller than the horizontal width of the main body part;

[0010] forming a dielectric layer and a conductive film layer on the stack in sequence, the dielectric layer and the conductive film layer covering the extension part;

[0011] etching the conductive film layer to expose the stack and form a plurality of conductive support layers;

[0012] etching the stack to expose the main body part;

[0013] forming a dielectric layer on the main body part;

[0014] forming an upper electrode on the dielectric layer.

[0015] In some embodiments, the step of forming a stack comprises:

[0016] forming a bottom support layer on the substrate;

[0017] forming a first sacrificial layer on the bottom support layer;

[0018] forming an intermediate support layer on the first sacrificial layer;

[0019] forming a second sacrificial layer on the intermediate support layer.

[0020] In some embodiments, the step of forming the lower electrode comprises:

[0021] forming a mask layer on the second sacrificial layer;

[0022] etching the stack according to the mask layer to form a capacitor hole in the stack;

[0023] forming a lower electrode in the capacitor hole;

[0024] removing part of the second sacrificial layer to make the lower electrode protrude out of the stack.

[0025] In some embodiments, the step of removing part of the second sacrificial layer comprises:

[0026] removing part of the second sacrificial layer by dry etching to form the extension;

[0027] wherein the height of the extension is substantially the same as the thickness of the intermediate support layer.

[0028] In some embodiments, the lower electrode is formed by filling the capacitor hole with a lower electrode material; the lower electrode comprises:

[0029] a plurality of first lower electrodes;

[0030] a plurality of second lower electrodes;

[0031] wherein the spacing between adjacent first lower electrodes is smaller than the spacing between adjacent second lower electrodes.

[0032] In some embodiments, the step of forming the conductive support layer comprises:

[0033] removing the conductive film layer between the extensions to expose the dielectric layer on the sidewalls of the extensions and to expose the stack;

[0034] removing the dielectric layer on the sidewalls of the extensions to expose the sidewalls of the extensions.

[0035] In some embodiments, the step of forming the conductive support layer comprises: removing a portion of the conductive film layer between adjacent first lower electrodes to expose the second sacrificial layer between adjacent first lower electrodes.

[0036] In some embodiments, the step of forming the upper electrode comprises:

[0037] depositing an upper electrode material on the dielectric layer, the upper electrode material also on the conductive support layer;

[0038] wherein the dielectric layer is between the upper electrode material and the conductive support layer.

[0039] In some embodiments, further comprising forming an upper plate on the conductive support layer, the upper plate in contact with the upper electrode on the conductive support layer.

[0040] In some embodiments, the upper plate also extends between adjacent body portions to contact the upper electrode between the body portions.

[0041] According to a second aspect of embodiments of the present disclosure, there is provided a semiconductor structure comprising:

[0042] a substrate;

[0043] a plurality of lower electrodes on the substrate, the lower electrodes comprising body portions and extension portions, the extension portions having a horizontal width smaller than a horizontal width of the body portions;

[0044] an intermediate support layer on a middle region of the body portions;

[0045] a conductive support layer on the extension portions, the conductive support layer having a dielectric layer between the conductive support layer and the extension portions;

[0046] a conductive pillar on the conductive support layer.

[0047] In some embodiments, the dielectric layer is also on the body portions, and an upper electrode is disposed on the dielectric layer.

[0048] In some embodiments, the conductive support layer extends between the lower electrodes to contact the upper electrode between the lower electrodes.

[0049] In some embodiments, the conductive support layer protrudes from the upper electrode.

[0050] In some embodiments, the conductive support layer has a thickness greater than a thickness of the intermediate support layer.

[0051] To sum up, the embodiment of the present disclosure proposes a semiconductor structure and a manufacturing method thereof. First, a lower electrode is formed in a stack, then an extension of the lower electrode is etched, so that the horizontal width of the extension is less than the horizontal width of the main body part, that is, the spacing between the extensions is increased, then a conductive support layer is formed on the extension, the lower electrode is supported by the conductive support layer, then the stack structure exposed by the conductive support layer is etched, so as to expose the main body part, and then a dielectric layer and an upper electrode are formed on the main body part, so as to form a capacitor structure. In the embodiment of the present disclosure, before the conductive support layer is formed, the extension is etched first, so that the horizontal width of the extension is reduced, and at the same time, the integrity of the main body part is ensured due to the blocking effect of the stack structure. After the main body part is exposed, the horizontal width of the extension is reduced, and the horizontal width of the extension is increased, which is beneficial to depositing the dielectric layer and the upper electrode on the main body part, so as to ensure the integrity of the capacitor, and the process is simple. BRIEF DESCRIPTION OF DRAWINGS

[0052] FIG. 1 is a schematic diagram of lateral etching of a top support layer during an etching process, according to an example embodiment;

[0053] FIG. 2 is a schematic diagram of lower electrode material connection, according to an example embodiment;

[0054] FIG. 3 is a schematic diagram of a residual first sacrificial layer, according to an example embodiment;

[0055] FIG. 4 is a flow chart of a manufacturing method of a semiconductor structure, according to an example embodiment;

[0056] FIG. 5 is a schematic diagram of forming a stack, according to an example embodiment;

[0057] FIG. 6 is a schematic diagram of forming a capacitor hole, according to an example embodiment;

[0058] FIG. 7 is a simplified top view of FIG. 6, according to an example embodiment;

[0059] FIG. 8 is another schematic diagram of forming a capacitor hole, according to an example embodiment;

[0060] FIG. 9 is a schematic diagram of filling an upper electrode material, according to an example embodiment;

[0061] FIG. 10 is a schematic diagram of forming a lower electrode, according to an example embodiment;

[0062] FIG. 11 is a simplified top view of FIG. 10, according to an example embodiment;

[0063] FIG. 12 is another schematic diagram of forming a lower electrode, according to an example embodiment;

[0064] FIG. 13 is a schematic view of the extension after etching, according to an exemplary embodiment;

[0065] FIG. 14 is a schematic view of forming a conductive film layer, according to an exemplary embodiment;

[0066] FIG. 15 is an enlarged view of the dashed line box in FIG. 14, according to an exemplary embodiment;

[0067] FIG. 16 is a schematic view of forming a conductive support layer, according to an exemplary embodiment;

[0068] FIG. 17 is a schematic view of forming an upper electrode, according to an exemplary embodiment;

[0069] FIG. 18 is a schematic view of the position of a dielectric layer, according to an exemplary embodiment;

[0070] FIG. 19 is a schematic view of removing a surface upper electrode, according to an exemplary embodiment;

[0071] FIG. 20 is a schematic view of forming an upper plate, according to an exemplary embodiment;

[0072] FIG. 21 is a schematic view of a semiconductor structure, according to an exemplary embodiment;

[0073] FIG. 22 is a schematic view of a second lower electrode, according to an exemplary embodiment;

[0074] FIG. 23 is a schematic view of an electronic device, according to an exemplary embodiment. DETAILED DESCRIPTION

[0075] The technical solutions of the present disclosure will be described in further detail below with reference to the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0076] The present disclosure will be described in more detail in the following paragraphs with reference to the accompanying drawings and embodiments. The advantages and features of the present disclosure will be more apparent from the following description and claims. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only to facilitate, clarify the purpose of assisting the description of the embodiments of the present disclosure.

[0077] It will be understood that the terms "on," "over," and "above" in the disclosure are to be interpreted in the broadest context possible so as to mean not only "on" something with no intervening intermediate structure or layer therebetween (i.e., directly on something), but also to include "on" something with intervening intermediate structure or layers therebetween.

[0078] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence.

[0079] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Further, the layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0080] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0081] As shown in FIG. 1, in some embodiments, when forming the columnar capacitor structure, a bottom support layer 102, a first sacrificial layer 103, an intermediate support layer 104, a second sacrificial layer 105, a top dielectric layer 1051, and a mask layer 106 can be sequentially formed on a substrate 101. Then, according to the mask layer 106, the top dielectric layer 1051, the second sacrificial layer 105, the intermediate support layer 104, the first sacrificial layer 103, and the bottom support layer 102 are etched in sequence, thereby forming a capacitor hole 107. In some embodiments, the material of the mask layer 106 is polysilicon, and the material of the top dielectric layer 1051 is silicon nitride. When the mask layer 106 is removed using etching gas, the etching gas has a large difference in etching selectivity between polysilicon and silicon nitride when forming the capacitor hole 107, and the top dielectric layer 1051 is etched by the etching gas all the time when etching downward, that is, the top dielectric layer 1051 is etched for a long time, so that the top dielectric layer 1051 has a certain side etching, thereby forming a groove 1071 on the top dielectric layer 1051.

[0082] As shown in FIGS. 2-3, in some embodiments, recesses 1071 are formed in some top dielectric layers 1051, and in more serious cases, the top dielectric layers 1051 are consumed by etching gas, so that when the lower electrode material 108 is filled in the capacitor holes 107, the lower electrode material 108 is interconnected in the areas where the top dielectric layers 1051 are consumed (in the dashed box in FIG. 3), i.e., the subsequent lower electrode is interconnected, resulting in a short circuit of the capacitor. At the same time, due to the interconnection of the lower electrode material 108, it is not possible to open a hole in this part of the lower electrode material 108, so that the first sacrificial layer 103 located below the lower electrode material 108 cannot be completely removed, i.e., part of the first sacrificial layer 103 remains, thus preventing the filling of the dielectric layer and the upper electrode in these areas, thereby damaging the integrity of the capacitor structure and reducing the capacitance.

[0083] As shown in FIG. 1, in some embodiments, researchers have also found that during the formation of the capacitor holes 107, as the aspect ratio of the capacitor holes becomes larger and larger, the spacing between some capacitor holes 107 becomes smaller than the spacing between other capacitor holes 107, which is also not conducive to the subsequent filling of the dielectric layer and the upper electrode, affecting the integrity of the capacitor structure.

[0084] As shown in FIG. 4, to improve the above problems, embodiments of the present disclosure propose a manufacturing method of a semiconductor structure, which can be used to manufacture a columnar capacitor, is conducive to the filling of the dielectric layer and the upper electrode, and simplifies the manufacturing process of the capacitor structure. The manufacturing method comprises:

[0085] S1: forming a stack on a substrate;

[0086] S2: forming a plurality of lower electrodes in the stack, the lower electrodes comprising a main body portion located in the stack and an extension portion protruding from the stack;

[0087] S3: etching the extension portion so that the horizontal width of the extension portion is smaller than the horizontal width of the main body portion;

[0088] S4: sequentially forming a dielectric layer and a conductive film layer on the stack, the dielectric layer and the conductive film layer covering the extension portion;

[0089] S5: etching the conductive film layer to expose the stack and form a plurality of conductive support layers;

[0090] S6: etching the stack to expose the main body portion;

[0091] S7: forming a dielectric layer on the main body portion, and forming an upper electrode on the dielectric layer.

[0092] As shown in FIG. 5, in step S1, a substrate 101 is first provided, and then a bottom support layer 102, a first sacrificial layer 103, an intermediate support layer 104, and a second sacrificial layer 105 are sequentially formed on the substrate 101, that is, the stack 10 is formed on the substrate 101. The substrate 10 can include silicon, germanium, silicon germanium, or a group III-V compound semiconductor (e.g., GaP, GaAs). In some embodiments, the substrate 10 can be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Structures such as word lines, bit lines, and the like can be included in the substrate 101.

[0093] As shown in FIG. 5, the stack 10 can be formed by a physical vapor deposition, chemical vapor deposition, or atomic layer deposition process. In embodiments of the present disclosure, the bottom support layer 102 and the intermediate support layer 104 can be of the same material, and the first sacrificial layer 103 and the second sacrificial layer 105 can be of the same material. The bottom support layer 102 and the intermediate support layer 104 are partially retained in subsequent etching processes and can support the lower electrode. The first sacrificial layer 103 and the second sacrificial layer 105 are completely removed in subsequent processes. The first sacrificial layer 103 and the second sacrificial layer 105 can be a material such as phosphoro silicate glass (PSG), boro phospho silicate glass (BPSG), or fluoro silicate glass (FSG) that is relatively soft; and the bottom support layer 102 and the intermediate support layer 104 can be a nitride such as silicon nitride, silicon carbon nitride, silicon oxynitride, or silicon boron nitride. phospho silicate Glass, FSG, etc.

[0094] As shown in FIG. 5, in embodiments of the present disclosure, the first sacrificial layer 103 and the second sacrificial layer 105 are substantially the same thickness, the bottom support layer 102 and the intermediate support layer 104 are substantially the same thickness, and the first sacrificial layer 103 is thicker than the bottom support layer 103. The first sacrificial layer 103 is thick, and both the first sacrificial layer 103 and the second sacrificial layer 105 are removed in subsequent processes, thereby increasing the capacitance. The thickness of the first sacrificial layer 103 can be 300-1000 nm, such as 400, 500, 600, 700, 800, 900 nm. The thickness of the bottom support layer 102 can be 10-80 nm, such as 20, 30, 40, 50, 60, 70 nm.

[0095] As shown in FIG. 5, after the stack 10 is formed, a mask layer 106 is formed directly on the stack 10, i.e., the mask layer 106 is formed directly on the second sacrificial layer 105. Then the mask layer 106 is patterned, so that the second sacrificial layer 105 can be exposed. In the embodiments of the present disclosure, the material of the mask layer 106 can be polysilicon. When the stack 10 is etched according to the mask layer 106, since the material of the second sacrificial layer 105 is silicon oxide, the etching selectivity of the etching gas for polysilicon and silicon oxide is small, so that the silicon oxide cannot be laterally etched. In the embodiments of the present disclosure, by forming the mask layer 106 directly on the second sacrificial layer 105, that is, the stack 10 does not include a top dielectric layer, so that the problem of subsequent lower electrode material connection can be prevented.

[0096] As shown in FIGS. 6-8, in step S2, the stack 10 is etched according to the mask layer 106, i.e., the second sacrificial layer 105, the intermediate support layer 104, the first sacrificial layer 103 and the bottom support layer 102 are etched, i.e., the capacitor holes 107 are formed in the stack 10. In some embodiments, the stack 10 can be etched by dry etching, i.e., part of the second sacrificial layer 105, part of the intermediate support layer 104, part of the first sacrificial layer 103 and part of the bottom support layer 102 are removed by dry etching. When etching, a large number of capacitor holes 107 are formed. Since the aspect ratio of the capacitor holes 107 is large, and the density of the capacitor holes 107 is getting larger and larger, in the etching process, the aperture of some capacitor holes 107 is large, and the aperture of some capacitor holes 107 is small. For example, as can be seen from FIG. 7, from left to right in FIG. 7, the aperture of the first capacitor hole 107 is small, and the apertures of the second and third capacitor holes 107 are large. As can be seen, the spacing between the first capacitor hole 107 and the second capacitor hole 107 is large, and the spacing between the second capacitor hole 107 and the third capacitor hole 107 is small, so that in the subsequent process, it is difficult to fill the medium layer and the upper electrode between the second capacitor hole 107 and the third capacitor hole 107. At the same time of forming the capacitor holes 107, the mask layer 106 is gradually consumed. After the capacitor holes 107 are formed, the mask layer 106 is also consumed. At the same time, since the intermediate support layer 104 is located in the middle region of the stack 10, when the capacitor holes 107 are formed, the etching time of the intermediate support layer 104 is reduced. Although the intermediate support layer 104 can be laterally etched, it will not cause the lower electrode material to be interconnected, and the intermediate support layer 104 will not be completely etched. Thus, the lower electrodes can be independent of each other and will not be short-circuited.

[0097] As shown in FIGS. 9-10, in step S2, after forming the capacitor hole 107, the lower electrode material 108 is filled into the capacitor hole 107. The embodiment of the present disclosure can form the lower electrode material 108 in the capacitor hole 107 by chemical vapor deposition, and the lower electrode material 108 can completely fill the capacitor hole 107. The lower electrode material 108 can be a metal nitride or a metal silicide, such as titanium nitride. Since the lower electrode material 108 completely covers the capacitor hole 107, a grinding process is performed on the lower electrode material 108, so that the lower electrode material 108 is flush with the second sacrificial layer 105, thereby forming independent lower electrodes. At the same time, since the second sacrificial layer 105 is not laterally etched, or in other words, the second sacrificial layer 105 is laterally etched to a small extent, the top of the second sacrificial layer 105 will not be etched away, thereby preventing the lower electrode material 108 from being interconnected, and thus preventing the problem of short circuiting of the lower electrode.

[0098] As shown in FIGS. 10-11, the embodiment of the present disclosure divides the lower electrode 11 into a first lower electrode 109 and a second lower electrode 110, that is, the lower electrode can include a plurality of first lower electrodes 109 and a plurality of second lower electrodes 110. The first lower electrode and the second lower electrode 110 are both independent of each other, that is, separated by the second sacrificial layer 105, the intermediate support layer 104, the first sacrificial layer 103, and the bottom support layer 102. As can be seen from FIG. 11, the spacing d1 between the first lower electrode 109 and the second lower electrode 110 is greater than the spacing d2 between the first lower electrode 109 and the first lower electrode 109. The spacing d3 between the second lower electrode 110 and the second lower electrode 110 can be greater than the spacing d1 between the first lower electrode 109 and the second lower electrode 110, that is, the spacing between the first lower electrode 109 and the first lower electrode 109 is the smallest. As can be seen from FIG. 10, the horizontal width of the second sacrificial layer 105 between the first lower electrode 109 and the first lower electrode 109 is the smallest.

[0099] As shown in FIG. 12, in step S3, after the lower electrode 11 (the first lower electrode 109 and the second lower electrode 110) is formed, dry etching is performed on the second sacrificial layer 105, so that the height of the second sacrificial layer 105 is lower than the lower electrode. The embodiments of the present disclosure take the second lower electrode 110 as an example, after the second sacrificial layer 105 is etched, the second lower electrode 110 protrudes from the second sacrificial layer 105, that is, the second lower electrode 110 can include a main body part 111 and an extension part 112, the main body part 111 can be located in the stack 10, and the extension part 112 can protrude from the stack 10, that is, the extension part 112 protrudes from the second sacrificial layer 105. In the embodiments of the present disclosure, the thickness of the second sacrificial layer 105 etched can be substantially the same as the thickness of the intermediate support layer 104, that is, the height of the extension part 112 can be substantially the same as the thickness of the intermediate support layer 104. If the height of the extension part 112 is too large, the height of the main body part 111 will be reduced, which may reduce the capacitance capacity. If the height of the extension part 112 is too small, when the conductive support layer is subsequently formed on the extension part 112, the height of the capacitor structure will be increased, which increases the risk of capacitor structure collapse (lower electrode collapse). Therefore, in the embodiments of the present disclosure, the height of the extension part 112 can be substantially the same as the thickness of the intermediate support layer 104, which can ensure the capacitance capacity and prevent the capacitor structure from collapsing.

[0100] As shown in FIG. 13, after the second lower electrode 110 is formed, the extension part 112 of the second lower electrode 109 is etched, so that the horizontal width of the extension part 112 is smaller than the horizontal width of the main body part 111. Since the horizontal width of the extension part 112 is small, the spacing between the extension parts 112 is increased. At the same time, due to the blocking effect of the second sacrificial layer 105, the etching gas will not affect the main body part 111, so that the integrity of the main body part 111 can be ensured. It should be noted that the structure of the first lower electrode 109 can refer to the structure of the second lower electrode 110.

[0101] As shown in FIGS. 14-15, in step S4, after the extension part 112 is etched, a dielectric layer 114 and a conductive film layer 113 can be sequentially formed on the stack 10. The dielectric layer 114 covers the surface of the extension part 112 and the surface of the second sacrificial layer 105, the conductive film layer 113 covers the dielectric layer 114, and the conductive film layer 113 can fill the gap between the extension parts 112, and the conductive film layer 113 also covers the extension part 112. The dielectric layer 114 and the conductive film layer 113 can be formed by a chemical vapor deposition process. The dielectric layer 114 can be a capacitor dielectric layer, which can be a high-K material, such as zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide, antimony oxide, and aluminum oxide. The conductive film layer 113 can be a silicon germanium layer or a tungsten metal layer. Since the dielectric layer 114 exists between the conductive film layer 113 and the extension part 112, a capacitor structure is formed, which increases the capacitance capacity.

[0102] As shown in FIG. 16, in steps S4-S5, after the conductive film layer 113 is formed, the conductive film layer 113 and the dielectric layer 114 are etched, i.e., the stack 10 is exposed, i.e., the second sacrificial layer 105 is exposed. At the same time, a plurality of conductive support layers 115 can be formed. In forming the conductive support layers 115, the conductive film layer 113 between the extensions 112 is etched first, so as to expose the dielectric layer 114 on the sidewall of the extension 112, and then the dielectric layer 114 is etched, so as to expose the sidewall of the extension 112. As shown in FIG. 16, the conductive support layer 115 can be located on the extension 112. The sidewall of the conductive support layer 115 can be flush with the sidewall of the extension 112, i.e., the conductive support layer 115 is not located between the extensions 112, i.e., the spacing between the extensions 112 is not reduced. After the second sacrificial layer 105 is exposed, the second sacrificial layer 105 and the first sacrificial layer 103 can be removed based on the gap between the conductive support layers 115 by using a wet removal solution through the gap, and at the same time, part of the intermediate support layer 104 is removed, so as to expose the main body 111.

[0103] As shown in FIG. 16, in the embodiment of the present disclosure, since the first lower electrode 109 and the second lower electrode 110 are independent of each other and are not interconnected, the second sacrificial layer 105 can be exposed in forming the conductive support layer 115. Therefore, when the second sacrificial layer 105 and the first sacrificial layer 103 are removed by using a wet solution, it can be ensured that the second sacrificial layer 105 and the first sacrificial layer 103 are completely removed, and residual parts of these sacrificial layers are effectively avoided.

[0104] As shown in FIG. 16, in the embodiment of the present disclosure, since the gap between the first lower electrodes 109 is small, the second sacrificial layer 105 between the first lower electrodes 109 is exposed in forming the conductive support layer 115. Therefore, the second sacrificial layer 105, the intermediate support layer 104 and the first sacrificial layer 103 between the first lower electrodes 109 can be removed by using a wet chemical solution. At the same time, the intermediate support layer 104 located directly below the conductive support layer 115 is not removed, so that the intermediate support layer 104 can be located on the middle region of the first lower electrode 109, thereby supporting the first lower electrode 109. Of course, the intermediate support layer 104 is also located on the middle region of the second lower electrode 110. The middle region can be the middle position of the first lower electrode 109 / second lower electrode 110.

[0105] As shown in FIG. 14 and FIG. 16, the embodiment of the present disclosure etches the extension 112 before forming the conductive support layer 115, i.e. reduces the horizontal width of the extension 112 and increases the spacing between the extensions 112; then fills the conductive film layer 113 between the extensions 112, and further etches the conductive film layer 113, thereby forming the conductive support layer 115. The embodiment of the present disclosure etches the extension 112 first, which can block the etching gas by the second sacrificial layer 105 to prevent the etching gas from etching the main body 111, thereby protecting the main body 111 and preventing the main body 111 from being damaged. Since only the extension 112 is etched, the etching process does not need to change the etching gas, and the etching process is relatively simple. At the same time, since the spacing between the extensions 112 is increased when etching the conductive film layer 113, it is easier to etch the conductive film layer 113 between the extensions 112, thereby ensuring that the second sacrificial layer 105 between the extensions 112 can be completely exposed. Of course, in some embodiments, the extension 112 is not etched when forming the lower electrode, but after forming the conductive film layer 113, the extension 112 is etched together with the conductive film layer 113 when etching the conductive film layer 113, thereby increasing the spacing between the extensions 112. Although this etching method can increase the spacing between the extensions 112, the spacing between the extensions 112 is small before the conductive film layer 113 is formed, which may form a cavity in the conductive film layer 113, thereby reducing the support of the conductive support layer 115. At the same time, since the conductive film layer 113, the dielectric layer 114 and the extension 112 need to be etched at the same time, the etching gas needs to be changed during the etching process, which makes the etching process relatively complex. Therefore, the embodiment of the present disclosure chooses to etch the extension 112 before forming the conductive film layer 113, thereby reducing the horizontal width of the extension 112.

[0106] As shown in FIG. 17-FIG. 18, in step S7, after the main body 111 is exposed, the dielectric layer 114 is first formed on the surface of the main body 111, and the dielectric layer 114 can be located on the conductive support layer 115 and also on the intermediate support layer 104. After forming the dielectric layer 114, the upper electrode 116 is formed on the dielectric layer 114, and the upper electrode 116 can completely cover the dielectric layer 114. FIG. 18(a) shows the positional relationship of the conductive support layer 115, the dielectric layer 114 and the upper electrode 116, and FIG. 18(b) shows the positional relationship of the main body 110, the dielectric layer 114 and the upper electrode 116. As can be seen from FIG. 18, the dielectric layer 114 is located between the conductive support layer 115 and the upper electrode 116. The dielectric layer 114 is located between the main body 110 and the upper electrode 116. The main body 110, the dielectric layer 114 and the upper electrode 116 can form a capacitor structure. The conductive support layer 115, the dielectric layer 114 and the upper electrode 116 can also form a capacitor structure, thereby increasing the capacitance.

[0107] As shown in FIGS. 17-18, in the embodiments of the present disclosure, the dielectric layer 114 is formed on the main body 111 by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. Since the extension 112 is etched, the horizontal width of the extension 112 is reduced, and the spacing between the extensions 112 is increased, so that the deposition atoms are more likely to extend to the area between the extensions 112 when the dielectric layer 114 is deposited, and thus the dielectric layer 114 is more likely to be formed on the main body 111. For example, in the present embodiment, since the spacing between the first lower electrodes 109 is small, and the height of the first lower electrode 109 is high, the horizontal width of the extension 112 of the first lower electrode 109 is reduced, the deposition atoms are more likely to enter the area between the extensions 112 of the first lower electrode 109, and thus more likely to enter the area between the main bodies 111 of the first lower electrodes 109, and thus more likely to form the dielectric layer 114 on the first lower electrode 109. Conversely, if the horizontal width of the extension 112 is not reduced, since the spacing between the first lower electrodes 109 is small, and the first lower electrode 109 is high, it is not easy to form the dielectric layer 114 on the first lower electrode 109, and thus the capacitor structure is not formed. After the dielectric layer 114 is formed, the spacing between the first lower electrodes 109 is smaller, and by reducing the horizontal width of the extension 112 on the first lower electrode 109, the spacing between the extensions 112 is increased, so that the deposition atoms are more likely to enter between the first lower electrodes 109, and thus the upper electrode 116 is formed on the dielectric layer 114. Of course, since the spacing between the second lower electrodes 110 is large, the extensions 112 on the second lower electrodes 110 are also etched, so that the dielectric layer 114 and the upper electrode 116 are more likely to be formed on the second lower electrodes 110. Since the sidewall of the conductive support layer 115 is flush with the sidewall of the extension 112, i.e., there is no conductive support layer 115 between the extensions 112 of adjacent first lower electrodes 109, so that the conductive support layer 115 does not occupy the area between the extensions 112 of adjacent first lower electrodes 109, so as to facilitate the deposition of the dielectric layer 114 and the upper electrode 116.

[0108] As shown in FIG. 18, in the embodiments of the present disclosure, the material of the dielectric layer 114 can be a high-K material, such as zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide, antimony oxide, and aluminum oxide. The material of the upper electrode 116 can be a metal nitride and a metal silicide, such as titanium nitride, titanium silicon nitride.

[0109] As shown in FIGS. 19-20, in embodiments of the present disclosure, the conductive support layer 115 is located on top of the second lower electrode 110, i.e. covers the extension 112 of the second lower electrode 110. Of course, the conductive support layer 115 also covers the extension 112 of the first lower electrode 109. Since the conductive support layer 115 can support the first lower electrode 109 and the second lower electrode 110, and since the conductive support layer 115 is conductive, it can also function as a wire, i.e. it can be interconnected with the metal pillars to achieve signal transmission. Of course, in some embodiments, after the upper electrode 116 is formed, the dielectric layer 114 and the upper electrode 116 on the upper surface of the conductive support layer 115 can be removed, i.e. the dielectric layer 114 and the upper electrode 116 on the sidewall of the conductive support layer 115 are exposed, i.e. the upper electrode 116 can extend from the first lower electrode 109 or the second lower electrode 110 to the conductive support layer 115, so that the conductive support layer 115 and the upper electrode 116 are coplanar, and then the upper plate 117 is formed on the conductive support layer 115, which can cover the conductive support layer 116. Part of the upper plate 117 can also be located in the area between adjacent conductive support layers 115 and extend between the main body 111, so as to be interconnected with the upper electrode 116 between the main body 111 and the conductive support layer 115 on the upper electrode 116, thereby increasing the contact area between the upper plate 117 and the upper electrode 116, reducing the contact resistance, and also serving as a support. The material of the upper plate 117 can be the same as that of the conductive support layer 115, and the upper plate 117 and the upper electrode 116 can be an integral structure, thereby serving as a support for the lower electrode and also serving as a conductor.

[0110] In some embodiments, the upper plate 117 can also only fill the area between the conductive support layers 115 and extend between the first lower electrodes 109, thereby serving as a support, so that the metal pillars can be directly formed on the conductive support layer 115. The conductive support layer 115 can serve as a support for the first lower electrode 109 and also serve as a conductor. At the same time, it can also reduce the height of the capacitor structure, reduce the pressure of the upper plate 117 on the first lower electrode 109 and the second lower electrode 110, and improve the risk of collapse of the first lower electrode 109 and the second lower electrode 110.

[0111] As shown in FIG. 21, the semiconductor structure according to the embodiment of the present disclosure can include a substrate 101, a plurality of first lower electrodes 109 and a plurality of second lower electrodes 110 on the substrate 101, which can be collectively referred to as lower electrodes. A bottom support layer 102 is on the bottom of the first lower electrode 109, a middle support layer 104 is on the middle region of the first lower electrode 109, a first conductive support layer 115 is on the top of the first lower electrode 109, and a second conductive support layer 117 is on the first conductive support layer 115, which together form a conductive support layer 119. The bottom support layer 102 and the middle support layer 104 are insulating materials, for example, silicon nitride. The first conductive support layer 115 is germanium silicon, and the second conductive support layer 117 is germanium silicon, which have the same material and can reduce the interface resistance. There is a dielectric layer between the first conductive support layer 115 and the first lower electrode 109, and a dielectric layer between the first conductive support layer 115 and the second lower electrode 110. Thus, the first conductive support layer 115 can support the first lower electrode 109 and the second lower electrode 110. At the same time, since the second conductive support layer 117 has a metal column 118 thereon, the signal can be transmitted to the first conductive support layer 115 through the metal column 118, and then to the capacitor structure, so the first conductive support layer 115 and the second conductive support layer 117 can also have a conductive effect.

[0112] As shown in FIGS. 21-22, the second lower electrode 110 is taken as an example for illustration according to the embodiment of the present disclosure. The second lower electrode 110 can include a main body part 111 and an extension part 112. The extension part 112 is above the main body part 111, and in the X direction (horizontal direction), the horizontal width of the extension part 112 is less than that of the main body part 111. Thus, the distance between the extension parts 112 is greater than that between the main body parts 111. At the same time, the first conductive support layer 115 can also be on the extension part 112, that is, the conductive support layer 115 covers the extension part 112, and the sidewall of the first conductive support layer 115 is flush with the sidewall of the extension part 112. At the same time, there is an upper electrode 116 on the sidewall of the first lower electrode 109, the second lower electrode 110, the extension part 112, and the sidewall of the first conductive support layer 115. The second conductive support layer 117 covers the first conductive support layer 115, and part of the second conductive support layer 117 is also between the first conductive support layers 115 and between the extension parts 112, and then extends to the main body parts 111, and then contacts the upper electrode 116 on the first conductive support layer 115, the extension part 112, and the main body part 111, thereby increasing the contact area and reducing the contact resistance. At the same time, since the second conductive support layer 117 extends to the main body parts 111, it can support the first lower electrode 109 and the second lower electrode 110.

[0113] As shown in FIGS. 21-22, in the embodiment of the present disclosure, since the height of the extension 112 is substantially the same as the thickness of the intermediate support layer 104, the main body portion 110 can have a proper height, ensuring the capacitance capacity; the overall height of the capacitor structure can also be reduced, reducing the risk of collapse of the lower electrode. In the embodiment, the conductive support layer 119 covers the extension 112, so the thickness of the conductive support layer 119 is greater than the thickness of the intermediate support layer 104. Therefore, by increasing the thickness of the conductive support layer 119, both the support effect and the resistance of the conductive support layer 119 can be reduced.

[0114] As shown in FIG. 21, there is also a dielectric layer 114 (see FIG. 18) between the upper electrode 116 and the first lower electrode 109, and there is also a dielectric layer 114 (see FIG. 18) between the first conductive support layer 115 and the extension 112. The upper electrode 116, the first lower electrode 109, and the dielectric layer 114 can collectively constitute a capacitor structure, and the first conductive support layer 115, the extension 112, and the dielectric layer 114 can also collectively constitute a capacitor structure, thereby increasing the capacitance capacity.

[0115] It should be noted that the method of manufacturing the semiconductor structure in FIG. 21 can refer to the above description.

[0116] As shown in FIG. 23, the embodiment of the present disclosure also proposes an electronic device 100, which can include a semiconductor structure 200, which can refer to the structure in FIG. 21, and the method of manufacturing the semiconductor structure 200 can refer to the above description. The electronic device 100 can include one or more of, for example, a smart phone, a tablet personal computer (PC), a mobile phone, a video phone, an electronic book (e-book) reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MPEG-1 audio layer 3 (MP3) player, a mobile medical device, a camera, a home appliance, a medical device, an Internet of Things (IoT) device, and a wearable device. The wearable device can be a type of accessory, a type of fabric or clothing, a type of body attachment, or a type of implantable circuit. The accessory-type wearable device can be, for example, a watch, a ring, a bracelet, an anklet, a necklace, glasses, contact lenses, or a head-mounted device (HMD).

[0117] In summary, the embodiment of the present disclosure proposes a semiconductor structure and a manufacturing method thereof. After forming the second sacrificial layer on the substrate, the mask layer is directly formed on the second sacrificial layer, that is, after forming the stack layer not including the top support layer (silicon nitride), when etching the stack layer, the etching gas cannot perform lateral etching on the second sacrificial layer, so as to ensure that the lower electrode is not connected, thereby the first sacrificial layer and the second sacrificial layer can be completely cleaned in the subsequent process, avoiding the residual first sacrificial layer, and thus being beneficial to form the capacitor.

[0118] Secondly, due to the large aspect ratio of the capacitor hole and the large density of the capacitor hole, the aperture of some capacitor holes is increased, so that the diameter of the first lower electrode is increased, resulting in a small spacing between the first lower electrodes. Therefore, by reducing the horizontal width of the extension part and increasing the spacing between the extension parts, the spacing between the extension parts is greater than the spacing between the main body parts, so that it is easier for the deposited atoms to enter between the main body parts, thereby being beneficial to form the dielectric layer and the upper electrode, so as to ensure the formation of the capacitor structure and simplify the process.

[0119] Thirdly, since the conductive support layer is located on the extension part, it can support the lower electrode. At the same time, the conductive support layer can also be used as the upper plate, that is, for power transmission. Since there is a dielectric layer between the conductive support layer and the extension part, a capacitor structure can be formed to increase the capacitance.

[0120] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, Comprising: forming a stack (10) on a substrate; forming a plurality of lower electrodes (109, 110) in the stack, the lower electrodes comprising a main body portion (11) in the stack and an extension portion (112) protruding from the stack; etching the extension portion so that the horizontal width of the extension portion is less than the horizontal width of the main body portion; forming a dielectric layer (114) and a conductive film layer (113) on the stack in sequence, the dielectric layer and the conductive film layer covering the extension portion; etching the conductive film layer to expose the stack and form a plurality of conductive support layers (115); etching the stack to expose the main body portion; forming a dielectric layer (114) on the main body portion; forming an upper electrode (116) on the dielectric layer.

2. The production method according to claim 1, characterized by The step of forming the stack comprises: forming a bottom support layer on the substrate; forming a first sacrificial layer on the bottom support layer; forming an intermediate support layer on the first sacrificial layer; forming a second sacrificial layer on the intermediate support layer.

3. The production method according to claim 2, characterized by The step of forming the lower electrodes comprises: forming a mask layer on the second sacrificial layer; etching the stack according to the mask layer to form capacitor holes in the stack; forming lower electrodes in the capacitor holes; removing part of the second sacrificial layer so that the lower electrodes protrude from the stack.

4. The production method according to claim 3, characterized by The step of removing part of the second sacrificial layer comprises: removing part of the second sacrificial layer by dry etching to form the extension portion; wherein the height of the extension portion is substantially the same as the thickness of the intermediate support layer.

5. The production method according to claim 3, wherein The lower electrodes are formed by filling lower electrode material into the capacitor holes; the lower electrodes comprise: a plurality of first lower electrodes; a plurality of second lower electrodes; wherein the spacing between adjacent first lower electrodes is less than the spacing between adjacent second lower electrodes.

6. The production method according to any one of claims 1 to 5, characterized by, The step of forming the conductive support layers comprises: removing the conductive film layer between the extension portions to expose the dielectric layer on the sidewalls of the extension portions and to expose the stack; removing the dielectric layer on the sidewalls of the extension portions to expose the sidewalls of the extension portions.

7. The production method according to claim 6, wherein The step of forming the conductive support layers comprises: removing part of the conductive film layer between adjacent first lower electrodes to expose the second sacrificial layer between adjacent first lower electrodes.

8. The production method according to claim 1, wherein The step of forming the upper electrode comprises: depositing upper electrode material on the dielectric layer, the upper electrode material also being on the conductive support layers; wherein the upper electrode material and the conductive support layers are separated by the dielectric layer.

9. The production method according to any one of claims 1 to 5, characterized by, Further comprising forming an upper plate on the conductive support layers, the upper plate being in contact with the upper electrode on the conductive support layers.

10. The method of claim 9, wherein the method further comprises: The upper plate also extends between adjacent main body portions to be in contact with the upper electrode between the main body portions.

11. A semiconductor structure, characterized by Comprising: a substrate (101); a plurality of lower electrodes (109, 110) on the substrate, the lower electrodes comprising a main body portion (111) and an extension portion (112), the horizontal width of the extension portion being less than the horizontal width of the main body portion; an intermediate support layer (104) on a middle region of the main body portion; a conductive support layer (119) on the extension portion, with a dielectric layer (114) between the conductive support layer and the extension portion; a conductive pillar (118) on the conductive support layer.

12. The semiconductor structure of claim 11, wherein, The dielectric layer is also on the main body portion, and an upper electrode is also provided on the dielectric layer.

13. The semiconductor structure of claim 11, wherein, The conductive support layer extends to between the lower electrodes and contacts the upper electrode between the lower electrodes.

14. The semiconductor structure of claim 11, wherein, The conductive support layer protrudes from the upper electrode.

15. The semiconductor structure of claim 11, wherein, The thickness of the conductive support layer is greater than the thickness of the intermediate support layer.

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