Display control system and LED display apparatus

Abstract

A display control system and an electronic device. The display control system comprises: an LVDS differential transmission circuit (11), an input terminal of which is connected to a transmitting terminal of a target signal; a HUB circuit (12), an input terminal of which is connected to an output terminal of the LVDS differential transmission circuit (11); and an LVDS differential receiving circuit (21), an input terminal of which is connected to an output terminal of the HUB circuit (12). The LVDS differential transmission circuit (11) directly converts the target signal into a high-bandwidth and high-integration LVDS differential signal, which is then processed by the HUB circuit (12) to output a target differential signal, wherein differential signals and high voltages can achieve stable output over long distances, thereby ensuring that, when the display control system is used outdoors, a system power control box (1) can be installed indoors, thereby improving the safe and reliable operation of the system power control box (1) and enhancing the convenience of device maintenance.

Description

Display control system and LED display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202421459468.2, filed on June 24, 2024, entitled “A display control system and LED display device”, which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of LED display technology, in particular to a display control system and LED display device. BACKGROUND

[0004] In recent years, in order to ensure that the conventional LED (Light Emitting Diode) display screen can communicate stably and display normally, the system power control box usually supplies power and signal transmission for the LED display screen within a range of two meters. The reason is that when the transmission distance between the power control box and the module is more than 2m, there will be problems such as signal attenuation, phase offset, mutual crosstalk between signal lines, etc., which will cause electromagnetic interference and affect the stability of signal transmission.

[0005] Therefore, due to the transmission distance, the LED display screen and the system power control box can only be used in the same scene. However, the use scene of the LED display screen is relatively wide, and most of them are outdoor, and the environmental conditions of the outdoor are relatively harsh. It is inevitable that the system power control box will have the risk of water ingress, and the overall reliability is low, and it is easy to malfunction and the safety of outdoor maintenance is low. SUMMARY

[0006] The purpose of the present application is to provide a display control system and LED display device. The distance of data transmission from the system power control box to the display control system when using the display control system can be improved, so as to ensure that the system power control box can be installed indoors when using the display control system outdoors, ensure the safe and reliable operation of the system power control box, and improve the convenience of device maintenance.

[0007] To solve the above technical problems, the present application provides a display control system, comprising: a system power control box and an LED display module;

[0008] The system power control box comprises: an LVDS differential sending circuit for converting a target signal into an LVDS differential signal, the input end of the LVDS differential sending circuit being connected with the sending end of the target signal; and a HUB circuit for converting the LVDS differential signal into a target differential signal, the input end of the HUB circuit being connected with the output end of the LVDS differential sending circuit.

[0009] The LED display module comprises: an LVDS differential receiving circuit for receiving a target differential signal and converting the target differential signal into a control signal, and an input end of the LVDS differential receiving circuit is connected with an output end of a HUB circuit.

[0010] Preferably, the LVDS differential transmitting circuit comprises: a first diode array chip, a second diode array chip and a first input terminal;

[0011] The first group of pins of the first diode array chip, the second group of pins of the first diode array chip, the first group of pins of the first input terminal and the first end of the HUB circuit are connected; the third group of pins of the first diode array chip, the fourth group of pins of the first diode array chip, the second group of pins of the first input terminal and the second end of the HUB circuit are connected.

[0012] The first group of pins of the second diode array chip, the second group of pins of the second diode array chip and the third group of pins of the first input terminal are connected with the third end of the HUB circuit.

[0013] The first group of pins, the second group of pins, the third group of pins and the fourth group of pins of the first diode array chip, the first group of pins and the second group of pins of the second diode array chip and the first group of pins, the second group of pins and the third group of pins of the first input terminal are collectively used as output ends of the LVDS differential transmitting circuit; and the first end, the second end and the third end of the HUB circuit are collectively used as input ends of the HUB circuit.

[0014] Preferably, the HUB circuit comprises: a differential chip, a second input terminal, a third input terminal, an indicator light circuit and a test button.

[0015] The first group of pins of the differential chip is used as the first end of the HUB circuit and is connected with the first group of pins of the first diode array chip, the second group of pins of the first diode array chip and the first group of pins of the first input terminal; the second group of pins of the differential chip is used as the second end of the HUB circuit and is connected with the third group of pins of the first diode array chip, the fourth group of pins of the first diode array chip and the second group of pins of the first input terminal; and the third group of pins of the differential chip is used as the third end of the HUB circuit and is connected with the first group of pins of the second diode array chip, the second group of pins of the second diode array chip and the third group of pins of the first input terminal.

[0016] The fourth group of pins of the differential chip is connected with the first group of pins of the second input terminal, and the fifth group of pins of the differential chip is connected with the second group of pins of the second input terminal.

[0017] The sixth group of pins of the differential chip is connected with the first group of pins of the third input terminal, and the seventh group of pins of the differential chip is connected with the second group of pins of the third input terminal.

[0018] The key pin of the differential chip is connected with the first end of the indicator light circuit and the first end of the test key, the LED pin of the differential chip is connected with the second end of the indicator light circuit, and the second end of the test key is grounded.

[0019] The eighth group of pins of the differential chip is connected with the input end of the LVDS differential receiving circuit as the output end of the HUB circuit.

[0020] Preferably, the system power supply control box further comprises a high-voltage power supply circuit for supplying power to the LED display module, and the input end of the high-voltage power supply circuit is connected with the power supply end.

[0021] Preferably, the high-voltage power supply circuit comprises a fourth input terminal and a power supply circuit, wherein the power supply circuit comprises a switch regulator chip and a power supply circuit.

[0022] The socket of the fourth input terminal is connected with the power supply end as the input end of the high-voltage power supply circuit, the first group of pins of the fourth input terminal is connected with the input pin of the switch regulator chip, and the second group of pins of the fourth input terminal is grounded.

[0023] The output pin of the switch regulator chip is connected with the input end of the power supply circuit.

[0024] The output end of the power supply circuit is the output end of the high-voltage power supply circuit.

[0025] Preferably, the LVDS differential receiving circuit comprises a high-speed interface chip, a first signal enhancement circuit and a second signal enhancement circuit.

[0026] The first group of pins of the high-speed interface chip is connected with the output end of the HUB circuit as the input end of the LVDS differential receiving circuit, the second group of pins of the high-speed interface chip is connected with the input end of the first signal enhancement circuit, and the third group of pins of the high-speed interface chip is connected with the first end of the second signal enhancement circuit.

[0027] Preferably, the LED display module further comprises:

[0028] a bus driving circuit for receiving and driving and amplifying the control signal, and the input end of the bus driving circuit is connected with the output end of the HUB circuit.

[0029] an LED module control circuit for receiving the control signal after driving and amplification and displaying the data corresponding to the control signal, and the input end of the LED module control circuit is connected with the output end of the bus driving circuit.

[0030] The first step-down circuit is connected with the output end of the high-voltage power supply circuit, and the output end of the first step-down circuit is connected with the power supply end of the bus driving circuit and the power supply end of the LED module control circuit.

[0031] The second step-down circuit is connected with the output end of the first step-down circuit, and the output end of the second step-down circuit is connected with the power supply end of the LVDS differential receiving circuit.

[0032] Preferably, the first step-down circuit comprises a step-down chip, a first RC filter circuit, a second RC filter circuit, a third RC filter circuit and a MOS tube circuit.

[0033] The first group of pins of the step-down chip is connected with the first end of the first RC filter circuit; the second group of pins of the step-down chip is connected with the first end of the second RC filter circuit; the third group of pins of the step-down chip is connected with the first end of the MOS tube circuit; and the fourth group of pins of the step-down chip is connected with the first input end of the third RC filter circuit.

[0034] The second end of the first RC filter circuit is connected with the output end of the high-voltage power supply circuit as the input end of the first step-down circuit.

[0035] The second end of the second RC filter circuit is grounded.

[0036] The second input end of the third RC filter circuit is connected with the output end of the MOS tube circuit, and the output end of the third RC filter circuit is connected with the input end of the second step-down circuit, the power supply end of the bus driving circuit and the power supply end of the LED module control circuit as the output end of the first step-down circuit.

[0037] Preferably, the bus driving circuit comprises a first bus transceiver chip and a second bus transceiver chip.

[0038] The first group of pins of the first bus transceiver chip is connected with the fourth group of pins of the high-speed interface chip; the second group of pins of the first bus transceiver chip is connected with the fifth group of pins of the high-speed interface chip; the third group of pins of the first bus transceiver chip is grounded; and the power supply pin of the first bus transceiver chip is connected with the output end of the first step-down circuit as the power supply end of the bus driving circuit.

[0039] The first group of pins of the second bus transceiver chip is connected with the sixth group of pins of the high-speed interface chip, the second group of pins of the second bus transceiver chip is connected with the input end of the LED module control circuit as the output end of the bus driving circuit, and the power supply pin of the second bus transceiver chip is connected with the output end of the first-stage voltage reduction circuit as the power supply end of the bus driving circuit.

[0040] The first group of pins of the first bus transceiver chip, the second group of pins of the first bus transceiver chip and the first group of pins of the second bus transceiver chip are collectively used as the input end of the bus driving circuit.

[0041] Preferably, the second-stage voltage reduction circuit comprises a voltage stabilizer chip and a voltage stabilization circuit.

[0042] The input pin of the voltage stabilizer chip is connected with the output end of the high-voltage power supply circuit as the input end of the second-stage voltage reduction circuit, and the output pin of the voltage stabilizer chip is connected with the input end of the voltage stabilization circuit.

[0043] The output end of the voltage stabilization circuit is connected with the power supply end of the LVDS differential receiving circuit as the output end of the second-stage voltage reduction circuit.

[0044] To solve the above technical problems, the application further provides an LED display device comprising the display control system.

[0045] This application provides a display control system comprising: a system power control box and an LED display module; wherein the system power control box includes: an LVDS differential transmitting circuit for converting a target signal into an LVDS differential signal, the input terminal of which is connected to the transmitting terminal of the target signal; a HUB circuit for converting the LVDS differential signal into a target differential signal, the input terminal of which is connected to the output terminal of the LVDS differential transmitting circuit; and a high-voltage power supply circuit for supplying power to the LED display module, the input terminal of which is connected to the power supply terminal; the LED display module includes: an LVDS differential receiving circuit for receiving the target differential signal and converting it into a control signal, the input terminal of which is connected to the output terminal of the HUB circuit. Therefore, the display control system provided in this application consists of two parts: a system power control box and an LED display module. The LVDS differential transmitting circuit directly converts the target signal into a high-bandwidth, highly integrated LVDS differential signal. This signal is then processed by a hub circuit and output as the target differential signal. This differential signal can achieve stable output over long distances and is sent to the LED display module. The LVDS differential receiving circuit in the LED display module converts the target differential signal into a control signal, which is then displayed on the screen. A high-voltage power supply circuit provides power, enabling high-voltage long-distance transmission of the signal to the LED display module. This allows the system power control box to be installed indoors when the display control system is used outdoors, improving the safe and reliable operation of the system power control box and enhancing the ease of component maintenance. Attached Figure Description

[0046] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 is a schematic diagram of a display control system provided in an embodiment of this application;

[0048] Figure 2(a) is a first circuit diagram of the LVDS differential transmission circuit provided in an embodiment of this application;

[0049] Figure 2(b) is a second circuit diagram of the LVDS differential transmission circuit provided in the embodiment of this application;

[0050] Figure 2(c) is a third circuit diagram of the LVDS differential transmission circuit provided in the embodiment of this application;

[0051] Figure 3(a) is a first circuit diagram of the HUB circuit provided in an embodiment of this application;

[0052] Fig. 3(b) is a second circuit diagram of the HUB circuit according to an embodiment of the present application;

[0053] Fig. 3(c) is a third circuit diagram of the HUB circuit according to an embodiment of the present application;

[0054] Fig. 3(d) is a fourth circuit diagram of the HUB circuit according to an embodiment of the present application;

[0055] Fig. 3(e) is a fifth circuit diagram of the HUB circuit according to an embodiment of the present application;

[0056] Fig. 3(f) is a sixth circuit diagram of the HUB circuit according to an embodiment of the present application;

[0057] Fig. 4(a) is a first circuit diagram of the high-voltage power supply circuit according to an embodiment of the present application;

[0058] Fig. 4(b) is a second circuit diagram of the high-voltage power supply circuit according to an embodiment of the present application;

[0059] Fig. 5 is a circuit diagram of the LVDS differential receiving circuit according to an embodiment of the present application;

[0060] Fig. 6 is a complete schematic diagram of the display control system according to an embodiment of the present application;

[0061] Fig. 7 is a circuit diagram of the first-stage voltage reduction circuit according to an embodiment of the present application;

[0062] Fig. 8(a) is a first circuit diagram of the bus driving circuit according to an embodiment of the present application;

[0063] Fig. 8(b) is a second circuit diagram of the bus driving circuit according to an embodiment of the present application;

[0064] Fig. 9 is a circuit diagram of the second-stage voltage reduction circuit according to an embodiment of the present application;

[0065] Fig. 10 is a circuit diagram of the LED module control circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0066] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0067] The core of the present application is to provide a display control system and an LED display device.

[0068] In order to make the person skilled in the art better understand the present application, the present application is further described in detail below in combination with the drawings and specific embodiments.

[0069] Fig. 1 is a schematic diagram of a display control system provided by an embodiment of the present application, as shown in Fig. 1, the display control system comprises a system power control box 1 and an LED display module 2.

[0070] The system power control box 1 comprises an LVDS differential transmission circuit 11 for converting a target signal into an LVDS differential signal (Low-Voltage Differential Signaling), an input end of the LVDS differential transmission circuit 11 being connected to a transmission end of the target signal; and a HUB circuit 12 for converting the LVDS differential signal into a target differential signal, an input end of the HUB circuit 12 being connected to an output end of the LVDS differential transmission circuit 11.

[0071] The LED display module 2 comprises an LVDS differential receiving circuit 21 for receiving the target differential signal and converting the target differential signal into a control signal, an input end of the LVDS differential receiving circuit 21 being connected to an output end of the HUB circuit 12.

[0072] In a specific embodiment, the target signal is a signal to be transmitted from the transmission end of the target signal.

[0073] In specific embodiments, the display control system provided by the present application comprises two parts: a system power control box 1 and an LED display module 2. The LVDS differential transmission circuit 11 in the system power control box 1 converts the target signal into high-bandwidth high-integration LVDS differential signals under program processing and outputs the signals. The LVDS differential signals include 12 groups of RGB data signals (red, green and blue data signals of the column scanning circuit), 5 decoding signals (A: address signal of the row scanning circuit; B: serial clock signal; C: data signal; D: enable control signal; E: address signal of the row scanning circuit) and 3 clock instruction signals (DCLK: data clock signal of the column scanning circuit; GCLK: display clock of the column scanning circuit; LAT: data and instruction latching signal of the column scanning circuit). The LVDS differential signals are driven and processed by the HUB circuit 12 and then output target differential signals. The target differential signals include three pairs of (TX\RX\GCLK) differential signals, and the three pairs of differential signals can realize stable transmission of more than 70 meters. When the target differential signals are output to the LED display module 2, the interface conversion chip in the LVDS differential receiving circuit 21 converts the three pairs of (TX\RX\GCLK) differential signals into control signals (TTL / COMS form signals, in which the TTL / COMS form signals correspond to 12 RGB data signals, 5 decoding signals (ABCDE) and 3 clock instruction signals DCLK, GCLK and LAT, and finally the data corresponding to the display control signals is displayed by the display screen.

[0074] It should be noted that the present application does not limit the specific structure of the LVDS differential transmission circuit, the HUB circuit and the LVDS differential receiving circuit, and they can be set by the user as needed while meeting the above functions.

[0075] The display control system provided by the application comprises a system power control box and an LED display module. The system power control box comprises an LVDS differential transmission circuit for converting a target signal into an LVDS differential signal, an input end of the LVDS differential transmission circuit being connected with a transmission end of the target signal; a HUB circuit for converting the LVDS differential signal into a target differential signal, an input end of the HUB circuit being connected with an output end of the LVDS differential transmission circuit; and the LED display module comprises an LVDS differential receiving circuit for receiving the target differential signal and converting the target differential signal into a control signal, an input end of the LVDS differential receiving circuit being connected with an output end of the HUB circuit. It can be seen that the display control system provided by the application is composed of the system power control box and the LED display module. The LVDS differential transmission circuit directly converts the target signal into a high-bandwidth and high-integration LVDS differential signal, and then outputs the target differential signal after processing by the HUB circuit. The differential signal can be stably outputted at a distance of more than a certain distance and is transmitted to the LED display module. The LVDS differential receiving circuit in the LED display module converts the target differential signal into the control signal, and finally the display screen displays the data corresponding to the control signal. In this way, when the display control system is used outdoors, the system power control box can be installed indoors, thereby improving the safe and reliable operation of the system power control box and improving the convenience of device maintenance.

[0076] On the basis of the above-mentioned embodiments, as a preferred embodiment, the system power control box further comprises a high-voltage power supply circuit 13 for supplying power to the LED display module, an input end of the high-voltage power supply circuit 13 being connected with a power supply end. The high-voltage power supply circuit 13 of the system power control box 1 generally outputs a DC 24-48V voltage, which can be transmitted to the LED display module at a long distance to supply power to the LED display module, so that the signal can be transmitted to the LED display module at a long distance. In this way, when the display control system is used outdoors, the system power control box can be installed indoors, thereby improving the safe and reliable operation of the system power control box and improving the convenience of device maintenance.

[0077] It should be noted that the specific structure of the high-voltage power supply circuit is not limited in the application, and can be set by the user as needed while meeting the above-mentioned functions.

[0078] On the basis of the above-mentioned embodiments, as a preferred embodiment, as shown in FIG. 2(a), FIG. 2(b) and FIG. 2(c), the LVDS differential transmission circuit 11 comprises a first diode array chip T1, a second diode array chip T2 and a first input terminal J4.

[0079] Wherein, as shown in the figure, the first group of pins (pin 1 and pin 2) of the first diode array chip T1 is connected to the second group of pins (pin 10 and pin 9) of the first diode array chip T1, the first group of pins (pin 1 and pin 2) of the first input terminal J4 is connected to the first end of the HUB circuit 12, the third group of pins (pin 4 and pin 5) of the first diode array chip T1 is connected to the fourth group of pins (pin 7 and pin 6) of the first diode array chip T1, the second group of pins (pin 3 and pin 4) of the first input terminal J4 is connected to the second end of the HUB circuit; in addition, the pin 3 and the pin 8 of the first diode array chip T1 are grounded.

[0080] The first group of pins (pin 1 and pin 2) of the second diode array chip T2 is connected to the second group of pins (pin 10 and pin 9) of the second diode array chip T2, the third group of pins (pin 5 and pin 6) of the first input terminal J4 is connected to the third end of the HUB circuit; in addition, the pin 3 and the pin 8 of the second diode array chip T2 are grounded, the pin 4-pin 7 of the second diode array chip T2 are empty pins, and the pin 7-pin 10 of the first input terminal J4 are grounded.

[0081] Wherein, the first group of pins, the second group of pins, the third group of pins and the fourth group of pins of the first diode array chip T1, the first group of pins and the second group of pins of the second diode array chip T2, and the first group of pins and the second group of pins of the first input terminal J4 are collectively used as the output end of the LVDS differential transmission circuit; and the first end, the second end and the third end of the HUB circuit are collectively used as the input end of the HUB circuit.

[0082] Wherein, it is to be noted that the LVDS differential transmission circuit provided by the present application is only a part of the circuit for realizing the output of the LVDS differential signal, and the specific circuit can be set by the user as needed.

[0083] Wherein, as a preferred embodiment, the model of the first diode array chip T1 and the second diode array chip T2 is RCLAMP0524, the model of the first input terminal J4 is HEAD2X5-DIP-2.0-90, and the main chip of the whole LVDS differential transmission circuit is an FPGA chip.

[0084] The present application provides a specific circuit of an LVDS differential transmission circuit, under the circuit structure, the target signal can be converted into an output high-bandwidth high-integration LVDS differential signal under program processing, and the stable transmission of the signal over a long distance is realized.

[0085] On the basis of the above-mentioned embodiments, as a preferred embodiment, as shown in FIG. 3(a), FIG. 3(b), FIG. 3(c), FIG. 3(d), FIG. 3(e) and FIG. 3(f), the HUB circuit 12 comprises: a differential chip JH1 (A\B), a second input terminal J2, a third input terminal J3, an indicator light circuit J8 and a test button K1.

[0086] In which, the first group of pins (pin 180 and pin 178) of the differential chip JH1 are connected with the first group of pins (pin 1 and pin 2) of the first diode array chip T1, the second group of pins (pin 10 and pin 9) of the first diode array chip T1 and the first group of pins (pin 1 and pin 2) of the first input terminal J4 as the first end of the HUB circuit 12; the second group of pins (pin 175 and pin 173) of the differential chip JH1 are connected with the third group of pins (pin 4 and pin 5) of the first diode array chip T1, the fourth group of pins (pin 7 and pin 6) of the first diode array chip T1 and the second group of pins (pin 3 and pin 4) of the first input terminal J4 as the second end of the HUB circuit 12; the third group of pins (pin 33 and pin 31) of the differential chip JH1 are connected with the first group of pins (pin 1 and pin 2) of the second diode array chip T2, the second group of pins (pin 10 and pin 9) of the second diode array chip T2 and the third group of pins (pin 5 and pin 6) of the first input terminal J4 as the third end of the HUB circuit 12;

[0087] The fourth group of pins (pin 32, pin 38, pin 44 and pin 50) of the differential chip JH1 are connected with the first group of pins (pin 1, pin 3, pin 5 and pin 7) of the second input terminal J2, and the fifth group of pins (pin 30, pin 36, pin 42 and pin 48) of the differential chip JH1 are connected with the second group of pins (pin 2, pin 4, pin 6 and pin 8) of the second input terminal J2; in addition, the pin 9 and pin 10 of the second input terminal J2 are grounded.

[0088] The sixth group of pins (pin 129, pin 135, pin 141 and pin 147) of the differential chip JH1 are connected with the first group of pins (pin 1, pin 3, pin 5 and pin 7) of the third input terminal J3, and the seventh group of pins (pin 131, pin 137, pin 143 and pin 149) of the differential chip JH1 are connected with the second group of pins (pin 2, pin 4, pin 6 and pin 8) of the third input terminal J3; in addition, the pin 9 and pin 10 of the third input terminal J3 are grounded.

[0089] The key pin (pin 155) of the differential chip JH1 is connected with the first end (pin 2) of the indicator light circuit J8 and the first end of the test key K1, the LED pin (pin 156) of the differential chip JH1 is connected with the second end (pin 6) of the indicator light circuit J8; the second end of the test key is grounded.

[0090] The eighth group of pins (pin 27-pin 38, pin 41-pin 52, pin 55, pin 57, pin 60, pin 62, pin 64, pin 66, pin 70, pin 72, pin 74, pin 76, pin 78, pin 80, pin 173-pin 184, pin 187-pin 198, pin 201-pin 208, pin 216, pin 218, pin 224, pin 226) of the differential chip JH1 are connected with the input end of the LVDS differential receiving circuit 11 as the output end of the HUB circuit 12.

[0091] Among them, the pins 178, 180, 188, 190, 196, 198, 206, 208, 216, 218, 224, 226, 32, 34, 42, 44, 50, 52, 60, 62, 70, 72, 78, 80 of the eighth group of pins of the differential chip JH1 are RX receiving signal pins, in addition to which, capacitors C1-C24, resistors R1-R12 are connected with the RX receiving signal pins respectively, the capacitors play the role of direct current isolation and alternating current transmission, and the resistors are impedance matching resistors.

[0092] The pins 173, 175, 174, 176, 177, 179, 181, 183, 182, 184, 187, 189, 191, 193, 195, 197, 192, 194, 202, 204, 201, 203, 205, and 207 of the eighth group of pins of the differential chip JH1 are TX transmitting signal pins.

[0093] The pins 31, 33, 27, 29, 28, 30, 36, 38, 66, 64, 74, 76, 35, 37, 41, 43, 45, 47, 46, 48, 49, 51, 55, and 57 of the eighth group of pins of the differential chip JH1 are clock signal (GCLK) pins.

[0094] In addition, pin 1 of the indicator light circuit J8 is grounded, pin 3 and pin 4 are connected with resistors R45 and R46 respectively and then connected with the power supply VCC3.3.

[0095] In the embodiment, the model of the second input terminal J2 and the third input terminal J3 is HEAD2X5-DIP-2.0-90, the model of the indicator light circuit J8 is HEAD1X6-DIP-2.0-180, and the model of the test button K1 is KEY2X2-SMD-4.

[0096] It should be noted that the present application is only one possible implementation, but is not limited to only this implementation, and can be set by the user as needed.

[0097] The present application provides a HUB circuit structure, under which the LVDS differential signal is processed and then the target differential signal is outputted, so as to realize stable transmission of signal data of more than 70 meters.

[0098] In the embodiment, as a preferred embodiment, as shown in FIG. 4(a) and FIG. 4(b), the high-voltage power supply circuit 13 comprises a fourth input terminal J7 and a power supply circuit, wherein the power supply circuit comprises a switch regulator chip UD1 and a power supply circuit.

[0099] In the embodiment, as a preferred embodiment, as shown in FIG. 4(a) and FIG. 4(b), the high-voltage power supply circuit 13 comprises a fourth input terminal J7 and a power supply circuit, wherein the power supply circuit comprises a switch regulator chip UD1 and a power supply circuit.

[0100] The output pins (pin 2, pin 3, pin 4 and pin 5) of the switch regulator chip UD1 are connected with the input end of the power supply circuit.

[0101] The output end of the power supply circuit is the output end of the high-voltage power supply circuit 13.

[0102] In the embodiment, the fourth input terminal J7 further comprises a diode D1, wherein the diode D1 is connected with the first group of pins of the fourth input terminal J7 and the second group of pins of the fourth input terminal J7.

[0103] As a preferred, the power supply circuit comprises: resistors RB3, RB4, RB2 and RB1; capacitors CE1, CC2, CC1, CE2, CC6 and C33; inductors LU1 and L1; diodes D2 and D3. Wherein, the first pin of the switching regulator chip UD1 and the first end of the capacitor CE1, the first end of the capacitor CC2 are connected in common, and are connected with the first group of pins of the fourth input terminal J7; the second pin of the switching regulator chip UD1 is connected with the first end of the inductor LU1 and the first end of the diode D2; the third pin of the switching regulator chip UD1 is connected with the first end of the resistor RB4 and grounded; the fourth pin of the switching regulator chip UD1 is connected with the first end of the resistor RB2, the first end of the resistor RB3 and the first end of the capacitor CC1; the fifth pin of the switching regulator chip UD1 is connected with the second end of the resistor RB4 and the first end of the resistor RB3; the sixth pin of the switching regulator chip UD1 is grounded; the second end of the capacitor CE1 and the second end of the resistor RB2 are grounded; the second end of the capacitor CC2 is connected with the second end of the resistor RB3; the second end of the inductor LU1 is connected with the second end of the resistor RB1, the second end of the capacitor CC1, the first end of the capacitor CE2, the first end of the capacitor CC6, the first end of the triode D3 and the first end of the inductor L1; the second end of the inductor L1 and the first end of the capacitor CC3 are commonly used as the output end of the high-voltage power supply circuit; the second end of the diode D2 is connected with the second end of the capacitor CE2, the second end of the capacitor CC6, the second end of the triode D3, the second end of the capacitor CC6 and the second end of the capacitor CC3, and is grounded.

[0104] Wherein, the fourth input terminal J7 is used as the power supply input interface of the high-voltage power supply circuit 13, and the switching regulator chip UD1 is used as the circuit management chip of the high-voltage power supply circuit 13, so that the input 24V / 48V voltage is 4.2V, and the LED display module is powered.

[0105] Wherein, as a preferred, the model of the switching regulator chip UD1 is LM2596.

[0106] It should be noted that the present application is only one possible implementation, but is not limited to only this implementation, and can be set by the user as needed.

[0107] The present application provides a specific circuit diagram of a high-voltage power supply circuit, which is used to power the LED display module. Since the input voltage of the high-voltage power supply circuit is high voltage, the overall power line diameter is thinner, the cost is lower, and a stable foundation is provided for long-distance transmission of signal output.

[0108] On the basis of the above embodiment, as a preferred embodiment, as shown in Figure 5, the LVDS differential receiving circuit 21 comprises: a high-speed interface chip UZ2, a first signal enhancement circuit, a second signal enhancement circuit;

[0109] The first group of pins (pin 4-pin 9) of the high-speed interface chip UZ2 are connected to the input end of the LVDS differential receiving circuit and the output end of the HUB circuit; the second group of pins (pin 31-pin 34) of the high-speed interface chip UZ2 are connected to the input end of the first signal enhancement circuit; and the third group of pins (pin 24) of the high-speed interface chip UZ2 are connected to the first end of the second signal enhancement circuit.

[0110] As a preferred embodiment, the high-speed interface chip UZ2 further comprises resistors RZ1, RZ2 and RZ3; capacitors CZ1, CZ2 and CZ9; an LED lamp LED1; and an inductor LZ7. The resistor RZ1 is connected to pin 2 of the high-speed interface chip UZ2 and the LED1, and the other end of the LED1 is connected to VCC3.3V as a power supply end; the resistors RZ2 and RZ3 are respectively connected to pin 10 and pin 11 of the high-speed interface chip UZ2, and are further connected to VCC3.3V; the capacitors CZ1 and CZ2 are respectively connected to pin 5 and pin 6 of the high-speed interface chip UZ2; the first end of the capacitor CZ9 is connected to pin 0 of the high-speed interface chip UZ2 and the first end of the inductor LZ7, and is grounded; and the second end of the capacitor CZ9 is connected to the second end of the inductor LZ7, and is grounded. As a preferred embodiment, the specification of the high-speed interface chip UZ2 is TBS614.

[0111] As a preferred embodiment, the first signal enhancement circuit comprises inductors CZ14, CZ3, CZ5 and CZ4; and resistors RZ10, RZ11, RZ7 and RZ17. The first end of the capacitor CZ3 is connected to the first end of the capacitor CZ14, the first end of the resistor RZ7, the first end of the capacitor CZ4, pin 34 and pin 31 of the high-speed interface chip UZ2, and is further connected to VCC3.3V; the second end of the capacitor CZ3 is connected to the second end of the capacitor CZ14, the first end of the resistor RZ10 and the first end of the resistor RZ11, and is grounded; the second end of the resistor RZ10 and the second end of the resistor RZ11 are connected to pin 33 of the high-speed interface chip UZ2; the second end of the resistor RZ7 is connected to the first end of the resistor RZ17 and the first end of the capacitor CZ5, and is further connected to pin 32 of the high-speed interface chip UZ2; and the second end of the resistor RZ17 and the second end of the capacitor CZ5 are connected to the second end of the capacitor CZ4.

[0112] As a kind of preferred, the second signal enhancement circuit includes: resistors RZ15, RZ18, RZ14 and RZ16;Triode QA2. Wherein, the first end of resistor RZ14 as the first end of second signal enhancement circuit is connected with the pin 24 of high-speed interface chip UZ2, the second end of resistor RZ14 is connected with the first end of resistor RZ15, the first end of resistor RZ18 and the base of triode QA2;The second end of resistor RZ15 is connected with resistor RZ16;The second end of resistor RZ18 is connected with the emitter of triode QA2, and is grounded;The second end of resistor RZ16 is connected with the collector of triode QA2.

[0113] It should be noted that the circuit provided by the present application is only one possible implementation, but is not limited to only this implementation, and can be set by the user as needed.

[0114] The present application provides a specific structure of LVDS differential receiving circuit, under this structure, the signal bandwidth of the display screen provided by the present application is up to 1GHz, the integration is higher, the wiring design is simple, and it is stable and reliable.

[0115] On the basis of the above embodiment, as a preferred embodiment, as shown in Figure 6, the LED display module 2 further comprises:

[0116] The bus driving circuit 22 is used for receiving control signals and driving and amplifying the control signals, and the input end of the bus driving circuit 22 is connected with the output end of the HUB circuit 21;

[0117] The LED module control circuit 23 is used for receiving the control signals after driving and amplification, and displaying the data corresponding to the control signals, and the input end of the LED module control circuit 23 is connected with the output end of the bus driving circuit 22;

[0118] The first-stage voltage reduction circuit 24 is used for receiving the power provided by the high-voltage power supply circuit 13, and supplying power to the LVDS differential receiving circuit 21, the bus driving circuit 22 and the LED module control circuit 23, and the input end of the first-stage voltage reduction circuit 24 is connected with the output end of the high-voltage power supply circuit 13, and the output end of the first-stage voltage reduction circuit 24 is connected with the power supply end of the bus driving circuit 22 and the power supply end of the LED module control circuit 23;

[0119] The second-stage voltage reduction circuit 25 is used for receiving the power provided by the first-stage voltage reduction circuit 24, and supplying power to the LVDS differential receiving circuit 21, and the input end of the second-stage voltage reduction circuit 25 is connected with the output end of the first-stage voltage reduction circuit 24, and the output end of the second-stage voltage reduction circuit 25 is connected with the power supply end of the LVDS differential receiving circuit 21.

[0120] As a preferred, as shown in Figure 7, the first-stage voltage reduction circuit 24 is a DC-DC circuit, which comprises a voltage reduction chip U8, a first RC filter circuit, a second RC filter circuit, a third RC filter circuit and a MOS tube circuit;

[0121] The first group of pins (pin 19, pin 8, pin 2, pin 9, pin 1, pin 11, pin 20 and pin 7) of the voltage reduction chip U8 are connected to the first end of the first RC filter circuit; the second group of pins (pin 7, pin 21, pin 14, pin 3, pin 5, pin 4 and pin 10) of the voltage reduction chip U8 are connected to the first end of the second RC filter circuit; the third group of pins (pin 15, pin 16, pin 17 and pin 18) of the voltage reduction chip U8 are connected to the first end of the MOS tube circuit; the fourth group of pins (pin 6, pin 12 and pin 13) of the voltage reduction chip U8 are connected to the first input end of the third RC filter circuit; the second end of the first RC filter circuit is connected to the output end of the high-voltage power supply circuit 13 as the input end of the first-stage voltage reduction circuit; the second end of the second RC filter circuit is grounded; the second input end of the third RC filter circuit is connected to the output end of the MOS tube circuit, and the output end of the third RC filter circuit is connected to the input end of the second-stage voltage reduction circuit, the power supply end of the bus driving circuit and the power supply end of the LED module control circuit as the output end of the first-stage voltage reduction circuit.

[0122] The first RC filter circuit includes capacitors CE2, C1B, C2B, C3B, C16B, C4B and C5B, and resistors R1B, R3B, R6B, R4B, R5B and R19B. The first end of the capacitor CE2 is connected to the output end (VCC24V / 48V) of the high-voltage power supply circuit 13 and the pin 19 of the voltage reduction chip U8, and the second end of the capacitor CE2 is connected to the second ends of the capacitors C1B, C2B, C3B and C16B, the first end of the resistor R1B and the ground. The second end of the resistor R1B is connected to the pin 8 of the voltage reduction chip U8. The first end of the capacitor C4B is grounded, and the second end of the capacitor C4B is connected to the first end of the resistor R3B and the pin 2 of the voltage reduction chip U8. The second end of the resistor R3B is connected to the pin 9 of the voltage reduction chip U8. The first end of the resistor R6B is connected to VDD3.8V, and the second end of the resistor R6B is connected to the first end of the capacitor C5B and the pin 1 of the voltage reduction chip U8. The second end of the capacitor C5B is connected to the first end of the resistor R4B and the ground. The second end of the resistor R4B is connected to the pin 11 of the voltage reduction chip U8. The first end of the resistor R5B is connected to VCC24V, the first end of the resistor R19 is connected to the signal end (POWER ON / OFF), and the second end of the resistor R5B is connected to the second end of the resistor R19 and the pin 20 of the voltage reduction chip U8.

[0123] The second RC filter circuit includes resistors R2B, R9B, R16B and R20B, and capacitors C8B, C15B and C10B. The first end of the resistor R2B is connected to the pin 7 of the voltage reduction chip U8, and the second end of the resistor R2B is grounded. The first end of the resistor R9B is connected to the first end of the capacitor C8B, and the second end of the resistor R9B is connected to the first ends of the capacitors C15B and C10B, the first end of the resistor R16B and the ground. The second end of the capacitor C8B is connected to the second end of the capacitor C15B and the pin 5 of the voltage reduction chip U8. The second end of the capacitor C10B is connected to the pin 4 of the voltage reduction chip U8. The second end of the resistor R16B is connected to the first end of the resistor R20B, the pin 10 of the voltage reduction chip U8, and the pin 2 of the voltage reduction chip U8. The second end of the resistor R21 is connected to the pin 2 of the voltage reduction chip U8. The pins 21, 14 and 3 of the voltage reduction chip U8 are connected to the ground.

[0124] The MOS tube circuit comprises resistors R12B, R13B, R14B and R15B, capacitors C11B and C6B, a diode D3, and MOS tubes Q5, Q6, Q7, Q8, Q9 and Q10. The first end of the resistor R12B is connected to pin 17 of the voltage reduction chip U8, the second end of the resistor R12B is connected to pin 19 of the voltage reduction chip U8, the drain and gate of the MOS tube Q5, the drain and gate of the MOS tube Q7, and the drain and gate of the MOS tube Q9; the first end of the resistor R13B is connected to pin 18 of the voltage reduction chip U8, the second end of the resistor R13B is connected to the first end of the capacitor C11B and the first end of the diode D3; the second end of the diode D3 is connected to pin 2 of the voltage reduction chip U8; the second end of the capacitor C11B is connected to pin 16 of the voltage reduction chip U8, the source of the MOS tube Q5, the source of the MOS tube Q7, the source of the MOS tube Q9, the gate and drain of the MOS tube Q6, the gate and drain of the MOS tube Q8, the gate and drain of the MOS tube Q10, the first end of the resistor R14B, and the first end of the resistor R15B, and is connected to the second input end of the third RC filter circuit as the output end of the MOS tube circuit; the second end of the resistor R14B is connected to pin 15 of the voltage reduction chip U8; the second end of the resistor R15B is connected to the first end of the capacitor C6B; and the second end of the capacitor C6B is connected to the source of the MOS tube Q6, the source of the MOS tube Q8, and the source of the MOS tube Q10, and is grounded.

[0125] The third RC filter circuit comprises: an inductor L1B; resistors R17B, R21B, R7B, R8B, R18B, R10B and R11B; and capacitors C14B, C7B, CC4, CC5, CC6, CC7, C13B and C9B. The first end of the inductor L1B is connected to the output end of the MOS tube circuit as the second input end of the third RC filter circuit. The second end of the inductor L1B is connected to the first end of the resistor R17B, the first end of the resistor R21B and the first end of the resistor R7B. The second end of the resistor R17B is connected to the first end of the resistor R21B, the first end of the resistor R8B, the first end of the resistor R18B, the first end of the resistor R11B, the first end of the capacitor CC4, the first end of the capacitor CC5, the first end of the capacitor CC6, the first end of the capacitor CC7, the first end of the capacitor C13B, the first end of the capacitor C12B, the first end of the capacitor C9B, and is connected to the output end of the third RC filter circuit, the power supply end of the LVDS differential receiving circuit 21, the power supply end of the bus driving circuit 22 and the power supply end of the LED module control circuit 23. The second end of the resistor R7B is connected to the first end of the capacitor C14B and the pin 13 of the voltage reduction chip U8. The second end of the resistor R8B is connected to the second end of the capacitor C14B and the pin 12 of the voltage reduction chip U8. The second end of the resistor R18B is connected to the first end of the resistor R10B, the pin 6 of the voltage reduction chip U8 and the first end of the capacitor C7B. The second end of the resistor R10B is grounded. The second end of the resistor R11B is connected to the second end of the capacitor C7B. The second end of the capacitor CC4, the second end of the capacitor CC5, the second end of the capacitor CC6, the second end of the capacitor CC7, the second end of the capacitor C13B, the second end of the capacitor C12B and the second end of the capacitor C9B are connected and grounded.

[0126] The bus driving circuit 22 includes a first bus transceiver chip UZ3 and a second bus transceiver chip UZ4, and the model of the first bus transceiver chip UZ3 and the second bus transceiver chip UZ4 is 74HC245-0.65. The first group of pins (pin 18, pin 16 and pin 15) of the first bus transceiver chip UZ3 is connected with the fourth group of pins (pin 18, pin 19 and pin 20) of the high-speed interface chip UZ2; the second group of pins (pin 13, pin 12 and pin 11) of the first bus transceiver chip UZ3 is connected with the fifth group of pins (pin 23, pin 22 and pin 21) of the high-speed interface chip UZ2; the third group of pins (pin 2, pin 4, pin 5, pin 7, pin 8 and pin 9) of the first bus transceiver chip UZ3 is grounded, and in the process of grounding, each pin is connected with a capacitor respectively, which are CF1, CF2, CF3, CF4, CF5 and CF6 respectively; the power pin (pin 20) of the first bus transceiver chip UZ3 is connected with the output end of the first step-down circuit 24 as the power supply end of the bus driving circuit 22; in addition, the pin 17, pin 14, pin 1, pin 10 and pin 19 of the first bus transceiver chip UZ3 are grounded, and the pin 10, pin 19 and pin 20 of the first bus transceiver chip UZ3 further include a capacitor CZ6 in the process of connection.

[0127] The first group of pins (pin 2-pin 7) of the second bus transceiver chip UZ4 is connected with the sixth group of pins (pin 40-pin 35) of the high-speed interface chip UZ2, and the second group of pins (pin 18-pin 13) of the second bus transceiver chip UZ4 is connected with the input end of the LED module control circuit as the output end of the bus driving circuit; the power pin (pin 20) of the second bus transceiver chip UZ4 is connected with the output end of the second step-down circuit 25 as the power supply end of the bus driving circuit 22; the first group of pins of the first bus transceiver chip UZ3, the second group of pins of the first bus transceiver chip UZ3 and the first group of pins of the second bus transceiver chip UZ4 are collectively used as the input end of the bus driving circuit 22. In addition, the pin 8, pin 9 and pin 10 of the second bus transceiver chip UZ4 are grounded; the pin 19 of the second bus transceiver chip UZ4 is connected with the pin 20 in the process of connection, and the pin 19 is grounded; the pin 1 of the second bus transceiver chip UZ4 is connected with the pin 20; the pin 11 and pin 12 of the second bus transceiver chip UZ4 are empty pins.

[0128] As a preferred embodiment, the second step-down circuit 25 is an LDO circuit, which includes a voltage stabilizer chip UZ1 and a voltage stabilizing circuit.

[0129] The input pin (pin 3) of the voltage stabilizer chip UZ1 is connected to the output terminal of the high-voltage power supply circuit 13 as the input terminal of the secondary voltage reduction circuit 25, and the output pin (pin 2 and pin 4) of the voltage stabilizer chip UZ1 is connected to the input terminal of the voltage stabilizing circuit; the output terminal of the voltage stabilizing circuit is connected to the output terminal of the secondary voltage reduction circuit 25 and the power supply terminal of the LVDS differential receiving circuit 22.

[0130] The voltage stabilizing circuit includes capacitors CZ15, CZ16 and CZ13. The first end of the capacitor CZ15, the first end of the capacitor CZ16 and the first end of the capacitor CZ13 are connected to pin 2 of the voltage stabilizer chip UZ1 and pin 4 of the voltage stabilizer chip UZ1, and are connected to the output terminal of the secondary voltage reduction circuit 35 and the power supply terminal of the LVDS differential receiving circuit 21. The second end of the capacitor CZ15 and the second end of the capacitor CZ16 are connected to the second end of the capacitor CZ13 and are grounded. In addition, it also includes a capacitor C12, wherein the first end of the capacitor C12 is connected to pin 3 of the voltage stabilizer chip UZ1, and the second end of the capacitor C12 is connected to pin 1 of the voltage stabilizer chip UZ1 and is grounded.

[0131] As a preferred, as shown in FIG. 10, the LED module control circuit 23 includes a terminal JO1, wherein the first group of pins (pin 1-pin 6) of the terminal JO1 are connected to the second group of pins (pin 18-pin 13) of the second bus transceiver chip UZ4; the second group of pins (pin 13-16) of the terminal JO1 are connected to the pins (pin 27-pin 30) of the high-voltage high-speed interface chip UZ2.

[0132] Under the structure of the above circuit, the specific embodiment of the display control system provided by the application is: the second input terminal J2 and the third input terminal J3 are network control signals of the system power control box 1, J8 is a pilot lamp circuit of the system power control box 1, and K1 is a test button of the system power control box 1. The fourth input terminal J7 is a 24V / 48V power supply input interface, and the switch regulator chip UD1 reduces the input 24V / 48V voltage to 4.2V to supply power to the system power control box 1 and the HUB circuit 12. The system power control box 1 converts the TTL / COMS signal (which contains 12 RGB data signals, 5 decoding signals (ABCDE) and 3 control signals (DCLK, GCLK, LAT)) into a set of high-integration three-pair LVDS differential signals (TX\RX\GCLK) with a bandwidth close to 1GHz, which is output to the first input terminal J4 after impedance matching by the HUB circuit 12 and processing by the first diode array chip T1 and the second diode array chip T2. The system power control box 1 can output a maximum of 12 sets of high-bandwidth high-integration LVDS differential signals, and each set of high-bandwidth high-integration LVDS differential signal can be stably transmitted to the LED display module 2 for more than 70 meters, and the high-voltage power supply circuit of the system power control box 1 outputs DC 24-48V voltage, which can realize high-voltage long-distance transmission to the LED display module 2.

[0133] The LED display module includes a high-speed interface chip UZ2 (TBS614) for processing the LVDS differential signal, a bus driving circuit 22, a secondary voltage reduction circuit 25 and a primary voltage reduction circuit 24. The high-speed interface chip UZ2 (TBS614) has a bandwidth of up to 1GHz, can convert the set of LVDS differential signals (TX\RX\GCLK) output by the system control power supply box 1 into TTL / COMS signals (which contain 12 RGB data signals, 5 decoding signals (ABCDE) + 3 control signals (DCLK, GCLK, LAT)) after long-distance transmission through a line more than 60 meters long, and send the TTL / COMS signals to the LED module control circuit 23 after driving amplification processing by the first bus transceiver chip UZ3 and the second bus transceiver chip UZ4. The TBS614 can effectively reduce the number of interconnection lines, simplify the design wiring, improve the stability of transmission, support clock spread spectrum adjustment function, and be easy to pass EMC detection. The secondary voltage reduction circuit 25 is an LDO circuit, which outputs 3.3V to supply power to the high-speed interface UZ2, the first bus transceiver chip UZ3 and the second bus transceiver chip UZ4. The primary voltage reduction circuit 24 reduces the DC 24-48V voltage output by the high-voltage power supply circuit 13 of the system control power supply box 1 to 3.8V to supply power to the circuit in the LED display module 2 after long-distance transmission through a high-voltage long line.

[0134] It should be noted that the circuit provided in this application is only one possible implementation method, but is not limited to this one implementation method. Users can configure it according to their own needs.

[0135] This application provides a display control system comprising: a system power control box and an LED display module; wherein the system power control box includes: an LVDS differential transmitting circuit for converting a target signal into an LVDS differential signal, the input terminal of which is connected to the transmitting terminal of the target signal; and a HUB circuit for converting the LVDS differential signal into a target differential signal, the input terminal of which is connected to the output terminal of the LVDS differential transmitting circuit; the LED display module includes: an LVDS differential receiving circuit for receiving the target differential signal and converting it into a control signal, the input terminal of which is connected to the output terminal of the HUB circuit. Therefore, the display control system provided in this application consists of two parts: a system power control box and an LED display module. The LVDS differential transmitting circuit directly converts the target signal into a high-bandwidth, highly integrated LVDS differential signal. This signal is then processed by a hub circuit and output as the target differential signal. This differential signal can achieve stable output over long distances and is sent to the LED display module. The LVDS differential receiving circuit in the LED display module converts the target differential signal into a control signal, which is then displayed on the screen as the corresponding data. This ensures that when the display control system is used outdoors, the system power control box can be installed indoors, thereby improving the safe and reliable operation of the system power control box and increasing the convenience of component maintenance.

[0136] To address the aforementioned technical problems, this application also provides an LED display device, including the aforementioned display control system, and possessing the same beneficial effects. The embodiments of the electronic device provided in this application are the same as those described above, and will not be repeated here.

[0137] The foregoing has provided a detailed description of a display control system and an LED display device provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from the principles thereof, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0138] It also needs to be explained that in the present specification, the relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

Claims

1. A display control system, comprising: System power control box and LED display module; The system power control box includes: an LVDS differential transmission circuit for converting a target signal into an LVDS differential signal, wherein the input terminal of the LVDS differential transmission circuit is connected to the transmission terminal of the target signal; and a HUB circuit for converting the LVDS differential signal into a target differential signal, wherein the input terminal of the HUB circuit is connected to the output terminal of the LVDS differential transmission circuit. The LED display module includes an LVDS differential receiving circuit for receiving the target differential signal and converting the target differential signal into a control signal, wherein the input terminal of the LVDS differential receiving circuit is connected to the output terminal of the HUB circuit.

2. The display control system according to claim 1, wherein, The LVDS differential transmission circuit includes: a first diode array chip, a second diode array chip, and a first input terminal; The first set of pins of the first diode array chip, the second set of pins of the first diode array chip, the first set of pins of the first input terminal are connected to the first terminal of the HUB circuit, and the third set of pins of the first diode array chip, the fourth set of pins of the first diode array chip, the second set of pins of the first input terminal are connected to the second terminal of the HUB circuit. The first set of pins of the second diode array chip, the second set of pins of the second diode array chip, and the third set of pins of the first input terminal are connected to the third terminal of the HUB circuit. The first group of pins, the second group of pins, the third group of pins, and the fourth group of pins of the first diode array chip, the first group of pins, the second group of pins of the second diode array chip, and the first group of pins, the second group of pins, and the third group of pins of the first input terminal together serve as the output terminal of the LVDS differential transmission circuit; the first terminal, the second terminal, and the third terminal of the HUB circuit together serve as the input terminal of the HUB circuit.

3. The display control system according to claim 2, wherein, The HUB circuit includes: a differential chip, a second input terminal, a third input terminal, an indicator light circuit, and a test button; Wherein, the first set of pins of the differential chip serves as the first terminal of the HUB circuit and is connected to the first set of pins of the first diode array chip, the second set of pins of the first diode array chip, and the first set of pins of the first input terminal; the second set of pins of the differential chip serves as the second terminal of the HUB circuit and is connected to the third set of pins of the first diode array chip, the fourth set of pins of the first diode array chip, and the second set of pins of the first input terminal; the third set of pins of the differential chip serves as the third terminal of the HUB circuit and is connected to the first set of pins of the second diode array chip, the second set of pins of the second diode array chip, and the third set of pins of the first input terminal. The fourth set of pins of the differential chip is connected to the first set of pins of the second input terminal, and the fifth set of pins of the differential chip is connected to the second set of pins of the second input terminal. The sixth group of pins of the differential chip is connected to the first group of pins of the third input terminal, and the seventh group of pins of the differential chip is connected to the second group of pins of the third input terminal. The button pin of the differential chip is connected to the first terminal of the indicator light circuit and the first terminal of the test button; the LED pin of the differential chip is connected to the second terminal of the indicator light circuit; the second terminal of the test button is grounded. The eighth group of pins of the differential chip is connected to the input of the LVDS differential receiver circuit as the output terminal of the HUB circuit.

4. The display control system according to any one of claims 1-3, wherein, The system power control box also includes a high-voltage power supply circuit for supplying power to the LED display module, and the input terminal of the high-voltage power supply circuit is connected to the power supply terminal.

5. The display control system according to claim 4, wherein, The high-voltage power supply circuit includes: a fourth input terminal and a power supply circuit; wherein, the power supply circuit includes a switching regulator chip and a power supply circuit; The fourth input terminal is connected to the power supply terminal as the input terminal of the high-voltage power supply circuit. The first set of pins of the fourth input terminal is connected to the input pins of the switch regulator chip, and the second set of pins of the fourth input terminal is grounded. The output pin of the switch regulator chip is connected to the input terminal of the power supply circuit; The output terminal of the power supply circuit serves as the output terminal of the high-voltage power supply circuit.

6. The display control system according to any one of claims 1-5, wherein, The LVDS differential receiver circuit includes: a high-speed interface chip, a first signal enhancement circuit, and a second signal enhancement circuit; The first set of pins of the high-speed interface chip is connected to the output of the HUB circuit as the input of the LVDS differential receiver circuit; the second set of pins of the high-speed interface chip is connected to the input of the first signal enhancement circuit; and the third set of pins of the high-speed interface chip is connected to the first terminal of the second signal enhancement circuit.

7. The display control system according to claim 6, wherein, The LED display module also includes: A bus driver circuit is used to receive the control signal and amplify the control signal. The input terminal of the bus driver circuit is connected to the output terminal of the HUB circuit. An LED module control circuit is used to receive the amplified control signal and display the corresponding data of the control signal. The input terminal of the LED module control circuit is connected to the output terminal of the bus drive circuit. A first-stage step-down circuit is used to receive the power provided by the high-voltage power supply circuit and to power the LVDS differential receiving circuit, the bus driving circuit and the LED module control circuit. The input terminal of the first-stage step-down circuit is connected to the output terminal of the high-voltage power supply circuit, and the output terminal of the first-stage step-down circuit is connected to the power supply terminal of the bus driving circuit and the power supply terminal of the LED module control circuit. A second-stage buck circuit is used to receive the power provided by the first-stage buck circuit and to power the LVDS differential receiver circuit. The input terminal of the second-stage buck circuit is connected to the output terminal of the first-stage buck circuit, and the output terminal of the second-stage buck circuit is connected to the power supply terminal of the LVDS differential receiver circuit.

8. The display control system according to claim 7, wherein, The first-stage buck circuit includes: a buck chip, a first RC filter circuit, a second RC filter circuit, a third RC filter circuit, and a MOSFET circuit; The first set of pins of the buck converter chip is connected to the first terminal of the first RC filter circuit; the second set of pins of the buck converter chip is connected to the first terminal of the second RC filter circuit; the third set of pins of the buck converter chip is connected to the first terminal of the MOS transistor circuit; and the fourth set of pins of the buck converter chip is connected to the first input terminal of the third RC filter circuit. The second terminal of the first RC filter circuit is connected to the output terminal of the high-voltage power supply circuit as the input terminal of the first-stage step-down circuit. The second terminal of the second RC filter circuit is grounded; The second input terminal of the third RC filter circuit is connected to the output terminal of the MOS transistor circuit. The output terminal of the third RC filter circuit serves as the output terminal of the first-stage buck circuit and is connected to the input terminal of the second-stage buck circuit, the power supply terminal of the bus driver circuit, and the power supply terminal of the LED module control circuit.

9. The display control system according to claim 8, wherein, The bus driving circuit includes: a first bus transceiver chip and a second bus transceiver chip. Wherein, the first group of pins of the first bus transceiver chip is connected to the fourth group of pins of the high-speed interface chip; the second group of pins of the first bus transceiver chip is connected to the fifth group of pins of the high-speed interface chip; the third group of pins of the first bus transceiver chip is grounded; and the power supply pin of the first bus transceiver chip is connected to the output terminal of the first-stage buck circuit as the power supply terminal of the bus drive circuit. The first set of pins of the second bus transceiver chip is connected to the sixth set of pins of the high-speed interface chip; the second set of pins of the second bus transceiver chip is connected to the input of the LED module control circuit as the output of the bus driver circuit; the power supply pin of the second bus transceiver chip is connected to the output of the first-stage buck circuit as the power supply of the bus driver circuit. The first set of pins of the first bus transceiver chip, the second set of pins of the first bus transceiver chip, and the first set of pins of the second bus transceiver chip together serve as the input terminals of the bus driver circuit.

10. The display control system according to claim 8 or 9, wherein, The secondary step-down circuit includes: a voltage regulator chip and a voltage regulator circuit; The input pin of the voltage regulator chip is connected to the output of the high-voltage power supply circuit as the input terminal of the secondary step-down circuit, and the output pin of the voltage regulator chip is connected to the input terminal of the voltage regulator circuit. The output terminal of the voltage regulator circuit is connected to the power supply terminal of the LVDS differential receiver circuit, serving as the output terminal of the secondary step-down circuit.

11. The display control system according to any one of claims 1-10, wherein, The LVDS differential signal includes 12 sets of RGB data signals, 5 decoding signals, and 3 clock command signals.

12. The display control system according to any one of claims 1-11, wherein, The target differential signal includes three pairs of differential signals, namely a pair of TX differential signals, a pair of RX differential signals, and a pair of GCLK differential signals.

13. An LED display device comprising the display control system according to any one of claims 1-12.

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