Signal processing method, signal processing apparatus, and storage medium, computer device and computer program product

Abstract

Disclosed in the embodiments of the present application are a signal processing method and apparatus, and a storage medium and a device. The method comprises: acquiring a delay instruction of a modulation signal, and determining the number of target delayed clock cycles corresponding to the delay instruction; on the basis of the number of target delayed clock cycles, performing an exact division operation on the number of standard clock cycles, and on the basis of an exact division operation result, generating at least one no-operation instruction; on the basis of the number of target delayed clock cycles, performing a modulo operation on the number of standard clock cycles, and on the basis of a modulo operation result, determining the number of delayed clock cycles of a preset length; after the at least one no-operation instruction, on the basis of the number of delayed clock cycles of the preset length, performing delay supplementation on the modulation signal, so as to generate a modulation signal that has been subjected to delay supplementation; and performing, in advance and by the number of standard clock cycles, signal demodulation on the modulation signal that has been subjected to delay supplementation, so as to obtain a signal demodulation result.

Description

Signal processing method, signal processing device, storage medium, computer device, and computer program product

[0001] Cross-reference to related applications

[0002] The present application is based on and claims priority to Chinese Patent Application No. 2024108555717, filed on June 27, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the field of quantum technology, and in particular to a signal processing method, a signal processing device, a storage medium, a computer device, and a computer program product. BACKGROUND

[0004] A quantum computer can perform a computing task using a quantum bit, and the essence of the computing task is to perform a quantum gate operation on the quantum bit. However, there is a certain deviation between the computing result obtained by the quantum gate operation and the expected result, and therefore, the quantum gate needs to be calibrated before performing the computing task, so as to improve the accuracy of the quantum computing result. The closeness between the computing result actually obtained by the quantum gate operation and the expected result is the fidelity of the quantum gate, and the fidelity of the quantum gate can be improved through calibration means.

[0005] In related technologies, in order to obtain higher fidelity of the quantum gate, various phase micro-processing needs to be performed on the calibration signal. In terms of signal level description, a clock delay processing is performed on each calibration signal through a delay instruction, so as to avoid noise between multiple calibration signals and affect the fidelity of the quantum gate.

[0006] However, in order to ensure stable operation of the quantum computer, a no operation (NOP) instruction and a standard clock cycle number required when the NOP instruction is executed need to be set. Since the clock cycle number of the delay instruction is usually not a multiple of the standard clock cycle number, a certain delay clock cycle number needs to be supplemented to align the delay instruction, so that the delay instruction and the NOP instruction are in step. However, the supplemented delay clock cycle number will cause redundant clock consumption and increase the calibration time of the quantum gate. SUMMARY

[0007] The embodiments of the present application provide a signal processing method, a signal processing device, a storage medium, a computer device, and a computer program product, which can reduce the clock cycle number of signal processing, thereby reducing the calibration time of the quantum gate and improving the calibration efficiency of the quantum gate.

[0008] To solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0009] A signal processing method, the method is executed by a computer device, comprising:

[0010] Obtain a delay instruction of a modulation signal, and determine a target delay clock cycle number corresponding to the delay instruction;

[0011] Divide the standard clock cycle number by the target delay clock cycle number, and generate at least one no-operation instruction according to the division result;

[0012] Perform a modulo operation on the standard clock cycle number based on the target delay clock cycle number, and determine a delay clock cycle number of a preset length according to the modulo operation result;

[0013] After the at least one no-operation instruction, delay supplement the modulation signal according to the delay clock cycle number of the preset length, and generate a delay-supplemented modulation signal;

[0014] Signal demodulation is performed on the delay-supplemented modulation signal in advance by the standard clock cycle number, and a signal demodulation result is obtained.

[0015] A signal processing method and device, comprising:

[0016] An obtaining unit configured to obtain a delay instruction of a modulation signal, and determine a target delay clock cycle number corresponding to the delay instruction;

[0017] A division unit configured to divide the standard clock cycle number by the target delay clock cycle number, and generate at least one no-operation instruction according to the division result;

[0018] A modulo unit configured to perform a modulo operation on the standard clock cycle number based on the target delay clock cycle number, and determine a delay clock cycle number of a preset length according to the modulo operation result;

[0019] A delay supplement unit configured to delay supplement the modulation signal according to the delay clock cycle number of the preset length after the at least one no-operation instruction, and generate a delay-supplemented modulation signal, the clock cycle number of the delay-supplemented modulation signal being the same as the standard clock cycle number;

[0020] A signal demodulation unit configured to perform signal demodulation on the delay-supplemented modulation signal in advance by the standard clock cycle number, and obtain a signal demodulation result.

[0021] A computer-readable storage medium, the computer-readable storage medium stores a plurality of instructions, the instructions are suitable for being loaded by a processor to execute the above-mentioned signal processing method.

[0022] A computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the above signal processing method when executing the computer program.

[0023] A computer program product or computer program comprises computer instructions stored in a storage medium. The processor of a computer device reads the computer instructions from the storage medium, and the processor executes the computer instructions to implement the above signal processing method.

[0024] The embodiment of the present application obtains a delay instruction of a modulation signal, and determines a target delay clock cycle number corresponding to the delay instruction; performs integer division operation on a standard clock cycle number according to the target delay clock cycle number, and generates at least one no-operation instruction according to an integer division operation result; performs modulo operation on the standard clock cycle number based on the target delay clock cycle number, and determines a delay clock cycle number of a preset length according to a modulo operation result; after the at least one no-operation instruction, delays and supplements the modulation signal according to the delay clock cycle number of the preset length to generate a delayed and supplemented modulation signal, and the clock cycle number of the delayed and supplemented modulation signal is the same as the standard clock cycle number; and performs signal demodulation on the delayed and supplemented modulation signal in advance by the standard clock cycle number to obtain a signal demodulation result.

[0025] In this way, the integer division operation is performed on the standard clock cycle number according to the target delay clock cycle number obtained, at least one no-operation instruction is generated according to an integer division operation result, to avoid missing part of the clock cycle number of the target delay clock cycle number caused by the at least one no-operation instruction, the modulo operation is performed on the standard clock cycle number based on the target delay clock cycle number, the delay clock cycle number of the preset length that needs to be delayed and supplemented is determined according to a modulo operation result, and then the modulation signal is delayed and supplemented according to the delay clock cycle number of the preset length to generate a delayed and supplemented modulation signal, thereby avoiding the missing caused by directly using the target delay clock cycle number in the related art, and the delayed and supplemented modulation signal is a standard clock cycle number that can be directly executed, accordingly, the signal demodulation can be performed in advance by the standard clock cycle number at the demodulation end to obtain a signal demodulation result, compared with the scheme in the related art that needs to align the delay instruction by supplementing a certain delay clock cycle number, the present application can also realize signal alignment without supplementing a certain delay clock cycle to the delay instruction, reduces the clock cycle number of signal processing, and further reduces the calibration time of the quantum gate and improves the calibration efficiency of the quantum gate.

[0026] Other features and advantages of the embodiments of the present application will be set forth in the following description, and in part will be apparent from the description, or can be learned by practice of the embodiments of the present application. The objects and other advantages of the embodiments of the present application will be realized and attained by the structure particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0028] Fig. 1 is a system architecture diagram of a quantum computing application provided by the embodiments of the present application.

[0029] Fig. 2 is a structural schematic diagram of quantum bit calibration provided by the embodiments of the present application.

[0030] Fig. 3 is a scene schematic diagram of a signal processing system provided by the embodiments of the present application.

[0031] Fig. 4 is a first flow schematic diagram of a signal processing method provided by the embodiments of the present application.

[0032] Fig. 5 is a first timing schematic diagram of a signal processing system provided by the embodiments of the present application.

[0033] Fig. 6 is a second timing schematic diagram of a signal processing system provided by the embodiments of the present application.

[0034] Fig. 7 is a third timing schematic diagram of a signal processing system provided by the embodiments of the present application.

[0035] Fig. 8 is a fourth timing schematic diagram of a signal processing system provided by the embodiments of the present application.

[0036] Fig. 9 is a second flow schematic diagram of a signal processing method provided by the embodiments of the present application.

[0037] Fig. 10 is a structural schematic diagram of a signal processing method device provided by the embodiments of the present application.

[0038] Fig. 11 is a structural schematic diagram of a terminal provided by the embodiments of the present application.

[0039] Fig. 12 is a structural schematic diagram of a server provided by the embodiments of the present application. DETAILED DESCRIPTION

[0040] In order to make the person skilled in the art better understand the scheme of the present application, the technical scheme in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor fall within the scope of protection of the present application.

[0041] It should be noted that in some processes described in the specification, claims and the above drawings, a plurality of steps appearing in a specific order are included, but it should be clearly understood that these steps can be executed or executed in parallel without the order appearing in the text, and the step number is only used to distinguish different steps, and the number itself does not represent any execution order. In addition, the descriptions such as "first", "second" or "target" in this paper are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0042] Before further detailing the embodiments of the present application, the terms and terms involved in the embodiments of the present application are explained, and the terms and terms involved in the embodiments of the present application are applicable to the following explanations:

[0043] 1) Quantum computing: Quantum computing is a computing method designed using the principles of quantum mechanics. The biggest difference between it and traditional computing is that it uses quantum bits (qubits) instead of traditional binary bits (bits) for computing. Quantum bits have different characteristics from traditional binary bits, the most important of which is that they can be in multiple states at the same time. Take the famous "Schrödinger's cat" as an example. A cat is locked in a sealed container with a small amount of radium and cyanide. The decay of radium exists a probability, if the radium decays, it will trigger the mechanism to break the bottle containing cyanide, and the cat will die; if the radium does not decay, the cat will survive. According to quantum mechanics theory, since the radioactive radium is in a superposition of decay and no decay, the cat should be in a superposition of dead and alive. The cat that is both dead and alive is called "Schrödinger's cat". However, it is impossible for a cat to be both dead and alive, so the result must be known after opening the container. However, because quantum bits can represent two states at the same time, they carry more information, and the same number of quantum bits can perform more data operations than classical computing, so quantum computing greatly improves the processing speed of computers.

[0044] 2) Quantum: The quantum in "quantum computing" refers to the smallest discrete unit used by the system to calculate the output.

[0045] 3) Qubit: The basic unit of information in quantum computing. Qubits play a similar role in quantum computing as bits do in classical computing, but their behavior is very different. Classical bits are binary, storing either a 0 or a 1 bit, but qubits can store superpositions of all possible states, such as the superposition of state |0> and state |1>, or the "dead" and "alive" states of Schrödinger's cat, but before the box is opened, the cat is in a superposition of both states. Because qubits can represent two states at once, they carry more information, allowing the same number of qubit units to perform more data operations than classical computers. This greatly increases the speed of computer processing.

[0046] 4) Superconducting quantum chip: The central processing unit of a superconducting quantum computer. A quantum computer is a machine that uses the principles of quantum mechanics to perform calculations. Based on the superposition principle and quantum entanglement of quantum mechanics, quantum computers have strong parallel processing capabilities and can solve some problems that classical computers cannot calculate. The zero-resistance property of superconducting qubits and the manufacturing process close to integrated circuits make the quantum computing system built with superconducting qubits one of the most promising systems for realizing practical quantum computing.

[0047] 5) IQ modulation / demodulation: IQ modulation is a frequency conversion technique in signal processing. I is in-phase, and q is quadrature. An IQ mixer is used to change the intermediate frequency (IF) signal used for analog signal modulation into a radio frequency (RF) signal (modulation / upconversion). The radio frequency signal is a modulated electric wave with a certain transmission frequency; when demodulating, the radio frequency signal is demodulated into an intermediate frequency signal (an intermediate frequency signal is a signal obtained by converting a high frequency signal, and to enable the amplifier to work stably and reduce interference, a general receiver converts a high frequency signal into an intermediate frequency signal) (demodulation / downconversion). Both IQ upconversion and downconversion use IQ mixers. In IQ modulation, the modulation signal refers to a signal composed of two orthogonal components, namely the in-phase (I) component and the quadrature (Q) component.

[0048] 6) Envelope: In the time domain, the envelope of a signal is the profile of its waveform. Envelope analysis is important in signal processing because it can help us understand the dynamic characteristics of a signal, such as its intensity, frequency, and phase changes. By analyzing the envelope of a signal, we can extract useful information from the signal, achieving the goals of signal demodulation, feature extraction, and fault diagnosis.

[0049] 7) Phase: A key parameter of a signal in the time domain, it describes the state of the signal waveform at a specific time. Phase is usually represented by an angle (degrees or radians), ranging from 0 to 360 degrees (or 0 to 2π radians).

[0050] 8) Delay instruction: In an IQ modulation system, an instruction that ensures the time synchronization of the signal paths of the I (in-phase) and Q (quadrature) components by introducing a delay. In order to ensure that the I (in-phase) and Q (quadrature) components can be correctly modulated and demodulated, the signal paths of the I (in-phase) and Q (quadrature) components need to be synchronized in time, which can be achieved by introducing a delay. This may be achieved through a specific instruction, which can be referred to as a "delay instruction".

[0051] 9) NO Operation (NOP): A pseudo instruction that will not be translated into any machine code, used for delay execution. In complex quantum control, due to the time delay of signal transmission and processing, different parts of the control signal may not be able to execute synchronously. The NOP instruction can be introduced as a buffering mechanism to ensure stable operation of quantum computing and optimize the execution efficiency of quantum instructions, ensuring that all control signals take effect at the correct time point.

[0052] 10) qubit calibration: The standardization of the control process of quantum states is the calibration process of qubits. Qubits are currently a storage and computing integrated structure, and data storage and operation control need to be based on accurate control of quantum states. After calibration, the qubit can maintain accurate control within a certain range of accuracy for a period of time.

[0053] 11) Quantum Gate: A basic operation in quantum computing, similar to logical gates in classical computing (such as AND, OR, NOT, etc.). It is used to perform specific operations on qubits, thus realizing the core component of quantum computing. Quantum gates can change the state of qubits, transfer information from one qubit to another, or create quantum entanglement, etc. Quantum gate function: according to the needs of the computing task, combine quantum circuits, then execute each quantum gate operation in the order of the quantum circuit, and finally get the computing result.

[0054] Common quantum gates include but are not limited to H gate, X gate, Y gate and Z gate:

[0055] Hadamard gate (H gate): Hadamard gate can transform a classical bit state (0 or 1) into a superposition state (|0>+|1>) or its inverse transformation. It is commonly used to create and manipulate superposition states, and is used in quantum algorithms for initial state preparation and interference phenomena.

[0056] Pauli-X gate (X gate): The Pauli-X gate is similar to the NOT gate in classical computing, which turns 0 to 1 and 1 to 0. It is used to perform a quantum bit flip operation in quantum computing.

[0057] Pauli-Y gate (Y gate): The Pauli-Y gate is similar to the X gate, but also introduces a complex factor, which is used to perform a quantum bit flip and phase transformation in quantum computing.

[0058] Pauli-Z gate (Z gate): The Pauli-Z gate performs a phase inversion operation on the bit, which keeps the phase of |0> unchanged and reverses the phase of |1>. It is used to change the relative phase of the quantum bit.

[0059] In order to better illustrate the embodiments of the present application, please refer to FIG. 1 and FIG. 2, FIG. 1 is a system architecture diagram of quantum computing application provided by the embodiments of the present application, and FIG. 2 is a structure diagram of quantum bit calibration provided by the embodiments of the present application.

[0060] In FIG. 1, it includes quantum chip A, dilution refrigerator B, control device C and computer D, etc.

[0061] The quantum chip A is a circuit acting on physical quantum bits, which is used to control quantum bits to perform quantum computing tasks, and also used to apply different calibration methods for quantum gates when performing fidelity calibration of quantum gates. A large number of quantum bit units are distributed in the quantum chip A.

[0062] The dilution refrigerator B is used to provide an extremely low temperature environment, such as 10 millikelvin (mk), for the quantum chip A, which helps to control the thermal noise in the quantum chip A and improve the performance of the quantum chip.

[0063] The control device C is used to control the quantum chip A to perform quantum computing tasks. The control device C can be an electronic control system or a microwave control system, etc. The computer D is used to initiate control instructions to the control device C. For example, the well-written quantum program is compiled by the computer D to generate instructions sent to the control device C. The control device C converts the above instructions into microwave control signals and transmits them to the quantum chip A, which controls the quantum bits by the quantum chip A. The computer D can be a quantum computer, or a hybrid execution environment of classical computer and quantum computer.

[0064] In some embodiments, please continue to refer to FIG. 2, in the calibration process of the superconducting quantum bit, the currently commonly used method is based on the IQ mixing technology, through the IQ mixer E, the low frequency control signal (bit measurement frequency) is converted into a high frequency signal, and the converted high frequency signal is transmitted to the location where the quantum chip is located through the microwave transmission line. At the receiving end, another IQ mixer E (which can also be understood as a demodulator) is used to down-convert the received high frequency signal back to a low frequency control signal, so as to perform digital signal processing (DSP) on the low frequency control signal, such as filtering, sampling and digital demodulation, etc. In this way, various calibration tasks of the quantum bit are realized, such as various quantum gate standards.

[0065] In the related art, when the computer D receives a quantum computing task, it needs to determine the quantum bit in the quantum chip A that can execute the quantum computing task from a large number of quantum bits in the quantum chip A. As can be seen, for different quantum computing tasks, the quantum bits used in the quantum chip A can be different. Therefore, before the computer D executes each quantum computing task, the fidelity of the plurality of quantum gates corresponding to the corresponding quantum bit can be calibrated to improve the accuracy of the execution result of the quantum computing task. If the computer D receives a plurality of quantum computing tasks, the fidelity of the plurality of quantum gates corresponding to the quantum bit used for each quantum computing task can be calibrated in turn. If the fidelity calibration of the quantum gate for a quantum computing task takes a long time, the execution of other quantum computing tasks will also be delayed, therefore, the speed of the fidelity calibration of the quantum gate is particularly important for the speed of the quantum computing task.

[0066] Under a specific quantum computing task, it is necessary to determine a plurality of quantum bits participating in the calculation, and to calibrate the fidelity of the plurality of quantum gates corresponding to each quantum bit. Since the quantum gate calibration essentially controls the state of the quantum bit by applying a radio frequency modulation signal to the quantum bit, thereby realizing gate operation, in the calibration process, a large amount of signals will be generated. Due to the calibration of multiple quantum bits and the length transformation of the quantum circuit, the signals in different parts cannot be synchronized to take effect, which affects the stable operation of the quantum computing, therefore, a no-operation instruction is introduced, which corresponds to a number of standard clock cycles, which is a standardized instruction period, for example, 20 clock cycles (Clock Cycles).

[0067] In order to obtain higher fidelity of quantum gates, it is usually necessary to process the calibration signals in various phases. In terms of signal level description, the calibration signals can be clock delayed by a delay instruction. By using the delay instruction, noise can be avoided between the calibration signals, and the fidelity of the quantum gates can be affected. For example, if the phase difference between the end point of the first calibration signal and the end point of the second calibration signal is too large, for example, greater than 180 degrees, noise will be generated, and the fidelity of the quantum gates will be affected.

[0068] However, since the number of clock cycles executed by the delay instruction is usually not a multiple of the number of standard clock cycles, the delay instruction needs to be supplemented with a certain number of delay clock cycles to align the delay instruction with the no-operation instruction. As a result, redundant clock consumption will be generated, and the calibration time of the quantum gates will be increased.

[0069] In order to solve the above problems, the embodiment of the present application provides a signal processing method. The target delay clock cycle number of the delay instruction of the modulation signal is obtained, the target delay clock cycle number is divided by the number of standard clock cycles, at least one no-operation instruction is generated according to the division result, and the number of standard clock cycles is taken modulo the target delay clock cycle number. The preset length of the delay clock cycle number that needs to be delayed is determined according to the modulo operation result, and then the modulation signal is delayed by the preset length of the delay clock cycle number to generate the delayed modulation signal. The target delay clock cycle number is avoided, and the delayed modulation signal is a standard clock cycle number that can be directly executed. Accordingly, the demodulation end can perform signal demodulation in advance by the number of standard clock cycles to obtain a signal demodulation result.

[0070] In this way, the delay instruction does not need to be supplemented with a certain number of delay clock cycles (taking the next one) to align, and no redundant clock cycle number will be generated, thereby reducing the calibration time of the quantum gates and improving the calibration efficiency of the quantum gates. For specific implementation process, please continue to refer to the following specific embodiments.

[0071] Please refer to FIG. 3, which is a scene schematic diagram of a signal processing system provided by the embodiment of the present application. It includes a terminal 140, an Internet 130, a gateway 120, a server 110 formed by a quantum computer, etc.

[0072] The terminal 140 includes but is not limited to a mobile phone, a computer, a smart voice interactive device, a smart home appliance, a vehicle-mounted terminal, an aircraft, etc. In addition, it can be a single device or a collection of multiple devices. The terminal 140 can communicate with the Internet 130 in a wired or wireless manner to exchange data.

[0073] The server 110 refers to a computer system capable of providing certain services to the terminal 140, and can be a quantum computer. Compared with the ordinary terminal 140, the server 110 has higher requirements in stability, security, performance, and the like. The server 110 can be a high-performance computer in a network platform, a cluster of multiple high-performance computers, a part of a high-performance computer (for example, a virtual machine), a combination of parts of multiple high-performance computers (for example, virtual machines), or the like.

[0074] The gateway 120 is also called an inter-network connector or a protocol converter. The gateway implements network interconnection at the transport layer and is a computer system or device that acts as a conversion role. The gateway is a translator between two systems using different communication protocols, data formats or languages, or even completely different architectures. Meanwhile, the gateway can also provide filtering and security functions. Messages sent by the terminal 140 to the server 110 are sent to the corresponding server 110 through the gateway 120. Messages sent by the server 110 to the terminal 140 are also sent to the corresponding terminal 140 through the gateway 120.

[0075] The signal processing method of the embodiment of the present application can be implemented in the server 110.

[0076] It should be noted that the scenario diagram of the signal processing system shown in FIG. 1 is only an example, and the signal processing system and scenario described in the embodiment of the present application are used to more clearly illustrate the technical solutions of the embodiment of the present application, and do not constitute a limitation on the technical solutions provided by the embodiment of the present application. Those skilled in the art can know that, with the evolution of signal processing and the appearance of new business scenarios, the technical solutions provided by the embodiment of the present application are also applicable to similar technical problems.

[0077] In the embodiment, the signal processing method device will be described from the perspective of the signal processing method device, which can be integrated in a computer with a storage unit and a microprocessor installed and having computing power. The computer can be a quantum computer.

[0078] Referring to FIG. 4, FIG. 4 is a first flowchart of the signal processing method provided by the embodiment of the present application. The signal processing method comprises the following steps:

[0079] In step 201, a delay instruction of a modulated signal is obtained, and a target delay clock cycle number corresponding to the delay instruction is determined.

[0080] It should be noted that, with the continuous development of science and technology, human beings have higher and higher requirements for information processing and transmission, and quantum computing, as a new and efficient computing method, is increasingly attracting attention. In quantum computing, quantum modulation and demodulation technology is an indispensable key part. Quantum modulation technology refers to encoding the original signal to generate a modulated signal to be transmitted to a quantum bit. Quantum demodulation technology refers to demodulating the modulated signal to restore the original signal, so that the modulated signal can be processed and analyzed by a quantum chip.

[0081] In the calibration process of the superconducting quantum bit, the commonly used method at present is based on IQ mixing technology. The bit measurement frequency (measurement bit stream) is mapped on the IQ coordinate according to certain rules by the IQ mixing technology to generate a digital signal sequence (restored original signal), wherein each sequence contains an IQ value, and the IQ value is composed of two complex components: I (in-phase component) and Q (quadrature component). The two components are actually orthogonal to each other. Therefore, the envelope and phase of the signal can be described by the digital signal sequence, each sequence contains a corresponding phase, and the digital signal sequence is converted into an analog signal by a digital-to-analog converter (DAC) and modulated to generate a modulated signal output to the controller of the quantum bit. The modulated signal is a signal used to control the state transition of the quantum bit, usually a microwave pulse. These signals interact with other physical parameters through the resonance frequency of the quantum bit, thereby changing the state of the quantum bit and realizing quantum logic operation. The parameters of the modulated signal, such as frequency, amplitude, shape and duration, will affect the performance of the quantum gate.

[0082] In order to better illustrate the embodiments of the present application, please refer to the first timing diagram of the signal processing system provided by the embodiments of the present application shown in FIG. 5. As shown in FIG. 5, the digital signal sequence has 40 sampling points, which includes sampling points 0 to 39, each sampling point corresponds to a different phase, and 40 sampling points will generate 40 accumulated phases.

[0083] It can be understood that, since the quantum gate calibration essentially controls the state of the quantum bit by applying a radio frequency modulation signal to the quantum bit to realize gate operation, a large amount of signals will be generated during the calibration process. Due to the calibration of multiple quantum bits and the length transformation of the quantum circuit, the signals of different parts cannot be implemented synchronously, which affects the stable operation of quantum computing. In related technologies, in order to obtain higher quantum gate fidelity, various phase micro-processing of the calibration signal is usually required. In terms of signal level description, the calibration signal can be processed by a delay (DELAY) instruction to delay the clock. Through the delay instruction, noise can be avoided between the calibration signals, which affects the fidelity of the quantum gate.

[0084] In some embodiments, before step 201, the following processing is performed: determining the phase difference between the modulation signal and the target modulation signal adjacent to the modulation signal; in response to the phase difference being greater than a preconfigured phase difference, obtaining a preconfigured delay instruction as the delay instruction of the modulation signal, wherein the number of delay clock cycles of the preconfigured delay instruction is the target number of delay clock cycles.

[0085] For example, the preconfigured phase difference and the target number of delay clock cycles are set according to the actual application scenario, for example: the preconfigured phase difference is 180 degrees; the delay instruction is an instruction for generating a plurality of delay clock cycles for the modulation signal, and the phase corresponding to each delay clock cycle is 0 relative to the reference point, so that the adjacent modulation signals are spaced apart to avoid the influence of noise on the calibration of the quantum gate.

[0086] For example, the phase difference between the phase of the end point of the former calibration signal and the phase of the end point of the latter calibration signal is too large, for example, greater than 180 degrees, which will cause noise and affect the fidelity of the quantum gate. Please continue to refer to FIG. 5, a delay instruction with a number of delay clock cycles of 35 clock cycles can be generated for the digital signal sequence of 40 sampling points in the figure, and then a planned signal is obtained. In the planned signal, the first 35 sampling points are all delayed and filled with a phase number of 0, which means that the phase of the wave is zero relative to the reference point and no noise is generated. In this way, the phase between the former signal and the latter signal is spaced apart to avoid the influence of noise on the calibration of the quantum gate. On the last 5 sampling points (sampling points 35 to 39), the corresponding digital signal sequence can be converted into modulation signals 12345.

[0087] In the embodiments of the present application, in order to realize subsequent clock cycle number supplement, the modulation signal (calibration signal in the above) needs to be obtained in advance. The delay instruction corresponding to the modulation signal 12345 in the figure can be obtained, and the target number of delay clock cycles (dt) corresponding to the delay instruction is determined to obtain 35 clock cycles.

[0088] In the embodiments of the present application, the delay with a phase of 0 can provide a stable reference point for the calibration of the quantum gate, so that the calibration process is more accurate. By comparing the phases of the quantum bits before and after the quantum gate operation, the performance of the quantum gate can be evaluated, and the parameters thereof can be adjusted accordingly. By adding a delay with a phase of 0 between operations, the phase drift caused by the interaction between the quantum bits and the environment can be reduced, and the fidelity of the atomic calibration can be improved.

[0089] In step 202, the standard number of clock cycles is divided by the target number of delay clock cycles, and at least one no-operation instruction is generated according to the division result.

[0090] For example, a standard clock cycle refers to a fixed time interval of a clock signal, that is, the length of time from a clock edge (rising edge or falling edge) to the next same edge. The standard clock cycle number is the number of standard clock cycles required to execute a no-operation instruction, and one no-operation instruction corresponds to one standard clock cycle number.

[0091] Please continue to refer to FIG. 5. Due to the calibration of the multi-qubit and the length transformation of the quantum circuit, the signals in different parts cannot be synchronized to take effect, which affects the stable operation of quantum computing. Therefore, a no-operation instruction is needed, which corresponds to one standard clock cycle number, that is, a standardized instruction period, for example, 20 clock cycles. In order to better illustrate the embodiments of the present application, the standard clock cycle number is taken as 20 clock cycles, which can be 10 nanoseconds (ns) in real time unit.

[0092] In the related art, the target delay clock cycle number (35 clock cycles) can be floored to obtain one standard clock cycle number as the trigger time of the analog wave trigger, which can be 20 clock cycles as the analog wave trigger time. Since the 35 clock cycles are not multiples of the standard clock cycle number 20, in order to align the two, a certain number of delay clock cycles need to be added to the delay instruction to align it. The delay instruction can be supplemented with 5 clock cycles (by the next method, floored), so that the 35 clock cycles are updated to 40 clock cycles, which can be aligned with the standard clock cycle number, so that the effective modulation signal 12345 is aligned to the integer multiple of 10 ns and is actually sent to the modulation signal 12345 at 40 clock cycles. This will produce 5 extra clock cycles, causing the modulation signal 12345 to be significantly delayed, and the data acquisition side will start receiving the waveform and demodulation after a certain delay of the cable and the above-mentioned time of taking the next method, which is also delayed by 5 clock cycles. This actually introduces an average delay of 10 clock cycles in the calibration process of each quantum gate, causing unnecessary clock consumption, increasing the number of clock cycles for signal processing, and reducing the efficiency of quantum gate calibration.

[0093] To solve the above technical problems, the present application can first divide the standard clock cycle number by the target delay cycle number, determine a preset number of no-operation instructions according to the division result, and take out the clock cycle number that is an integer multiple of the standard clock cycle number from the target delay cycle number through the preset number of no-operation instructions. Unlike the related art, which supplements a certain number of delay cycles to the target delay cycle number, the clock cycle number corresponding to the preset number of no-operation instructions can be the time of the analog wave trigger and the time of the data acquisition trigger.

[0094] In some embodiments, the dividing the number of standard clock cycles by the number of target delay clock cycles and generating at least one no-operation instruction according to the division result can include:

[0095] (1) dividing the number of standard clock cycles by the number of target delay clock cycles to obtain a division result;

[0096] (2) determining a preset number according to the division number indicated by the division result;

[0097] (3) generating the preset number of no-operation instructions.

[0098] Please refer to FIG. 6 for details. When the number of target delay clock cycles is 35, the number of standard clock cycles can be divided by 35 to obtain a division result. The division number of the division result is 1. According to the division number 1 indicated by the division result, the preset number is also 1.

[0099] In some embodiments, one no-operation instruction, for example, qwait1, is generated, and the number of clock cycles 20 corresponding to the no-operation instruction is used as the time of analog wave triggering and the time of data collection triggering. Based on the one no-operation instruction, the number of clock cycles 20 that is an integer multiple of the number of standard clock cycles can be obtained from the number of target delay clock cycles 35.

[0100] In the embodiments, the operations in the quantum computer are usually controlled by clock signals, and each quantum gate operation can require multiple clock cycles to complete. The down rounding by the division operation can ensure that the number of clock cycles is an integer multiple of the required period of the quantum gate operation, thereby reducing unnecessary clock waiting time. The down rounding by the division operation reduces unnecessary clock consumption and improves the efficiency of quantum gate calibration.

[0101] In step 203, the number of standard clock cycles is divided by the number of target delay clock cycles based on the number of target delay clock cycles, and the number of delay clock cycles of a preset length is determined according to the division result.

[0102] The modulo operation refers to the remainder of the division of two numbers. Since the preset number of no-operation instructions will miss part of the clock cycles of the target delay clock cycle number, resulting in the invalidation of part of the delay clock cycles of the delay instruction, the embodiment of the present application can perform a modulo operation on the standard clock cycle number based on the target delay clock cycle number, and determine the delay clock cycle number of the preset length according to the modulo operation result. Unlike the padding method of taking the next one of the target delay clock cycle number of the no-operation instruction in related technologies, the embodiment of the present application can pad the missed part of the clock cycle of the target delay clock cycle number by the delay clock cycle number of the preset length, without the need for additional clock cycles, unnecessary clock consumption, increased clock cycle number of signal processing, and reduced efficiency of quantum gate calibration.

[0103] In some embodiments, the modulo operation on the standard clock cycle number based on the target delay clock cycle number, and the determination of the delay clock cycle number of the preset length according to the modulo operation result can include:

[0104] (1) performing a modulo operation on the standard clock cycle number based on the target delay clock cycle number to obtain a modulo operation result;

[0105] (2) determining a corresponding preset length according to the remainder indicated by the modulo operation result;

[0106] (3) generating the delay clock cycle number of the preset length.

[0107] As shown in FIG. 6, when the target delay cycle number is 35, a modulo operation can be performed on the standard clock cycle number based on the target delay cycle number 35 to obtain a modulo operation result, and the remainder of the modulo operation result is 15. According to the remainder 15 indicated by the modulo operation result, a corresponding preset length of 15 is determined.

[0108] In some embodiments, the delay clock cycle number of the preset length of 15 is generated, and the modulation signal can be delayed by the delay cycle number of the preset length of 15 for subsequent delay padding to pad the missed part of the clock cycle of the target delay clock cycle number.

[0109] Unlike related technologies that need to pad the delay instruction by 5 clock cycles to take the next one, so that the target delay cycle number 35 is updated to 40 clock cycles, which can be aligned with the standard clock cycle number, compared with the scheme of aligning the effective modulation signal 12345 to the integer multiple of 10 ns to be sent at the moment, the present application does not need to pad the clock cycle, can save unnecessary clock consumption, reduce the clock cycle number of signal processing, and improve the efficiency of quantum gate calibration.

[0110] In step 204, after the at least one no-operation instruction, the modulation signal is delayed and supplemented according to a preset number of delay clock periods, to generate a delayed and supplemented modulation signal.

[0111] In order to make up for the missing part of the target number of delay clock periods, after the preset number of no-operation instructions, the modulation signal can be delayed and supplemented according to a preset number of delay clock periods, to generate a delayed and supplemented modulation signal, the number of clock periods of the delayed and supplemented modulation signal being the same as the number of standard clock periods. In this way, the delayed and supplemented standard clock is a directly executable standard clock period, and the number of clock periods corresponding to the preset number of no-operation instructions, plus the number of delay clock periods of the preset length, is exactly the target number of delay clock periods. This achieves the target number of delay clock periods of the delay instruction without the need for clock period supplementation, and still enables the modulation signal to be sent to the data acquisition side, reducing the number of clock periods of signal processing and improving the efficiency of quantum gate calibration.

[0112] In some embodiments, the modulation signal is delayed and supplemented according to a preset number of delay clock periods to generate a delayed and supplemented modulation signal, including:

[0113] (1) determining the front signal slot position of the modulation signal;

[0114] (2) before the front signal slot position of the modulation signal, the modulation signal is delayed and supplemented according to a preset number of delay clock periods to generate a delayed and supplemented modulation signal.

[0115] In an example, in the processing of the modulation signal, a buffer or a queue is used to store the modulation signal in order to introduce a delay in the processing. The position of the modulation signal in the queue is the signal slot position, and the front signal slot position of the modulation signal refers to the signal slot position adjacent to and before the signal slot position of the modulation signal. The rear signal slot position is also referred to below, and the rear signal slot position of the modulation signal refers to the signal slot position adjacent to and after the signal slot position of the modulation signal.

[0116] In order to better illustrate the embodiments of the present application, please refer to FIG. 6. The pre-signal slot position of the modulation signal 12345 can be determined. In this way, after at least one no-operation instruction, for example, after the no-operation instruction qwait1, the modulation signal 12345 is delayed and supplemented before the pre-signal slot of the modulation signal according to the number of delay clock cycles of the preset length of 15, to generate the delayed and supplemented modulation signal. The number of clock cycles of the delayed and supplemented modulation signal is 20, which is the same as the standard clock cycle number 20. In this way, the delayed and supplemented standard clock is the directly executable standard clock cycle number, and the clock cycle number 20 corresponding to the no-operation instruction qwait1 plus the number of delay clock cycles of the preset length 15 is exactly the target delay clock cycle number 35. The modulation signal is sent to the data acquisition side, the number of clock cycles of signal processing is reduced, and the efficiency of quantum gate calibration is improved without the need for clock cycle supplementation of the delay instruction.

[0117] In step 205, the delayed and supplemented modulation signal is signal demodulated by a number of standard clock cycles to obtain a signal demodulation result.

[0118] The delayed and supplemented modulation signal can be output to the controller of the quantum bit for demodulation. Correspondingly, the controller of the quantum bit can demodulate the delayed and supplemented modulation signal to obtain a digital signal sequence, and perform calculation based on the digital signal sequence to convert into a signal demodulation result. The signal demodulation result is the actual calculation result, and the proximity between the actual calculation result and the expected result is determined to determine the corresponding quantum gate fidelity, to implement one-time quantum gate fidelity testing, and to determine whether to continue to calibrate the quantum gate according to the quantum gate fidelity.

[0119] For example, the quantum gate fidelity is an index for measuring the accuracy of quantum gate operation in quantum computing. The quantum gate fidelity describes the proximity between the actually executed quantum gate operation and the ideal quantum gate operation.

[0120] In some embodiments, the signal demodulation is implemented by the controller of the quantum bit, and the signal demodulation result is characterized as an actual probability distribution. After step 205, the following processing is further performed: determining an expected probability distribution corresponding to the quantum gate operation of the controller of the quantum bit; and performing trace operation based on the actual probability distribution and the expected probability distribution to obtain a fidelity corresponding to the quantum gate operation.

[0121] For example, the trace operation refers to the sum of the diagonal elements of an n-order matrix A. The fidelity corresponding to the quantum gate operation can be gate fidelity, and the trace operation of the actual probability distribution and the expected probability distribution can be characterized as the following formula (1):

[0122] where F g is the gate fidelity, and Tr is the trace operation. A quantum gate operation is used to represent a quantum process. The gate fidelity is used to describe the difference between an ideal gate and an actual gate. The expected gate is u, corresponding to the expected probability distribution u(p), and the actual gate is e, corresponding to the actual probability distribution e(p). The fidelity can be determined by the final state under the same initial state.

[0123] In some embodiments, the fidelity corresponding to the quantum gate operation can also be the process fidelity, which is represented by the following formula (2): F p (e, u) = Tr(eu) / Tr(e) Tr(u) (2)

[0124] where F p is the process fidelity, which is based on the gate fidelity F g and the Hilbert space dimension d = N 2 The process fidelity can be converted by the formula F g = (1 + dF p ) / (1 + d). The Hilbert space is a complete inner product space, which is a special kind of vector space with the following properties: for any sequence of vectors in the space, if the sequence converges to a vector according to the norm defined by the inner product, then the limit vector also belongs to the space. The dimension of the Hilbert space refers to the number of basis vectors in the space. In quantum mechanics, a quantum state can be regarded as a vector in a Hilbert space, and the dimension of the Hilbert space of a quantum system is usually infinite because it can contain an infinite number of quantum states. Actual physical systems often have a finite number of degrees of freedom, so their corresponding Hilbert space dimensions, although infinite, are usually countably infinite, meaning they can be represented by a countable basis set.

[0125] In the related art, since the delay instruction is aligned with a certain number of delay clock cycles, the target delay clock cycle number of the delay instruction is taken in the next standard clock cycle, so the receiving side will receive the delay supplemented modulation signal and demodulate it in the next standard clock cycle, resulting in a delay of one standard clock cycle in the execution time of the delay supplemented modulation signal. Therefore, compared with the related art, the receiving side can demodulate the delay supplemented modulation signal one standard clock cycle earlier, reduce the number of clock cycles for signal processing, and improve the efficiency of quantum gate calibration. Signal modulation and demodulation no longer need to align the delay instruction, and each quantum gate calibration saves an average of 10 clock cycles, and the cross-quantum bit does not appear to be misaligned, and the precision is improved.

[0126] In some embodiments, the signal demodulation of the delay-supplemented modulated signal by the number of standard clock cycles in advance obtains a signal demodulation result, including:

[0127] (1) When it is detected that the target delay clock cycle number is not an integer multiple of the number of standard clock cycles, the signal demodulation of the delay-supplemented modulated signal by the number of standard clock cycles in advance obtains a signal demodulation result.

[0128] (2) When it is detected that the target delay clock cycle number is an integer multiple of the number of standard clock cycles, the signal demodulation of the delay-supplemented modulated signal obtains a signal demodulation result.

[0129] It should be noted that when the target delay clock cycle number of the delay instruction is an integer multiple of the number of standard clock cycles, the number of standard clock cycles is directly divided by the target delay clock cycle number according to the integer division operation, and the delay instruction can be directly converted into a corresponding number of no-operation instructions. At this time, the delay-supplemented modulated signal does not need to be supplemented with delay, and the signal demodulation of the delay-supplemented demodulated signal directly obtains a signal demodulation result.

[0130] Correspondingly, when it is detected that the target delay clock cycle number is not an integer multiple of the number of standard clock cycles, it is indicated that the delay-supplemented modulated signal will be received and demodulated at the next number of standard clock cycles by default on the receiving side, resulting in a delay of one number of standard clock cycles in the execution time of the delay-supplemented modulated signal. Therefore, the signal demodulation of the delay-supplemented modulated signal by one number of standard clock cycles in advance obtains a signal demodulation result, reduces the number of clock cycles of signal processing, and improves the efficiency of quantum gate calibration.

[0131] In some embodiments, the signal demodulation of the delay-supplemented modulated signal by the number of standard clock cycles in advance obtains a signal demodulation result, including:

[0132] (1.1) The delay-supplemented modulated signal is demodulated by the number of standard clock cycles in advance to obtain a demodulated original signal;

[0133] (1.2) The front signal slot position of the original signal is determined;

[0134] (1.3) The original signal is supplemented with delay according to the number of delay clock cycles of the preset length before the front signal slot position of the original signal, to generate a delay-supplemented original signal. The number of clock cycles of the delay-supplemented original signal is the same as the number of standard clock cycles;

[0135] (1.4) The delay-supplemented original signal is calculated to obtain a signal demodulation result.

[0136] Please continue to refer to FIG. 5, in the related art, due to the fetch-one method of the delay instruction, 5 clock cycles are supplemented, making it 40 clock cycles, and accordingly, the receiving side in the original will start receiving the waveform after the fetch-one method and start demodulation, and the receiving side corresponding to the embodiment of the application does not supplement the delay for the modulated signal, therefore, it is necessary to demodulate the modulated signal after the delay on the basis of the modulated signal opportunity received in the related art, one standard clock in advance.

[0137] For example, the principle of modulation in the embodiment of the application is IQ modulation, and the principle of demodulation processing is IQ demodulation, and the demodulation processing can be realized by the following method: the received signal is mixed with the locally generated quadrature carrier. Through two orthogonal mixers, I component and Q component are recovered respectively. Through a filter, frequency components and noise not required in the application process are removed to obtain filtered I component and Q component, and the filtered I component and Q component pass through a low-pass filter respectively to recover the original information signal (signal demodulation result).

[0138] Please continue to refer to FIG. 6, in the clock cycle of the original fetch-one method, the waveform is directly received and the demodulation processing is started at the same time, and since the sampling point with a phase of 0 is empty after demodulation, therefore, the original signal after demodulation will only retain the digital signal sequence 35-39, but the calculation of the digital signal sequence 35-39 also needs to meet the limitation of one standard clock cycle number 20, therefore, the pre-signal slot position of the original signal can be determined, and similar to the delay supplement of the modulated signal, the original signal can be delayed and supplemented according to the delay clock cycle number of the preset length 15 before the pre-signal slot position of the original signal, to generate the original signal after the delay supplement, since the clock cycle number of the original signal after the delay supplement is the same as the standard clock cycle number 20, therefore, the original signal after the delay supplement can be directly calculated to obtain the signal demodulation result.

[0139] In some embodiments, step 204, the modulated signal is delayed and supplemented according to the delay clock cycle number of the preset length to generate the modulated signal after the delay supplement, comprising:

[0140] (2.1) determining the pre-signal slot position and the post-signal slot position of the modulated signal;

[0141] (2.2) dividing the delay clock cycle number of the preset length into a first delay clock cycle number of a first sub-preset length and a second delay clock cycle number of a second sub-preset length;

[0142] (2.3) delaying and supplementing the modulated signal according to the first delay clock cycle number of the first sub-preset length before the pre-signal slot position of the modulated signal to obtain an intermediate modulated signal;

[0143] (2.4) after the post-signal-slot position of the modulated signal, delaying the intermediate modulated signal according to the number of delay clock cycles of the second sub preset length, to generate a delayed and supplemented modulated signal.

[0144] For better illustration of the embodiments of the present application, please refer to FIG. 7, the pre-signal-slot position and the post-signal-slot position of the modulated signal 12345 can be determined, and in this way, the number of delay clock cycles of the preset length can be divided into the number of delay clock cycles of the first sub preset length and the number of delay clock cycles of the second sub preset length, for example, the first sub preset length is 10, and the second sub preset length is 5.

[0145] Based on this, after at least one no-operation instruction, for example, after the no-operation instruction qwait1, before the pre-signal-slot of the modulated signal, the modulated signal 12345 is delayed and supplemented according to the number of delay clock cycles of the first sub preset length of 10, to generate an intermediate modulated signal, and then after the post-signal-slot position of the modulated signal, the intermediate modulated signal is delayed and supplemented according to the number of delay clock cycles of the second sub preset length of 5, to obtain a delayed and supplemented modulated signal, the number of clock cycles of the delayed and supplemented modulated signal is 20, which is the same as the standard clock cycle number 20, in this way, the delayed and supplemented standard clock is the directly executable standard clock cycle number, and the clock cycle number 20 corresponding to the no-operation instruction qwait1, plus the number of delay clock cycles of the preset length 15, is exactly the target delay clock cycle number 35, which realizes that the target delay clock cycle number of the delay instruction can be achieved without clock cycle supplement of the delay instruction, reduces the clock cycle number of signal processing, improves the efficiency of quantum gate calibration, and because the corresponding second sub preset length of delay clock cycle number is also supplemented at the post-signal-slot position of the modulated signal, the current calibration signal can avoid noise between the next calibration signal through the second sub preset length of delay clock cycle number, which can further improve the efficiency of quantum gate calibration.

[0146] In some embodiments, the number of delay clock cycles of the preset length can be divided into the number of delay clock cycles of the first sub preset length and the number of delay clock cycles of the second sub preset length, which can include:

[0147] (3.1) obtaining a first weight value and a second weight value, the first weight value being greater than the second weight value;

[0148] (3.2) dividing the number of delay clock cycles of the first sub preset length according to the number of delay clock cycles of the preset length and the first weight value;

[0149] (3.3) according to the number of delay clock cycles of the preset length and the second weight value, divide the number of delay clock cycles of the second sub preset length.

[0150] The first weight value and the second weight value are weights set according to user requirements. It should be noted that the sum of the first weight value and the second weight value is 1. In order to ensure the noise of the previous calibration signal, it is necessary to ensure that the first weight value is greater than the second weight value. For example, the first weight value can be two-thirds, and the second weight value can be one-third.

[0151] Please continue to refer to FIG. 7. According to the number of delay clock cycles of the preset length 15 and the first weight value two-thirds, the number of delay clock cycles of the first sub preset length 10 is divided. Correspondingly, according to the number of delay clock cycles of the preset length 15 and the second weight value one-third, the number of delay clock cycles of the second sub preset length 5 is divided.

[0152] Correspondingly, the modulation signal after the delay supplement is demodulated by the standard clock cycle number in advance, and a signal demodulation result is obtained, including:

[0153] (4.1) The modulation signal after the delay supplement is demodulated by the standard clock cycle number in advance, and a demodulated original signal is obtained.

[0154] (4.2) Determine the front signal slot position and the rear signal slot position of the original signal.

[0155] (4.3) Before the front signal slot position of the original signal, the original signal is delayed and supplemented according to the number of delay clock cycles of the first sub preset length, and an intermediate original signal is obtained.

[0156] (4.4) After the rear signal slot position of the original signal, the intermediate original signal is delayed and supplemented according to the number of delay clock cycles of the second sub preset length, and a delayed and supplemented original signal is generated. The clock cycle number of the delayed and supplemented original signal is the same as the standard clock cycle number.

[0157] (4.5) The delayed and supplemented original signal is calculated to obtain a signal demodulation result.

[0158] Please continue to refer to FIG. 5. In the related art, because the delay instruction is taken in the advance method, 5 clock cycles are supplemented, so that it is 40 clock cycles. Correspondingly, it will make the original receiving side start receiving the waveform and start demodulation after the advance method. Corresponding to the receiving side of the present application, because the modulation signal is not delayed and supplemented, therefore, it is necessary to demodulate the modulation signal after the delay supplement based on the timing of the modulation signal after the delay supplement in the related art. Advance a standard clock.

[0159] Please continue to refer to FIG. 7, the original method of taking in the clock cycle directly start receiving waveform and start demodulation processing, because the sampling point demodulation after phase 0 is empty, therefore, the original signal after demodulation will only keep digital signal sequence 35-39, but also need to meet the calculation of digital signal sequence 35-39 for a standard clock cycle number 20 limit, therefore, can determine the original signal before signal slot position and after signal slot position, similar to the delay of the modulated signal, before the original signal before signal slot, according to the first sub preset length of 10 delay clock cycle number of original signal delay, generate intermediate original signal, then after the original signal after signal slot position, according to the second sub preset length of 5 delay clock cycle number, the intermediate original signal delay, get the delay of the original signal after delay, because the clock cycle number of the original signal after delay is 20 and the standard clock cycle number 20 is the same, therefore, can directly calculate the original signal after delay, get signal demodulation result.

[0160] In some embodiments, step 204, delay the modulated signal according to the preset length of the delay clock cycle number, generate the modulated signal after delay, including:

[0161] (5.1) determine the modulated signal after signal slot position;

[0162] (5.2) after the modulated signal after signal slot position, delay the modulated signal according to the preset length of the delay clock cycle number, generate the modulated signal after delay.

[0163] In order to better illustrate the embodiments of the present application, please refer to Figure 8, the post signal slot position of the modulation signal 12345 can be determined, and then the modulation signal 12345 is delayed and supplemented after the post signal slot of the modulation signal, according to the number of delay clock cycles of the preset length 15, to generate the delayed and supplemented modulation signal, the number of clock cycles of the delayed and supplemented modulation signal is 20, which is the same as the standard clock cycle number 20, so that the delayed and supplemented modulation signal is a standard clock cycle number that can be directly executed, and the clock cycle number 20 corresponding to the empty operation instruction qwait1 plus the number of delay clock cycles of the preset length 15 is exactly the target delay clock cycle number 35, which realizes the target delay clock cycle number of the delay instruction without clock cycle supplement, still can realize the target delay clock cycle number of the delay instruction, reduces the number of clock cycles of signal processing, improves the efficiency of quantum gate calibration, and because the number of delay clock cycles of the preset length is also supplemented at the post signal slot position of the modulation signal, the current calibration signal can avoid noise with the next calibration signal through the number of delay clock cycles of the preset length, which can further improve the efficiency of quantum gate calibration.

[0164] It should be noted that, in order to ensure that the current calibration signal and the previous calibration signal can avoid noise, the above steps can only be performed when the preset number of empty operation instructions is not 0, because when the preset number of empty operation instructions is not 0, a delay interval can be ensured between the current calibration signal and the previous calibration signal, otherwise, there is no delay interval between the two, which will cause noise and affect the fidelity of the quantum gate.

[0165] Correspondingly, the delay-supplemented modulation signal is demodulated by the standard clock cycle number to obtain a signal demodulation result, including:

[0166] (6.1) The delay-supplemented modulation signal is demodulated by the standard clock cycle number to obtain a demodulated original signal;

[0167] (6.2) The post signal slot position of the original signal is determined;

[0168] (6.3) The original signal is delayed and supplemented after the post signal slot position of the original signal, according to the number of delay clock cycles of the preset length, to generate a delayed and supplemented original signal, the number of clock cycles of the delayed and supplemented original signal is the same as the standard clock cycle number;

[0169] (6.4) The delayed and supplemented original signal is calculated to obtain a signal demodulation result.

[0170] Please continue to refer to FIG. 5, in the related art, because of the fetch-one method of the delay instruction, 5 clock cycles are supplemented, so that it is 40 clock cycles, and correspondingly, it will make the receiving side in the original start to receive the waveform after the fetch-one method and start demodulation, and the receiving side corresponding to the embodiment of the application does not supplement the delay to the modulated signal, therefore, it is necessary to demodulate the modulated signal after the delay on the basis of the modulated signal opportunity received by the related art after the delay supplement, one standard clock in advance.

[0171] Please continue to refer to FIG. 8, in the clock cycle of the original fetch-one method, the waveform is directly received and the demodulation processing is started, because the sampling point with a phase of 0 is empty after demodulation, therefore, the original signal after demodulation will only retain the digital signal sequence 35-39, but the calculation of the digital signal sequence 35-39 also needs to meet the limit of one standard clock cycle number 20, therefore, it can be determined that the post-signal slot position of the original signal, similar to the delay supplement of the modulated signal, the original signal can be delayed and supplemented after the post-signal slot position of the original signal according to the delay clock cycle number of the preset length 15, to generate the original signal after the delay supplement, because the clock cycle number of the original signal after the delay supplement is the same as the standard clock cycle number 20, therefore, the original signal after the delay supplement can be directly calculated to obtain the signal demodulation result.

[0172] From the above, the embodiment of the application obtains the delay instruction of the modulated signal, and determines the target delay clock cycle number corresponding to the delay instruction; the standard clock cycle number is divided by the target delay clock cycle number, and at least one no-operation instruction is generated according to the division result; the standard clock cycle number is taken modulo the target delay clock cycle number, and the delay clock cycle number of the preset length is determined according to the modulo result; the modulated signal is delayed and supplemented according to the delay clock cycle number of the preset length after the at least one no-operation instruction, to generate the modulated signal after the delay supplement, the clock cycle number of the modulated signal after the delay supplement is the same as the standard clock cycle number; the modulated signal after the delay supplement is demodulated in advance by the standard clock cycle number, to obtain the signal demodulation result.

[0173] In the embodiment of the present application, the target delay clock cycle number is obtained, the standard clock cycle number is divided by the target delay clock cycle number, at least one no-operation instruction is generated according to the division result, and the standard clock cycle number is taken modulo the target delay clock cycle number, the preset length of the delay clock cycle number that needs to be supplemented is determined according to the modulo operation result, and then the modulation signal is supplemented according to the preset length of the delay clock cycle number, to generate the modulation signal after delay supplement, so as to avoid the omission of the target delay clock cycle number, and the modulation signal after delay supplement is the standard clock cycle number that can be directly executed, accordingly, the demodulation end can perform signal demodulation in advance by the standard clock cycle number to obtain the signal demodulation result. Compared with the related art scheme of supplementing a certain delay clock cycle number to the delay instruction for alignment, the present application can also achieve signal alignment without supplementing a certain delay clock cycle to the delay instruction, thereby reducing the clock cycle number of signal processing and further reducing the calibration time of the quantum gate and improving the calibration efficiency of the quantum gate.

[0174] The method described in the above embodiments will be further described in detail by way of example.

[0175] In this embodiment, the signal processing method and device will be specifically integrated in a computer, which can be a quantum computer.

[0176] In order to better illustrate the embodiments of the present application, please refer to FIG. 9, which is a second flowchart of the signal processing method provided by the embodiments of the present application. It includes:

[0177] In step 301, the delay instruction of the modulation signal is obtained, and the target delay clock cycle number corresponding to the delay instruction is determined.

[0178] Please continue to refer to FIG. 6, the delay instruction of the digital signal sequence of 40 sampling points can be generated with a delay clock cycle number of 35 clock cycles, and then the planned signal is obtained. In the planned signal, the first 35 sampling points are delayed and filled with a phase number of 0 to be spaced apart from the phase of the previous signal to avoid noise affecting the calibration of the quantum gate. In the last 5 sampling points, that is, the sampling points from 35 to 39, the corresponding digital signal sequence can be converted into the modulation signal 12345.

[0179] In the embodiments of the present application, in order to realize subsequent clock cycle number supplement, the modulation signal needs to be obtained in advance. The delay instruction corresponding to the modulation signal 12345 in the figure can be obtained, and the target delay clock cycle number (dt) corresponding to the delay instruction is determined, such as 35 clock cycles.

[0180] In step 302, the target delay clock period number is divided by the standard clock period number to obtain a division result, a preset number corresponding to the division number indicated by the division result is determined, and at least one no-operation instruction is generated.

[0181] Please continue to refer to FIG. 6, when the target delay period number is 35, the target delay period number 35 can be divided by the standard clock period number 20 to obtain a division result, the division number of the division result is 1, and the preset number corresponding to the division number 1 indicated by the division result is also 1.

[0182] In some embodiments, 1 no-operation instruction is generated, for example: qwait1, and the clock period number 20 corresponding to the 1 no-operation instruction is used as the time of the analog wave trigger and the time of the data acquisition trigger. Based on the 1 no-operation instruction, the clock period number 20 that is an integer multiple of the standard clock period number can be taken from the target delay period number 35.

[0183] In step 303, the target delay clock period number is taken modulo the standard clock period number to obtain a modulo result, a preset length corresponding to the remainder indicated by the modulo result is determined, and a delay clock period number of the preset length is generated.

[0184] Please continue to refer to FIG. 6, when the target delay period number is 35, the target delay period number 35 can be taken modulo the standard clock period number to obtain a modulo result, the remainder of the modulo result is 15, and the preset length corresponding to the remainder 15 indicated by the modulo result is 15.

[0185] In some embodiments, a delay clock period number of a preset length of 15 is generated, and the missing part of the clock period number of the target delay clock period number can be supplemented by the delay period number of the preset length of 15 to the modulated signal in the future.

[0186] Compared with the prior art that needs to supplement 5 clock periods to the delay instruction, when the target delay period number 35 is updated to 40 clock periods, it can be aligned with the standard clock period number, and compared with the scheme of aligning the effective modulated signal 12345 to the integer multiple of 10ns to send at the moment, the present application does not need to supplement the clock period, can save unnecessary clock consumption, reduce the clock period number of signal processing, and improve the efficiency of quantum gate calibration.

[0187] In step 304, the front signal slot position of the modulated signal is determined after the at least one no-operation instruction, the modulated signal is delayed and supplemented according to the delay clock period number of the preset length before the front signal slot position of the modulated signal, and a modulated signal after delay and supplementation is generated.

[0188] Please continue to refer to FIG. 6, the pre-signal slot position of the modulation signal 12345 can be determined, and the modulation signal 12345 is delayed and supplemented according to the preset length of 15 delay clock cycles before the pre-signal slot of the modulation signal after at least one no-operation instruction, for example, the no-operation instruction qwaitl, and the delay-supplemented modulation signal has the same clock cycle number 20 as the standard clock cycle number 20. In this way, the delay-supplemented standard clock is a directly executable standard clock cycle number, and the clock cycle number 20 corresponding to the no-operation instruction qwaitl plus the preset length of the delay clock cycle number 15 is exactly the target delay clock cycle number 35. The modulation signal is sent to the data acquisition side to reduce the clock cycle number of signal processing and improve the efficiency of quantum gate calibration without clock cycle supplement of the delay instruction.

[0189] In step 305, when it is detected that the target delay clock cycle number is not an integer multiple of the standard clock cycle number, the delay-supplemented modulation signal is demodulated in advance by the standard clock cycle number to obtain a demodulated original signal, and the pre-signal slot position of the original signal is determined.

[0190] Correspondingly, when it is detected that the target delay clock cycle number is not an integer multiple of the standard clock cycle number, it is indicated that the delay-supplemented modulation signal will be received and demodulated at the next standard clock cycle number by default at the receiving side, resulting in a delay of one standard clock cycle number in the execution time of the delay-supplemented modulation signal. Therefore, the delay-supplemented modulation signal needs to be demodulated in advance by one standard clock cycle number. Please continue to refer to FIG. 6, the waveform is directly received and the demodulation processing is started on the clock cycle of the original take-in method. Since the sampling point with a phase of 0 is empty after demodulation, the demodulated original signal only retains the digital signal sequence 35-39. However, the calculation of the digital signal sequence 35-39 also needs to meet the limitation of one standard clock cycle number 20. Therefore, the pre-signal slot position of the original signal can be determined.

[0191] In step 306, the original signal is delayed and supplemented according to the preset length of the delay clock cycle number before the pre-signal slot position of the original signal to generate a delay-supplemented original signal, and the delay-supplemented original signal is calculated to obtain a signal demodulation result.

[0192] Please continue to refer to FIG. 6, similarly to the delay supplement of the modulated signal, the original signal can be delayed and supplemented according to the number of delay clock cycles of the preset length 15 before the front signal slot position of the original signal, to generate the original signal after delay supplement. Since the number of clock cycles of the original signal after delay supplement is the same as the standard clock cycle number 20, the original signal after delay supplement can be directly calculated to obtain the signal demodulation result.

[0193] In step 307, when it is detected that the target delay clock cycle number is an integer multiple of the standard clock cycle number, the modulated signal after delay supplement is subjected to signal demodulation to obtain the signal demodulation result.

[0194] When the target delay clock cycle number of the delay instruction is an integer multiple of the standard clock cycle number, the standard clock cycle number can be directly divided by the target delay clock cycle number to convert the delay instruction into a corresponding number of no-operation instructions. At this time, the modulated signal does not need to be subjected to delay supplement, and the demodulated signal after delay supplement can be directly subjected to signal demodulation to obtain the signal demodulation result.

[0195] The specific implementation of each of the above steps can be referred to the foregoing embodiments, which will not be described herein again.

[0196] To better implement the signal processing method provided by the embodiments of the present application, the embodiments of the present application further provide a device based on the above signal processing method. The meanings of the terms are the same as those in the above signal processing method, and the specific implementation details can be referred to the description in the method embodiments.

[0197] Please refer to FIG. 10, which is a structural schematic diagram of the signal processing method device provided by the embodiments of the present application. The signal processing method device is applied to a computer, which can be a quantum computer. The signal processing method device can include an acquisition unit 401, an integer division unit 402, a modulo unit 403, a delay supplement unit 404, and a signal demodulation unit 405, etc.

[0198] The acquisition unit 401 is configured to acquire a delay instruction of a modulated signal, and determine a target delay clock cycle number corresponding to the delay instruction.

[0199] The integer division unit 402 is configured to perform an integer division operation on a standard clock cycle number according to the target delay clock cycle number, and generate at least one no-operation instruction according to the integer division operation result.

[0200] In some embodiments, the integer division unit 402 is configured to:

[0201] perform an integer division operation on the standard clock cycle number by the target delay clock cycle number to obtain an integer division operation result;

[0202] determine a preset length according to the remainder indicated by the modulo operation result;

[0203] generate the preset length of delay clock cycles.

[0204] The modulo unit 403 is configured to perform modulo operation on the standard clock cycle number based on the target delay clock cycle number, and determine the preset length of delay clock cycles according to a modulo operation result.

[0205] In some embodiments, the modulo unit 403 is configured to:

[0206] perform modulo operation on the standard clock cycle number based on the target delay clock cycle number to obtain a modulo operation result;

[0207] determine a preset length according to the remainder indicated by the modulo operation result;

[0208] generate the preset length of delay clock cycles.

[0209] The delay supplement unit 404 is configured to perform delay supplement on the modulation signal according to the preset length of delay clock cycles after the preset number of NOP instructions, to generate a delay-supplemented modulation signal, and the delay-supplemented modulation signal has the same number of clock cycles as the standard clock cycle number.

[0210] In some embodiments, the delay supplement unit 404 is configured to:

[0211] determine a front signal slot position of the modulation signal after the preset number of NOP instructions;

[0212] perform delay supplement on the modulation signal according to the preset length of delay clock cycles before the front signal slot position of the modulation signal, to generate a delay-supplemented modulation signal.

[0213] In some embodiments, the delay supplement unit 404 includes:

[0214] A determination subunit (not identified) is configured to determine a front signal slot position and a rear signal slot position of the modulation signal;

[0215] A division subunit (not identified) is configured to divide the preset length of delay clock cycles into a first sub-preset length of delay clock cycles and a second sub-preset length of delay clock cycles;

[0216] A first delay supplement subunit (not identified) is configured to perform delay supplement on the modulation signal according to the first sub-preset length of delay clock cycles before the front signal slot position of the modulation signal, to obtain an intermediate modulation signal;

[0217] The second delay supplement subunit (not labeled) is configured to delay and supplement the intermediate modulation signal according to a number of delay clock periods of the second sub preset length after a post-signal slot position of the modulation signal, to generate a delay-supplemented modulation signal.

[0218] In some embodiments, the division subunit (not labeled) is configured to:

[0219] obtain a first weight value and a second weight value, the first weight value being greater than the second weight value;

[0220] divide the number of delay clock periods of the preset length into a first number of delay clock periods of a first sub preset length according to the first weight value;

[0221] divide the number of delay clock periods of the preset length into a second number of delay clock periods of a second sub preset length according to the second weight value.

[0222] In some embodiments, the delay supplement unit 405 is further configured to:

[0223] determine a post-signal slot position of the modulation signal;

[0224] delay and supplement the modulation signal according to a number of delay clock periods of a preset length after the post-signal slot position, to generate a delay-supplemented modulation signal.

[0225] The signal demodulation unit 405 is configured to perform signal demodulation on the delay-supplemented modulation signal in advance by a standard clock period, to obtain a signal demodulation result.

[0226] In some embodiments, the signal demodulation unit 405 is configured to:

[0227] perform signal demodulation on the delay-supplemented modulation signal in advance by the standard clock period when it is detected that the target number of delay clock periods is not an integer multiple of the standard clock period, to obtain a signal demodulation result.

[0228] In some embodiments, the signal demodulation unit 405 is further configured to:

[0229] perform demodulation processing on the delay-supplemented modulation signal in advance by the standard clock period, to obtain a demodulated original signal;

[0230] determine a pre-signal slot position of the original signal;

[0231] delay and supplement the original signal according to a number of delay clock periods of a preset length before the pre-signal slot position, to generate a delay-supplemented original signal, the number of clock periods of the delay-supplemented original signal being the same as the standard clock period;

[0232] The original signal after the delay supplement is calculated to obtain a signal demodulation result.

[0233] In some embodiments, the signal demodulation unit 405 is further configured to:

[0234] The modulated signal after the delay supplement is demodulated by the standard clock cycle number in advance to obtain a demodulated original signal;

[0235] The front signal slot position and the rear signal slot position of the original signal are determined;

[0236] The original signal is supplemented by the delay clock cycle number of the first sub-preset length before the front signal slot position of the original signal to obtain an intermediate original signal;

[0237] The intermediate original signal is supplemented by the delay clock cycle number of the second sub-preset length after the rear signal slot position of the original signal to generate an original signal after the delay supplement, and the clock cycle number of the original signal after the delay supplement is the same as the standard clock cycle number;

[0238] The original signal after the delay supplement is calculated to obtain a signal demodulation result.

[0239] In some embodiments, the signal demodulation unit 405 is further configured to:

[0240] The modulated signal after the delay supplement is demodulated by the standard clock cycle number in advance to obtain a demodulated original signal;

[0241] The rear signal slot position of the original signal is determined;

[0242] The original signal is supplemented by the delay clock cycle number of the preset length after the rear signal slot position of the original signal to generate an original signal after the delay supplement, and the clock cycle number of the original signal after the delay supplement is the same as the standard clock cycle number;

[0243] The original signal after the delay supplement is calculated to obtain a signal demodulation result.

[0244] In some embodiments, the obtaining unit 401 is configured to, before obtaining the delay instruction of the modulated signal, determine a phase difference between the modulated signal and a target modulated signal adjacent to the modulated signal;

[0245] In response to the phase difference being greater than a preconfigured phase difference, a preconfigured delay instruction is obtained as the delay instruction of the modulated signal, wherein the delay clock cycle number of the preconfigured delay instruction is a target delay clock cycle number.

[0246] In some embodiments, the signal demodulation is implemented by the controller of the qubit, and a result of the signal demodulation is characterized as an actual probability distribution; the signal demodulation unit 405 is further configured to perform signal demodulation on the modulation signal after the delay compensation by a number of standard clock cycles in advance, to obtain a signal demodulation result, and determine an expected probability distribution corresponding to the quantum gate operation of the controller of the qubit.

[0247] The trace operation is performed based on the actual probability distribution and the expected probability distribution, to obtain the fidelity corresponding to the quantum gate operation.

[0248] The specific implementation of each unit can be referred to the foregoing embodiments, which will not be described herein.

[0249] As can be seen from the foregoing, the delay instruction of the modulation signal is acquired by the acquisition unit 401, and the target delay clock cycle number corresponding to the delay instruction is determined; the standard clock cycle number is divided by the target delay clock cycle number by the integer division unit 402, and at least one no-operation instruction is generated based on the result of the integer division operation; the standard clock cycle number is taken modulo the target delay clock cycle number by the modulo unit 403, and the delay clock cycle number of the preset length is determined based on the result of the modulo operation; the delay compensation unit 404 performs delay compensation on the modulation signal based on the delay clock cycle number of the preset length after the at least one no-operation instruction, to generate the modulation signal after the delay compensation, and the clock cycle number of the modulation signal after the delay compensation is the same as the standard clock cycle number; the signal demodulation unit 405 performs signal demodulation on the modulation signal after the delay compensation by the standard clock cycle number in advance, to obtain a signal demodulation result.

[0250] In this way, the standard clock cycle number is divided by the target delay clock cycle number, at least one no-operation instruction is generated based on the result of the integer division operation, and since the preset number of no-operation instructions will omit part of the clock cycle number of the target delay clock cycle number, the standard clock cycle number is taken modulo the target delay clock cycle number, the delay clock cycle number of the preset length that needs to be compensated is determined based on the result of the modulo operation, and then the modulation signal is compensated based on the delay clock cycle number of the preset length, to generate the modulation signal after the delay compensation, so as to avoid omission of the target delay clock cycle number, and the modulation signal after the delay compensation is a standard clock cycle number that can be directly executed. Accordingly, the demodulation end can perform signal demodulation by the standard clock cycle number in advance, to obtain a signal demodulation result. Compared with the scheme in the related art that needs to align the delay instruction by compensating a certain delay clock cycle, the present application can achieve signal alignment without compensating the delay instruction by a certain delay clock cycle, reduces the clock cycle number of signal processing, and further reduces the calibration time of the quantum gate and improves the calibration efficiency of the quantum gate.

[0251] The specific implementation of each unit can refer to the foregoing embodiments, which will not be described here.

[0252] Referring to FIG. 11, FIG. 11 is a structural block diagram of part of a terminal 140 implementing an embodiment of the present application, which includes a radio frequency (RF) circuit 510, a memory 515, an input unit 530, a display unit 540, a sensor 550, an audio circuit 560, a wireless fidelity (WiFi) module 570, a processor 580, and a power supply 590, and the like. Those skilled in the art can understand that the structure of the terminal 140 shown in FIG. 11 does not constitute a limitation on the mobile phone or computer, and can include more or fewer components than those shown, or combine certain components, or different component arrangements.

[0253] The RF circuit 510 can be used for receiving and sending signals in the process of receiving or calling, especially receiving the downlink information of the base station and processing it by the processor 580, and sending the uplink data to the base station.

[0254] The memory 515 can be used to store software programs and modules, and the processor 580 can execute various function applications and data processing of the terminal by running the software programs and modules stored in the memory 515.

[0255] The input unit 530 can be used to receive input digital or character information, and generate key signal input related to the setting and function control of the terminal. For example, the input unit 530 can include a touch panel 531 and other input devices 532.

[0256] The display unit 540 can be used to display input information or provided information and various menus of the terminal. The display unit 540 can include a display panel 541.

[0257] The audio circuit 560, the speaker 561, and the microphone 562 can provide an audio interface.

[0258] The terminal 140 of the embodiments of the present application includes but is not limited to a mobile phone, a computer, a smart voice interactive device, a smart home appliance, a vehicle-mounted terminal, an aircraft, and the like. The embodiments of the present application can be applied to various scenarios, including but not limited to cloud technology, artificial intelligence, intelligent transportation, and assisted driving.

[0259] FIG. 12 is a block diagram of a structure of a part of the server 110 implementing the embodiments of the present application. The server 110 can vary greatly in configuration or performance and can include one or more central processing units (CPUs) 622 (e.g., one or more processors) and a memory 632, one or more storage media 630 (e.g., one or more mass storage devices) storing applications 642 or data 644. The memory 632 and the storage media 630 can be volatile or non-volatile storage. The programs stored in the storage media 630 can include one or more modules (not shown in the figure), each of which can include a series of instructions for operating on the server 600. For example, the central processing unit 622 can be configured to communicate with the storage media 630 and execute the series of instructions stored in the storage media 630 on the server 600.

[0260] The server 600 can also include one or more power supplies 626, one or more wired or wireless network interfaces 650, one or more input / output interfaces 658, and / or one or more operating systems 641, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0261] The central processing unit 622 in the server 600 can be configured to execute the signal processing method of the embodiments of the present application, for example:

[0262] obtaining a delay instruction of a modulated signal and determining a target number of delay clock cycles corresponding to the delay instruction;

[0263] performing an integer division operation on a standard number of clock cycles according to the target number of delay clock cycles, and generating at least one no-operation instruction according to a result of the integer division operation;

[0264] performing a modulo operation on the standard number of clock cycles based on the target number of delay clock cycles, and determining a number of delay clock cycles of a preset length according to a result of the modulo operation;

[0265] delaying the modulated signal by the number of delay clock cycles of the preset length after the preset number of no-operation instructions, to generate a delayed modulated signal, the delayed modulated signal having the same number of clock cycles as the standard number of clock cycles;

[0266] performing signal demodulation on the delayed modulated signal in advance of the standard number of clock cycles to obtain a signal demodulation result.

[0267] The embodiment of the present application further provides a computer readable storage medium, which is used for storing program codes, and the program codes are used for executing the signal processing method of each of the foregoing embodiments.

[0268] The embodiment of the present application further provides a computer program product, which comprises a computer program. A processor of a computer device reads the computer program and executes, so that the computer device executes the signal processing method.

[0269] The delay instruction of the modulated signal is acquired, and the target delay clock cycle number corresponding to the delay instruction is determined;

[0270] The standard clock cycle number is divided by the target delay clock cycle number, and at least one no-operation instruction is generated according to the division result;

[0271] The standard clock cycle number is taken modulo the target delay clock cycle number, and the delay clock cycle number of the preset length is determined according to the modulo result;

[0272] After the preset number of no-operation instructions, the modulated signal is delayed and supplemented according to the delay clock cycle number of the preset length, and a delayed and supplemented modulated signal is generated, and the clock cycle number of the delayed and supplemented modulated signal is the same as the standard clock cycle number;

[0273] The delayed and supplemented modulated signal is signal demodulated in advance by the standard clock cycle number, and a signal demodulation result is obtained.

[0274] In addition, the terms "comprise" and "include" and any variations thereof are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or device that includes a list of steps or units is not necessarily limited to those clearly listed steps or units, but can include other steps or units that are not clearly listed or inherent to such processes, methods, products or devices.

[0275] It should be understood that in the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, "A and / or B" can mean that there are three cases of only A, only B, and A and B at the same time, wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b or c can mean a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, and c can be single or multiple.

[0276] It should be understood that in the description of the embodiments of the present application, the meaning of multiple (or multiple items) is two or more, greater than, less than, more than, etc. is not included in the number, and above, below, etc. is included in the number.

[0277] In several embodiments provided by the embodiments of the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division, and actual implementation can have another division manner. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0278] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, which can be located in one place, or can be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0279] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0280] If the integrated unit is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application essentially or say the part that makes a contribution to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0281] It should also be understood that the various embodiments provided by the present application can be combined in any manner to achieve different technical effects.

[0282] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works together with other related parts to achieve a predetermined target, and can be implemented entirely or partially by using software, hardware (such as a processing circuit or a memory) or a combination thereof. Similarly, one processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be a part of an overall module or unit that includes the functions of the module or unit.

[0283] The above is a specific description of the embodiments of the present application, but the embodiments of the present application are not limited to the above-described embodiments. Those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the embodiments of the present application, and these equivalent modifications or replacements are all included in the scope defined by the embodiments of the present application.

Claims

1. A signal processing method, the method being performed by a computer device, the method comprising: obtaining a delay instruction of a modulated signal, and determining a target delay clock cycle number corresponding to the delay instruction; performing an integer division operation on a standard clock cycle number according to the target delay clock cycle number, and generating at least one no-operation instruction according to an integer division operation result; performing a modulo operation on the standard clock cycle number based on the target delay clock cycle number, and determining a preset length of delay clock cycle numbers according to a modulo operation result; delaying the modulated signal by the preset length of delay clock cycle numbers after the at least one no-operation instruction, to generate a delayed modulated signal, a clock cycle number of the delayed modulated signal being the same as the standard clock cycle number; performing signal demodulation on the delayed modulated signal by the standard clock cycle number in advance, to obtain a signal demodulation result.

2. The signal processing method of claim 1, wherein, The delaying the modulated signal by the preset length of delay clock cycle numbers to generate the delayed modulated signal comprises: determining a front signal slot position of the modulated signal; delaying the modulated signal by the preset length of delay clock cycle numbers before the front signal slot position of the modulated signal, to generate the delayed modulated signal.

3. The signal processing method of claim 2, wherein, The performing signal demodulation on the delayed modulated signal by the standard clock cycle number in advance to obtain the signal demodulation result comprises: when it is detected that the target delay clock cycle number is not an integer multiple of the standard clock cycle number, performing signal demodulation on the delayed modulated signal by the standard clock cycle number in advance, to obtain the signal demodulation result.

4. The signal processing method according to claim 2 or 3, wherein The performing signal demodulation on the delayed modulated signal by the standard clock cycle number in advance to obtain the signal demodulation result comprises: performing demodulation processing on the delayed modulated signal by the standard clock cycle number in advance, to obtain a demodulated original signal; determining a front signal slot position of the original signal; delaying the original signal by the preset length of delay clock cycle numbers before the front signal slot position of the original signal, to generate a delayed original signal, a clock cycle number of the delayed original signal being the same as the standard clock cycle number; performing calculation on the delayed original signal, to obtain the signal demodulation result.

5. The signal processing method of claim 1, wherein, The delaying the modulated signal by the preset length of delay clock cycle numbers to generate the delayed modulated signal comprises: determining a front signal slot position and a rear signal slot position of the modulated signal; dividing the preset length of delay clock cycle numbers into a first sub preset length of delay clock cycle numbers and a second sub preset length of delay clock cycle numbers; delaying the modulated signal by the first sub preset length of delay clock cycle numbers before the front signal slot position of the modulated signal, to obtain an intermediate modulated signal; delaying the intermediate modulated signal by the second sub preset length of delay clock cycle numbers before the rear signal slot position of the modulated signal, to obtain the delayed modulated signal. After a post-signal-slot position of the modulation signal, the intermediate modulation signal is delayed and supplemented according to the second sub-pre-set length of delay clock cycle numbers, to generate a delayed and supplemented modulation signal.

6. The signal processing method of claim 5, wherein, The pre-set length of delay clock cycle numbers is divided into a first sub-pre-set length of delay clock cycle numbers and a second sub-pre-set length of delay clock cycle numbers, including: A first weight value and a second weight value are obtained, the first weight value being greater than the second weight value; The pre-set length of delay clock cycle numbers is divided into a first sub-pre-set length of delay clock cycle numbers according to the first weight value; The pre-set length of delay clock cycle numbers is divided into a second sub-pre-set length of delay clock cycle numbers according to the second weight value.

7. The signal processing method according to claim 5 or 6, wherein The delayed and supplemented modulation signal is signal-demodulated by the standard clock cycle number in advance, to obtain a signal-demodulation result, including: The delayed and supplemented modulation signal is demodulated by the standard clock cycle number in advance, to obtain a demodulated original signal; A pre-signal-slot position and a post-signal-slot position of the original signal are determined; The original signal is delayed and supplemented before the pre-signal-slot position according to the first sub-pre-set length of delay clock cycle numbers, to obtain an intermediate original signal; The intermediate original signal is delayed and supplemented after the post-signal-slot position according to the second sub-pre-set length of delay clock cycle numbers, to generate a delayed and supplemented original signal, the clock cycle number of the delayed and supplemented original signal being the same as the standard clock cycle number; The delayed and supplemented original signal is calculated, to obtain a signal-demodulation result.

8. The signal processing method of claim 1, wherein, The modulation signal is delayed and supplemented according to the pre-set length of delay clock cycle numbers, to generate a delayed and supplemented modulation signal, including: A post-signal-slot position of the modulation signal is determined; The modulation signal is delayed and supplemented after the post-signal-slot position according to the pre-set length of delay clock cycle numbers, to generate a delayed and supplemented modulation signal.

9. The signal processing method of claim 8, wherein, The delayed and supplemented modulation signal is signal-demodulated by the standard clock cycle number in advance, to obtain a signal-demodulation result, including: The delayed and supplemented modulation signal is demodulated by the standard clock cycle number in advance, to obtain a demodulated original signal; A post-signal-slot position of the original signal is determined; The original signal is delayed and supplemented after the post-signal-slot position according to the pre-set length of delay clock cycle numbers, to generate a delayed and supplemented original signal, the clock cycle number of the delayed and supplemented original signal being the same as the standard clock cycle number; The delayed and supplemented original signal is calculated, to obtain a signal-demodulation result.

10. The signal processing method according to any one of claims 1 to 9, wherein, The target delay clock cycle number is divided by the standard clock cycle number, to obtain a division result, and a plurality of no-operation instructions are generated according to the division result, including: The target delay clock cycle number is divided by the standard clock cycle number, to obtain a division result; A pre-set number corresponding to the division result is determined according to a division number indicated by the division result; generate the preset number of no-operation instructions.

11. The signal processing method according to any one of claims 1 to 10, wherein, The modulo operation of the target delay clock cycle number on the standard clock cycle number is performed, and a preset length of delay clock cycle numbers is determined according to a modulo operation result. The modulo operation of the target delay clock cycle number on the standard clock cycle number is performed, and a preset length of delay clock cycle numbers is determined according to a modulo operation result. The modulo operation of the target delay clock cycle number on the standard clock cycle number is performed, and a preset length of delay clock cycle numbers is determined according to a modulo operation result. The modulo operation of the target delay clock cycle number on the standard clock cycle number is performed, and a preset length of delay clock cycle numbers is determined according to a modulo operation result.

12. The signal processing method according to claim 3 or 4, wherein The method further comprises: When it is detected that the target delay clock cycle number is an integer multiple of the standard clock cycle number, the modulated signal after the delay supplement is signal demodulated to obtain a signal demodulation result.

13. The signal processing method according to any one of claims 1 to 12, wherein, Before the delay instruction of the modulated signal is acquired, the method further comprises: A phase difference between the modulated signal and a target modulated signal adjacent to the modulated signal is determined; In response to the phase difference being greater than a preconfigured phase difference, a preconfigured delay instruction is acquired as the delay instruction of the modulated signal, where a delay clock cycle number of the preconfigured delay instruction is the target delay clock cycle number.

14. The signal processing method according to any one of claims 1 to 13, wherein, The signal demodulation is implemented by a controller of a quantum bit, and the signal demodulation result is represented as an actual probability distribution; After the modulated signal after the delay supplement is signal demodulated in advance by the standard clock cycle number to obtain a signal demodulation result, the method further comprises: An expected probability distribution corresponding to a quantum gate operation of the controller of the quantum bit is determined; Trace operation is performed based on the actual probability distribution and the expected probability distribution to obtain a fidelity corresponding to the quantum gate operation.

15. A signal processing method device, the device comprising: An acquisition unit configured to acquire a delay instruction of a modulated signal and determine a target delay clock cycle number corresponding to the delay instruction; An integer division unit configured to perform integer division operation on a standard clock cycle number according to the target delay clock cycle number, and generate at least one no-operation instruction according to an integer division operation result; A modulo unit configured to perform modulo operation of the target delay clock cycle number on the standard clock cycle number, and determine a preset length of delay clock cycle numbers according to a modulo operation result; A delay supplement unit configured to supplement the modulated signal with a delay according to the preset length of delay clock cycle numbers after the at least one no-operation instruction, to generate a modulated signal after the delay supplement, where a clock cycle number of the modulated signal after the delay supplement is the same as the standard clock cycle number; A signal demodulation unit configured to signal demodulate the modulated signal after the delay supplement in advance by the standard clock cycle number to obtain a signal demodulation result.

16. A computer readable storage medium storing a plurality of instructions, the instructions being adapted to be loaded by a processor to execute the signal processing method of any one of claims 1 to 14.

17. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the signal processing method according to any one of claims 1 to 14 when executing the computer program.

18. A computer program product comprising a computer program or instructions, wherein the computer program or instructions implement the signal processing method according to any one of claims 1 to 14 when executed by a processor.

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