Power device and manufacturing method, power module, power conversion circuit, and vehicle

Abstract

A power device and a manufacturing method, a power module, a power conversion circuit, and a vehicle. The power device comprises: a semiconductor structure comprising a substrate (10) and an epitaxial layer (20); a first doping type region (40) located on the surface of the epitaxial layer (20) distant from the substrate (10); a first through hole (61) passing through an insulating layer (60) and exposing part of the first doping type region (40); an ohmic contact layer (70) located inside the first through hole (61); a channel layer (80) comprising first sub-regions (81), a second sub-region (82) and third sub-regions (83), wherein the orthographic projection of the second sub-region (82) on the substrate (10) coincides with the orthographic projection of the ohmic contact layer (70) on the substrate (10), and each first sub-region (81) is located on the side of the corresponding third sub-region (83) distant from the second sub-region (82); and a gate oxide layer (90) covering the first sub-regions (81) of the channel layer (80) while exposing the first sub-regions (81) at both side edges of the channel layer (80), wherein the orthographic projections of the third sub-regions (83) on the substrate (10) coincide with the orthographic projection of a gate (100) on the substrate (10).

Description

Power device and manufacturing method, power module, power conversion circuit, and vehicle

[0001] This application claims priority to the Chinese patent application No. 202410858957.3, filed on June 28, 2024, to the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, for example, to a power device and manufacturing method, a power module, a power conversion circuit, and a vehicle. BACKGROUND

[0003] In a conventional power device, the epitaxial layer and the channel region of a planar structure silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) are both silicon carbide. Since the interface state density of the silicon carbide material is relatively high, the channel mobility thereof is often lower than 30 cm2 / V·s. The conventional planar structure SiC MOSFET forms a channel on the 4H-SiC (000-1) surface, but the interface defect density of the (000-1) surface is high, which reduces the channel mobility of the silicon carbide. The SiC MOSFET of a trench structure forms a channel on the 4H-SiC (11-20) surface, and the interface defect density of the (11-20) surface is relatively low, which improves the channel mobility of the silicon carbide to a certain extent. However, the trench angle and the right angle (or obtuse angle) structure at the bottom of the SiC MOSFET of the trench structure intensify the electric field, which is easily reversed and broken down. SUMMARY

[0004] The present application provides a power device and manufacturing method, a power module, a power conversion circuit, and a vehicle, which can improve the channel mobility without changing the original reverse breakdown characteristic.

[0005] According to an aspect of the present application, a power device is provided, comprising:

[0006] a semiconductor structure, wherein the semiconductor structure comprises a substrate and an epitaxial layer, the substrate is of a first doping type; the epitaxial layer is located on one side of the substrate, and the epitaxial layer and the substrate are of the same doping type; a first doping type region is located on a surface of the epitaxial layer away from the substrate;

[0007] an insulating layer, the insulating layer is located on a side of the epitaxial layer away from the substrate, and the insulating layer is provided with a first through hole, the first through hole penetrates through the insulating layer, and part of the first doping type region is exposed;

[0008] an ohmic contact layer, the ohmic contact layer is located inside the first through hole;

[0009] A channel layer is located on a side of the ohmic contact layer away from the substrate, and covers the ohmic contact layer and the insulating layer; the channel layer comprises a first sub-region, a second sub-region, and a third sub-region, and the second sub-region is coincident with the projection of the ohmic contact layer on the substrate; the first sub-region is located on a side of the third sub-region away from the second sub-region; the first sub-region and the second sub-region are of a first doping type;

[0010] A gate oxide layer is located on a side of the channel layer away from the substrate, and covers the second sub-region, the third sub-region, and part of the first sub-region;

[0011] A gate electrode is located on a side of the gate oxide layer away from the substrate, and covers part of the gate oxide layer, and the third sub-region is coincident with the projection of the gate electrode on the substrate.

[0012] According to another aspect of the present application, a power module is provided, comprising a substrate and the power device of any of the embodiments of the present application, and the substrate is used for carrying the power device.

[0013] According to another aspect of the present application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction.

[0014] The power conversion circuit comprises a circuit board and the power device of any of the embodiments of the present application, and the power device is electrically connected to the circuit board.

[0015] According to another aspect of the present application, a vehicle is provided, comprising a load and the power conversion circuit of any of the embodiments of the present application, and the power conversion circuit is used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current, or converting direct current into alternating current, and then inputting to the load.

[0016] According to another aspect of the present application, a preparation method of a power device is provided, comprising:

[0017] A semiconductor structure is prepared, wherein the semiconductor structure comprises a substrate and an epitaxial layer, the substrate is of a first doping type; the epitaxial layer is located on a side of the substrate, and the epitaxial layer has the same doping type as the substrate;

[0018] A first doping type region is formed on a surface of the epitaxial layer away from the substrate; an insulating layer is formed on a side of the epitaxial layer away from the substrate; the insulating layer is provided with a first through hole, the first through hole penetrates through the insulating layer, and exposes part of the first doping type region;

[0019] An ohmic contact layer is formed in the first through hole;

[0020] A channel sub-layer is formed on a side of the ohmic contact layer away from the substrate; the channel sub-layer covers the ohmic contact layer and the insulating layer;

[0021] forming a gate oxide sub-layer on a side of the channel sub-layer away from the substrate; the gate oxide sub-layer covers the channel sub-layer;

[0022] forming a gate on a side of the gate oxide sub-layer away from the substrate; the gate covers part of the gate oxide sub-layer;

[0023] performing ion implantation of a first doping type on the channel sub-layer by taking the gate as a mask to form a first sub-region and a second sub-region, so as to form a channel layer; a normal projection of the second sub-region on the substrate and a normal projection of the ohmic contact layer on the substrate coincide; the channel layer comprises the first sub-region, the second sub-region and a third sub-region; a normal projection of the third sub-region on the substrate and a normal projection of the gate on the substrate coincide; the first sub-region is located on a side of the third sub-region away from the second sub-region; the first sub-region and the second sub-region are of the first doping type;

[0024] etching the gate oxide sub-layer to form a gate oxide layer; the gate oxide layer covers the second sub-region, the third sub-region and part of the first sub-region. BRIEF DESCRIPTION OF DRAWINGS

[0025] FIG. 1 is a structural schematic diagram of a power device provided by an embodiment of the present application.

[0026] FIG. 2 is a structural schematic diagram of another power device provided by an embodiment of the present application.

[0027] FIG. 3 is a flowchart of a preparation method of a power device provided by an embodiment of the present application.

[0028] FIG. 4 is an intermediate structural schematic diagram of a power device provided by an embodiment of the present application.

[0029] FIG. 5 is an intermediate structural schematic diagram of another power device provided by an embodiment of the present application.

[0030] FIG. 6 is an intermediate structural schematic diagram of another power device provided by an embodiment of the present application.

[0031] FIG. 7 is an intermediate structural schematic diagram of another power device provided by an embodiment of the present application.

[0032] FIG. 8 is an intermediate structural schematic diagram of another power device provided by an embodiment of the present application.

[0033] FIG. 9 is a flowchart of a preparation method of another power device provided by an embodiment of the present application.

[0034] FIG. 10 is an intermediate structural schematic diagram of another power device provided by an embodiment of the present application.

[0035] FIG. 11 is an intermediate structural schematic diagram of another power device provided by an embodiment of the present application.

[0036] FIG. 12 is a flowchart of a preparation method of another power device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. The described embodiments are part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present application.

[0038] The terms "first", "second", and the like in the present application are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units can include other steps or units not clearly listed or inherent to the process, method, product, or device.

[0039] The embodiments of the present application provide a power device, and FIG. 1 is a structural schematic diagram of a power device provided by the embodiments of the present application. Referring to FIG. 1, the power device comprises a semiconductor structure, wherein the semiconductor structure comprises a substrate 10 and an epitaxial layer 20, the substrate 10 is of a first doping type; the epitaxial layer 20 is located on one side of the substrate 10, and the epitaxial layer 20 is of the same doping type as the substrate 10; a first doping type region 40 is located on a surface of the epitaxial layer 20 away from the substrate 10.

[0040] An insulating layer 60 is located on a side of the epitaxial layer 20 away from the substrate 10, the insulating layer 60 is provided with a first through hole 61, the first through hole 61 penetrates through the insulating layer 60, and part of the first doping type region 40 is exposed; an ohmic contact layer 70 is located inside the first through hole 61; a channel layer 80 is located on a side of the ohmic contact layer 70 away from the substrate 10, and the channel layer 80 covers the ohmic contact layer 70 and the insulating layer 60; the channel layer 80 comprises a first sub-region 81, a second sub-region 82, and a third sub-region 83, the second sub-region 82 is coincident with a projection of the ohmic contact layer 70 on the substrate 10; the first sub-region 81 is located on a side of the third sub-region 83 away from the second sub-region 82; the first sub-region 81 and the second sub-region 82 are of the first doping type.

[0041] A gate oxide layer 90 is located on the side of the channel layer 80 away from the substrate 10, covering the second sub-region 82, the third sub-region 83 and part of the first sub-region 81; a gate electrode 100 is located on the side of the gate oxide layer 90 away from the substrate 10, covering part of the gate oxide layer 90, and the third sub-region 83 is coincident with the projection of the gate electrode 100 on the substrate 10.

[0042] The power device can be a silicon carbide MOSFET device. If the power device is an N-type device, the first doping type is N-type, and the second doping type is P-type. If the power device is a P-type device, the first doping type is P-type, and the second doping type is N-type. For example, if the power device is an N-type device, the substrate 10 is an N+ substrate, for example, an N+ silicon carbide substrate. The epitaxial layer 20 is an N- epitaxial layer, for example, an N- silicon carbide epitaxial layer. The first doping type region 40 is an N+ region, for example, an N+ silicon carbide layer. The N+ region can be formed by implanting N-type ions into the first doping type region 40. The N-type ions can be phosphorus (P) ions or nitrogen (N) ions. If the power device is a P-type device, the substrate 10 is a P+ substrate, and the epitaxial layer 20 is a P- epitaxial layer.

[0043] The insulating layer 60 can be a silicon dioxide layer. The insulating layer 60 can allow carriers to flow from the channel layer 80 to the first doping type region 40 through the ohmic contact layer 70, avoiding the current directly flowing into the well region 30 and causing current runaway. The material of the ohmic contact layer 70 can be a metal, for example, nickel (Ni), titanium (Ti), titanium nitride (TiN), or molybdenum (Mo). The ohmic contact layer 70 is arranged between the second sub-region 82 and the first doping type region 40 to form a good ohmic contact. The material of the gate electrode 100 can be polysilicon. The polysilicon can be doped with phosphorus (P) ions to make the gate electrode 100 a low-resistance conductor. The material of the channel layer 80 can be polysilicon or indium-gallium-zinc-oxide (IGZO). If polysilicon is used, the entire channel layer 80 can be doped with boron (B) ions to adjust the threshold voltage of the channel layer 80. The first sub-region 81 and the second sub-region 82 can be N+ regions, for example, N+ polysilicon regions. The third sub-region 83 is a polysilicon layer. The first sub-region 81 and the second sub-region 82 are used to increase the conductivity and reduce the on-resistance. The third sub-region 83 is coincident with the projection of the gate electrode 100 on the substrate 10, so that the projection of the gate electrode 100 on the substrate 10 does not overlap with the projection of the ohmic contact layer 70 on the substrate 10. This can reduce the parasitic capacitance, reduce device loss, and improve device performance.

[0044] Optionally, due to the material properties of the polysilicon and indium gallium zinc oxide material, the polysilicon and indium gallium zinc oxide material has high mobility, and the channel layer 80 is in series with the first doped type region 40 and the epitaxial layer 20, both of which are silicon carbide, which has high breakdown characteristics and a large band gap width, so that the device channel mobility can be improved without affecting the reverse breakdown characteristics of the device. The material of the gate oxide layer 90 can be silicon dioxide, and the gate oxide layer formed by silicon thermal oxidation can reduce gate oxide defects.

[0045] The power device provided by the application comprises a semiconductor structure, wherein the semiconductor structure comprises a substrate 10 and an epitaxial layer 20, the substrate 10 is of a first doped type; the epitaxial layer 20 is located on one side of the substrate 10, and the epitaxial layer 20 has the same doped type as the substrate 10; a first doped type region 40 is located on a surface of the epitaxial layer 20 away from the substrate 10; an insulating layer 60 is located on one side of the epitaxial layer 20 away from the substrate 10, and the insulating layer 60 is provided with a first through hole 61, the first through hole 61 penetrates through the insulating layer 60, and part of the first doped type region 40 is exposed; an ohmic contact layer 70 is located inside the first through hole 61; a channel layer 80 is located on one side of the ohmic contact layer 70 away from the substrate 10, and the channel layer 80 covers the ohmic contact layer 70 and the insulating layer 60; the channel layer 80 comprises a first sub-region 81, a second sub-region 82 and a third sub-region 83, the second sub-region 82 is coincident with a projection of the ohmic contact layer 70 on the substrate 10; the first sub-region 81 is located on one side of the third sub-region 83 away from the second sub-region 82; the first sub-region 81 and the second sub-region 82 are of the first doped type; a gate oxide layer 90 is located on one side of the channel layer 80 away from the substrate 10, and the gate oxide layer 90 covers the second sub-region 82, the third sub-region 83 and part of the first sub-region 81; a gate electrode 100 is located on one side of the gate oxide layer 90 away from the substrate 10, and the gate electrode 100 covers part of the gate oxide layer 90, and the third sub-region 83 is coincident with a projection of the gate electrode 100 on the substrate 10. The embodiment of the application can improve the device channel mobility through the channel layer 80; the channel layer 80 is in series with the first doped type region 40 and the epitaxial layer 20, so that the device channel mobility can be improved without affecting the reverse breakdown characteristics of the device.

[0046] Optionally, FIG. 2 is a structure schematic diagram of another power device provided by the embodiment of the application, the channel layer 80 further comprises a fourth sub-region 84, the fourth sub-region 84 is located between the first sub-region 81 and the third sub-region 83, and between the third sub-region 83 and the second sub-region 82; the doping concentration of the fourth sub-region 84 is less than the doping concentration of the first sub-region 81.

[0047] The fourth sub-region 84 can be an N-region, and the fourth sub-region 84 is an N-polysilicon region in an example, to form a light dope drain (LDD) structure.

[0048] Optionally, referring to FIG. 1 and FIG. 2, the power device further includes a second doping type region 50 and a well region 30, the second doping type region 50 is located on the surface of the epitaxial layer 20 away from the substrate 10, the second doping type region 50 is located on the side of the well region 30 away from the first doping type region 40, the well region 30 is located on both sides of the first doping type region 40 and contacts the first doping type region 40, and the well region 30 is of the second doping type, the insulating layer 60 further includes a second through hole 62, the second through hole 62 penetrates the insulating layer 60 and exposes part of the second doping type region 50.

[0049] If the device is an N-type device, the well region 30 can be a P-type well region (PW region), and the PW region can be formed by implanting P-type ions into the well region 30, and the P-type ions can be aluminum (Al) ions or boron (B) ions; the second doping type region 50 can be a P+ region, and the P-type ions doped in the second doping type region 50 can be aluminum (Al) ions or boron (B) ions; the second doping type region 50 is arranged to improve the conductivity of the device, form a good contact region, and improve the performance of the device; the channel layer 80, the ohmic contact layer 70 and the first doping type region 40 form a first conduction path, and the second doping type region 50, the well region 30 and the first doping type region 40 form a second conduction path; the two conduction paths formed can improve the channel mobility of the device while not affecting the reverse breakdown characteristics of the device.

[0050] Optionally, referring to FIG. 1 and FIG. 2, the number of the second doping type region 50 and the well region 30 is two; the region between the two well regions 30 is the first doping type region 40; the channel layer 80 includes two first sub-regions 81, one second sub-region 82 and two third sub-regions 83, and the arrangement order along a first direction is the first sub-region 81, the third sub-region 83, the second sub-region 82, the third sub-region 83 and the first sub-region 81, and the first direction is perpendicular to the substrate 10 and points to the epitaxial layer 20; the gate oxide layer 90 exposes part of the first sub-region 81 on both sides; the gate electrode 100 includes a first gate electrode 101 and a second gate electrode 102, the first gate electrode 101 is in the same position as one of the third sub-regions 83 in the substrate 10, and the second gate electrode 102 is in the same position as another of the third sub-regions 83 in the substrate 10.

[0051] The first gate 101 is in the same projection on the substrate 10 as a third sub-area 83 on the substrate 10, and the second gate 102 is in the same projection on the substrate as another third sub-area 83 on the substrate, so that the parasitic capacitance can be reduced, the device loss can be reduced, the device performance can be improved, the device channel mobility can be improved through the channel layer 80, and the device reverse breakdown characteristic can not be affected while the device channel mobility is improved.

[0052] Optionally, referring to FIG. 1 and FIG. 2, the power device further includes a planarization layer 110, the planarization layer 110 is located on a side of the gate 100 away from the substrate 10, and the planarization layer 110 covers the gate 100 and the gate oxide layer 90 not covered by the gate 100.

[0053] The material of the planarization layer 110 can be silicon dioxide, and the planarization layer 110 can play an insulating and isolating role.

[0054] Optionally, referring to FIG. 1 and FIG. 2, the power device further includes a first electrode 121 and a second electrode 122; the first electrode 121 is located on a side of the substrate 10 away from the epitaxial layer 20, and the first electrode 121 covers the substrate 10; and the second electrode 122 is located on a side of the planarization layer 110 away from the substrate 10, and the second electrode 122 covers the planarization layer 110, the second doped type area 50, and the first sub-area 81 not covered by the planarization layer 110.

[0055] The first electrode 121 can be a drain electrode, and the second electrode 122 can be a source electrode; the material of the first electrode 121 and the second electrode 122 can be titanium, titanium nitride, or aluminum; and the first electrode 121 and the second electrode 122 can be set to have a relatively large thickness to reduce the resistance.

[0056] Optionally, referring to FIG. 1 and FIG. 2, the power device further includes a packaging structure 130, the packaging structure 130 includes a passivation layer 131 and a protective layer 132; the passivation layer 131 is located on a side of the second electrode 122 away from the substrate 10, and the passivation layer 131 is partially overlapped with the planarization layer 110 on the substrate 10; and the protective layer 132 is located on a side of the passivation layer 131 away from the substrate 10, and the protective layer 132 covers the passivation layer 131 and a sidewall on a side away from an edge of the passivation layer 131.

[0057] The area not encapsulated by the encapsulation structure 130 is a lead area of the gate 100, the lead area is used to connect the gate 100 with the outside, the material of the passivation layer 131 includes silicon dioxide (SiO2) and / or silicon nitride (SiN), which can be a laminated structure of silicon dioxide (SiO2) and silicon nitride (SiN), or a single silicon dioxide layer or a single silicon nitride layer; the material of the protective layer 132 can be polyimide (PI); and the encapsulation structure 130 can protect the device.

[0058] The power module provided by the embodiment of the present application has the same beneficial effects as the power device provided by any embodiment of the present application.

[0059] The power module provided by the embodiment of the present application has the same beneficial effects as the power device provided by any embodiment of the present application.

[0060] The power conversion circuit provided by the embodiment of the present application has the same beneficial effects as the power device provided by any embodiment of the present application.

[0061] The power conversion circuit provided by the embodiment of the present application has the same beneficial effects as the power device provided by any embodiment of the present application.

[0062] The vehicle provided by the embodiment of the present application has the same beneficial effects as the power device provided by any embodiment of the present application.

[0063] The vehicle provided by the embodiment of the present application has the same beneficial effects as the power device provided by any embodiment of the present application.

[0064] The preparation method of the power device provided by the embodiment of the present application has the same beneficial effects as the power device provided by any embodiment of the present application.

[0065] S110, a semiconductor structure is prepared, wherein the semiconductor structure includes a substrate and an epitaxial layer, the substrate is of a first doping type; the epitaxial layer is located on one side of the substrate, and the epitaxial layer and the substrate are of the same doping type.

[0066] The power device provided by the embodiment of the present application has the same beneficial effects as the power device provided by any embodiment of the present application.

[0067] S120, forming a first doping type region on a surface of the epitaxial layer away from the substrate.

[0068] In the embodiment, the first doping type region is formed by using a plasma enhanced chemical vapor deposition (PECVD) and a photolithography technology, transferring a pattern of a mask to a mask plate, and sequentially forming the first doping type region.

[0069] S130, forming an insulating layer on a side of the epitaxial layer away from the substrate; the insulating layer is provided with a first through hole penetrating through the insulating layer and exposing a part of the first doping type region.

[0070] In the embodiment, the surface defects of the epitaxial layer 20 are removed by a sacrificial oxidation, and the insulating layer 60 is grown on a surface of the epitaxial layer 20 away from the substrate 10 by a thermal oxidation technology. The insulating layer 60 can be a silicon dioxide layer. The insulating layer 60 is opened by a photolithography to form a first through hole 61.

[0071] S140, forming an ohmic contact layer in the first through hole.

[0072] In the embodiment, the ohmic contact layer 70 is deposited and photolithographed in the first through hole 61 to form a pattern of the ohmic contact layer 70. The ohmic contact layer 70 is generally made of a metal such as nickel (Ni), titanium (Ti), titanium nitride (TiN), or molybdenum (Mo).

[0073] S150, forming a channel sub-layer on a side of the ohmic contact layer away from the substrate; the channel sub-layer covers the ohmic contact layer and the insulating layer.

[0074] In the embodiment, the channel sub-layer 801 is formed on a side of the ohmic contact layer 70 away from the substrate 10. For example, the channel sub-layer 801 is formed by depositing intrinsic polysilicon, and then performing B ion doping on the entire surface to adjust the threshold voltage of the channel sub-layer 801. Then, a pattern of the channel sub-layer 801 is formed by a photolithography.

[0075] S160, forming a gate oxide sub-layer on a side of the channel sub-layer away from the substrate; the gate oxide sub-layer covers the channel sub-layer.

[0076] In the application, FIG. 8 is a schematic diagram of an intermediate structure of another power device, and FIG. 8 shows that the gate oxide sub-layer 91 is formed by high-temperature dry oxygen, so that the gate oxide defects can be reduced.

[0077] S170, forming a gate on the side of the gate oxide sub-layer away from the substrate, and the gate covers part of the gate oxide sub-layer.

[0078] In the application, FIG. 8 is a schematic diagram of an intermediate structure of another power device, and FIG. 8 shows that the gate oxide sub-layer 91 is formed by high-temperature dry oxygen, so that the gate oxide defects can be reduced.

[0079] S180, using the gate as a mask, performing ion implantation of a first doping type on the channel sub-layer to form a first sub-region and a second sub-region, so as to form a channel layer; the second sub-region is in the orthographic projection of the substrate and the orthographic projection of the ohmic contact layer coincide; the channel layer includes the first sub-region, the second sub-region and a third sub-region, and the third sub-region is in the orthographic projection of the substrate and the orthographic projection of the gate coincide; the first sub-region is located on the side of the third sub-region away from the second sub-region; and the first sub-region and the second sub-region are of the first doping type.

[0080] In the application, FIG. 8 is a schematic diagram of an intermediate structure of another power device, and FIG. 8 shows that the gate oxide sub-layer 91 is formed by high-temperature dry oxygen, so that the gate oxide defects can be reduced.

[0081] S190, etching the gate oxide sub-layer to form a gate oxide layer; the gate oxide layer covers the second sub-region, the third sub-region and part of the first sub-region.

[0082] In the application, the gate oxide layer is formed by etching the gate oxide sub-layer through etching and photolithography processes.

[0083] Optionally, FIG. 9 is a flowchart of another method for manufacturing a power device, and FIG. 9 shows that after the ion implantation of the first doping type is performed on the channel sub-layer to form the first sub-region and the second sub-region, so as to form the channel layer, the method further includes:

[0084] S210, forming a first mask on the side of the gate oxide sub-layer away from the substrate.

[0085] In the application, FIG. 8 is a schematic diagram of an intermediate structure of another power device, and FIG. 8 shows that the gate oxide sub-layer 91 is formed by high-temperature dry oxygen, so that the gate oxide defects can be reduced.

[0086] S220, patterning the first mask.

[0087] In the application, FIG. 8 is a schematic diagram of an intermediate structure of another power device, and FIG. 8 shows that the gate oxide sub-layer 91 is formed by high-temperature dry oxygen, so that the gate oxide defects can be reduced.

[0088] S230, performing ion implantation of the first doping type on the channel layer through the patterned first mask plate to form a fourth sub-region; the fourth sub-region is located between the first sub-region and the third sub-region, and between the third sub-region and the second sub-region; the doping concentration of the fourth sub-region is less than the doping concentration of the first sub-region.

[0089] As shown in FIG. 2, the ion of the first doping type can be N-type ion, and the fourth sub-region 84 can be N-region. For example, the fourth sub-region 84 is N-polysilicon region, forming LDD structure. The fourth sub-region 84 can also bear part of voltage, reducing the drain electric field, and improving the reliability and stability of the device.

[0090] S240, removing the first mask plate.

[0091] The first mask plate can be removed by a conventional process.

[0092] Optionally, before etching the gate oxide sub-layer to form the gate oxide layer, the method further comprises: forming a planarization sub-layer on the side of the gate away from the substrate; the planarization sub-layer covers the gate and the gate oxide sub-layer not covered by the gate.

[0093] The planarization sub-layer can be deposited on the basis of FIG. 8 by a deposition process.

[0094] Etching the gate oxide sub-layer to form the gate oxide layer comprises: etching the planarization sub-layer and the gate oxide sub-layer at the same time to form the planarization layer and the gate oxide layer; and exposing the first sub-region on both sides of the channel layer of the gate oxide layer and the planarization layer.

[0095] As shown in FIGS. 10-11, the planarization sub-layer and the gate oxide sub-layer are etched at the same time to form the planarization layer 110 and the gate oxide layer 90. The silicide metal can be deposited through the hole opened to the second electrode, and the ohmic contact is formed by the contact between the first sub-region 81 and the metal annealed by rapid thermal annealing (RTA). The polycide is deposited through the hole opened to the gate 100 connected to the outside, and the gate resistance is reduced. The aluminum metal can be deposited to form the first electrode 121 and the second electrode 122, and the first electrode 121 and the second electrode 122 can be thickened to reduce the resistance. As shown in FIG. 1, the packaging structure 130 can be deposited by PECVD in the subsequent process. Finally, the back surface is thinned, the metal is deposited, the laser is annealed, and the back metal is thickened to improve the performance of the device.

[0096] Optionally, FIG. 12 is a flowchart of another method for manufacturing a power device according to an embodiment of the present application. Referring to FIG. 12, before forming the first doped region in the epitaxial layer away from the substrate, the method comprises:

[0097] S310, forming a second mask plate on the side of the epitaxial layer away from the substrate.

[0098] Referring to FIG. 4, the second mask plate can be formed based on FIG. 4. The material of the second mask plate can be silicon dioxide. The second mask plate covers the epitaxial layer 20.

[0099] S320, patterning the second mask plate.

[0100] The PECVD and photolithography technology are used to transfer the pattern of the photo mask to the second mask plate. The second mask plate on the second doped region is removed.

[0101] S330, performing ion implantation of the second doped type on the epitaxial layer through the patterned second mask plate to form the second doped region.

[0102] Referring to FIG. 5, the ions of the second doped type can be P-type ions. The doped P-type ions can be aluminum (Al) ions or boron (B) ions.

[0103] S340, removing the second mask plate.

[0104] The second mask plate can be removed by a conventional process.

[0105] S350, forming a third mask plate on the side of the epitaxial layer away from the substrate.

[0106] Referring to FIG. 5, the third mask plate is formed after the second doped region 50 is formed. The third mask plate covers the epitaxial layer 20 and the second doped region 50 in the epitaxial layer.

[0107] S360, patterning the third mask plate.

[0108] The PECVD and photolithography technology are used to transfer the pattern of the photo mask to the third mask plate. The third mask plate on the well region is removed.

[0109] S370, performing ion implantation of the second doped type on the epitaxial layer through the patterned third mask plate to form the well region.

[0110] Referring to FIG. 5, the ions of the second doped type can be P-type ions. The doped P-type ions can be aluminum (Al) ions or boron (B) ions.

[0111] S380, removing the third mask plate.

[0112] The third mask plate can be removed by a conventional process.

[0113] The preparation method of the power device provided in the embodiments of the present application has the same beneficial effects as the power device described in any of the embodiments of the present application.

Claims

1. A power device, comprising: A semiconductor structure, wherein the semiconductor structure includes a substrate and an epitaxial layer, the substrate being of a first doping type; the epitaxial layer is located on one side of the substrate, the epitaxial layer having the same doping type as the substrate; the first doping type region is located on the surface of the epitaxial layer away from the substrate; An insulating layer is located on the side of the epitaxial layer away from the substrate. The insulating layer has a first through-hole that penetrates the insulating layer and exposes a portion of the first doped region. An ohmic contact layer is located inside the first through-hole; A channel layer is located on the side of the ohmic contact layer away from the substrate, and the channel layer covers the ohmic contact layer and the insulating layer; the channel layer includes a first sub-region, a second sub-region, and a third sub-region, wherein the orthographic projection of the second sub-region onto the substrate coincides with the orthographic projection of the ohmic contact layer onto the substrate; the first sub-region is located on the side of the third sub-region away from the second sub-region; the first and second sub-regions are of a first doping type; A gate oxide layer is located on the side of the channel layer away from the substrate, and the gate oxide layer covers the second sub-region, the third sub-region, and a portion of the first sub-region; A gate is located on the side of the gate oxide layer away from the substrate, the gate covers a portion of the gate oxide layer, and the orthographic projection of the third sub-region on the substrate coincides with the orthographic projection of the gate on the substrate.

2. The power device according to claim 1, wherein, The channel layer further includes a fourth sub-region, which is located between the first sub-region and the third sub-region, and between the third sub-region and the second sub-region; the doping concentration of the fourth sub-region is less than that of the first sub-region.

3. The power device according to claim 1, further comprising: A second doped region and a well region are located on the surface of the epitaxial layer away from the substrate; the second doped region is located on the side of the well region away from the first doped region; the well region is located on both sides of the first doped region and is in contact with the first doped region; the well region is of the second doped type. The insulating layer further includes a second through-hole that penetrates the insulating layer and exposes a portion of the second doped region.

4. The power device according to claim 3, wherein, The number of the second doping type region and the number of the well regions are both two; the region between the two well regions is the first doping type region; The channel layer includes two first sub-regions, one second sub-region, and two third sub-regions, arranged in the order of first sub-region, third sub-region, second sub-region, third sub-region, and first sub-region along a first direction, the first direction being perpendicular to the direction from the substrate to the epitaxial layer; the gate oxide layer exposes portions of the first sub-regions at both edges; The gate includes a first gate and a second gate, wherein the orthographic projection of the first gate onto the substrate coincides with the orthographic projection of one of the third sub-regions onto the substrate; and the orthographic projection of the second gate onto the substrate coincides with the orthographic projection of another of the third sub-regions onto the substrate.

5. The power device according to claim 1, further comprising: A planarization layer is located on the side of the gate away from the substrate, and the planarization layer covers the gate and the gate oxide layer not covered by the gate.

6. The power device according to claim 5, further comprising: First electrode and second electrode; The first electrode is located on the side of the substrate away from the epitaxial layer, and the first electrode covers the substrate; The second electrode is located on the side of the planarization layer away from the substrate, and the second electrode covers the planarization layer, the second doped type region, and the first sub-region not covered by the planarization layer.

7. The power device according to claim 6, further comprising: The packaging structure includes a passivation layer and a protective layer; The passivation layer is located on the side of the second electrode away from the substrate, and the orthographic projection of the passivation layer on the substrate overlaps with the orthographic projection of the planarization layer on the substrate. The protective layer is located on the side of the passivation layer away from the substrate, and the protective layer covers the passivation layer and the sidewall of the passivation layer away from the edge.

8. A power module comprising a substrate and at least one power device as claimed in any one of claims 1-7, wherein the substrate is configured to carry the power device.

9. A power conversion circuit, said power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one power device as described in any one of claims 1-7, wherein the power device is electrically connected to the circuit board.

10. A vehicle, comprising a load and a power conversion circuit as claimed in claim 9, the power conversion circuit being configured to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the power to the load.

11. A method for fabricating a power device, comprising: A semiconductor structure is fabricated, wherein the semiconductor structure includes a substrate and an epitaxial layer, the substrate being of a first doping type; the epitaxial layer is located on one side of the substrate, and the epitaxial layer has the same doping type as the substrate; A first doped region is formed on the surface of the epitaxial layer away from the substrate; An insulating layer is formed on the side of the epitaxial layer away from the substrate; the insulating layer is provided with a first through-hole, the first through-hole penetrating the insulating layer and exposing a portion of the first doped type region; An ohmic contact layer is formed inside the first through-hole; A channel sublayer is formed on the side of the ohmic contact layer away from the substrate; the channel sublayer covers the ohmic contact layer and the insulating layer; A gate oxide sublayer is formed on the side of the channel sublayer away from the substrate; the gate oxide sublayer covers the channel sublayer; A gate is formed on the side of the gate oxide layer away from the substrate; the gate covers a portion of the gate oxide layer; Using the gate as a mask, ion implantation of the first doping type is performed on the channel sublayer to form a first sub-region and a second sub-region, thereby forming the channel layer; the orthographic projection of the second sub-region onto the substrate coincides with the orthographic projection of the ohmic contact layer onto the substrate; the channel layer includes the first sub-region, the second sub-region, and a third sub-region, the orthographic projection of the third sub-region onto the substrate coincides with the orthographic projection of the gate onto the substrate; the first sub-region is located on the side of the third sub-region away from the second sub-region; the first and second sub-regions are of the first doping type; The gate oxide sublayer is etched to form a gate oxide layer; the gate oxide layer covers the second sub-region, the third sub-region, and a portion of the first sub-region.

12. The fabrication method according to claim 11, wherein after using the gate as a mask to perform ion implantation of a first doping type on the channel sublayer to form a first sub-region and a second sub-region, thereby forming the channel layer, the method further comprises: A first mask is formed on the side of the gate oxide layer far away from the substrate; Pattern the first mask; The first patterned mask is used to implant ions of the first doping type into the channel layer to form a fourth sub-region. The fourth sub-region is located between the first sub-region and the third sub-region, and between the third sub-region and the second sub-region; the doping concentration of the fourth sub-region is less than that of the first sub-region. Remove the first mask.

13. The fabrication method according to claim 11, wherein before etching the gate oxide sublayer to form the gate oxide layer, the method further comprises: A planarization sublayer is formed on the side of the gate away from the substrate; The planarization sublayer covers the gate and the gate does not cover the gate oxide sublayer; Etching the gate oxide sublayer to form a gate oxide layer includes: Simultaneously etch the planarization sublayer and the gate oxide sublayer to form a planarization layer and a gate oxide layer; This exposes the first sub-regions at both edges of the channel layer, such that the gate oxide layer and the planarization layer are exposed.

14. The fabrication method according to claim 11, wherein before forming a first doped region on the surface of the epitaxial layer away from the substrate, the method further comprises: A second mask is formed on the side of the epitaxial layer away from the substrate; Pattern the second mask; The epitaxial layer is implanted with ions of a second doping type using the patterned second mask to form a second doping type region. Remove the second mask; A third mask is formed on the side of the epitaxial layer away from the substrate; Pattern the third mask; The epitaxial layer is implanted with ions of the second type of doping through the patterned third mask to form a well region. Remove the third mask.

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