QFN packaged chip

Abstract

A QFN packaged chip. The QFN packaged chip comprises a package body (1), a lead frame (2), a bare die (3), four rows of first package pads (4), and at least one set of reinforced package pads (5). The lead frame (2) and the bare die (3) are packaged in the package body (1), and a ground pad (31) of the bare die (3) is electrically connected to the lead frame (2). Each set of reinforced package pads (5) is located at one corner of the bottom of the package body (1). Each set of reinforced package pads (5) comprises a first reinforced package pad (51) and a second reinforced package pad (52), and the distance between the first reinforced package pad (51) and a vertex (10) of the corner where the first reinforced package pad (51) is located is greater than the distance between the second reinforced package pad (52) and said vertex (10). The first reinforced package pad (51) is electrically connected to the lead frame (2), and the second reinforced package pad (52) is electrically connected to the lead frame (2) or is in a floating signal state.

Description

QFN package chip

[0001] The present disclosure claims priority to the Chinese patent application No. 202410866337.4, filed on June 29, 2024, and entitled "QFN package chip", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of packaging, in particular to a quad flat no-lead package (QFN) package chip. BACKGROUND

[0003] The quad flat no-lead package (QFN) package chip is square or rectangular. Four rows of package pads are arranged on the four edges of the bottom of the QFN package chip, and the four rows of package pads are used for welding with the pads on the printed circuit board (PCB) to realize the fixation and electrical connection of the QFN package chip and the PCB.

[0004] When the QFN package chip is subjected to stress, the package pads at the four corners of the bottom of the QFN package chip are prone to cracking, which reduces the reliability of the QFN package chip. SUMMARY

[0005] The present disclosure provides a quad flat no-lead package (QFN) package chip. The corners of the bottom of the QFN package chip include first and second reinforcing package pads arranged at intervals, which can improve the welding strength of the corners of the QFN package chip and thus improve the reliability of the QFN package chip. The technical solution of the QFN package chip is as follows.

[0006] The present disclosure provides a QFN package chip. The QFN package chip includes a package body, a lead frame, a bare chip, four rows of first package pads, and at least one group of reinforcing package pads. The lead frame and the bare chip are packaged in the package body, and the ground pads of the bare chip are electrically connected to the lead frame. The four rows of first package pads are respectively arranged on the four edges of the bottom of the package body, and the first package pads are electrically connected to the signal pads or the ground pads of the bare chip. Each group of reinforcing package pads is located at a corner of the bottom of the package body. Each group of reinforcing package pads includes at least a first reinforcing package pad and a second reinforcing package pad, and the distance from the first reinforcing package pad to the vertex of the corner is greater than the distance from the second reinforcing package pad to the vertex. The first reinforcing package pad is electrically connected to the lead frame, and the second reinforcing package pad is electrically connected to the lead frame or the signal is suspended.

[0007] The package is a plastic package. The lead frame forms a skeleton part of the QFN package chip and is used to electrically connect the ground package pads together. The die refers to an unpackaged chip, which can also be referred to as a Die or a bare Die. The die includes pads, and the pads of the die are used to electrically connect the die to the lead frame or the package pads (such as the first package pads). The pads of the die include ground pads and signal pads. The ground pads are used for grounding, and the signal pads are used for transmitting high-speed signals. At least a part of the ground pads of the die is electrically connected to the lead frame, so that the lead frame is grounded and the package pads (such as the enhanced package pads) connected to the lead frame are also grounded.

[0008] The four rows of first package pads are exposed on the four edges of the bottom of the package, and are used to fix and electrically connect the QFN package chip to a printed circuit board (PCB). The first package pads are divided into signal package pads and ground package pads. The signal package pads are electrically connected to the signal pads of the die and are used to transmit high-speed signals. The ground package pads are electrically connected to the ground pads of the die and are used to ensure signal reflow and prevent signal crosstalk. The electrical connection between the ground package pads and the ground pads of the die can be achieved by connecting the ground package pads to the lead frame (such as integrated connection or through an electrical connection line).

[0009] In the technical solution provided by the present disclosure, each group of enhanced package pads includes at least a first enhanced package pad and a second enhanced package pad arranged at intervals, and the first enhanced package pad and the second enhanced package pad are less likely to crack at the same time. Moreover, since the first enhanced package pad and the second enhanced package pad are arranged at intervals, the cracking of one of the enhanced package pads will not directly cause the cracking of the other enhanced package pad. In this way, the reliability of the welding of the enhanced package pads is improved, and the reliability of the protection of the first package pads by the enhanced package pads is improved, that is, the reliability of the welding of the first package pads is improved.

[0010] Moreover, the first enhanced package pad is electrically connected to the lead frame, so that the first enhanced package pad is grounded. In this way, the first enhanced package pad can also play a role in ensuring signal reflow and reducing signal crosstalk. Furthermore, since the second enhanced package pad is closer to the vertex of the corner of the package than the first enhanced package pad, in general, the second enhanced package pad will crack before the first enhanced package pad, that is, the second enhanced package pad can protect the first enhanced package pad, which improves the reliability of the grounding of the first enhanced package pad.

[0011] In a possible implementation, the second enhanced packaging pad is electrically connected with the lead frame. In this way, the second enhanced packaging pad is grounded, and thus the second enhanced packaging pad can also play a role in protecting signal reflow and reducing signal crosstalk. Moreover, since the first enhanced packaging pad and the second enhanced packaging pad are both grounded, when one of the enhanced packaging pads (for example, the second enhanced packaging pad) cracks, the other enhanced packaging pad (for example, the first enhanced packaging pad) can still play a role in preventing signal crosstalk of the first packaging pad near the corner.

[0012] In a possible implementation, the QFN packaged chip has a side length greater than or equal to 10 mm and less than or equal to 14 mm.

[0013] In a possible implementation, the QFN packaged chip has a size of 10 mm*10 mm, 11 mm*11 mm, 12 mm*12 mm, 13 mm*13 mm, or 14 mm*14 mm.

[0014] In a possible implementation, the lead frame includes a main frame and at least one branch frame. The bare chip is fixed to the main frame, and a ground pad of the bare chip is electrically connected with the main frame. One end of each branch frame is connected with the main frame, and the other end extends toward a corner of the package. At least two regions of the branch frame are exposed at the bottom of the package, and the at least two regions form at least the first enhanced packaging pad and the second enhanced packaging pad. That is, the first enhanced packaging pad and the second enhanced packaging pad are integrally formed with the lead frame. The lead frame is made of metal.

[0015] In a possible implementation, the two first packaging pads closest to the first enhanced packaging pad are respectively a first edge packaging pad and a second edge packaging pad. The first edge packaging pad and the second edge packaging pad are respectively located on two adjacent sides of the package. A first reference line is tangent to the first edge packaging pad and the second edge packaging pad, and the first edge packaging pad and the second edge packaging pad are located on a side of the first reference line close to a vertex. The first reference line intersects the first enhanced packaging pad. The first edge packaging pad and the second edge packaging pad are both signal packaging pads.

[0016] The technical solution provided by the present disclosure can be summarized as follows: When the second enhanced packaging pad cracks, the first edge packaging pad, the second edge packaging pad, and the first enhanced packaging pad are simultaneously subjected to stress, and thus the first edge packaging pad, the second edge packaging pad, and the first enhanced packaging pad assist each other, thereby improving the reliability of the welding of the first edge packaging pad, the second edge packaging pad, and the first enhanced packaging pad. In addition, the first enhanced packaging pad can also reduce the signal crosstalk of the first edge packaging pad and the second edge packaging pad.

[0017] It should be noted that when the second reinforcing packaging pad cracks, any one of the first edge packaging pad, the second edge packaging pad and the first reinforcing packaging pad cracks, which will cause the QFN packaging chip to be unusable. Among them, the first edge packaging pad and the second edge packaging pad crack and the signal is missing, and the first reinforcing packaging pad cracks and the QFN packaging chip is unusable due to serious signal crosstalk. It can be seen that the first edge packaging pad, the second edge packaging pad and the first reinforcing packaging pad are equally important.

[0018] In a possible implementation, the first reinforcing packaging pad is located on one side of the first reference line close to the vertex. In this way, generally speaking, the first reinforcing packaging pad will crack before the first edge packaging pad and the second edge packaging pad, that is, the first reinforcing packaging pad can protect the first edge packaging pad and the second edge packaging pad.

[0019] In a possible implementation, the first reinforcing packaging pad and the second reinforcing packaging pad are located on the diagonal of the bottom of the packaging body. In this way, the QFN packaging chip is more uniformly stressed as a whole, reducing the possibility that the QFN packaging chip cracks due to uneven stress.

[0020] In a possible implementation, the reinforcing packaging pad further includes a third reinforcing packaging pad and a fourth reinforcing packaging pad. The third reinforcing packaging pad and the fourth reinforcing packaging pad are located on two sides of the diagonal, and the third reinforcing packaging pad, the fourth reinforcing packaging pad and the lead frame are electrically connected or the signal is suspended. Among them, the distance from the vertex of the corner to the third reinforcing packaging pad and the fourth reinforcing packaging pad is less than the distance from the vertex of the first reinforcing packaging pad. In this way, the second reinforcing packaging pad, the third reinforcing packaging pad and the fourth reinforcing packaging pad can all protect the first reinforcing packaging pad, achieving the effect of "one protection for many", greatly reducing the possibility of cracking of the first reinforcing packaging pad, and further improving the reliability of the first reinforcing packaging pad grounding.

[0021] In addition, by arranging a plurality of small-area reinforcing packaging pads in one corner, compared with arranging one large-area reinforcing packaging pad in the corner, the reinforcing packaging pad can improve the area of the reinforcing area. Because, in order to avoid the solder of the reinforcing packaging pad from being connected to the first packaging pad, a minimum gap is required between the reinforcing packaging pad and the first packaging pad, and the larger the area of the reinforcing packaging pad, the more solder is required, and the larger the gap is required. Therefore, compared with the large-area reinforcing packaging pad, the small-area reinforcing packaging pad can be closer to the first packaging pad, thereby increasing the area of the reinforcing area.

[0022] In a possible implementation, the third enhanced package pad and the fourth enhanced package pad are electrically connected with the lead frame. In this way, as long as one of the first enhanced package pad, the second enhanced package pad, the third enhanced package pad and the fourth enhanced package pad keeps grounded, the signal crosstalk can be prevented, and the signal integrity of the QFN package chip is ensured.

[0023] In a possible implementation, the third enhanced package pad is located at a first side of the bottom of the package body, and the fourth enhanced package pad is located at a second side of the bottom of the package body. The third enhanced package pad is spaced apart from the second side by a distance less than 1 mm, and the fourth enhanced package pad is spaced apart from the first side by a distance less than 1 mm. In this way, the third enhanced package pad and the fourth enhanced package pad are relatively close to the corresponding side, so that the four rows of first package pads can be arranged normally according to the arrangement of the package body when there is no enhanced package pad in the corner of the package body, and it is not necessary to remove some first package pads to obtain a large corner area to arrange multiple enhanced package pads. That is, the arrangement of the enhanced package pad does not occupy the resources of the first package pad (signal package pad). Since the closer to the vertex of the corner, the greater the possibility of cracking of the package pad, generally, the distance between the first package pad and the corresponding side is required to be greater than 1 mm.

[0024] In a possible implementation, the third enhanced package pad is spaced apart from the second side by a distance less than 0.95 mm, and the fourth enhanced package pad is spaced apart from the first side by a distance less than 0.95 mm.

[0025] In a possible implementation, the second reference line is tangent to the third enhanced package pad and the fourth enhanced package pad, and the second enhanced package pad and the fourth enhanced package pad are located on a side of the second reference line close to the vertex. The first enhanced package pad and the second enhanced package pad are arranged on two sides of the second reference line. In this way, the preset cracking sequence is that the second enhanced package pad cracks first, the third enhanced package pad and the fourth enhanced package pad crack later, and the first enhanced package pad cracks last.

[0026] In a possible implementation, the QFN package chip further includes four rows of second package pads, the four rows of second package pads are located in the region surrounded by the four rows of first package pads and are respectively opposite to the four rows of first package pads. The second package pads are electrically connected to the signal pads or the ground pads of the bare chip. A third reference line extends along the direction of the rows of second package pads and is tangent to the side of the second package pads away from the first package pads. A fourth reference line extends along the direction of the rows of second package pads and is tangent to the side of the second package pads close to the first package pads. At least part of the first enhanced package pad is located between the third reference line and the fourth reference line. In this way, the first enhanced package pad can also reduce the signal crosstalk of the second package pads.

[0027] In a possible implementation, each group of enhanced package pads includes one first enhanced package pad and two second enhanced package pads. The first enhanced package pad is located on the diagonal line of the bottom of the package body, and the two second enhanced package pads are located on the two sides of the diagonal line.

[0028] In a possible implementation, each group of enhanced package pads includes two first enhanced package pads and one second enhanced package pad. The second enhanced package pad is located on the diagonal line of the bottom of the package body, and the two first enhanced package pads are located on the two sides of the diagonal line.

[0029] In a possible implementation, the QFN package chip includes four groups of enhanced package pads, and the four groups of enhanced package pads are respectively located in the four corners of the bottom of the package body. In this way, the reliability of the soldering of the four corners of the QFN package chip is high. BRIEF DESCRIPTION OF DRAWINGS

[0030] FIG. 1 is a schematic diagram of a QFN package chip in the related art;

[0031] FIG. 2 is a schematic diagram of the top of a QFN package chip according to an embodiment of the present disclosure;

[0032] FIG. 3 is a schematic diagram of the internal structure of the QFN package chip shown in FIG. 2;

[0033] FIG. 4 is a schematic diagram of the bottom of a QFN package chip according to an embodiment of the present disclosure;

[0034] FIG. 5 is a schematic diagram of the internal structure of the QFN package chip shown in FIG. 4;

[0035] FIG. 6 is a schematic diagram of the internal structure of a QFN package chip according to an embodiment of the present disclosure;

[0036] FIG. 7 is a schematic diagram of the bottom of a QFN package chip according to an embodiment of the present disclosure;

[0037] Fig. 8 is a partial view of a corner of a QFN package chip according to an embodiment of the present disclosure;

[0038] Fig. 9 is a partial view of a corner of a QFN package chip according to an embodiment of the present disclosure;

[0039] Fig. 10 is a partial view of a corner of a QFN package chip according to an embodiment of the present disclosure;

[0040] Fig. 11 is a partial view of a corner of a QFN package chip according to an embodiment of the present disclosure;

[0041] Fig. 12 is a partial view of a corner of a QFN package chip according to an embodiment of the present disclosure;

[0042] Fig. 13 is a partial view of a corner of a QFN package chip according to an embodiment of the present disclosure;

[0043] Fig. 14 is a partial view of a corner of a QFN package chip according to an embodiment of the present disclosure;

[0044] Fig. 15 is a partial view of a corner of a QFN package chip according to an embodiment of the present disclosure;

[0045] Fig. 16 is a three-dimensional view of a lead frame according to an embodiment of the present disclosure;

[0046] Fig. 17 is a three-dimensional view of a branch frame of a lead frame according to an embodiment of the present disclosure.

[0047] Legend 1, package, 10, vertex, 11, first edge, 12, second edge; 2, lead frame, 21, main frame, 22, branch frame, 220, opening, 221, main branch frame, 222, sub-branch frame; 3, bare chip, 31, ground pad, 32, signal pad; 4, first package pad, 41, first edge package pad, 42, second edge package pad; 5, enhanced package pad, 51, first enhanced package pad, 52, second enhanced package pad, 53, third enhanced package pad, 54, fourth enhanced package pad; 6, second package pad; 7, center pad; A, first reference line, B, second reference line, C, third reference line, D, fourth reference line, E, fifth reference line, F, sixth reference line, G, seventh reference line, X, diagonal line. DETAILED DESCRIPTION

[0048] The conductive path inside a quad flat no-lead package (QFN) packaged chip is short, the self-inductance coefficient and the wiring resistance in the package are low, so that more excellent electrical performance can be provided, and the QFN packaged chip is suitable for high-speed signal application scenarios such as 10G serdes. As shown in FIG. 1, the QFN packaged chip is square or rectangular, and four rows of first packaging pads 4 are arranged on the four edges of the bottom of the QFN packaged chip. The four rows of first packaging pads 4 are used for welding with pads on a printed circuit board (PCB) to realize fixation and electrical connection of the QFN packaged chip and the PCB.

[0049] Since the packaging pads located at the four corners of the bottom of the QFN packaged chip are prone to cracking, in the related art, the first packaging pads 4 are arranged to avoid the four corners of the bottom of the package 1. Meanwhile, a large-area reinforcing packaging pad 5 is arranged at each of the four corners. The reinforcing packaging pad 5 is used for protecting the first packaging pads 4 to improve the reliability of the welding of the first packaging pads 4.

[0050] However, the technical solutions in the related art at least have the following technical problems. First, in some solutions, the reinforcing packaging pad 5 is suspended in signal and is only used for protecting the first packaging pads 4. However, this occupies the resources of the packaging pads of the QFN packaged chip. Moreover, although the reinforcing packaging pad 5 has a large area, the reinforcing packaging pad 5 still has a high probability of cracking. This is because the cracking of part of the reinforcing packaging pad 5 will quickly lead to the cracking of the entire reinforcing packaging pad 5.

[0051] Second, in other solutions, the reinforcing packaging pad 5 is grounded. However, since the reinforcing packaging pad 5 is located at the corner of the bottom of the packaged chip, the reinforcing packaging pad 5 still has a high probability of cracking. After the reinforcing packaging pad 5 grounded cracks, the signal reflow cannot be guaranteed, which will cause the signal crosstalk of the first packaging pads 4 located on both sides of the reinforcing packaging pad 5 to become serious, causing the QFN packaged chip to malfunction.

[0052] In view of the above technical problems, the present disclosure provides a QFN packaged chip. FIG. 2 is a schematic diagram of a top of a QFN packaged chip according to an embodiment of the present disclosure, and FIG. 3 is a schematic diagram of an internal structure of the QFN packaged chip shown in FIG. 2. FIG. 4 is a schematic diagram of a bottom of a QFN packaged chip according to an embodiment of the present disclosure, and FIG. 5 is a schematic diagram of an internal structure of the QFN packaged chip shown in FIG. 4. As shown in FIGS. 2-5, the QFN packaged chip includes a package body 1, a lead frame 2, a bare chip 3, four rows of first package pads 4, and at least one set of enhanced package pads 5. The lead frame 2 and the bare chip 3 are encapsulated in the package body 1. FIG. 6 is a schematic diagram of an internal structure of a QFN packaged chip according to an embodiment of the present disclosure, and FIG. 7 is a schematic diagram of a bottom of a QFN packaged chip according to an embodiment of the present disclosure. As shown in FIG. 6, the ground pads 31 of the bare chip 3 are electrically connected to the lead frame 2. As shown in FIGS. 6 and 7, the four rows of first package pads 4 are respectively located on four edges of the bottom of the package body 1, and the first package pads 4 are electrically connected to the signal pads 32 or the ground pads 31 of the bare chip 3. Each set of enhanced package pads 5 is located at a corner of the bottom of the package body 1, and each set of enhanced package pads 5 includes at least two spaced-apart enhanced package pads. For example, as shown in FIG. 8, each set of enhanced package pads 5 includes at least a first enhanced package pad 51 and a second enhanced package pad 52 which are spaced apart.

[0053] In some examples, the QFN packaged chip has a side length greater than or equal to 10 mm and less than or equal to 14 mm. For example, the QFN packaged chip has a size of 10 mm x 10 mm, 11 mm x 11 mm, 12 mm x 12 mm, 13 mm x 13 mm, or 14 mm x 14 mm.

[0054] The package body 1 can be a plastic package body. The lead frame 2 forms a skeleton part of the QFN packaged chip, and is used to electrically connect the ground package pads together.

[0055] The bare chip 3 refers to an unpackaged chip, which can also be referred to as a Die or a bare Die. The bare chip 3 includes pads, and the pads of the bare chip 3 are used to achieve electrical connection between the bare chip 3 and the lead frame 2 or the package pads (such as the first package pads 4). The pads of the bare chip 3 include ground pads 31 and signal pads 32. The ground pads 31 are used for grounding, and the signal pads 32 are used for transmitting high-speed signals. At least a part of the ground pads 31 of the bare chip 3 are electrically connected to the lead frame 2, so that the lead frame 2 is grounded, and the package pads connected to the lead frame 2 are also grounded.

[0056] The four rows of first packaging pads 4 are exposed on four edges of the bottom of the package 1, and are used to fix and electrically connect the QFN packaged chip to a PCB. The first packaging pads 4 include signal packaging pads and ground packaging pads. The signal packaging pads are electrically connected to the signal pads 32 of the bare chip 3, and are used to transmit high-speed signals. The ground packaging pads are electrically connected to the ground pads 31 of the bare chip 3, and are used to ensure signal return and prevent signal crosstalk. As shown in FIG. 6, the ground packaging pads are electrically connected to the ground pads 31 of the bare chip 3, and can be achieved by electrically connecting (such as integrally connecting or connecting through an electrically connecting wire) the ground packaging pads to the lead frame 2. The enhanced packaging pads 5 are exposed at the corners of the bottom of the package 1, and are used to be welded to pads on the PCB.

[0057] In the technical solution provided by the embodiments of the present disclosure, each group of enhanced packaging pads 5 includes at least two enhanced packaging pads 5 arranged at intervals. Compared with the technical solution in which each corner includes only one enhanced packaging pad 5 in FIG. 1, the possibility of simultaneous cracking of the two enhanced packaging pads 5 is lower. Moreover, since the two enhanced packaging pads 5 are arranged at intervals, cracking of one enhanced packaging pad 5 does not directly cause cracking of the other enhanced packaging pad 5. In this way, the reliability of the enhanced packaging pads 5 in protecting the first packaging pads 4 is improved, that is, the reliability of the welding of the first packaging pads 4 is improved.

[0058] In some examples, as shown in FIG. 8, the first enhanced packaging pad 51 and the second enhanced packaging pad 52 are both electrically connected to the lead frame 2, and thus the first enhanced packaging pad 51 and the second enhanced packaging pad 52 are both grounded. In this way, in addition to protecting the first packaging pads 4, the first enhanced packaging pad 51 and the second enhanced packaging pad 52 can also ensure signal return and reduce signal crosstalk. Moreover, since the first enhanced packaging pad 51 and the second enhanced packaging pad 52 are arranged at the same corner of the package 1, the distance between them is relatively short. Therefore, after one of the first enhanced packaging pad 51 and the second enhanced packaging pad 52 cracks, the other one can still ensure signal return and reduce signal crosstalk, so that the QFN packaged chip can still be used normally. This makes the QFN packaged chip provided by the embodiments of the present disclosure meet the packaging reliability requirements and the signal integrity (SI) requirements of high-speed signals such as 10G serdes.

[0059] It can be understood that, in the technical solution in the related art shown in FIG. 1, since each corner has only one ground enhanced packaging pad 5, if the enhanced packaging pad 5 located at the corner cracks, the signal crosstalk between the first packaging pads 4 near the corner of the QFN packaged chip will rapidly deteriorate, resulting in that the QFN packaged chip cannot be used.

[0060] In some examples, the signal of the first enhanced package pad 51 is suspended, and the signal of the second enhanced package pad 52 is suspended, and the enhanced package pad 5 is only used for protecting the first enhanced package pad 4.

[0061] In some examples, as shown in FIG. 8 and FIG. 9, the distance between the first enhanced package pad 51 and the vertex 10 of the corner is greater than the distance between the second enhanced package pad 52 and the vertex 10. Alternatively, the first enhanced package pad 51 and the second enhanced package pad 52 are arranged on the two sides of a reference line (for example, the second reference line B in FIG. 9), and the first enhanced package pad 51 is close to the center point of the package 1, and the second enhanced package pad 52 is close to the vertex 10. The first enhanced package pad 51 is electrically connected to the lead frame 2.

[0062] The technical scheme provided by the embodiments of the present disclosure is that the distance between the first enhanced package pad 51 and the vertex 10 is greater than the distance between the second enhanced package pad 52 and the vertex 10, so that the second enhanced package pad 52 is located at the periphery of the bottom of the package 1 compared with the first enhanced package pad 51. Generally, the second enhanced package pad 52 will crack before the first enhanced package pad 51, that is, the second enhanced package pad 52 can protect the first enhanced package pad 51, which improves the reliability of the ground of the first enhanced package pad 51.

[0063] In some examples, the signal of the second enhanced package pad 52 is suspended, and the second enhanced package pad 52 is only used for protecting the first enhanced package pad 51 and the first package pad 4.

[0064] In some examples, as shown in FIG. 8, the second enhanced package pad 52 is electrically connected to the lead frame 2, and the second enhanced package pad 52 is grounded. The second enhanced package pad 52 is used for protecting the first enhanced package pad 51 and ensuring signal reflow and reducing signal crosstalk.

[0065] In some examples, as shown in FIG. 3-FIG. 7, the QFN package chip includes four groups of enhanced package pads 5, and the four groups of enhanced package pads 5 are respectively located at the four corners of the bottom of the package 1. In this way, the welding reliability of each corner of the QFN package chip is high, and the reliability of the QFN package chip is improved.

[0066] In some examples, the QFN package chip includes two groups of enhanced package pads 5, and the two groups of enhanced package pads 5 are respectively located in the two opposite corners of the bottom of the package 1.

[0067] In the following, the position of the second enhanced package pad 52 is exemplarily described.

[0068] When the package pads of a QFN package chip crack, generally, the peripheral package pads crack first, and then the inner package pads crack. Specifically, a reference line is drawn, which is perpendicular to the diagonal line X of the package body 1, for example, the first reference line A in FIG. 9. The reference line is coincided with the vertex 10 of the corner, and is translated to the center position of the package body 1, then the contact order of the reference line and each package pad is the crack order of each package pad.

[0069] Based on the crack order, in some examples, as shown in FIG. 9, it is assumed that the two first package pads 4 closest to the first enhanced package pad 51 are the first edge package pad 41 and the second edge package pad 42. The first edge package pad 41 and the second edge package pad 42 are located on two adjacent sides of the package body 1, respectively. As shown in FIG. 9, it is assumed that the first reference line A is tangent to the first edge package pad 41 and the second edge package pad 42, and the first edge package pad 41 and the second edge package pad 42 are located on the side of the first reference line A close to the vertex 10. Then, the second enhanced package pad 52 is located on the side of the first reference line A close to the vertex 10. The first edge package pad 41 and the second edge package pad 42 are signal package pads.

[0070] Further, in some examples, as shown in FIG. 9, it is assumed that the fifth reference line E passes through the center point of the first edge package pad 41 and the center point of the second edge package pad 42, and the second enhanced package pad 52 is located on the side of the fifth reference line E close to the vertex 10. In this way, the second enhanced package pad 52 will generally crack before the first edge package pad 41 and the second edge package pad 42, so that the second enhanced package pad 52 can protect the first edge package pad 41 and the second edge package pad 42.

[0071] Further, in some examples, as shown in FIG. 9, it is assumed that the seventh reference line G is tangent to the first edge package pad 41 and the second edge package pad 42, and the first edge package pad 41 and the second edge package pad 42 are located on the side of the seventh reference line G away from the vertex 10. Then, the second enhanced package pad 52 is located on the side of the seventh reference line G close to the vertex 10.

[0072] Next, the position of the first enhanced package pad 51 is exemplarily described.

[0073] In some examples, as shown in FIG. 9, the first reference line A intersects the first reinforcing package pad 51. In this way, when the peripheral second reinforcing package pad 52 cracks, the first reinforcing package pad 51, the first edge package pad 41 and the second edge package pad 42 are simultaneously stressed, and the first edge package pad 41, the second edge package pad 42 and the first reinforcing package pad 51 mutually assist each other, thereby improving the reliability of the soldering of the first edge package pad 41, the second edge package pad 42 and the first reinforcing package pad 51. In addition, this positional relationship also facilitates the first reinforcing package pad 51 to reduce signal crosstalk of the first edge package pad 41 and the second edge package pad 42.

[0074] It should be noted that when the second reinforcing package pad 52 cracks, any one of the first edge package pad 41, the second edge package pad 42 and the first reinforcing package pad 51 cracks, which will cause the QFN package chip to be unusable. Among them, the first edge package pad 41 and the second edge package pad 42 crack to cause signal loss, and the first reinforcing package pad 51 cracks to cause the QFN package chip to be unusable due to serious signal crosstalk. It can be seen that the first edge package pad 41, the second edge package pad 42 and the first reinforcing package pad 51 are equally important.

[0075] Of course, in other examples, the first reinforcing package pad 51 is located on one side of the first reference line A close to the vertex 10 (for example, as shown in FIG. 15). In this way, the first reinforcing package pad 51 can protect the first edge package pad 41 and the second edge package pad 42.

[0076] In some examples, as shown in FIG. 10, the fifth reference line E intersects the first reinforcing package pad 51. Of course, in other examples, the first reinforcing package pad 51 can also be located on one side of the fifth reference line E close to the vertex 10.

[0077] In some examples, as shown in FIGS. 8-13, the first reinforcing package pad 51 and the second reinforcing package pad 52 are located on the diagonal line X of the bottom of the package body 1. In this way, the stress on the corners of the package body 1 is more uniform, thereby reducing the possibility of cracking of the package pads of the QFN package chip due to uneven stress.

[0078] In some examples, as shown in FIGS. 8-13, the first reinforcing package pad 51 and the second reinforcing package pad 52 are symmetrically distributed about the diagonal line X of the bottom of the package body 1.

[0079] In addition to the first enhanced packaging pad 51 and the second enhanced packaging pad 52, in some examples, as shown in FIGS. 8-12, each group of enhanced packaging pads 5 further includes a third enhanced packaging pad 53 and a fourth enhanced packaging pad 54. The third enhanced packaging pad 53 and the fourth enhanced packaging pad 54 are located on both sides of the diagonal line X, and the third enhanced packaging pad 53, the fourth enhanced packaging pad 54 are electrically connected with the lead frame 2 or the signal is suspended.

[0080] In some examples, as shown in FIGS. 8-12, the third enhanced packaging pad 53 and the fourth enhanced packaging pad 54 are away from the vertex 10 at a distance less than the distance between the first enhanced packaging pad 51 and the vertex 10.

[0081] In this way, the second enhanced packaging pad 52, the third enhanced packaging pad 53 and the fourth enhanced packaging pad 54 can all protect the first enhanced packaging pad 51, achieving the effect of "one protection for many", greatly reducing the possibility of cracking of the first enhanced packaging pad 51, and improving the reliability of the first enhanced packaging pad 51 grounding. In addition, it also reduces the possibility of cracking of the first packaging pad 4. Among them, through actual measurement, compared with not setting the enhanced packaging pad 5 in the corner, the setting of the first enhanced packaging pad 51, the second enhanced packaging pad 52, the third enhanced packaging pad 53 and the fourth enhanced packaging pad 54 makes the reliability of the solder joint of the first packaging pad 4 improved by 24%.

[0082] In some examples, as shown in FIGS. 8-12, the third enhanced packaging pad 53 and the fourth enhanced packaging pad 54 are both electrically connected with the lead frame 2. In this way, as long as one of the first enhanced packaging pad 51, the second enhanced packaging pad 52, the third enhanced packaging pad 53 and the fourth enhanced packaging pad 54 is grounded, the signal can be guaranteed to be effectively reflowed.

[0083] It needs to be explained that, as shown in FIG. 11, compared with the related art of setting one large-area reinforcing packaging pad 5, the technical solution provided by the embodiment of the present disclosure uses multiple small-area reinforcing packaging pads 5 arranged at intervals to replace the large-area reinforcing packaging pad 5. Among them, the reinforcing area of the large-area reinforcing packaging pad 5 is shown as the area framed by the dashed line in FIG. 11. It can be seen that, compared with the large-area reinforcing packaging pad 5, the multiple small-area reinforcing packaging pads 5 arranged at intervals in the embodiment of the present disclosure can increase the area of the reinforcing area, thereby further improving the reliability of the solder joint. This is because, in order to avoid the solder of the reinforcing packaging pad 5 from being connected to the first packaging pad 4, a minimum gap is required between the reinforcing packaging pad 5 and the first packaging pad 4, and the larger the area of the reinforcing packaging pad 5, the more solder is required to be used, and the larger the gap required. Therefore, compared with the large-area reinforcing packaging pad 5, the small-area reinforcing packaging pad 5 in the embodiment of the present disclosure can be closer to the first packaging pad 4, thereby increasing the area of the reinforcing area.

[0084] Next, the relative positional relationship of the first reinforcing packaging pad 51, the second reinforcing packaging pad 52, the third reinforcing packaging pad 53, and the fourth reinforcing packaging pad 54 will be exemplarily described.

[0085] In some examples, as shown in FIG. 9, it is assumed that the second reference line B is tangent to the third reinforcing packaging pad 53 and the fourth reinforcing packaging pad 54, and the third reinforcing packaging pad 53 and the fourth reinforcing packaging pad 54 are located on the side of the second reference line B close to the vertex 10. The first reinforcing packaging pad 51 and the second reinforcing packaging pad 52 are arranged on the two sides of the second reference line B. In this way, when cracking occurs, the second reinforcing packaging pad 52 cracks first, then the third reinforcing packaging pad 53 and the fourth reinforcing packaging pad 54 crack, and the first reinforcing packaging pad 51 cracks last.

[0086] In some examples, as shown in FIG. 10, it is assumed that the sixth reference line F passes through the center point of the third reinforcing packaging pad 53 and the center point of the fourth reinforcing packaging pad 54. The first reinforcing packaging pad 51 and the second reinforcing packaging pad 52 are arranged on the two sides of the sixth reference line F.

[0087] In some examples, as shown in FIG. 12, it is assumed that the third reinforcing packaging pad 53 is located at the first edge 11 of the bottom of the packaging body 1, and the fourth reinforcing packaging pad 54 is located at the second edge 12 of the bottom of the packaging body 1. The distance d1 between the side of the third reinforcing packaging pad 53 away from the second edge 12 and the second edge 12 is less than 1 mm, and the distance d1 between the side of the fourth reinforcing packaging pad 54 away from the first edge 11 and the first edge 11 is less than 1 mm.

[0088] In this way, the third and fourth reinforcing package pads 53 and 54 are closer to the vertex 10, and do not hinder the normal arrangement of the first package pads 4, so that the QFN package chip does not need to remove part of the first package pads 4 in order to arrange the third and fourth reinforcing package pads 53 and 54. Generally, the distance between the first package pads 4 and the vertex 10 cannot be less than 1 mm. In some examples, the above-mentioned d1 and d2 are less than 0.9 mm.

[0089] In some examples, as shown in FIGS. 6 and 7, the QFN package chip further includes four rows of second package pads 6, which are located in the area surrounded by the four rows of first package pads 4 and are respectively opposite to the four rows of first package pads 4. The second package pads 6 are electrically connected to the signal pads 32 or the ground pads 31 of the bare chip 3. In this way, the density of the package pads on the QFN package chip is improved.

[0090] In some examples, as shown in FIGS. 9 and 10, a third reference line C extends along the direction of the rows of second package pads 6 and is tangent to the side of the second package pads 6 away from the first package pads 4. A fourth reference line D extends along the direction of the rows of second package pads 6 and is tangent to the side of the second package pads 6 close to the first package pads 4. At least part of the first reinforcing package pad 51 is located between the third reference line C and the fourth reference line D. In this way, the grounded first reinforcing package pad 51 can also prevent signal crosstalk of the second package pads 6 on both sides, so that the first reinforcing package pad 51 can be shared by two rows of first package pads 4 and two rows of second package pads 6, and the number of required grounded first package pads 4 and second package pads 6 is reduced.

[0091] It should be noted that each group of reinforcing package pads 5 provided by the embodiments of the present disclosure can also not include the third and fourth reinforcing package pads 53 and 54. In some examples, as shown in FIG. 13, each group of reinforcing package pads 5 includes one first reinforcing package pad 51 and one second reinforcing package pad 52. The first and second reinforcing package pads 51 and 52 are located on the diagonal line X of the bottom of the package body 1.

[0092] In some examples, as shown in FIG. 14, each group of reinforcing package pads 5 includes one first reinforcing package pad 51 and two second reinforcing package pads 52. The first reinforcing package pad 51 is located on the diagonal line X of the bottom of the package body 1, and the two second reinforcing package pads 52 are located on both sides of the diagonal line X.

[0093] It should be noted that the two second enhanced package pads 52 in FIG. 14 can also be considered as the third enhanced package pad 53 and the fourth enhanced package pad 54 in FIGS. 8-12, and the description of the relevant sizes and positions of the third enhanced package pad 53 and the fourth enhanced package pad 54 in FIGS. 8-12 is also applicable to the two second enhanced package pads 52 in FIG. 14, which will not be repeated here.

[0094] In some examples, as shown in FIG. 15, each group of enhanced package pads 5 includes two first enhanced package pads 51 and one second enhanced package pad 52. The second enhanced package pad 52 is located on the diagonal line X of the bottom of the package 1, and the two first enhanced package pads 51 are located on both sides of the diagonal line X.

[0095] It should be noted that the two first enhanced package pads 51 in FIG. 15 can also be considered as the third enhanced package pad 53 and the fourth enhanced package pad 54 in FIGS. 8-12, and the description of the relevant sizes and positions of the third enhanced package pad 53 and the fourth enhanced package pad 54 in FIGS. 8-12 is also applicable to the two first enhanced package pads 51 in FIG. 15, which will not be repeated here.

[0096] Next, the implementation of the enhanced package pad 5 will be exemplarily described.

[0097] In some examples, as shown in FIG. 16, the lead frame 2 includes a main frame 21 and at least one branch frame 22. As shown in FIG. 2, the bare chip 3 is fixed to the main frame 21, and the ground pad 31 of the bare chip 3 is electrically connected to the main frame 21. One end of each branch frame 22 is connected to the main frame 21, and the other end extends towards one corner of the package 1. At least two regions of the branch frame 22 are exposed on the bottom of the package 1, and at least form the first enhanced package pad 51 and the second enhanced package pad 52. Alternatively, it can also be understood that each enhanced package pad 5 is integrally connected with the branch frame 22.

[0098] In the embodiment, the lead frame 2 is formed by the following method: a piece of metal sheet is attached to a piece of film, the metal sheet is etched, and the remaining parts after etching form the lead frame 2, the first package pad 4 and the second package pad 6, respectively.

[0099] In some examples, as shown in FIG. 16, four regions of the branch frame 22 are exposed. The four regions form the first enhanced package pad 51, the second enhanced package pad 52, the third enhanced package pad 53 and the fourth enhanced package pad 54, respectively.

[0100] In some examples, as shown in FIG. 17, the branch frame 22 includes one main branch frame 221 and three sub-branch frames 222. One end of the main branch frame 221 is connected with the main frame 21, and the other end is connected with the three sub-branch frames 222. Among them, the exposed area of the main branch frame 221 forms the first enhanced packaging pad 51, and the exposed areas of the three branch frames 222 respectively form the second enhanced packaging pad 52, the third enhanced packaging pad 53 and the fourth enhanced packaging pad 54.

[0101] In some examples, as shown in FIG. 12, the branch frame 22 includes an opening 220, and the first enhanced packaging pad 51, the second enhanced packaging pad 52, the third enhanced packaging pad 53 and the fourth enhanced packaging pad 54 surround the opening 220.

[0102] In some examples, as shown in FIG. 15, three areas of the branch frame 22 are exposed. The three areas respectively form two first enhanced packaging pads 51 and one second enhanced packaging pad 52.

[0103] In some examples, as shown in FIG. 15, the branch frame 22 includes one main branch frame 221 and three sub-branch frames 222. One end of the main branch frame 221 is connected with the main frame 21, and the other end is connected with the three sub-branch frames 222. Among them, the exposed areas of the three sub-branch frames 222 respectively form two first enhanced packaging pads 51 and one second enhanced packaging pad 52. As shown in FIG. 15, the exposed area of the sub-branch frame 222 located at the middle position of the three sub-branch frames 222 forms one second enhanced packaging pad 52.

[0104] In some examples, as shown in FIG. 14, three areas of the branch frame 22 are exposed. The three areas respectively form one first enhanced packaging pad 51 and two second enhanced packaging pads 52.

[0105] In some examples, as shown in FIG. 14, the branch frame 22 includes one main branch frame 221 and two sub-branch frames 222. One end of the main branch frame 221 is connected with the main frame 21, and the other end is connected with the two sub-branch frames 222. Among them, the exposed area of the main branch frame 221 forms the first enhanced packaging pad 51, and the exposed parts of the two sub-branch frames 222 respectively form two second enhanced packaging pads 52.

[0106] In some examples, as shown in FIGS. 4, 5, 7 and 16, the QFN packaging chip further includes a middle pad 7 located at the bottom of the packaging body 1, and the four rows of first packaging pads 4 surround the middle pad 7. Among them, the middle pad 7 is used for heat dissipation and grounding.

[0107] In some examples, the intermediate pad 7 is integrally connected with the main branch frame 221. Alternatively, it can also be understood that at least one region of the main branch frame 221 is exposed at the bottom of the package 1, and the exposed region forms the intermediate pad 7.

[0108] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the common meanings of the terms to those skilled in the art of the present disclosure. The above description is only optional embodiments of the present disclosure, and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A QFN packaged chip, characterized in that, The QFN packaged chip includes a package body (1), a lead frame (2), a bare chip (3), four rows of first package pads (4) and at least one set of enhanced package pads (5); The lead frame (2) and the bare chip (3) are encapsulated in the package (1), and the ground pad (31) of the bare chip (3) is electrically connected to the lead frame (2); The four rows of first package pads (4) are located on the four sides of the bottom of the package body (1), and the first package pads (4) are electrically connected to the ground pad (31) or signal pad (32) of the bare chip (3). Each set of the enhanced package pads (5) is located at a corner of the bottom of the package body (1). Each set of the enhanced package pads (5) includes at least a first enhanced package pad (51) and a second enhanced package pad (52). The distance of the first enhanced package pad (51) from the vertex (10) of the corner is greater than the distance of the second enhanced package pad (52) from the vertex (10). The first enhanced package pad (51) is electrically connected to the lead frame (2), and the second enhanced package pad (52) is electrically connected to the lead frame (2) or the signal is left floating.

2. The QFN packaged chip according to claim 1, characterized in that, The lead frame (2) includes a main frame (21) and at least one branch frame (22); The bare chip (3) is fixed to the main frame (21), and the grounding pad (31) of the bare chip (3) is electrically connected to the main frame (21); One end of each of the branch frames (22) is connected to the main frame (21), and the other end extends toward a corner of the package (1). At least two regions of the branch frames (22) are exposed at the bottom of the package (1), and the at least two regions form at least the first reinforced package pad (51) and the second reinforced package pad (52).

3. The QFN packaged chip according to claim 1 or 2, characterized in that, Let the two first package pads (4) closest to the first enhanced package pad (51) be the first edge package pad (41) and the second edge package pad (42), respectively. The first edge package pad (41) and the second edge package pad (42) are located on two adjacent sides of the package body (1); Assume that the first reference line (A) is tangent to both the first edge package pad (41) and the second edge package pad (42), and that the first edge package pad (41) and the second edge package pad (42) are located on the side of the first reference line (A) closer to the vertex (10); The first reference line (A) intersects with the first enhanced package pad (51), or the first enhanced package pad (51) is located on the side of the first reference line (A) closer to the vertex (10).

4. The QFN packaged chip according to any one of claims 1-3, characterized in that, The first reinforced package pad (51) and the second reinforced package pad (52) are located on the diagonal (X) at the bottom of the package (1).

5. The QFN packaged chip according to claim 4, characterized in that, Each set of the enhanced package pads (5) further includes a third enhanced package pad (53) and a fourth enhanced package pad (54); The third enhanced package pad (53) and the fourth enhanced package pad (54) are located on both sides of the diagonal (X). The distance of the third enhanced package pad (53) and the fourth enhanced package pad (54) from the vertex (10) is greater than the distance of the first enhanced package pad (51) from the vertex (10). The third enhanced package pad (53) and the fourth enhanced package pad (54) are electrically connected to the lead frame (2) or the signal is left floating.

6. The QFN packaged chip according to claim 5, characterized in that, it is provided that... The third enhanced packaging pad (53) is located on the first side (11) of the bottom of the package (1), and the fourth enhanced packaging pad (54) is located on the second side (12) of the bottom of the package (1). The distance between the third reinforced packaging pad (53) away from the second side (12) and the second side (12) is less than 1 mm, and the distance between the fourth reinforced packaging pad (54) away from the first side (11) and the first side (11) is less than 1 mm.

7. The QFN packaged chip according to claim 5 or 6, characterized in that, Assume that the second reference line (B) is tangent to both the third enhanced package pad (53) and the fourth enhanced package pad (54), and that the third enhanced package pad (53) and the fourth enhanced package pad (54) are located on the side of the second reference line (B) closer to the vertex (10); The first enhanced package pad (51) and the second enhanced package pad (52) are located on both sides of the second reference line (B).

8. The QFN packaged chip according to any one of claims 1-7, characterized in that, The QFN packaged chip also includes four rows of second packaged pads (6), which are located in the area enclosed by the four rows of first packaged pads (4). The second packaged pads (6) are electrically connected to the signal pads (32) or ground pads (31) of the bare chip (3). Let the third reference line (C) extend along the direction of the row of the second package pad (6) and be tangent to the side of the second package pad (6) away from the first package pad (4). Let the fourth reference line (D) extend along the direction of the row of the second package pad (6) and be tangent to the side of the second package pad (6) close to the first package pad (4). At least a portion of the first enhanced package pad (51) is located between the third reference line (C) and the fourth reference line (D).

9. The QFN packaged chip according to any one of claims 1-3, characterized in that, Each set of the enhanced package pads (5) includes one first enhanced package pad (51) and two second enhanced package pads (52); The first enhanced package pad (51) is located on the diagonal (X) at the bottom of the package (1), and the two second enhanced package pads (52) are located on both sides of the diagonal (X).

10. The QFN packaged chip according to any one of claims 1-3, characterized in that, Each set of the enhanced package pads (5) includes two first enhanced package pads (51) and one second enhanced package pad (52); The second enhanced package pad (52) is located on the diagonal (X) at the bottom of the package (1), and the two first enhanced package pads (51) are located on both sides of the diagonal (X).

11. The QFN packaged chip according to any one of claims 1-10, characterized in that, The QFN packaged chip includes four sets of enhanced package pads (5), which are located at the four corners of the bottom of the package body (1).

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