Semiconductor structure and semiconductor integrated structure

Abstract

Embodiments of the present disclosure provide a semiconductor structure, comprising: a substrate, wherein a dielectric layer is covered on the substrate, and the dielectric layer comprises a first region and a second region surrounding the first region; a first conductive pad provided in the first region of the dielectric layer, wherein a top surface of the first conductive pad is provided with a recess or protrusion portion, and the dielectric layer covers the top surface of the first conductive pad; and a first bonding pad provided in the second region of the dielectric layer, wherein the first bonding pad is provided around the first conductive pad, the first bonding pad has a top surface exposed to the dielectric layer, and a bottom surface of the first bonding pad is higher than the top surface of the first conductive pad. The semiconductor structure provided by the embodiments of the present disclosure has a second region surrounding the periphery of the first region, wherein a first bonding pad is provided in the second region, and the first bonding pad can effectively prevent the impact of a raised or recessed surface of the first region on the product yield.

Description

Semiconductor structure and semiconductor integrated structure

[0001] The present disclosure claims priority to the Chinese patent application No. 202410846462.9, filed on June 26, 2024, entitled “Semiconductor structure and semiconductor integrated structure”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a semiconductor integrated structure. BACKGROUND

[0003] Direct Bonding is a microelectronic manufacturing technology that refers to the tight connection between two semiconductor wafers or other planar materials through direct contact and interatomic forces without the presence of intermediate substances. Hybrid Bonding is a semiconductor integration technology that combines the characteristics of direct bonding and metal interconnection. In hybrid bonding, some areas use direct bonding to form strong connections through interatomic interactions, while in other specific areas, electrical connections are achieved through metal contacts or metal-to-metal bonding. Direct bonding technology and hybrid bonding technology are commonly used in chip stacking, 3D integrated circuits, microelectromechanical systems (MEMS), and other micro-nano systems, and have broad application prospects.

[0004] Regardless of direct bonding or hybrid bonding, there are very high requirements for the flatness of the surface to be bonded before bonding. For example, in the hybrid bonding process, the direct bonding area requires extremely high surface cleanliness and extremely low surface roughness to ensure close contact between atoms and good bonding quality. Any surface irregularities, particles or defects can cause bonding failure or reduce electrical performance. Therefore, before hybrid bonding, in order to improve the bonding yield, the surface treatment of the wafer is crucial, and various chemical mechanical polishing (CMP) or other cleaning technologies are usually used to optimize the surface flatness and cleanliness, but this also brings additional costs. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor structure with higher yield and lower manufacturing cost.

[0006] The problems to be solved by the technical spirits of the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] According to an example embodiment of the present disclosure, a semiconductor structure includes: a substrate, a dielectric layer covering the substrate, the dielectric layer including a first region and a second region surrounding the first region; a first conductive pad disposed in the dielectric layer of the first region, a top surface of the first conductive pad having a concave or convex portion, the dielectric layer covering the top surface of the first conductive pad; a first bonding pad disposed in the dielectric layer of the second region, the first bonding pad surrounding the first conductive pad, the first bonding pad having a top surface exposed to the dielectric layer, a bottom surface of the first bonding pad being higher than the top surface of the first conductive pad.

[0008] According to an example embodiment of the present disclosure, the semiconductor structure further includes a second bonding pad disposed in the dielectric layer of the first region, a bottom surface of the second bonding pad being electrically connected to the top surface of the first conductive pad, the second bonding pad having a top surface exposed to the dielectric layer.

[0009] According to an example embodiment of the present disclosure, the first conductive pad further includes an extension portion extending into the dielectric layer of the second region, the first bonding pad being disposed in the dielectric layer on the extension portion.

[0010] According to an example embodiment of the present disclosure, the semiconductor structure further includes a second bonding pad disposed in the dielectric layer of the first region, a bottom surface of the second bonding pad being electrically connected to the top surface of the first conductive pad, the second bonding pad having a top surface exposed to the dielectric layer.

[0011] According to an example embodiment of the present disclosure, the substrate further includes a third region disposed outside the second region or inside the second region, the dielectric layer covering the third region, the dielectric layer of the third region having a second conductive pad and a third bonding pad disposed therein, a bottom surface of the third bonding pad being electrically connected to a top surface of the second conductive pad, and a bottom surface of the second conductive pad and a bottom surface of the first conductive pad being coplanar, the third bonding pad having a top surface exposed to the dielectric layer.

[0012] According to an example embodiment of the present disclosure, a surface of the dielectric layer of the first region has a convex or concave portion relative to a surface of the dielectric layer of the second region.

[0013] According to an example embodiment of the present disclosure, the second region includes a plurality of first bonding pads uniformly distributed thereon, and the third region includes a plurality of third bonding pads uniformly distributed thereon, a spacing between each of the first bonding pads being greater than a spacing between each of the third bonding pads.

[0014] According to an example embodiment of the present disclosure, in a first direction, the second region includes at least one first bonding pad connected integrally as a whole, and the third region includes a plurality of third bonding pads arranged at intervals.

[0015] According to an example embodiment of the present disclosure, the first conductive pad includes a first portion and a second portion, the convex or concave portion of the top surface of the first conductive pad is located at the first portion, and the second bonding pad is formed on and connected to the second portion.

[0016] According to an example embodiment of the present disclosure, the first conductive pad is a test pad.

[0017] According to an example embodiment of the present disclosure, the second conductive pad is a signal pad.

[0018] According to an example embodiment of the present disclosure, the semiconductor structure further includes: a device layer formed on the substrate; and an interconnection layer formed on the device layer and electrically connected to the device layer, the first conductive pad being located on and electrically connected to the interconnection layer.

[0019] According to an example embodiment of the present disclosure, a semiconductor integrated structure is also provided, including a first semiconductor structure and a second semiconductor structure connected through opposite bonding surfaces, the first semiconductor structure including: a substrate, a dielectric layer covering the substrate, the dielectric layer including a first region and a second region surrounding the first region; a first conductive pad disposed in the dielectric layer of the first region, a top surface of the first conductive pad having a concave or convex portion, the dielectric layer covering the top surface of the first conductive pad; and a first bonding pad disposed in the dielectric layer of the second region, the first bonding pad surrounding the first conductive pad, the first bonding pad having a top surface exposed to the dielectric layer, a bottom surface of the first bonding pad being higher than the top surface of the first conductive pad, the first bonding pad being exposed to the top surface of the dielectric layer and the top surface of the dielectric layer as a bonding surface of the first semiconductor structure; the second semiconductor structure including: a substrate, a dielectric layer covering the substrate, the dielectric layer including a third region and a fourth region surrounding the third region; a third conductive pad disposed in the dielectric layer of the third region, a top surface of the third conductive pad having a concave or convex portion, the dielectric layer covering the top surface of the third conductive pad; and a fourth bonding pad disposed in the dielectric layer of the third region, the fourth bonding pad surrounding the third conductive pad, the fourth bonding pad having a top surface exposed to the dielectric layer, a bottom surface of the fourth bonding pad being higher than the top surface of the third conductive pad, the fourth bonding pad being exposed to the top surface of the dielectric layer and the top surface of the dielectric layer as a bonding surface of the second semiconductor structure; and the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure being aligned and bonded.

[0020] According to an example embodiment of the present disclosure, the semiconductor integrated structure further includes a bonding cavity between the bonding surfaces, the bonding cavity being located between the top surface of the dielectric layer of the first region and the top surface of the dielectric layer of the third region.

[0021] The semiconductor structure provided by the embodiments of the present disclosure has a second region surrounding the periphery of the first region, wherein the first bonding pad is arranged in the second region, and the first bonding pad can effectively prevent the influence of the convex or concave surface of the first region on product yield. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure.

[0023] FIGS. 1A-1C are schematic diagrams of a semiconductor structure according to some embodiments of the present disclosure;

[0024] FIGS. 2A-2C are schematic diagrams of a semiconductor structure according to some embodiments of the present disclosure;

[0025] FIGS. 3A-3B are schematic diagrams of a semiconductor structure according to some embodiments of the present disclosure;

[0026] FIGS. 4A-4D are schematic diagrams of a semiconductor structure according to some embodiments of the present disclosure;

[0027] FIGS. 5A-5B are schematic diagrams of a semiconductor structure according to some embodiments of the present disclosure;

[0028] FIG. 6 is a schematic diagram of a semiconductor integrated structure according to some embodiments of the present disclosure;

[0029] FIGS. 7A-7D are cross-sectional views of a specific position formed in a step of preparing a semiconductor structure, for describing a method of manufacturing a semiconductor structure according to embodiments of the present disclosure.

[0030] The above-described drawings have shown specific embodiments of the present disclosure, and more detailed descriptions will be given hereinafter. These drawings and written descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concept of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related disclosure, and not to limit the disclosure. In addition, it should be noted that only the relevant parts are shown in the drawings for convenience of description. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first", "second", "third" in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first", "second", "third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described.

[0032] The embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0033] In some embodiments of the present disclosure, a semiconductor structure 1 is provided, please refer to FIG. 1A and FIG. 1B, FIG. 1A is a top plan view of the semiconductor structure 1, and FIG. 1B is a cross-sectional view along the line A-A' in FIG. 1A. The semiconductor structure 1 includes a substrate 10 and a dielectric layer 2 covering the substrate 10, the dielectric layer 2 includes a first region 21 and a second region 22 on the substrate 10, and the second region 22 is a region surrounding the periphery of the first region 21 on the top plan view. The dielectric layer 2 in the first region 21 is provided with a first conductive pad 40, and the top surface of the first conductive pad 40 is covered by the dielectric layer 2. In the dielectric layer 2 of the second region 22, a first bonding pad 30 is provided, and the bottom surface of the first bonding pad 30 is higher than the top surface of the first conductive pad 40, and the top surface of the first bonding pad 30 is exposed on the top surface of the dielectric layer 2, that is, the first bonding pad 30 is formed in the dielectric layer 2 above the first conductive pad 40, and its top surface is not covered by the dielectric layer 2. The first bonding pad 30 surrounds the first conductive pad 40, that is, the projection of the pattern formed by the first bonding pad 30 on the top surface of the dielectric layer 2 surrounds the projection of the first conductive pad 40 on the top surface of the dielectric layer 2. In these embodiments, the first region 21 can be a region located at the center of the substrate 10.

[0034] In some embodiments, the first conductive pad 40 has a first portion and a second portion, the top surface 401 of the first portion is concave or convex relative to the top surface of the second portion, the top surface 401 can also be a top surface portion that has both concave and convex portions. The dielectric layer 2 conformally covers the top surface 401.

[0035] In other embodiments, referring to FIG. 1C, the first conductive pad 40 has an extended portion 402 that extends into the second region 22, the first bonding pad 30 is disposed in the dielectric layer 2 on the extended portion 402, and the top surface 401 of the first conductive pad 40 that is concave or convex on the top surface of the first conductive pad 40 is located on the top surface of the first conductive pad 40 in the first region 21. In some embodiments, the extended portion 402 can also extend into the second region 22 on other sides of the first region 21.

[0036] In some embodiments, the plurality of first bonding pads 30 are uniformly distributed in the second region 22, as shown in FIGS. 1A and 2A. The first bonding pad 30 can be a circular bonding pad or a substantially circular bonding pad, and the first bonding pad 30 can also be a quadrilateral bonding pad, such as a square or a rectangle.

[0037] In some embodiments, the first conductive pad 40 can be a metal pad formed of one or more combinations of aluminum metal, copper metal, nickel metal, and the like. The first bonding pad 30 can be copper, copper alloy, nickel, aluminum, tungsten, and combinations thereof. In some embodiments, the first conductive pad 40 and the first bonding pad 30 can contain different conductive materials, for example, the first conductive pad 40 contains aluminum and the first bonding pad 30 contains copper.

[0038] In some embodiments, the dielectric layer 2 can be a laminated structure composed of multiple layers of dielectric, for example, the first conductive pad 40 is located in one layer of dielectric and the first bonding pad 30 is located in another layer of dielectric.

[0039] In these embodiments, since the first region 21 and the second region 22 both include the dielectric layer 2, the first region 21 and the second region 22 are both a portion defined in the dielectric layer 2, and there is no obvious boundary between the two regions, and the two regions are defined by the locations of the first conductive pad 40 and the first bonding pad 30.

[0040] Since the first conductive pad 40 has an uneven top surface, the surface of the dielectric layer 2 in the first region 21 containing the first conductive pad 40 and the surface of the dielectric layer 2 in the second region 22 not containing the first conductive pad 40 have an undesirable height difference, which causes the two regions to have different bonding performance, thereby affecting the bonding effect. In these embodiments, by arranging the first bonding pad 30 around the first conductive pad 40 in the dielectric layer 2 above the periphery of the first conductive pad 40, the influence of the height difference between the first region 21 and the second region 22 on the bonding effect can be effectively improved. The presence of the first bonding pad 30 can control the occurrence of poor bonding effect between the first region 21 and the second region 22, preventing the influence of poor bonding effect on other regions. The area where the first bonding pad 30 is located can be set according to the size of the protruding or recessed area on the top surface of the first conductive pad 40, that is, the minimum distance between the first bonding pad 30 and the protruding or recessed area on the top surface of the first conductive pad 40 in the horizontal direction is controlled to satisfy a predetermined distance, that is, when the first conductive pad 40 has a portion extending into the second region 22, the first bonding pad can also be arranged on the extended portion of the first conductive pad 40, which can control the size of the first region 21 and the second region 22 and prevent waste of the effective area on the substrate.

[0041] In some embodiments, the minimum distance between the first bonding pad 30 and the protruding or recessed area 401 on the top surface of the first conductive pad 40 in the horizontal direction is 0.5 microns to 5 microns, for example, it can be 0.5 microns to 1 micron, 1 micron to 3 microns, 2.5 microns to 4 microns, or 4 microns to 5 microns.

[0042] In some embodiments, the width of the first conductive pad 40 in the horizontal plane is 2 microns to 5 microns, and the maximum width of the protruding or recessed area 401 on the top surface of the first conductive pad 40 in the horizontal plane is 0.5 microns to 1.5 microns.

[0043] Another semiconductor structure 1 is provided in some embodiments, which is different from the semiconductor structure shown in FIGS. 1A-1C. The semiconductor structure 1 in these embodiments has a second bonding pad 31 disposed on the first conductive pad 40. Please refer to FIGS. 2A-2B for details. FIG. 2A is a top plan view of the semiconductor structure 1, and FIG. 2B is a cross-sectional view along line A-A’ in FIG. 2A. The second bonding pad 31 is disposed in the dielectric layer 2 of the first region 21 and above the first conductive pad 40. In some embodiments, the projection of the second bonding pad 31 on the top surface of the dielectric layer 2 is located in the projection of the first conductive pad 40 on the top surface of the dielectric layer 2. The second bonding pad 31 is connected to the first conductive pad 40 through an interconnect structure 311, and the top surface of the second bonding pad 31 is exposed on the top surface of the dielectric layer 2, i.e., the top surface of the second bonding pad 31 is not covered by the dielectric layer 2. The bottom surface of the interconnect structure 311 is disposed on the top surface of the second portion of the first conductive pad 40, and the bottom surface of the interconnect structure 311 does not contact the top surface 401 of the first portion of the first conductive pad 40. In some embodiments, the bottom surface of the interconnect structure 311 can also contact the top surface 401.

[0044] In some embodiments, as shown in FIG. 2C, which is a cross-sectional view along line A-A’ in FIG. 2A, the first conductive pad 40 includes an extension portion 402 extending into the dielectric layer 2 of the second region 22, and the extension portion 402 extends into the dielectric layer 2 below the first bonding pad 30. In some embodiments, the extension portion 402 can also extend into the second region 22 on the other side of the first region 21.

[0045] In some embodiments, the number of the first conductive pads 40 in the first region 21 can be multiple, and the number of the second bonding pads 31 corresponding to the first conductive pads 40 can also be multiple. The second bonding pad 31 can be a circular bonding pad or a substantially circular bonding pad, and the second bonding pad 31 can also be a quadrilateral bonding pad, such as a square or a rectangle.

[0046] In some embodiments, the second bonding pad 31 is disposed in the dielectric layer 2 above the first conductive pad 40, i.e., the second bonding pad 31 can not be electrically connected to the first conductive pad 40. In these embodiments, the bottom surface of the first bonding pad 30 and the bottom surface of the second bonding pad 31 are located in the same plane.

[0047] In these embodiments, the second bonding pad 31 can also be disposed on the top surface of the first conductive pad 40. The disposition of the second bonding pad 31 can further control the adverse bonding effect between the first region 21 and the second region 22 to the area between the top surface of the first bonding pad 30 and the top surface of the second bonding pad 31, and reduce the area affected by the adverse bonding effect.

[0048] In other embodiments, the first bonding pads 30 have an integral structure surrounding the first region 21, as shown in FIGS. 3A and 3B. FIG. 3A shows that the first bonding pads 30 include a bonding pad 301 extending in one side of the second region 22 and a plurality of bonding pads 302 in another side of the second region 22, which are in an integral structure. The bonding pad 301 can be distributed in two opposite sides of the second region 22. The bonding pads 302 can be distributed in the other two opposite sides of the second region 22. FIG. 3B shows a schematic view of the first bonding pads 30 having an integral structure surrounding the first region 21. It is noted that the integral structure herein means that the structure exists as a whole without separated parts.

[0049] In some embodiments, the bonding pad 301 can be distributed in one side or more than one side of the second region 22. In some embodiments, the bonding pad 302 can be distributed in one side or more than one side of the second region 22, and the bonding pad 302 can also extend in one side of the second region 22 in an integral structure.

[0050] In these embodiments, by using the first bonding pads 30 having an integral structure, the poor bonding effect in the first region 21 can be more reliably controlled, and the first bonding pads 30 having an integral structure can further improve the heat dissipation and heat conduction capacity of the semiconductor structure.

[0051] In some embodiments, the first conductive pads 40 are test pads or test pads for performing circuit probe test (CP Test), and the convex or concave top surface portion 401 of the first conductive pads 40 can be an area where a probe mark is formed after a test probe contacts the top surface of the first conductive pads 40. The top surface of the first conductive pads 40 is also covered with a barrier layer (not shown), which is formed between the dielectric layer 2 and the top surface of the first conductive pads 40. The barrier layer on the convex or concave top surface portion 401 is removed during the probe test, so that the top surface portion 401 directly contacts the dielectric layer 2. The material of the barrier layer can be titanium nitride.

[0052] In some embodiments, the first bonding pads 30 are virtual metal pads without current passing, and the second bonding pads 31 can be virtual metal pads without current passing or metal pads with current passing, in which case the current is conducted through the first conductive pads 40 and the second bonding pads 31. The second bonding pads 31 can be copper, copper alloy, nickel, aluminum, tungsten, or a combination thereof.

[0053] In some embodiments, the dielectric layer 2 can be a laminated structure composed of multiple layers of dielectric, for example, the first conductive pads 40 are located in one layer of dielectric, and the first bonding pads 30 and the second bonding pads 31 are located in another layer of dielectric.

[0054] In some embodiments, another semiconductor structure 1 is provided, with reference to FIGS. 4A-4B. FIG. 4A is a top plan view of the semiconductor structure 1, and FIG. 4B is a cross-sectional view along line A-A’ in FIG. 4A. The overlying dielectric layer 2 of the semiconductor structure 1 further includes a third region 23 outside the second region 22, the third region 23 having a second conductive pad 41 disposed therein, the dielectric layer 2 over the second conductive pad 41 having a third bonding pad 32 disposed therein, a bottom surface of the third bonding pad 32 being electrically connected to a top surface of the second conductive pad 41 via an interconnect structure 321 disposed therebetween, the third bonding pad 32 further having a top surface exposed to a top surface of the dielectric layer 2. In these embodiments, the first region 21 can be a region at a center of the substrate 10, and the third region 23 can be a region at an edge of the substrate 10.

[0055] In some embodiments, the third bonding pad 32 can be directly electrically connected to the second conductive pad 41. That is, a bottom surface of the third bonding pad 32 abuts a top surface of the second conductive pad 41.

[0056] In some embodiments, the plurality of third bonding pads 32 are uniformly distributed in the third region 23, and the plurality of first bonding pads 30 are uniformly distributed in the second region 22, each first bonding pad 30 having a first pitch therebetween, and each third bonding pad 32 having a second pitch therebetween, the first pitch being greater than the second pitch. In some embodiments, the first pitch can be 0.5-2 microns, and the second pitch can be 0.2-1 micron.

[0057] In some embodiments, the first bonding pad 30 and the third bonding pad 32 can be the same or substantially the same shape, such as both being circular bonding pads, substantially circular bonding pads, or quadrilateral bonding pads, such as square or rectangular. In some embodiments, the first bonding pad 30 and the third bonding pad 32 can also have the same or substantially the same surface area, specifically, in a horizontal direction, a width or diameter of the first bonding pad 30 and the third bonding pad 32 can be the same. In some embodiments, the first bonding pad 30 has a greater surface area than the third bonding pad 32, such as, in a horizontal direction, a width or diameter of the first bonding pad 30 is greater than a width or diameter of the third bonding pad 32. In some embodiments, the width or diameter of the first bonding pad 30 is 0.05-2 microns, and the width or diameter of the third bonding pad 32 is 0.05-1.5 microns.

[0058] In some embodiments, the first conductive pad 40 and the second conductive pad 41 can be formed in the same step of a metal interconnection routing process, in which case, the bottom surface of the second conductive pad 41 and the bottom surface of the first conductive pad 40 are co-planar, and the top surface of the second conductive pad 41 does not have a protruding or recessed portion, i.e., the top surface of the second conductive pad 41 can be co-planar or substantially co-planar with the top surface of the second portion of the first conductive pad 40. In some embodiments, the first conductive pad 40 and the second conductive pad 41 can be metal pads formed of one or more combinations of aluminum metal, copper metal, nickel metal, etc. For example, the first conductive pad 40 and the second conductive pad 41 can both be aluminum-containing metal pads.

[0059] Continuing with FIG. 4C, FIG. 4C provides another semiconductor structure 1, which is based on the semiconductor structure of FIG. 4A and further includes a second bonding pad 31 in the first region 21, the second bonding pad 31 being located on and connected with the first conductive pad 40. The positional relationship between the second bonding pad 31 and the first conductive pad 40 can be referred to the description of the previous embodiments, which will not be repeated here. The second bonding pad 31 can have the same or substantially the same shape as the first bonding pad 30 and the third bonding pad 32, e.g., all being circular bonding pads, substantially circular bonding pads, or quadrilateral bonding pads, e.g., square or rectangular. In some embodiments, the second bonding pad 31 can also have the same or substantially the same surface area as the first bonding pad 30 and the third bonding pad 32, specifically, in the horizontal direction, the width or diameter of the second bonding pad 31 can be the same as that of the first bonding pad 30 and the third bonding pad 32. In some embodiments, the surface area of the second bonding pad 31 can be greater than that of the first bonding pad 30 and the third bonding pad 32, e.g., in the horizontal direction, the width or diameter of the second bonding pad 31 can be greater than that of the first bonding pad 30 and the third bonding pad 32. In some embodiments, the width or diameter of the second bonding pad 31 can be 0.1-2 microns. In some embodiments, the number of the second bonding pads 31 in the first region 21 can be multiple, which can be uniformly distributed in the first region 21 or not, and the spacing between each second bonding pad 31 and the first bonding pad 30 can be equal to or greater than the spacing between each first bonding pad 30 and each third bonding pad 32.

[0060] In some embodiments, the second conductive pad 41 can be a signal pad or a signal pad different from the first conductive pad 40.

[0061] In some embodiments, the top surface of the dielectric layer 2 of the first region 21 can have a protruding or recessed portion 210 relative to the top surface of the dielectric layer 2 of the second region 22, as shown in FIGS. 1A-4C. The projection of the top surface 401 of the first conductive pad 40 on the top surface of the dielectric layer 2 of the first region 21 overlaps with the portion 210.

[0062] In some embodiments, as shown in FIG. 4D, the dielectric layer 2 includes a first dielectric layer 201 and a second dielectric layer 202, the second dielectric layer 202 is formed on the first dielectric layer 201, the first conductive pad 40 and the second conductive pad 41 are formed on the first dielectric layer 201, and the first bonding pad 30 is formed in the second dielectric layer 202, i.e., the first conductive pad 40 and the second conductive pad 41 are formed in different dielectric layers from the first bonding pad 30. In some embodiments, the third bonding pad 32 is also formed in the second dielectric layer 202, and the interconnection structure 321 connects the second conductive pad 41 through the first dielectric layer 201 and the second dielectric layer 202. The top surface of the first conductive pad 40 has a portion not covered by the first dielectric layer 201, for example, the top surface portion 401 is not covered by the first dielectric layer 201, and the second dielectric layer 202 covers the top surface of the first conductive pad 40 not covered by the first dielectric layer 201. For example, the second dielectric layer 202 covers the top surface portion 401.

[0063] In some embodiments, the first dielectric layer 201 and the second dielectric layer 202 can be a single-layer dielectric layer composed of a single-layer dielectric or a multi-layer dielectric layer composed of a multi-layer dielectric. For example, the first dielectric layer 201 can be a laminated structure composed of one or both of silicon oxide and silicon nitride, and the second dielectric layer 202 can be a laminated structure composed of one or more of silicon oxide, silicon carbon nitride, silicon nitride, and silicon carbon oxide.

[0064] In some embodiments, there is also a barrier layer between the first conductive pad 40 and the second conductive pad 41 and the first dielectric layer 201, which can be a layer of titanium nitride, tungsten nitride, or other material that prevents diffusion or etch reflection of the first conductive pad 40 and the second conductive pad 41.

[0065] The semiconductor structure of the embodiments of the present disclosure includes a device layer 60 located in the substrate 10 and an interconnection layer 50 located on the device layer 60, and the device layer 60 is electrically connected to the first conductive pad 40 and the second conductive pad 41 through the interconnection layer 50. The device layer 60 can include a storage unit and / or a control unit, for example, the device layer 60 includes a DRAM storage unit and / or a control unit composed of CMOS transistors. The interconnection layer 50 can include multiple layers of metal wires and interconnection structures connecting between the layers of metal wires. In some embodiments, the interconnection layer 50 can also be composed of only one layer of metal wires, for example, it can be a conductive via structure.

[0066] In some embodiments, the first bonding pad 30, the second bonding pad 31, and the third bonding pad 32 are exposed to the surface of the top surface of the dielectric layer 2, and the top surface of the dielectric layer 2 is the surface of the semiconductor structure for bonding with another semiconductor structure.

[0067] In some embodiments, the third region 23 can be disposed within the first region 21, as shown in FIG. 5A, and the first region 21 can be disposed around the third region 23. In these embodiments, the third region 23 can be a region in the center of the substrate 10, and the first region 21 and the second region 22 can be regions at the edges of the substrate 10. The first bonding pad 30, the third bonding pad 32, and the conductive pads in the dielectric layer can be disposed as described in the foregoing embodiments, and will not be described again here.

[0068] In some embodiments, the third region 23 can be disposed within the first region 21, as shown in FIG. 5A, and the first region 21 can be disposed around the third region 23. In these embodiments, the third region 23 can be a region in the center of the substrate 10, and the first region 21 and the second region 22 can be regions at the edges of the substrate 10. The first bonding pad 30, the third bonding pad 32, and the conductive pads in the dielectric layer can be disposed as described in the foregoing embodiments, and will not be described again here.

[0069] Embodiments of the present disclosure also provide a semiconductor integrated structure including a first semiconductor structure 1 and a second semiconductor structure 1' connected by opposite bonding surfaces. As shown in FIG. 6, the first semiconductor structure 1 includes a substrate 10 and a dielectric layer 2 covering the substrate 10, and the dielectric layer 2 has a first region 21 and a second region 22 surrounding the first region 21. The dielectric layer 2 of the first region 21 has a first conductive pad 40 disposed therein, and the dielectric layer 2 of the second region 22 has a first bonding pad 30 disposed therein, and the first bonding pad 30 is not connected to the first conductive pad 40. The first conductive pad 40 has a recessed or protruding partial top surface 401 on the top surface thereof, and the first conductive pad 40 is electrically connected to a device layer 60 by an interconnection structure 50. The semiconductor structure 1' includes a substrate 10' and a dielectric layer 2' covering the substrate 10', and the dielectric layer 2' has a third region 21' and a fourth region 22' corresponding to the first region 21 and the second region 22 of the first semiconductor structure 1, respectively. Similar to the first semiconductor structure 1, the dielectric layer 2 of the third region 21' of the second semiconductor structure 1' has a third conductive pad 40' disposed therein, and the dielectric layer 2 of the fourth region 22' has a third bonding pad 30' disposed therein, and the third bonding pad 30' is not electrically connected to the third conductive pad 40'. The third conductive pad 40' has a recessed or protruding partial top surface 401' on the top surface thereof, and the third conductive pad 40' is electrically connected to a device layer 60' by an interconnection structure 50'.

[0070] In some embodiments, the surface of the dielectric layer 2 of the first semiconductor structure 1 and the first bonding pad 30 serve as bonding surfaces, the surface of the dielectric layer 2' of the second semiconductor structure 1' and the third bonding pad 30' serve as bonding surfaces, and the bonding surfaces are bonded to each other, wherein the first bonding pad 30 is aligned and connected to the third bonding pad 30'.

[0071] In some embodiments, the first bonding pad 30 and the third bonding pad 30' in the first semiconductor structure 1 and the second semiconductor structure 1' are designed in mirror symmetry along the bonding surfaces.

[0072] In some embodiments, the first semiconductor structure 1 and the second semiconductor structure 1' also respectively have corresponding regions 23 and 23', and the region 23 is further provided with a bonding pad 32, which is electrically connected to a conductive pad 41 provided in the region 23, and the conductive pad 41 is also connected to the device layer 60 through a part of the interconnection structure 50. The region 23' of the second semiconductor structure 1' is provided with a bonding pad 32' corresponding to the bonding pad 32, and a conductive pad 41' electrically connected to the bonding pad 32' below the bonding pad 32', and the conductive pad 41' is connected to the device layer 60' through a part of the interconnection structure 50'. The bonding pad 32 and the bonding pad 32' are aligned and bonded.

[0073] In some embodiments, the first semiconductor structure 1 and the second semiconductor structure 1' have a bonding cavity 211 on the bonding surface, and the bonding cavity 211 is arranged between the first region 21 and the third region 21'. In some embodiments, the bonding cavity 211 can have one or more.

[0074] In some embodiments, the first semiconductor structure 1 and the second semiconductor structure 1' can be semiconductor structures of the same type, for example, both are DRAM structures. The first semiconductor structure 1 and the second semiconductor structure 1' can also be semiconductor structures of different types, for example, one of which is a semiconductor structure containing memory cells, and the other is a semiconductor structure containing logic cells.

[0075] In the semiconductor structure of the embodiments of the present disclosure, the bonding cavity caused by the cavity and the protrusion remaining on the first conductive pad is controlled in the first region, and the first bonding pad in the second region can effectively prevent the bonding cavity from extending from the first region to other regions, because the expansion amount of the first bonding pad is greater than that of the dielectric layer during the bonding process, so that the first bonding pad is also firmly connected when the dielectric layer in the first region is bonded, and the bonding strength of the first bonding pad is greater than the bonding strength between the dielectric layers, so that the extension path of the bonding cavity in the first region is controlled by the first bonding pad, so that the bonding cavity cannot extend to the third region, and cannot have adverse effects on the bonding of the third bonding pad.

[0076] To make the disclosure clearer, the following further describes the process of forming a semiconductor structure.

[0077] Please refer to FIG. 7A-7D. FIG. 7A-7D are cross-sectional views of a semiconductor device in an embodiment of the disclosure, provided in the order of formation.

[0078] In some embodiments, as shown in FIG. 7A, a substrate 10 is provided, the substrate 10 has a device layer 60 therein, the device layer 60 is provided with a semiconductor device, such as a transistor or the like. An interconnection layer 50 is provided on the device layer 60, a first dielectric layer 201 is provided on the interconnection layer 50, the first dielectric layer 201 is provided with a first conductive pad 40 and a second conductive pad 41 electrically connected with the interconnection layer 50, the first dielectric layer 201 has a void 402 therein, a portion of the surface of the first conductive pad 40 is exposed by the void 402. In some embodiments, a portion of the surface of the second conductive pad 41 can also be exposed. In some embodiments, the substrate 10 is a wafer.

[0079] Continuing to refer to FIG. 7B, after a portion of the surface of the first conductive pad 40 is exposed, a CP test is performed on the first conductive pad 40, the test is performed by a probe of a testing machine being pressed on the exposed surface of the first conductive pad 40. Since the first conductive pad 40 is softer than the probe, after the test is completed, the exposed surface of the first conductive pad 40 is damaged by the probe, forming a portion of the surface 401 that is concave or convex relative to the other portions of the surface of the first conductive pad 40 that are not damaged by the probe.

[0080] Continuing to refer to FIG. 7C, after the test is completed, a second dielectric layer 202 is formed on the first dielectric layer 201, the second dielectric layer 202 covers the portion of the surface 401 of the first conductive pad, and the surface of the second dielectric layer 202 has an uneven portion 210 that is convex or concave.

[0081] Due to the presence of the portion of the surface 401 of the first conductive pad 40, the surface of the second dielectric layer 202 formed by a thin film deposition process such as CVD also has an uneven portion 210. Generally speaking, an uneven surface of the second dielectric layer 202 is not desirable, because it can cause the risk of failure in the process steps after the formation of the second dielectric layer 202. To obtain a second dielectric layer 202 with a relatively flat surface, multiple planarization processes are required, which means that a thicker second dielectric layer needs to be deposited when performing the planarization processes. However, a thicker second dielectric layer can further amplify the height difference between the uneven portion 210 and other portions, increasing the load of the planarization processes. Unlike the prior art, in the embodiments of the disclosure, the second dielectric layer 202 is formed without the need for planarization processes such as CMP processes, so that a relatively thinner second dielectric layer 202 can be formed.

[0082] Referring to FIG. 7D, after forming the second dielectric layer 202, the first bonding pad 30 in the second region 22, the interconnection structure 321, and the third bonding pad 32 in the third region 23 are formed in the second dielectric layer 202. The process of forming the first bonding pad 30 and the third bonding pad 32 is Damascene process or a process of forming a metal interconnection structure known to those skilled in the art. In the process of forming the first bonding pad 30 and the third bonding pad 32, a deposition and planarization process of a metal film is involved. The planarization process is mainly to make the surface of the first bonding pad 30 and the third bonding pad 32 have a relatively flat surface. Therefore, after the first bonding pad 30 and the third bonding pad 32 are formed, the surface of the second dielectric layer 202 still has the uneven region 210.

[0083] In some embodiments, the bonding pad 31 connected with the first conductive pad 40 can also be formed in the first region 21 at the same time. The final structure can be referred to FIG. 4C.

[0084] In some embodiments, the second dielectric layer 202 can be a multi-layer dielectric layer structure, such as a stacked structure of silicon oxide and silicon carbon nitride. The first bonding pad 30 and the third bonding pad 32 have a part formed in the silicon oxide and a part formed in the silicon carbon nitride.

[0085] After the first bonding pad 30 and the third bonding pad 32 are formed, the surface of the semiconductor structure can be processed to form a bonding surface for bonding connection with another semiconductor structure. The structure of the semiconductor structures after bonding can be referred to FIG. 6. The bonding process is direct bonding process or hybrid bonding process. In the bonding process, the first bonding pad 30 and the third bonding pad 32 are bonded with each other, the dielectric layers in different regions are bonded with each other, and the uneven surfaces 210 are not bonded with each other, so that the bonding cavities 211 are formed on the bonding surface.

[0086] In the process of forming the semiconductor structure, the high-precision dielectric layer planarization process is not needed, which is beneficial to reduce the cost of the process.

[0087] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, comprising: A substrate having a dielectric layer covering it, the dielectric layer comprising a first region and a second region surrounding the first region; A first conductive pad is disposed in the dielectric layer in the first region, the top surface of the first conductive pad having a recessed or raised portion, and the dielectric layer covers the top surface of the first conductive pad. A first bonding pad is disposed in the dielectric layer in the second region, the first bonding pad is disposed around the first conductive pad, the first bonding pad has a top surface exposed to the dielectric layer, and the bottom surface of the first bonding pad is higher than the top surface of the first conductive pad.

2. The semiconductor structure according to claim 1, characterized in that, It also includes a second bonding pad disposed in the dielectric layer in the first region, the bottom surface of the second bonding pad being electrically connected to the top surface of the first conductive pad, the second bonding pad having a top surface exposed to the dielectric layer.

3. The semiconductor structure according to claim 1, characterized in that, The first conductive pad further includes an extension portion that extends into the dielectric layer of the second region, and the first bonding pad is disposed in the dielectric layer on the extension portion.

4. The semiconductor structure according to claim 3, characterized in that, It also includes a second bonding pad disposed in the dielectric layer in the first region, the bottom surface of the second bonding pad being electrically connected to the top surface of the first conductive pad, the second bonding pad having a top surface exposed to the dielectric layer.

5. The semiconductor structure according to claim 1, characterized in that, The substrate further includes a third region disposed outside or inside the second region, the dielectric layer covering the third region, the dielectric layer of the third region having a second conductive pad and a third bonding pad disposed therein, the bottom surface of the third bonding pad being electrically connected to the top surface of the second conductive pad, and the bottom surface of the second conductive pad and the bottom surface of the first conductive pad being coplanar, the third bonding pad having a top surface exposed to the dielectric layer.

6. The semiconductor structure according to claim 1, characterized in that, The surface of the dielectric layer in the first region has a protruding or recessed portion relative to the surface of the dielectric layer in the second region.

7. The semiconductor structure according to claim 5, characterized in that, The second region includes a plurality of uniformly distributed first bonding pads, and the third region includes a plurality of uniformly distributed third bonding pads, wherein the spacing between each first bonding pad is greater than the spacing between each third bonding pad.

8. The semiconductor structure according to claim 5, characterized in that, In a first direction, the second region includes at least one integrally connected first bonding pad, and the third region includes a plurality of spaced-apart third bonding pads.

9. The semiconductor structure according to claim 2 or 4, characterized in that, The first conductive pad includes a first portion and a second portion, with a protruding or recessed portion of the top surface of the first conductive pad located in the first portion, and the second bonding pad formed on and connected to the second portion.

10. The semiconductor structure according to claim 1, characterized in that, The first conductive pad is a test pad.

11. The semiconductor structure according to claim 5, characterized in that, The second conductive pad is a signal pad.

12. A semiconductor integrated structure, comprising a first semiconductor structure and a second semiconductor structure connected by opposing bonding surfaces, the first semiconductor structure comprising: A substrate having a dielectric layer covering it, the dielectric layer comprising a first region and a second region surrounding the first region; A first conductive pad is disposed in the dielectric layer in the first region, the top surface of the first conductive pad having a recessed or raised portion, and the dielectric layer covers the top surface of the first conductive pad. A first bonding pad is disposed in the dielectric layer in the second region, the first bonding pad is disposed around the first conductive pad, the first bonding pad has a top surface exposed to the dielectric layer, the bottom surface of the first bonding pad is higher than the top surface of the first conductive pad, and the first bonding pad exposed to the top surface of the dielectric layer and the top surface of the dielectric layer serve as the bonding surface of the first semiconductor structure. The second semiconductor structure includes: A substrate having a dielectric layer covering it, the dielectric layer including a third region and a fourth region surrounding the third region; A third conductive pad is disposed in the dielectric layer in the third region, the top surface of the third conductive pad having a recessed or raised portion, and the dielectric layer covers the top surface of the third conductive pad. A fourth bonding pad is disposed in the dielectric layer in the third region, the fourth bonding pad is disposed around the third conductive pad, the fourth bonding pad has a top surface exposed to the dielectric layer, the bottom surface of the fourth bonding pad is higher than the top surface of the third conductive pad, and the fourth bonding pad exposed to the top surface of the dielectric layer and the top surface of the dielectric layer serve as the bonding surface of the second semiconductor structure; The bonding surface of the first semiconductor structure is aligned and bonded with the bonding surface of the second semiconductor structure.

13. The integrated structure according to claim 12, characterized in that, It also includes bonding voids located between the bonding surfaces, the bonding voids being located between the top surface of the dielectric layer in the first region and the top surface of the dielectric layer in the third region.

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