Gate drive circuit and display panel

Abstract

A gate drive circuit and a display panel. The gate drive circuit comprises: an input module (110), and a first output module (120), wherein the input module (110) and a first control end of the first output module (120) are connected at a first node (N1); the input module (110) is configured to control, in response to a first clock signal (ECK1), an input signal (EIN) to be transmitted to the first node (N1); and the first output module (120) is configured to control the output of a first voltage signal (VG1) on the basis of the potential of the first node (N1).

Description

Gate drive circuit and display panel

[0001] The present application claims priority to the Chinese patent application No. 202410865635.1, filed on June 28, 2024, to the Chinese Patent Office, the whole content of the above application being incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, for example to a gate drive circuit and a display panel. BACKGROUND

[0003] With the continuous development of display technology, the application range of organic light-emitting diode display panels is becoming more and more extensive, and people's requirements for display panels are also becoming higher and higher.

[0004] However, the current organic light-emitting display products have display abnormalities, and the display effect of the display products needs to be improved. SUMMARY

[0005] The present application provides a gate drive circuit and a display panel to improve the display effect of the display panel.

[0006] According to an aspect of the present application, a gate drive circuit is provided, comprising:

[0007] an input module and a first output module, a first control end of the input module and the first output module being connected to a first node, the input module being configured to control the transmission of an input signal to the first node in response to a first clock signal; and the first output module being configured to control the output of a first voltage signal based on the potential of the first node;

[0008] a first control module and a second output module, a first control end of the first control module and the second output module being connected to a second node, the first control module being configured to control the potential of the second node based on at least the first clock signal, and the second output module being configured to control the output of a second voltage signal based on the potential of the second node.

[0009] According to another aspect of the present application, a gate drive circuit is provided, comprising:

[0010] a second control module and a first output module, a first control end of the second control module and the first output module being connected to a first node, the second control module being configured to control the potential of the first node based on at least a first clock signal; and the first output module being configured to control the output of a first voltage signal based on the potential of the first node;

[0011] A first control module and a second output module, the first control module is connected with the first control end of the second output module at a second node, the first control module is configured to control the potential of the second node based on at least the first clock signal, and the second output module is configured to control the output of the second voltage signal based on the potential of the second node.

[0012] According to another aspect of the present application, a display panel is provided, comprising a plurality of pixel circuits and a plurality of cascade-connected gate drive circuits, the gate drive circuit being the gate drive circuit according to any one of the embodiments of the present application;

[0013] The plurality of pixel circuits are arranged in an array.

[0014] Each of the gate drive circuits is connected to at least one row of the pixel circuits. BRIEF DESCRIPTION OF DRAWINGS

[0015] FIG. 1 is a structural schematic diagram of a gate drive circuit;

[0016] FIG. 2 is a structural schematic diagram of a gate drive circuit according to an embodiment of the present application;

[0017] FIG. 3 is a structural schematic diagram of another gate drive circuit according to an embodiment of the present application;

[0018] FIG. 4 is a schematic diagram of a gate drive signal;

[0019] FIG. 5 is a structural schematic diagram of another gate drive circuit according to an embodiment of the present application;

[0020] FIG. 6 is a structural schematic diagram of another gate drive circuit according to an embodiment of the present application;

[0021] FIG. 7 is a structural schematic diagram of another gate drive circuit according to an embodiment of the present application;

[0022] FIG. 8 is a structural schematic diagram of another gate drive circuit according to an embodiment of the present application;

[0023] FIG. 9 is a timing diagram corresponding to a gate drive circuit according to an embodiment of the present application;

[0024] FIG. 10 is a structural schematic diagram of another gate drive circuit according to an embodiment of the present application;

[0025] FIG. 11 is a flowchart of a driving method of a gate drive circuit according to an embodiment of the present application;

[0026] FIG. 12 is a flowchart of a driving method of another gate drive circuit according to an embodiment of the present application;

[0027] FIG. 13 is a structural schematic diagram of a display panel according to an embodiment of the present application;

[0028] Fig. 14 is a timing diagram corresponding to Fig. 13. DETAILED DESCRIPTION

[0029] The display panel includes a pixel circuit and a light emitting element. The pixel circuit is connected with the light emitting element and provides a driving current for the light emitting element so that the light emitting element emits light. The pixel circuit can be a 2T1C pixel circuit and its variants, or a 7T1C pixel circuit and its variants. The 2T1C pixel circuit includes two transistors and one storage capacitor, for example, a data writing transistor, a driving transistor and a storage capacitor. The 7T1C pixel circuit includes seven transistors and one storage capacitor, for example, a data writing transistor, a driving transistor, a threshold compensation transistor, a first initialization transistor, a second initialization transistor, a first light emitting control transistor, a second light emitting control transistor and a storage capacitor. In order to make the pixel circuit generate a driving current according to a target brightness, the on-off timing of the transistors in the pixel circuit needs to be controlled, that is, the on-off of the transistors is controlled. The gate driving circuit can output a gate driving signal and transmit the gate driving signal to the gate of the corresponding transistor, so as to control the on-off timing of the transistor, and further control the working timing of the pixel circuit, so as to control the driving current generated by the pixel circuit, so that the pixel circuit generates a driving current according to the target brightness, so that the light emitting brightness of the light emitting element is close to the target brightness.

[0030] Fig. 1 is a structural schematic diagram of a gate drive circuit. As shown in Fig. 1, the gate drive circuit comprises a first input transistor M1, a first output transistor M2, a second input transistor M3, a first control transistor M4, a first coupling capacitor C01, a second output transistor M5, a second coupling capacitor C02, a second control transistor M6, a third control transistor M7 and a third coupling capacitor C03. The first electrode of the first input transistor M1 is connected to a first signal IN, the control electrode of the first input transistor M1 is connected to a second signal CK1, the second electrode of the first input transistor M1 is connected to the control electrode of the first output transistor M2, the first electrode of the first output transistor M2 is connected to a high-level signal VGH, and the second electrode of the first output transistor M2 is an output terminal O1. The control electrode of the second input transistor M3 is connected to the first signal IN, the first electrode of the second input transistor M3 is connected to a low-level signal VGL, the second electrode of the second input transistor M3 is connected to the control electrode of the first control transistor M4, the first electrode of the first control transistor M4 is connected to a third signal CK2, the second electrode of the first control transistor M4 is connected to the control electrode of the second output transistor M5, the first electrode of the second output transistor M5 is connected to the low-level signal VGL, and the second electrode of the second output transistor M5 is the output terminal O1. The first coupling capacitor C01 is connected between the first electrode of the first control transistor M4 and the control electrode of the first control transistor M4. The second coupling capacitor C02 is connected between the first electrode of the second output transistor M5 and the control electrode of the second output transistor M5. The control electrode of the second control transistor M6 is connected to the control electrode of the second output transistor M5, the first electrode of the second control transistor M6 is connected to the low-level signal VGL, the second electrode of the second control transistor M6 is connected to the first electrode of the third control transistor M7, the second electrode of the third control transistor M7 is connected to the third signal CK2, and the control electrode of the third control transistor M7 is connected to the control electrode of the first output transistor M2. The first electrode of the third coupling capacitor C03 is connected to the first electrode of the third control transistor M7, and the second electrode of the third coupling capacitor C03 is connected to the control electrode of the first output transistor M2.

[0031] When the second signal CK1 is at a high level and the first signal IN is at a high level, the first input transistor M1 is turned on, the high level is transmitted to the gate of the first output transistor M2, the first output transistor M2 is turned on, and the high-level signal VGH is output. When the second signal CK1 is at a high level, the third signal CK3 is at a low level. Because the control electrode of the first output transistor M2 is at a high level, the second electrode of the third coupling capacitor C03 is at a high level, the third control transistor M7 is turned on, and the low level of the third signal CK3 is transmitted to the first electrode of the third coupling capacitor C03, and the first electrode of the third coupling capacitor C03 is at a low level.

[0032] When the third signal CK3 becomes high level, the first pole of the third coupling capacitor C03 is high level, and the second pole of the third coupling capacitor C03 is super high level, thereby maintaining the first output transistor M2 in conduction and continuously outputting the high level signal VGH.

[0033] When the first signal IN becomes low level, and the second signal CK1 is high level and the third signal CK3 is low level, the first input transistor M1 is turned on, the first output transistor M2 is turned off, the second input transistor M3 is turned off, the first control transistor M4 is also turned off, and the second output transistor M5 is turned off.

[0034] When the third signal CK3 becomes high level, the first control transistor M4 is controlled to be turned on through the first coupling capacitor C01, the first control transistor M4 transmits the high level of the third signal CK3 to the second output transistor M5, and the second output transistor M5 is turned on to output the low level signal VGL. At the same time, the second control transistor M6 is turned on to transmit the low level signal VGL to the third coupling capacitor C03, and the third coupling capacitor C03 transmits the low level to the control pole of the first output transistor M2 to maintain the first output transistor M2 in off state. The second coupling capacitor C02 can maintain the potential of the control pole of the second output transistor M5 to maintain the second output transistor M5 in conduction and continuously output the low level signal VGL.

[0035] Therefore, before the gate driving circuit outputs the low level signal VGL, the first output transistor M2 and the second output transistor M5 are both turned off for a period of time, which cannot better maintain the output of the gate driving circuit, resulting in that the gate driving signal generated by the gate driving circuit is floating, so that the conduction timing of the transistor in the pixel circuit cannot be accurately controlled, the driving current generated by the pixel circuit cannot be accurately controlled, and the light emitting element cannot accurately emit light according to the target brightness, so that the display effect of the display panel is poor.

[0036] Embodiments of the present application provide a gate driving circuit. FIG. 2 is a structural schematic diagram of a gate driving circuit provided by an embodiment of the present application. Referring to FIG. 2, the gate driving circuit comprises an input module 110, a first output module 120, a first control module 130 and a second output module 140. The first control end of the input module 110 and the first output module 120 is connected to a first node N1, and the input module 110 is configured to transmit an input signal EIN to the first node N1 in response to a first clock signal ECK1. The first output module 120 controls the output of a first voltage signal VG1 based on the potential of the first node N1. The first control end of the first control module 130 and the second output module 140 is connected to a second node N2, the first control module 130 controls the potential of the second node N2 based on at least the first clock signal ECK1, and the second output module 140 controls the output of a second voltage signal VG2 based on the potential of the second node N2.

[0037] The display panel where the gate drive circuit is located includes a plurality of pixel circuits and light emitting elements. The gate drive circuit is connected with the pixel circuit, and the pixel circuit is connected with the light emitting element. The output terminal Out of the gate drive circuit outputs a gate drive signal. The gate drive signal can be used to control the on-off timing of the transistor in the pixel circuit, and further control the pixel circuit to generate a drive current, so that the light emitting element emits light in response to the drive current. The first output module 120 and the second output module 140 are both connected with the output terminal Out of the gate drive circuit.

[0038] For example, the first clock signal ECK1 can include an effective level and an ineffective level. The effective level is a level for controlling the on-off of a plurality of modules, units or transistors, and the ineffective level is a level for controlling the off of a plurality of modules, units or transistors. The effective level can be a high level, and the ineffective level can be a low level. Alternatively, the effective level can be a low level, and the ineffective level can be a high level. When the first clock signal ECK1 is at the effective level, the input module 110 is turned on, and the input signal EIN is transmitted to the first control terminal (the first node N1) of the first output module 120. When the input signal EIN is at the effective level, the first output module 120 is turned on, and the first output module 120 outputs the first voltage signal VG1, so that the output terminal Out of the gate drive circuit is at the first voltage signal VG1. For example, when the first voltage signal VG1 is at the effective level, the corresponding transistor in the pixel circuit can be turned on.

[0039] When the first clock signal ECK1 is at the active level, the input module 110 is turned on, and if the input signal EIN jumps to the inactive level, the potential of the first node N1 is at the inactive level, and the first output module 120 is turned off. At the same time, the first control module 130 controls the potential of the second node N2 to be at the active level based on the first clock signal ECK1, so that the second output module 140 is turned on, and the second output module 140 outputs the second voltage signal VG2. For example, the second voltage signal VG2 is at the inactive level, which can control the corresponding transistor in the pixel circuit to be turned off. By setting the first control module 130 to control the potential of the second control end N2 based on the first clock signal ECK1, the second output module 140 can be turned on immediately after the first output module 120 is turned off, thereby outputting the second voltage signal VG2. Therefore, the potentials of the first node N1 and the second node N2 can be controlled based on the first clock signal ECK1, that is, the first output module 120 and the second output module 140 can be controlled based on the first clock signal ECK1. After the first output module 120 is controlled to be turned off based on the first clock signal ECK1, the second output module 140 can be controlled to be turned on immediately based on the first clock signal ECK1, thereby outputting the second voltage signal VG2. In this way, the situation that the second output module 140 is also turned off after the first output module 120 is turned off, resulting in that the output signal of the gate driving circuit cannot be maintained well, is avoided. Therefore, there is no situation that the first output module 120 and the second output module 140 are turned off at the same time, that is, after the output active level reaches the required time length, the inactive level can be output immediately, avoiding the floating of the gate driving signal output by the gate driving circuit, ensuring the stability of the gate driving signal, and reliably and stably controlling the turn-on timing of the transistor in the pixel circuit, thereby accurately controlling the driving current of the pixel circuit, so that the luminous brightness of the light emitting element is closer to the target brightness, and further the display panel can stably and accurately display the picture, which is beneficial to improving the display effect of the display panel.

[0040] The technical scheme of the embodiment can be that the input module can transmit the input signal to the first node in response to the first clock signal, control the turn-on or turn-off of the first output module, and the first output module can output the first voltage signal when turned on. The first control module can control the potential of the second node based on the first clock signal, thereby controlling the turn-on or turn-off of the second output module. Therefore, the potentials of the first node and the second node can be controlled based on the first clock signal, and after the first output module is controlled to be turned off based on the first clock signal, the second output module can be controlled to be turned on immediately based on the first clock signal, thereby outputting the second voltage signal. In this way, the situation that the first output module and the second output module are turned off at the same time is avoided, that is, after the output valid level reaches the required time length, the invalid level can be output immediately, the floating of the gate drive signal output by the gate drive circuit is avoided, the stability of the gate drive signal is ensured, the turn-on timing of the transistor in the pixel circuit can be reliably and stably controlled, the driving current of the pixel circuit is accurately controlled, the luminance of the light emitting element is closer to the target luminance, and the display panel stably and accurately displays the picture, which is beneficial to improving the display effect of the display panel.

[0041] On the basis of the above technical scheme, optionally, the first control module 130 controls the potential of the second node N2 based on the input signal EIN, the second voltage signal VG2 and the first clock signal ECK1.

[0042] For example, when the input signal EIN is a valid level, the first control module 130 controls the potential of the second node N2 to be an invalid level based on the second voltage signal VG2, so that the second output module 140 is turned off, thereby ensuring that the first output module 120 is turned on and the second output module 140 is turned off, and avoiding signal disorder of the output end Out of the gate drive circuit. When the first clock signal ECK1 is a valid level, the first control module 130 controls the potential of the second node N2 to be a valid level based on the first clock signal ECK1, so that the second output module 140 is turned on and the second output module 140 outputs the second voltage signal VG2. In this way, the first control module 130 can control the potential of the second node N2 based on the input signal EIN, the second voltage signal VG2 and the first clock signal ECK1, thereby controlling the output of the second output module 140.

[0043] On the basis of the above technical scheme, optionally, the first control module 130 is configured to, after the input signal EIN jumps from the first level to the second level, control the potential of the second node N2 to be the first level when the first clock signal ECK1 jumps from the second level to the first level, so that the second output module 140 is turned on and outputs the second voltage signal VG2.

[0044] For example, the first level is an effective level, and the second level is an ineffective level. When the input signal EIN is the first level, the first output module 120 can be controlled to be turned on and output the first voltage signal VG1. After the input signal EIN jumps from the first level to the second level, when the first clock signal ECK1 jumps from the second level to the first level, that is, the first clock signal ECK1 becomes the effective level, the first control module 130 can control the potential of the second node N2 to be the first level, that is, the potential of the second node N2 is the effective level, so that the second output module 140 is turned on and outputs the second voltage signal VG2. In this way, after the input signal EIN jumps from the first level to the second level, as long as the first clock signal ECK1 jumps from the second level to the first level, the second output module 140 can be immediately controlled to be turned on and output the second voltage signal VG2, avoiding the case that after the first output module 120 is turned off, the second output module 140 is also turned off, resulting in that the output signal of the gate driving circuit cannot be maintained well. Therefore, there is no case that the first output module 120 and the second output module 140 are turned off at the same time, that is, after the output effective level reaches the required time length, the ineffective level can be immediately output, avoiding the floating of the gate driving signal output by the gate driving circuit.

[0045] Optionally, the first level is the same as the first voltage signal VG1, and the second level is the same as the second voltage signal VG2. In this way, the first level and the first voltage signal VG1 are effective levels, and the second level and the second voltage signal VG2 are effective levels. When the first output module 120 is controlled to be turned on based on the first level of the first clock signal ECK1, the first output module 120 can output the first voltage signal VG1, that is, an effective level that can drive the transistor in the pixel circuit to be turned on. When the second output module 140 is controlled to be turned on based on the first level of the first clock signal ECK1, the second output module 140 can output the second voltage signal VG2, that is, an ineffective level that can drive the transistor in the pixel circuit to be turned off. In this way, a complete gate driving signal can be output, which can drive the transistor in the pixel circuit to be turned on or turned off, and control the conduction timing of the transistor in the pixel circuit.

[0046] Optionally, the first voltage signal VG1 is greater than the second voltage signal VG2. In this way, the first level is greater than the second level, that is, the first level is a high level and the second level is a low level. The first output module 120 can be turned on in response to the higher first level, so as to output the higher effective level first voltage signal VG1. The second output module 140 can be turned on in response to the higher first level, so as to output the lower ineffective level second voltage signal VG2. In this way, the output of the gate driving signal is realized, and the control of the timing of the pixel circuit is realized.

[0047] On the basis of the above-mentioned multiple technical solutions, the following describes modules that the gate drive circuit can also have, but does not limit the present application.

[0048] FIG. 3 is a structural schematic diagram of another gate drive circuit provided by an embodiment of the present application. Optionally, referring to FIG. 3, the gate drive circuit further includes a second control module 150, which is electrically connected with the first node N1. During the period when the first output module 120 outputs the first voltage signal VG1, the second control module 150 at least stably maintains the potential of the first node N1 based on the first clock signal ECK1, so as to avoid fluctuation of the potential of the first node N1, and achieve the effect of stable output of the first output module 120.

[0049] Optionally, during the period when the first output module 120 outputs the first voltage signal VG1, the absolute value of the potential of the first node N1 is greater than the absolute value of the effective level of the input signal EIN, thereby improving the ability of the first output module 120 to output the first voltage signal VG1. For example, taking the first output module 120 as an N-type transistor, the effective level of the input signal EIN is high, and the first voltage signal VG1 is also high. During the period when the first output module 120 outputs the first voltage signal VG1, the potential of the first node N1 is greater than the effective level of the input signal EIN, that is, the potential of the first node N1 is higher than the high level of the input signal EIN, thereby improving the ability of the N-type transistor to output the high level.

[0050] For example, the second control module 150 is configured to perform coupling control on the potential of the first node N1 based on the jump of the second level of the second clock signal ECK2 to the first level according to the first clock signal ECK1, the second clock signal ECK2 and the input signal EIN, so that the first output module 120 outputs the first voltage signal VG1.

[0051] For example, when the input signal EIN is at a valid level, the valid level is transmitted to the first node N1. When the first clock signal ECK1 is at a valid level, the input signal EIN can be transmitted to the first node N1. When the second level (invalid level) of the second clock signal ECK2 jumps to the first level (valid level), the potential of the first node N1 is coupled and controlled so that the potential of the first node N1 continues to change in the direction of the valid level and becomes a more valid level, which can better control the conduction of the first output module 120, so that the first output module 120 is fully turned on, and the first voltage signal VG1 is better output, that is, the output first voltage signal VG1 is more complete, so that the output gate drive signal can better control the conduction or turn-off of the transistor in the pixel circuit. For example, when the valid level is a low level, the potential of the first node N1 can be coupled and controlled to a super low level; when the valid level is a high level, the potential of the first node N1 can be coupled and controlled to a super high level.

[0052] Optionally, the waveform of the second clock signal ECK2 is the same as the waveform of the first clock signal ECK1. That is, the duty cycle of the first clock signal ECK1 is the same as that of the second clock signal ECK2, that is, in one period, the time length of the valid level of the first clock signal ECK1 and the second clock signal ECK2 is the same.

[0053] Optionally, the period of the second clock signal ECK2 is the same as the period of the first clock signal ECK1. For example, the period of the first clock signal ECK1 and the second clock signal ECK2 is two row times, and the row time is related to the refresh frequency and resolution of the display panel, that is, the row time can be calculated according to the refresh frequency and resolution.

[0054] Optionally, the waveform of the second clock signal ECK2 is delayed relative to the waveform of the first clock signal ECK1. In this way, when the first clock signal ECK1 is at a valid level, the second clock signal ECK2 is at an invalid level, and when the second clock signal ECK2 is at a valid level, the first clock signal ECK1 is at an invalid level. The first clock signal ECK1 and the second clock signal ECK2 cannot be at a valid level at the same time, so that each module can be accurately controlled to avoid control disorder.

[0055] Optionally, the waveform of the second clock signal ECK2 is half a period later than the waveform of the first clock signal ECK1. In this way, when the first clock signal ECK1 just controls the input module 110 to be turned on, the second clock signal ECK2 is at an invalid level and cannot couple and control the potential of the first node N1 to be a more valid level, and the input signal EIN at a valid level also cannot control the first output module 120 to be fully turned on, so that the first output module 120 can be shifted relative to the input signal EIN, so that the gate drive circuit can shift and output the input signal EIN.

[0056] And, the technical scheme of the embodiment, the first control module 130 controls the potential of the second node N2 based on the first clock signal ECK1, which can immediately control the second output module 140 to be turned on after the input signal EIN becomes invalid level. If the potential of the second node N2 is controlled based on the third signal CK2 (the second clock signal ECK2) in FIG. 1, the second output module 140 can be controlled to be turned on after a preset time delay after the input signal EIN becomes invalid level, and the first output module 120 and the second output module 140 are turned off at the same time. Therefore, the technical scheme of the embodiment can avoid the situation that the first output module 120 and the second output module 140 are turned off at the same time, and can avoid the floating of the gate drive signal.

[0057] Optionally, the duration of the active level in the first clock signal ECK1 is less than or equal to half a period; and optionally, the duration of the active level in the second clock signal ECK2 is less than or equal to half a period. In this way, the opening time of the first clock signal ECK1 can be ensured not to be too long, and the opening time of the second clock signal ECK2 can be ensured not to be too long, so that there can be a blank area between the active level of the first clock signal ECK1 and the second clock signal ECK2, which can avoid multiple modules from responding to the active level of the first clock signal ECK1 and the second clock signal ECK2 at the same time, and is beneficial to ensure the accuracy of control.

[0058] Optionally, the second control module 150 is configured to transmit the first level of the input signal EIN to the third node N3 of the second control module 150 when the first clock signal ECK1 is at the first level, and couple the potential of the third node N3 when the second clock signal ECK2 jumps from the second level to the first level, and transmit the coupled potential to the first node N1.

[0059] For example, when the first clock signal ECK1 is at the first level, the second control module 150 transmits the first level of the input signal EIN to the third node N3, so that the potential of the third node N3 is at the first level. When the second clock signal ECK2 jumps from the second level to the first level, the second control module 150 couples the potential of the third node N3, so that the potential of the third node N3 further changes in the direction of the first level, i.e. the potential of the third node N3 becomes a super-low level or a super-high level.

[0060] The third node N3 is coupled by the second control module 150 to transmit the coupled potential of the third node N3 to the first node N1, so that the potential of the first node N1 is further changed to the direction of the first level, and becomes the super low level or the super high level, that is, becomes the more effective level, so that it can be guaranteed that the first output module 120 can be completely opened, and it is beneficial to guarantee that the first output module 120 outputs the first voltage signal VG1.

[0061] Optionally, with reference to FIG. 3, the second control module 150 comprises: an input unit 151, a first control unit 152, a coupling unit 153, and a switching unit 154.

[0062] The control end of the input unit 151 is connected with the first clock signal ECK1, the first end of the input unit 151 is connected with the input signal EIN, and the second end of the input unit 151 is connected with the third node N3. The input unit 151 is configured to transmit the first level of the input signal EIN to the third node N3 when the first clock signal ECK1 is the first level; wherein the third node N3 is the first end of the coupling unit 153.

[0063] The control end of the first control unit 152 is connected with the third node N3, the first end of the first control unit 152 is connected with the second clock signal ECK2, and the second end of the first control unit 152 is connected with the second end of the coupling unit 153 at the fourth node N4. The first end of the coupling unit 153 is connected with the third node N3. The first control unit 152 is configured to couple the potential of the third node N3 when the second clock signal ECK2 jumps from the second level to the first level.

[0064] The control end of the switching unit 154 and the first end of the switching unit 154 are both connected with the third node N3, the second end of the switching unit 154 is connected with the first node N1, and the switching unit 154 is configured to transmit the coupled potential of the third node N3 to the first node N1 when the potential difference between the first node N1 and the third node N3 meets the conduction condition of the switching unit 154.

[0065] For example, when the first clock signal ECK1 is at the first level, the input unit 151 transmits the first level of the input signal EIN to the third node N3, i.e., to the first end of the coupling unit 153, at which time the first control unit 152 is turned on. When the second clock signal ECK2 jumps from the second level to the first level, the first control unit 152 transmits the first level to the second end of the coupling unit 153, so that the potential of the second end (the fourth node N4) of the coupling unit 153 changes. Since the charge stored by the coupling unit 153 does not change, i.e., the voltage difference across the coupling unit 153 does not change, when the potential of the second end (the fourth node N4) of the coupling unit 153 changes to the first level, the first end of the coupling unit 153 changes in the direction of the first level and becomes a more effective level.

[0066] For example, when the first level is low, the potential of the second end N4 of the coupling unit 153 changes to low, and since the voltage difference across the coupling unit 153 does not change, the first end of the coupling unit 153 further decreases and becomes an ultra-low level. When the first level is high, the potential of the second end N4 of the coupling unit 153 changes to high, and since the voltage difference across the coupling unit 153 does not change, the first end (the third node N3) of the coupling unit 153 further increases and becomes an ultra-high level.

[0067] When the potential of the third node N3 is at a level lower or higher than the first level (an ultra-high level or an ultra-low level) and the potential of the second node N2 is at the first level, the potential difference between the first node N1 and the third node N3 satisfies the turn-on condition of the switching unit 154, the switching unit 154 is turned on, and the switching unit 154 transmits the potential (an ultra-high level or an ultra-low level) of the third node N3 after coupling to the second node N2, so that the potential of the first node N1 becomes a more effective level (an ultra-high level or an ultra-low level), thereby ensuring that the first output module 120 is fully turned on.

[0068] After the second clock signal ECK2 changes to the second level, the potential of the third node N3 changes in the direction of the second level, and the potential difference between the first node N1 and the third node N3 does not satisfy the turn-on condition of the switching unit 154, so the switching unit 154 will not be turned on. The potential of the first node N1 maintains an ultra-high level or an ultra-low level, so that after the potential of the first node N1 becomes an ultra-high or ultra-low level, it will not change due to the jump of the second clock signal ECK2, thereby ensuring the stable conduction of the first output module 120 and further ensuring the stability of the gate drive signal. In the gate drive circuit shown in FIG. 1, the ultra-high level of the second pole of the third coupling capacitor C03 changes due to the jump of the third signal CK2, causing fluctuations in the gate drive signal output by the gate drive circuit.

[0069] For example, FIG. 4 is a schematic diagram of a gate drive signal. As shown in FIG. 4, based on the first clock signal ECK1 (the second signal CK1 in FIG. 1) and the second clock signal ECK2 (the third signal CK2 in FIG. 1), the active level of the output first gate drive signal V0 fluctuates, while the active level of the second gate drive signal V1 generated by the gate drive circuit of the embodiment remains stable. Therefore, the gate drive circuit of the embodiment can generate a stable gate drive signal, thereby ensuring stable control of the transistor in the pixel circuit.

[0070] FIG. 4 shows a case of generating a gate drive signal by the gate drive circuit, and does not limit the timing of the gate drive circuit.

[0071] Based on the technical solutions described above, FIG. 5 is a structural schematic diagram of another gate drive circuit provided by the embodiment of the application. Optionally, referring to FIG. 5, the second control module 150 further includes a second control unit 155, a control end of the second control unit 155 being connected with the second node N2, a first end of the second control unit 155 being connected with the second voltage signal VG2, and a second end of the second control unit 155 being connected with the second end of the coupling unit 153 to the fourth node N4. The second control unit 155 is configured to, when the potential of the second node N2 is the first level, transmit the second voltage signal VG2 to the fourth node N4.

[0072] For example, when the potential of the second node N2 is the active level, the second control unit 155 is turned on to transmit the second voltage signal VG2 to the second end (the fourth node N4) of the coupling unit 153, which can ensure that the first end of the coupling unit 153 is the active level or the inactive level, avoid the opening of the switching unit 154, and avoid the transmission of the active level to the first node N1, thereby ensuring that the potential of the first node N1 is the inactive level when the potential of the second node N2 is the active level.

[0073] Based on the technical solutions described above, the first output module 120 includes a second control end, the second control end of the first output module 120 being connected with the third voltage signal VG3, the first end of the first output module 120 being connected with the first voltage signal VG1, and the second end of the first output module 120 being connected with the output end Out of the gate drive circuit. In this way, the threshold voltage of the first output module 120 can be adjusted, the leakage current of the first output module 120 when turned off can be reduced, the power consumption can be reduced, and the first output module 120 can be ensured to maintain the off state when turned off. In this way, when the second output module 140 outputs the second voltage signal VG2, the first output module 120 is not completely turned off, the first output module 120 and the second output module 140 are turned on at different times, and the gate drive signal output includes the first voltage signal VG1 and the second voltage signal VG2.

[0074] Optionally, referring to FIG. 5, the first output module 120 comprises a first double-gate transistor T1; a first gate of the first double-gate transistor T1 is connected with the first node N1, a second gate of the first double-gate transistor T1 is connected with the third voltage signal VG3, a first pole of the first double-gate transistor T1 is connected with the first voltage signal VG1, and a second pole of the first double-gate transistor T1 is connected with the output end Out of the gate drive circuit.

[0075] The second output module 140 comprises a second double-gate transistor T2; a first gate of the second double-gate transistor T2 is connected with the second node N2, a second gate of the second double-gate transistor T2 is connected with the third voltage signal VG3, a first pole of the second double-gate transistor T2 is connected with the second voltage signal VG2, and a second pole of the second double-gate transistor T2 is connected with the output end Out of the gate drive circuit.

[0076] The first gate of the first double-gate transistor T1 can be a top gate, and the second gate of the first double-gate transistor T1 can be a bottom gate; the first gate of the second double-gate transistor T2 can be a top gate, and the second gate of the second double-gate transistor T2 can be a bottom gate. Alternatively, the first gate of the first double-gate transistor T1 can be a bottom gate, and the second gate of the first double-gate transistor T1 can be a top gate; the first gate of the second double-gate transistor T2 can be a bottom gate, and the second gate of the second double-gate transistor T2 can be a top gate.

[0077] For example, by connecting the second gate of the first double-gate transistor T1 and the second gate of the second double-gate transistor T2 with the third voltage signal VG3, the threshold voltage of the first double-gate transistor T1 and the second double-gate transistor T2 can be adjusted, so as to avoid large leakage current of the first double-gate transistor T1 and the second double-gate transistor T2 when they are turned off, reduce power consumption, and ensure that the first double-gate transistor T1 and the second double-gate transistor T2 can maintain the off state when they are turned off. In this way, the second double-gate transistor T2 is not completely turned off when the first double-gate transistor T1 outputs the first voltage signal VG1, and the first double-gate transistor T1 is not completely turned off when the second double-gate transistor T2 outputs the second voltage signal VG2, so that the first double-gate transistor T1 and the second double-gate transistor T2 are turned on at different times, and the gate drive signal output comprises the first voltage signal VG1 and the second voltage signal VG2.

[0078] For example, when the first double-gate transistor T1 is an N-type transistor, the third voltage signal VG3 is at a low level (e.g., less than 0) to lower the voltage at the second gate of the first double-gate transistor T1, so as to make the threshold voltage of the first double-gate transistor T1 positive-biased. In this case, the threshold voltage of the first double-gate transistor T1 is positively biased more, and the voltage at the first gate of the first double-gate transistor T1 does not need to be biased too negatively to turn off the first double-gate transistor T1. In this way, the threshold voltage of the first double-gate transistor T1 can be adjusted to ensure that the first double-gate transistor T1 is turned off. Similarly, when the second double-gate transistor T2 is an N-type transistor, the third voltage signal VG3 is at a low level (e.g., less than 0) to make the threshold voltage of the second double-gate transistor T2 positive-biased, so as to ensure that the second double-gate transistor T2 is turned off. In this way, the leakage current of the first double-gate transistor T1 and the second double-gate transistor T2 when turned off can be reduced. Similarly, when the first double-gate transistor T1 and the second double-gate transistor T2 are P-type transistors, the third voltage signal VG3 is at a high level (e.g., greater than 0) to make the threshold voltage of the first double-gate transistor T1 and the second double-gate transistor T2 negative-biased, so as to ensure that the first double-gate transistor T1 and the second double-gate transistor T2 are turned off, and the leakage current of the first double-gate transistor T1 and the second double-gate transistor T2 when turned off can be reduced.

[0079] Optionally, the third voltage signal VG3 is less than the second voltage signal VG2.

[0080] For example, the first double-gate transistor T1 and the second double-gate transistor T2 are N-type transistors. The second voltage signal VG2 is at a low level, and the third voltage signal VG3 is at a level lower than the second voltage signal VG2. In this way, when the first gate (the first node N1) of the first double-gate transistor T1 is at a low level and the first double-gate transistor T1 is turned off, a lower low level can be provided for the second gate of the first double-gate transistor T1, so as to make the threshold voltage of the first double-gate transistor T1 positive-biased, and ensure that the low level of the first node N1 maintains the turn-off of the first double-gate transistor T1. Similarly, the threshold voltage of the second double-gate transistor T2 can be adjusted to ensure that the second double-gate transistor T2 is turned off.

[0081] Based on the above technical solutions, FIG. 6 is a structural schematic diagram of another gate drive circuit provided by an embodiment of the present application. Optionally, referring to FIG. 6, the gate drive circuit further includes an adjusting module 160.

[0082] The first end of the adjusting module 160 accesses a third voltage signal VG3, the second end of the adjusting module 160 is connected to an eighth node N8 with the second control end of the first output module 120, the third end of the adjusting module 160 accesses a first control signal K1, the fourth end of the adjusting module 160 accesses a first clock signal ECK1, and the fifth end of the adjusting module 160 accesses a second clock signal ECK2; the adjusting module 160 is configured to adjust the voltage of the eighth node N8 (the second gate of the first double-gate transistor T1) based on the second clock signal ECK2 in response to the first control signal K1; and / or the adjusting module 160 is configured to adjust the voltage of the eighth node N8 (the second gate of the first double-gate transistor T1) based on the third voltage signal VG3 in response to the first clock signal ECK1. Optionally, the first control signal K1 is the same as the potential of the first node N1.

[0083] For example, when the potential of the first node N1 is an effective level, the first double-gate transistor T1 is turned on, and the adjusting module 160 adjusts the voltage of the second gate (the eighth node N8) of the first double-gate transistor T1 based on the effective level of the second clock signal ECK2 in response to the potential of the first node N1 (the first control signal K1). For example, the first double-gate transistor T1 is an N-type transistor, and the effective level is a high level, so that the voltage of the second gate (the eighth node N8) of the first double-gate transistor T1 can be raised, the threshold voltage of the first double-gate transistor T1 is more negative, the current of the first double-gate transistor T1 is larger when the voltage of the first gate of the first double-gate transistor T1 is unchanged, and the driving capability of the first double-gate transistor T1 is improved, so that the first voltage signal VG1 is better output, and the stability of the effective level of the output gate drive signal is ensured.

[0084] In addition, when the potential of the first node N1 is an ineffective level, the first double-gate transistor T1 is turned off, and the adjusting module 160 transmits the third voltage signal VG3 to the second gate of the first double-gate transistor T1 in response to the first clock signal ECK1, so that the threshold voltage of the first double-gate transistor T1 is positive, and the turn-off of the first double-gate transistor T1 can be ensured.

[0085] Optionally, referring to FIG. 6, the adjusting module 160 includes a third transistor T3, a fourth transistor T4 and a first capacitor C1.

[0086] The control electrode of the third transistor T3 accesses the first clock signal ECK1, the first electrode of the third transistor T3 accesses the third voltage signal VG3, and the second electrode of the third transistor T3 is connected to the eighth node N8.

[0087] The control electrode of the fourth transistor T4 is connected to the first control signal K1, the first electrode of the fourth transistor T4 is connected to the second clock signal ECK2, the second electrode of the fourth transistor T4 is connected to the first electrode of the first capacitor C1, and the second electrode of the first capacitor C1 is connected to the eighth node N8.

[0088] For example, when the potential of the first node N1 is a valid level, the first control signal K1 is a valid level, and the fourth transistor T4 is turned on. When the second clock signal ECK2 is a valid level, the first clock signal ECK1 is an invalid level, the third transistor T3 is not turned on, and the fourth transistor T4 transmits the valid level of the second clock signal ECK2 to the second gate of the first double-gate transistor T1 through the first capacitor C1, so that the potential of the second gate of the first double-gate transistor T1 is raised, the threshold voltage of the first double-gate transistor T1 is adjusted, and the driving capability of the first double-gate transistor T1 is improved. When the potential of the first node N1 is an invalid level, the first control signal K1 is an invalid level, and the fourth transistor T4 is turned off. When the first clock signal ECK1 is a valid level, the third transistor T3 is turned on, and the third transistor T3 transmits the third voltage signal VG3 to the second gate of the first double-gate transistor T1, so as to adjust the threshold voltage of the first double-gate transistor T1, ensure the turn-off of the first double-gate transistor T1, reduce the leakage current of the first double-gate transistor T1, and reduce the power consumption.

[0089] Based on the technical scheme, FIG. 7 is a structural schematic diagram of another gate drive circuit provided by the embodiment of the present application. Optionally, referring to FIG. 7, the gate drive circuit further comprises a node mutual control module 170, the node mutual control module 170 is connected to the first node N1 and the second node N2 respectively, and the node mutual control module 170 is configured to transmit the second voltage signal VG2 to the second node N2 in response to the potential of the first node N1.

[0090] For example, when the potential of the first node N1 is a first level, the first output module 120 is turned on to output the first voltage signal VG1, and at the same time, the node mutual control module 170 is turned on to transmit the second voltage signal VG2 to the second node N2, so that the potential of the second node N2 is an invalid level and the second output module 140 is turned off. In this way, the potentials of the first node N1 and the second node N2 are mutually controlled, the first output module 120 and the second output module 140 are alternately turned on, and the output state of the gate drive circuit is ensured to be accurate.

[0091] Based on the technical scheme, the specific structures of each module and unit are described below, but are not regarded as a limitation to the present application.

[0092] FIG. 8 is a structural schematic diagram of another gate drive circuit provided by the embodiment of the present application. Optionally, referring to FIG. 8, the input module 110 comprises a fifth transistor T5.

[0093] The control electrode of the fifth transistor T5 is connected to the first clock signal ECK1, the first electrode of the fifth transistor T5 is connected to the input signal EIN, and the second electrode of the fifth transistor T5 is connected to the first node N1. In this way, when the first clock signal ECK1 is at the active level, the fifth transistor T5 is turned on, and the input signal EIN can be transmitted to the first node N1.

[0094] Optionally, the first control module 130 comprises a sixth transistor T6, a seventh transistor T7 and a second capacitor C2.

[0095] The control electrode of the sixth transistor T6 is connected to the input signal EIN, the first electrode of the sixth transistor T6 is connected to the second voltage signal VG2, the second electrode of the sixth transistor T6 is connected to the control electrode of the seventh transistor T7, the first electrode of the seventh transistor T7 is connected to the first clock signal ECK1, and the second electrode of the seventh transistor T7 is connected to the second node N2.

[0096] The second capacitor C2 is connected between the control electrode of the seventh transistor T7 and the first electrode of the seventh transistor T7.

[0097] For example, when the input signal EIN is at the active level, the sixth transistor T6 is turned on, the second voltage signal VG2 (inactive level) is transmitted to the control electrode of the seventh transistor T7, so that the seventh transistor T7 is turned off, the potential of the second node N2 is set to the inactive level by the node mutual control module 170, and the second output module 140 is turned off. When the input signal EIN is at the inactive level, the sixth transistor T6 is turned off. When the first clock signal ECK1 is at the active level, the active level of the first clock signal ECK1 is transmitted to the control electrode of the seventh transistor T7 through the second capacitor C2, the seventh transistor T7 is turned on, the active level of the first clock signal ECK1 is transmitted to the second node N2, the potential of the second node N2 is at the active level, and the second output module 140 is turned on and outputs the second voltage signal VG2. In this way, after the input signal EIN jumps to the inactive level (the second level), when the first clock signal ECK1 jumps to the active level (the first level), the second output module 140 can be controlled to be turned on immediately.

[0098] Optionally, referring to FIG. 8, the input unit 151 comprises an eighth transistor T8 and a ninth transistor T9. The control electrode of the eighth transistor T8 is connected to the first clock signal ECK1, and the first electrode of the eighth transistor T8 is connected to the input signal EIN. The control electrode of the ninth transistor T9 is connected to the first voltage signal VG1, the first electrode of the ninth transistor T9 is electrically connected to the second electrode of the eighth transistor T8 at the seventh node N7, and the second electrode of the ninth transistor T9 is electrically connected to the third node N3. By arranging the eighth transistor T8, when the first clock signal ECK1 is at the first level, the eighth transistor T8 is turned on, and the input signal EIN can be transmitted to the third node N3. By arranging the ninth transistor T9, the control electrode of the ninth transistor T9 is connected to the first voltage signal VG1, so that the ninth transistor T9 is always open. When the third node N3 is at a more valid level (ultra-low level or ultra-high level), the voltage of the third node N3 can be prevented from being transmitted to the eighth transistor T8, thereby avoiding damage to the eighth transistor T8.

[0099] The first control unit 152 comprises a tenth transistor T10. The control electrode of the tenth transistor T10 is connected to the third node N3, the first electrode of the tenth transistor T10 is connected to the second clock signal ECK2, and the second electrode of the tenth transistor T10 is connected to the second end of the coupling unit 153.

[0100] For example, when the first clock signal ECK1 is at the valid level and the second clock signal ECK2 is at the invalid level, the eighth transistor T8 is turned on, and the valid level of the input signal EIN is transmitted to the third node N3, so that the tenth transistor T10 is turned on, and the tenth transistor T10 transmits the invalid level of the second clock signal ECK2 to the second end of the coupling unit 153. After the potential of the second clock signal ECK2 jumps to the valid level, the potential of the second end of the coupling unit 153 becomes the valid level, the charge stored in the coupling unit 153 does not change, the potential of the first end of the coupling unit 153 becomes the more valid level, and the more valid level is transmitted to the first node N1 through the switching unit 154, so that the first output module 120 is completely turned on.

[0101] The coupling unit 153 comprises a third capacitor C3. The first electrode of the third capacitor C3 is the first end of the coupling unit 153, and the second electrode of the third capacitor C3 is the second end of the coupling unit 153. The eighth transistor T8 transmits the valid level of the input signal EIN to the first electrode of the third capacitor C3, and the tenth transistor T10 transmits the invalid level of the second clock signal ECK2 to the second electrode of the third capacitor C3. After the potential of the second clock signal ECK2 jumps to the valid level, the potential of the second electrode (the fourth node N4) of the third capacitor C3 becomes the valid level, the charge stored in the third capacitor C3 does not change, and the potential of the first electrode (the third node N3) of the third capacitor C3 becomes the more valid level.

[0102] The switch unit 154 includes an eleventh transistor T11, the control electrode of the eleventh transistor T11 is connected to the third node N3, the first electrode of the eleventh transistor T11 is connected to the third node N3, and the second electrode of the eleventh transistor T11 is connected to the first node N1. When the potential of the third node N3 becomes a more valid level (an ultra-high level or an ultra-low level), the potential of the first node N1 is a valid level, the potential difference between the first node N1 and the third node N3 meets the conduction condition of the eleventh transistor T11, and the eleventh transistor T11 transmits the more valid level of the third node N3 to the first node N1. When the second clock signal ECK2 jumps from a valid level to an invalid level, the potential of the second electrode of the third capacitor C3 becomes an invalid level, the potential of the third node N3 becomes a valid level, and the potential of the first node N1 is a more valid level, the potential difference between the first node N1 and the third node N3 does not meet the conduction condition of the eleventh transistor T11, and the potential of the third node N3 cannot be transmitted to the first node N1. In this way, after the potential of the first node N1 becomes a more valid level, it will not change due to the jump of the second clock signal ECK2, which can ensure the stable conduction of the first output module 120, and further ensure that the gate drive signal output by the gate drive circuit is more stable.

[0103] Optionally, referring to FIG. 8, the second control unit 155 includes a twelfth transistor T12, the control electrode of the twelfth transistor T12 is connected to the second node N2, the first electrode of the twelfth transistor T12 is connected to the second voltage signal VG2, and the second electrode of the twelfth transistor T12 is connected to the second end of the coupling unit 153. When the potential of the second node N2 is a valid level, the twelfth transistor T12 is turned on to transmit the second voltage signal VG2 to the second end of the coupling unit 153, so that the first end of the coupling unit 153 is a valid level or an invalid level, the switch unit 154 is prevented from being turned on, and the valid level is prevented from being transmitted to the first node N1, thereby ensuring that when the potential of the second node N2 is a valid level, the potential of the first node N1 is an invalid level.

[0104] Optionally, referring to FIG. 8, the node mutual control module 170 includes a thirteenth transistor T13, the control electrode of the thirteenth transistor T13 is connected to the first node N1, the first electrode of the thirteenth transistor T13 is connected to the second voltage signal VG2, and the second electrode of the thirteenth transistor T13 is connected to the second node N2. When the first node N1 is a valid level, the thirteenth transistor T13 is turned on to transmit the second voltage signal VG2 to the second node N2, so that the second node N2 is an invalid level.

[0105] Optionally, referring to FIG. 8, the gate drive circuit further comprises a protection module 180 connected between the input module 110 and the first node N1, and a control end of the protection module 180 is connected to the first voltage signal VG1. The first voltage signal VG1 can control the protection module 180 to be turned on, and the protection module 180 is in a normally open state. When the potential of the first node N1 is a more effective level, the protection module 180 avoids transmitting the more effective level to the input module 110, thereby achieving the effect of protecting the input module 110.

[0106] Optionally, the protection module 180 comprises a fourteenth transistor T14, a first electrode of the fourteenth transistor T14 is connected to the first node N1, a second electrode of the fourteenth transistor T14 is connected to the input module 110 and the fifth node N5, and a control electrode of the fourteenth transistor T14 is connected to the first voltage signal VG1. The first voltage signal VG1 can control the fourteenth transistor T14 to be in a normally open state. When the fourteenth transistor T14 is an N-type transistor, the potential of the second electrode (for example, the drain electrode) of the fourteenth transistor T14 will not be higher than the potential of the first electrode (for example, the source electrode) of the fourteenth transistor T14. In this way, when the potential of the first node N1 is a more effective level (an ultrahigh level), the protection module 180 avoids transmitting the more effective level (the ultrahigh level) to the input module 110, thereby avoiding damaging the input module 110. When the fourteenth transistor T14 is a P-type transistor, the potential of the second electrode of the fourteenth transistor T14 will not be lower than the potential of the first electrode of the fourteenth transistor T14. In this way, when the potential of the first node N1 is a more effective level (an ultralow level), the protection module 180 avoids transmitting the more effective level (the ultralow level) to the input module 110, thereby avoiding damaging the input module 110.

[0107] Optionally, referring to FIG. 8, the gate drive circuit further comprises a maintenance module 190, a first end of the maintenance module 190 is connected to the second node N2, a second end of the maintenance module 190 is connected to the second voltage signal VG2, and the maintenance module 190 is configured to maintain the potential of the second node N2. Because the potential of the second end of the maintenance module 190 is the second voltage signal VG2, that is, the potential of the second end of the maintenance module 190 is a fixed potential, the potential of the first end of the maintenance module 190 is unchanged, thereby maintaining the potential of the second node N2.

[0108] Optionally, the maintenance module 190 comprises a fourth capacitor C4, a first electrode of the fourth capacitor C4 is electrically connected to the second node N2, and a second electrode of the fourth capacitor C4 is connected to the second voltage signal VG2. The fourth capacitor C4 can maintain the potential of the second node N2, thereby ensuring that the second output module 140 can continuously output the second voltage signal VG2.

[0109] The working timing of the gate drive circuit is described below in combination with a timing diagram of the working of the gate drive circuit, but is not intended to limit the present application.

[0110] FIG. 9 is a timing diagram corresponding to the gate drive circuit according to an embodiment of the present application. Optionally, referring to FIGS. 8 and 9, the working process of the gate drive circuit includes the following stages.

[0111] In the first stage t0, the input signal EIN is at low level, and when the first clock signal ECK1 is at high level, the fifth transistor T5 is turned on to transmit the low level of the input signal EIN to the second electrode (the fifth node N5) of the fifth transistor T5 and the first node N1, so that the first double-gate transistor T1 is turned off. The high level of the first clock signal ECK1 is coupled to the control electrode (the sixth node N6) of the seventh transistor T7 through the second capacitor C2, so that the seventh transistor T7 is turned on to transmit the high level of the first clock signal ECK1 to the second node N2, so that the second double-gate transistor T2 is turned on to output the second voltage signal VG2. In addition, the fourth capacitor C4 can maintain the potential VN2 of the second node N2, thereby maintaining the on state of the second double-gate transistor T2 to continuously output the second voltage signal VG2. In FIG. 9, the case where the second voltage signal VG2 is at low level is illustrated, but this is not limiting. The potential of the control electrode (the sixth node N6) of the seventh transistor T7 changes with the first clock signal ECK1.

[0112] In the second stage t1, the first clock signal ECK1 is at high level, the second clock signal ECK2 is at low level, and the input signal EIN is at high level. The fifth transistor T5 is turned on, the potential VN5 of the second electrode N5 of the fifth transistor T5 and the potential VN1 of the first node N1 are at high level, and the first double-gate transistor T1 is turned on, but the first double-gate transistor T1 is not completely turned on, so that the gate drive signal Vout output by the output end Out of the gate drive circuit is smaller than the expected high level.

[0113] At the same time, the sixth transistor T6 is turned on to transmit the second voltage signal VG2 to the control electrode N6 of the seventh transistor T7, the potential VN6 of the control electrode (the sixth node N6) of the seventh transistor T7 is at low level, and the seventh transistor T7 is turned off. The potential VN5 of the second electrode (the fifth node N5) of the fifth transistor T5 is at high level, so that the thirteenth transistor T13 is turned on to transmit the second voltage signal VG2 to the second node N2, so that the second double-gate transistor T2 is turned off.

[0114] Meanwhile, the eighth transistor T8 and the ninth transistor T9 are turned on, the eighth transistor T8 and the ninth transistor T9 transmit the high level of the input signal EIN to the third node N3, the potential of the third node N3 is high, i.e. the potential of the first pole of the third capacitor C3 is high. Then the tenth transistor T10 is turned on, transmits the low level of the second clock signal ECK2 to the second pole N4 of the third capacitor C3, the potential VN4 of the second pole (the fourth node N4) of the third capacitor C3 is low.

[0115] In the third stage t2, the first clock signal ECK1 is low, the second clock signal ECK2 is high, and the input signal EIN is high. The tenth transistor T10 is turned on, transmits the high level of the second clock signal ECK2 to the second pole of the third capacitor C3, the potential VN4 of the second pole (the fourth node N4) of the third capacitor C3 is high, the stored charge of the third capacitor C3 is unchanged, and the potential VN3 of the first pole (the third node) N3 of the third capacitor C3 becomes super high. The potential of the control pole of the eleventh transistor T11 is super high, the potential of the second pole (the first node N1) of the eleventh transistor T11 is high, the eleventh transistor T11 is turned on, transmits the super high level of the third node N3 to the first node N1, thereby controlling the first double-gate transistor T1 to be completely opened, outputting the first voltage signal VG1, at this time, the output gate drive signal is effective, thereby realizing the shift output of the input signal EIN.

[0116] And the input signal EIN is high, the sixth transistor T6 is turned on, transmits the second voltage signal VG2 to the sixth node N6, and the seventh transistor T7 is turned off. The potential VN5 of the fifth node N5 is high, the thirteenth transistor T13 is turned on, transmits the second voltage signal VG2 to the second node N2, so that the second double-gate transistor T2 is turned off.

[0117] In the fourth stage t3, the input signal EIN is high level, the second clock signal ECK2 is high level, and the first clock signal ECK1 is low level. When the second clock signal ECK2 becomes low level, the potential VN4 of the second pole (the fourth node N4) of the third capacitor C3 becomes low level, the potential VN3 of the first pole (the third node) N3 of the third capacitor C3 becomes high level, i.e. the potential of the control pole of the eleventh transistor T11 becomes high level, the potential of the second pole of the eleventh transistor T11 is super high level, the eleventh transistor T11 is not conductive, so that the high level of the third node N3 cannot be transmitted to the first node N1, and the potential VN1 of the first node N1 is maintained as super high level, so as to maintain the complete conduction of the first double-gate transistor T1 and ensure the stability of the output gate drive signal Vout. Therefore, in the fourth stage t3, the potential VN3 of the first pole (the third node) N3 of the third capacitor C3 and the potential VN4 of the second pole (the fourth node N4) of the third capacitor C3 change with the change of the second clock signal ECK2, and the potential VN1 of the first node N1 remains unchanged.

[0118] And the input signal EIN is high level, the sixth transistor T6 is conductive, the second voltage signal VG2 is transmitted to the sixth node N6, and the seventh transistor T7 is turned off. The potential VN5 of the fifth node N5 is high level, so that the thirteenth transistor T13 is conductive, the second voltage signal VG2 is transmitted to the second node N2, and the second double-gate transistor T2 is turned off.

[0119] In the fifth stage t4, the input signal EIN is low level, the first clock signal ECK1 is low level, and the second clock signal ECK2 is high level. The fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are not conductive. The potential VN4 of the second pole (the fourth node N4) of the third capacitor C3 is high level, the potential VN3 of the first pole (the third node) N3 of the third capacitor C3 is super high level, and the potential VN1 of the first node N1 is maintained as super high level, so as to maintain the complete conduction of the first double-gate transistor T1, continue to output the first voltage signal VG1, and realize the shift output of the input signal EIN.

[0120] And the potential VN5 of the fifth node N5 is high level, so that the thirteenth transistor T13 is conductive, the second voltage signal VG2 is transmitted to the second node N2, and the second double-gate transistor T2 is turned off.

[0121] In the sixth stage t5, the input signal EIN is at a low level, the first clock signal ECK1 is at a high level, and the second clock signal ECK2 is at a low level. The fifth transistor T5 is turned on, and the fifth transistor T5 transmits the low level of the input signal EIN to the fifth node N5, the fifth node N5 is at a low level, and the first node N1 is at a low level, so the first double-gate transistor T1 is turned off. The sixth transistor T6 is not turned on, the high level of the first clock signal ECK1 is coupled to the control electrode (the sixth node N6) of the seventh transistor T7 through the second capacitor C2, the potential VN6 of the control electrode N6 of the seventh transistor T7 is at a high level, the seventh transistor T7 is turned on, and the high level of the first clock signal ECK1 is transmitted to the second node N2, so the potential VN2 of the second node N2 is at a high level, the second double-gate transistor T2 is turned on, and the second voltage signal VG2 is output. The fourth capacitor C4 can maintain the potential VN2 of the second node N2, so that the second double-gate transistor T2 is continuously turned on, and the second voltage signal VG2 is continuously output, so that the gate drive signal Vout includes alternating high and low levels. In this way, after the first double-gate transistor T1 is turned off, the second double-gate transistor T2 can be immediately turned on, avoiding the case that the first double-gate transistor T1 and the second double-gate transistor T2 are both turned off, so that the stability and reliability of the output of the gate drive signal Vout can be ensured.

[0122] The transistors in FIGS. 5 to 8 of the embodiment are taken as N-type transistors for illustration, but are not limited thereto, in some other embodiments, the transistors in the gate drive circuit can all be P-type transistors, or part of the transistors can be N-type transistors and the other part can be P-type transistors, which are not limited by the embodiment. Correspondingly, in FIG. 9, a high level is taken as an effective level for illustration, that is, a case where a plurality of transistors are turned on in response to a high level is taken for illustration, but is not limited thereto.

[0123] The embodiment of the present application further provides a gate drive circuit, and FIG. 10 is a structural schematic diagram of another gate drive circuit provided by the embodiment of the present application, referring to FIG. 10, the gate drive circuit comprises:

[0124] The second control module 150 and the first output module 120, the first control end of the second control module 150 and the first output module 120 is connected to the first node N1, and the second control module 150 controls the potential of the first node N1 based on at least the first clock signal ECK1; the first output module 120 controls the output of the first voltage signal VG1 based on the potential of the first node N1;

[0125] The first control module 130 and the second output module 140, the first control end of the first control module 130 and the second output module 140 is connected to the second node N2, the first control module 130 controls the potential of the second node N2 based on at least the first clock signal ECK1, and the second output module 140 controls the output of the second voltage signal VG2 based on the potential of the second node N2.

[0126] Wherein, during the first output module 120 outputs the first voltage signal VG1, the second control module 150 stably maintains the potential of the first node N1 based on at least the first clock signal ECK1, avoids the potential of the first node N1 from fluctuating, and achieves the output of the first output module 120.

[0127] For example, when the first clock signal ECK1 is an effective level, the second control module 150 can control the potential of the first node N1 to be an effective level or a more effective level (an ultrahigh level or an ultralow level), so as to ensure that the first output module 120 can be completely opened, and to facilitate ensuring that the first output module 120 outputs the first voltage signal VG1.

[0128] If the input signal EIN is an invalid level, when the first clock signal ECK1 is an effective level, the first control module 130 controls the potential of the second node N2 to be an effective level based on the first clock signal ECK1, so that the second output module 140 is turned on, and the second output module 140 outputs the second voltage signal VG2.

[0129] Therefore, the potentials of the first node N1 and the second node N2 can be controlled based on the first clock signal ECK1, that is, the first output module 120 and the second output module 140 can be controlled based on the first clock signal ECK1. After the first output module 120 is controlled to be turned off based on the first clock signal ECK1, the second output module 140 can be controlled to be turned on immediately based on the first clock signal ECK1, so as to output the second voltage signal VG2. In this way, the situation that the second output module 140 is also turned off after the first output module 120 is turned off, resulting in that the output signal of the gate driving circuit cannot be maintained well, is avoided. Therefore, there is no situation that the first output module 120 and the second output module 140 are turned off at the same time, that is, after the output valid level reaches the required time length, the invalid level can be output immediately, so as to avoid the floating of the gate driving signal output by the gate driving circuit, ensure the stability of the gate driving signal, reliably and stably control the turn-on timing of the transistor in the pixel circuit, so as to accurately control the driving current of the pixel circuit, so that the luminance of the light emitting element is closer to the target luminance, and then the display panel stably and accurately displays the picture, which is beneficial to improving the display effect of the display panel. The remaining structures and working principles of the gate driving circuit are the same as those of the above-described gate driving circuit (any one of the gate driving circuits shown in FIGS. 3, 5 to 8), which will not be described here again.

[0130] The embodiment of the present application also provides a driving method of a gate driving circuit, which is used for driving the gate driving circuit provided by any one of the embodiments of the present application. FIG. 11 is a flow chart of the driving method of the gate driving circuit provided by the embodiment of the present application. Referring to FIG. 11, the driving method of the gate driving circuit comprises the following steps.

[0131] In S101, the input module controls the input signal to be transmitted to the first node in response to the first clock signal, and the first control module is closed based on at least the first clock signal; the second output module is closed in response to the potential of the second node, and the first output module controls the output of the first voltage signal based on the potential of the first node.

[0132] For example, as shown in FIG. 1, when the first clock signal ECK1 is a valid level, the input module 110 is turned on to transmit the input signal EIN to the first control end (the first node N1) of the first output module 120. When the input signal EIN is a valid level, the first output module 120 is turned on, and the first output module 120 outputs the first voltage signal VG1, so that the output end Out of the gate driving circuit is the first voltage signal VG1, for example, the first voltage signal VG1 is a valid level, so as to control the corresponding transistor in the pixel circuit to be turned on.

[0133] And, when the first clock signal ECK1 is at the active level, the first control module 130 is off, and the first control module 130 cannot control the potential of the second node N2 to be at the active level, and the second output module 140 is off, thereby ensuring that the gate drive circuit outputs one level signal at the same time.

[0134] S102, the input module transmits the input signal to the first node in response to the first clock signal, and the first control module transmits an active level to the second node based on at least the first clock signal; the first output module is off in response to the potential of the first node, and the second output module controls the output of the second voltage signal based on the potential of the second node.

[0135] For example, as shown in FIG. 1, when the first clock signal ECK1 is at the active level, the input module 110 is on, and if the input signal EIN jumps to the inactive level, the input module 110 transmits the low level of the input signal EIN to the first node N1, and the potential of the first node N1 is at the inactive level, and the first output module 120 is off. At the same time, the first control module 130 transmits an active level to the potential of the second node N2 based on at least the first clock signal ECK1, so that the second output module 140 is on, and the second output module 140 outputs the second voltage signal VG2. For example, the second voltage signal VG2 is at the inactive level, which can control the corresponding transistor in the pixel circuit to be off.

[0136] Therefore, by setting the first control module 130 to control the potential of the second control end N2 based on the first clock signal ECK1, the second output module 140 can be immediately turned on after the first output module 120 is turned off, thereby outputting the second voltage signal VG2. Therefore, the potentials of the first node N1 and the second node N2 can be controlled based on the first clock signal ECK1, that is, the first output module 120 and the second output module 140 can be controlled based on the first clock signal ECK1. After the first output module 120 is controlled to be off based on the first clock signal ECK1, the second output module 140 can be immediately turned on based on the first clock signal ECK1, thereby outputting the second voltage signal VG2.

[0137] In this way, the second output module 140 is prevented from being turned off after the first output module 120 is turned off, so that the output signal of the gate drive circuit cannot be maintained well. Therefore, the first output module 120 and the second output module 140 are not turned off at the same time, that is, the invalid level can be output immediately after the output valid level reaches the required time length, so that the gate drive signal output by the gate drive circuit is prevented from floating, the stability of the gate drive signal is ensured, the on timing of the transistor in the pixel circuit can be reliably and stably controlled, the driving current of the pixel circuit is accurately controlled, the luminance of the light emitting element is closer to the target luminance, and the display panel can stably and accurately display the picture, which is beneficial to improving the display effect of the display panel.

[0138] The embodiment of the present application further provides another driving method of a gate drive circuit, which is used for driving the gate drive circuit provided by any of the embodiments of the present application. FIG. 12 is a flowchart of the driving method of another gate drive circuit provided by the embodiment of the present application. Referring to FIG. 12, the driving method of the gate drive circuit comprises the following steps.

[0139] In S201, the second control module adjusts the potential of the first node based on at least the first clock signal, and the first control module is closed based on at least the first clock signal; the second output module is closed in response to the potential of the second node, and the first output module controls the output of the first voltage signal based on the potential of the first node.

[0140] For example, as shown in FIG. 10, when the first clock signal ECK1 is a valid level, the second control module 150 can adjust the potential of the first node N1 to a valid level or a more valid level (an ultrahigh level or an ultralow level), so as to ensure that the first output module 120 can be completely opened, and the output of the first voltage signal VG1 by the first output module 120 is facilitated.

[0141] When the first clock signal ECK1 is a valid level, the first control module 130 can be closed based on the first clock signal ECK1, so that the first control module 130 cannot control the potential of the second node N2 to be a valid level, and the second output module 140 is turned off, so as to ensure that the gate drive circuit outputs only one level signal at the same time.

[0142] In S202, the first control module transmits a valid level to the second node based on at least the first clock signal, and the second control module is closed based on at least the first clock signal; the first output module is closed in response to the potential of the first node, and the second output module controls the output of the second voltage signal based on the potential of the second node.

[0143] For example, as shown in FIG. 10, when the second control module 150 is closed based on at least the first clock signal ECK1, the potential of the first node N1 cannot be adjusted, so that the first output module 110 is closed.

[0144] If the input signal EIN is the invalid level and the first clock signal ECK1 is the valid level, the first control module 130 can transmit the valid level to the second node N2 based on the first clock signal ECK1, so that the second output module 140 is turned on, and the second output module 140 outputs the second voltage signal VG2. In this way, the second output module 140 can immediately output the second voltage signal VG2 when the first output module 110 is turned off.

[0145] The driving method of the embodiment can drive the gate drive circuit of any of the embodiments of the present application, and thus has the same effect as the gate drive circuit of any of the embodiments of the present application, which will not be repeated here. The embodiment of the present application also provides a display panel. FIG. 13 is a structural schematic diagram of a display panel provided by an embodiment of the present application. Referring to FIG. 13, the display panel includes a plurality of cascaded gate drive circuits, and the gate drive circuit is the gate drive circuit provided by any of the embodiments of the present application. The display panel includes, for example, a plurality of gate drive circuits 10 provided by any of the embodiments of the present application, and the plurality of gate drive circuits 10 are cascaded, and the input signal EIN of the nth-stage gate drive circuit 10 is provided by the output signal of the output terminal Out of the (n-1)th-stage gate drive circuit 10, where n is a positive integer greater than or equal to 2. The input signal EIN of the first-stage gate drive circuit 10 can be provided by an external device. The display panel can be, for example, a display panel on a mobile phone, a tablet, a Moving Picture Experts Group Audio Layer III (MP3), a Moving Picture Experts Group 4 (MP4), a smart watch, a smart helmet, or other wearable devices, etc. Since the display panel of the embodiment includes the gate drive circuit provided by any of the above embodiments, the display panel of the embodiment has the same effect as the gate drive circuit provided by any of the above embodiments, which will not be repeated here.

[0146] For example, as shown in FIG. 13, the display panel further includes a first clock signal line CLK1 and a second clock signal line CLK2, the first clock signal line CLK1 is configured to provide the first clock signal ECK1 to the mth-stage gate drive circuit 10, and the second clock signal line CLK2 is configured to provide the second clock signal ECK2 to the mth-stage gate drive circuit 10; the first clock signal line CLK1 is configured to provide the second clock signal ECK2 to the (m+1)th-stage gate drive circuit 10, and the second clock signal line CLK2 is configured to provide the first clock signal ECK1 to the (m+1)th-stage gate drive circuit 10. Wherein, m is a positive integer greater than or equal to 1, and m is an odd number.

[0147] Optionally, the display panel further comprises a plurality of pixel circuits 20 arranged in an array, and each stage of the gate driving circuit 10 is connected to at least one row of the pixel circuits 20. In this way, the gate driving signal output by each stage of the gate driving circuit 10 can be transmitted to at least one row of the pixel circuits 20 to control the timing of the at least one row of the pixel circuits 20.

[0148] Optionally, each stage of the gate driving circuit 10 is connected to one row of the pixel circuits 20.

[0149] For example, as shown in FIG. 13, the display panel further comprises a plurality of pixel circuits 20 arranged in an array, and the output terminal Out of each stage of the gate driving circuit is connected to one row of the pixel circuits 20 to control the transistors in the pixel circuits 20, thereby controlling the light emitting timing or light emitting duration of the light emitting device corresponding to the pixel circuits 20.

[0150] FIG. 14 is a timing diagram corresponding to FIG. 13. As shown in FIG. 14, the first stage of the gate driving signal Vout(1) output by the first stage of the gate driving circuit is shifted by half a clock period relative to the input signal EIN, the second stage of the gate driving signal Vout(2) output by the second stage of the gate driving circuit is shifted by half a clock period relative to the first stage of the gate driving signal Vout(1), the third stage of the gate driving signal Vout(3) output by the third stage of the gate driving circuit is shifted by half a clock period relative to the second stage of the gate driving signal Vout(2), and the fourth stage of the gate driving signal Vout(4) output by the fourth stage of the gate driving circuit is shifted by half a clock period relative to the third stage of the gate driving signal Vout(3). In this way, the output of the multi-stage gate driving signal is realized, and the output gate signal is only shifted relative to the input signal, and the waveform does not change, and better driving of each row of the pixel circuits 20 can be achieved. The output gate signal is shifted by half a clock period, i.e., one row time, relative to the input signal, thereby facilitating the row-by-row control of the pixel circuits 20 and facilitating the row-by-row lighting of the light emitting device. Four gate driving signals are taken as an example for illustration in FIG. 14, but the number of the gate driving signals output by the display panel is not limited.

[0151] It should be understood that the above-mentioned various forms of flow can be reordered, added or deleted. For example, the steps described in the present application can be executed in parallel or in sequence or in different orders, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0152] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A gate driving circuit, comprising: An input module and a first output module are provided, wherein the first control terminal of the input module and the first output module are connected to a first node, and the input module is configured to control the transmission of an input signal to the first node in response to a first clock signal. The first output module is configured to output a first voltage signal based on the potential control of the first node; A first control module and a second output module are connected at their first control terminals to a second node. The first control module is configured to control the potential of the second node based at least on the first clock signal, and the second output module is configured to control the output of a second voltage signal based on the potential of the second node.

2. The gate driving circuit according to claim 1, wherein, The first control module is configured to respond to the input signal changing from a first level to a second level and the first clock signal changing from a second level to a first level, control the potential of the second node to the first level, so that the second output module is turned on and outputs the second voltage signal.

3. The gate driving circuit according to claim 1 further includes: A second control module is electrically connected to the first node. The second control module is configured to stably maintain the potential of the first node at least based on the first clock signal during the period when the first output module outputs the first voltage signal. Alternatively, the second control module is configured to couple and control the potential of the first node based on the first clock signal, the second clock signal, and the input signal, and based on the transition from the second level to the first level of the second clock signal, so that the first output module outputs the first voltage signal; Alternatively, the second control module is configured to transmit the first level of the input signal to the third node of the second control module in response to the first clock signal being at the first level, and to couple the potential of the third node to the first node in response to the second clock signal changing from the second level to the first level, and transmit the coupled potential to the first node.

4. The gate driving circuit according to claim 3, wherein, The second control module includes: an input unit, a first control unit, a coupling unit, and a switching unit; The control terminal of the input unit is connected to the first clock signal, the first terminal of the input unit is connected to the input signal, the second terminal of the input unit is connected to the third node, and the input unit is configured to respond to the first clock signal at a first level and transmit the first level of the input signal to the third node. The control terminal of the first control unit is connected to the third node, the first terminal of the first control unit is connected to the second clock signal, the second terminal of the first control unit is connected to the second terminal of the coupling unit to the fourth node, the first terminal of the coupling unit is connected to the third node, and the first control unit is configured to couple the potential of the third node in response to the second clock signal changing from the second level to the first level. The control terminal and the first terminal of the switching unit are both connected to the third node, and the second terminal of the switching unit is connected to the first node. The switching unit is configured to transmit the potential of the third node to the first node in response to the potential difference between the first node and the third node satisfying the conduction condition of the switching unit. The input unit includes an eighth transistor and a ninth transistor. The control electrode of the eighth transistor is connected to the first clock signal, the first electrode of the eighth transistor is connected to the input signal, the control electrode of the ninth transistor is connected to the first voltage signal, the first electrode of the ninth transistor and the second electrode of the eighth transistor are electrically connected to the seventh node, and the second electrode of the ninth transistor is electrically connected to the third node. The first control unit includes a tenth transistor, the control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is connected to the second clock signal, and the second electrode of the tenth transistor is connected to the second terminal of the coupling unit to the fourth node; The coupling unit includes a third capacitor, the first terminal of the third capacitor is the first end of the coupling unit, and the second terminal of the third capacitor is the second end of the coupling unit. The switching unit includes an eleventh transistor, the control electrode of the eleventh transistor is electrically connected to the third node, the first electrode of the eleventh transistor is electrically connected to the third node, and the second electrode of the eleventh transistor is electrically connected to the first node. The second control module further includes a second control unit. The control terminal of the second control unit is connected to the second node. The first terminal of the second control unit is connected to the second voltage signal. The second terminal of the second control unit is connected to the second terminal of the coupling unit to the fourth node. The second control unit is configured to transmit the second voltage signal to the fourth node in response to the potential of the second node being at a first level. The second control unit includes a twelfth transistor, the control electrode of which is electrically connected to the second node, the first electrode of which is connected to the second voltage signal, and the second electrode of which is connected to the second end of the coupling unit to the fourth node.

5. The gate driving circuit according to claim 1, wherein, The first output module includes a second control terminal, the second control terminal of the first output module is connected to a third voltage signal, the first terminal of the first output module is connected to the first voltage signal, and the second terminal of the first output module is connected to the output terminal of the gate driving circuit. The first output module includes a first dual-gate transistor; The first gate of the first dual-gate transistor is connected to the first node, the second gate of the first dual-gate transistor is connected to the third voltage signal, the first terminal of the first dual-gate transistor is connected to the first voltage signal, and the second terminal of the first dual-gate transistor is connected to the output terminal of the gate driving circuit. The second output module includes a second dual-gate transistor; The first gate of the second dual-gate transistor is connected to the second node, the second gate of the second dual-gate transistor is connected to the third voltage signal, the first terminal of the second dual-gate transistor is connected to the second voltage signal, and the second terminal of the second dual-gate transistor is connected to the output terminal of the gate driving circuit. The third voltage signal is less than the second voltage signal.

6. The gate drive circuit according to claim 5 further includes an adjustment module; The first terminal of the adjustment module is connected to the third voltage signal, the second terminal of the adjustment module is connected to the eighth node along with the second control terminal of the first output module, the third terminal of the adjustment module is connected to the first control signal, the fourth terminal of the adjustment module is connected to the first clock signal, and the fifth terminal of the adjustment module is connected to the second clock signal. The adjustment module is configured to: adjust the voltage of the eighth node based on the second clock signal in response to the first control signal, or adjust the voltage of the eighth node based on the third voltage signal in response to the first clock signal; The first control signal is at the same potential as the first node.

7. The gate driving circuit according to claim 6, wherein, The adjustment module includes a third transistor, a fourth transistor, and a first capacitor; The control electrode of the third transistor is connected to the first clock signal, the first electrode of the third transistor is connected to the third voltage signal, and the second electrode of the third transistor is connected to the eighth node; The control electrode of the fourth transistor is connected to the first control signal, the first electrode of the fourth transistor is connected to the second clock signal, the second electrode of the fourth transistor is connected to the first electrode of the first capacitor, and the second electrode of the first capacitor is connected to the eighth node.

8. The gate driving circuit according to claim 1, further comprising: The node interconnection module is connected to the first node and the second node respectively, and is configured to transmit the second voltage signal to the second node in response to the potential of the first node; The node mutual control module includes a thirteenth transistor. The control electrode of the thirteenth transistor is connected to the first node, the first electrode of the thirteenth transistor is connected to a second voltage signal, and the second electrode of the thirteenth transistor is connected to the second node.

9. The gate driving circuit according to claim 1, wherein, The input module includes a fifth transistor; the control electrode of the fifth transistor is connected to the first clock signal, the first electrode of the fifth transistor is connected to the input signal, and the second electrode of the fifth transistor is connected to the first node; The first control module includes a sixth transistor, a seventh transistor, and a second capacitor; The control electrode of the sixth transistor is connected to the input signal, the first electrode of the sixth transistor is connected to the second voltage signal, the second electrode of the sixth transistor and the control electrode of the seventh transistor are connected to the sixth node, the first electrode of the seventh transistor is connected to the first clock signal, and the second electrode of the seventh transistor is connected to the second node; The second capacitor is connected between the control electrode of the seventh transistor and the first electrode of the seventh transistor.

10. The gate drive circuit according to claim 1, further comprising a protection module and a maintenance module; The protection module is connected between the input module and the first node, and the control terminal of the protection module is connected to the first voltage signal; The protection module includes a fourteenth transistor, the first terminal of which is connected to the first node, the second terminal of which is connected to the input module at the fifth node, and the control terminal of which is connected to a first voltage signal. The first end of the sustaining module is connected to the second node, the second end of the sustaining module is connected to the second voltage signal, and the sustaining module is configured to maintain the potential of the second node; The sustaining module includes a fourth capacitor, the first terminal of which is electrically connected to the second node, and the second terminal of which is connected to the second voltage signal.

11. A gate driving circuit, comprising: A second control module and a first output module, wherein the second control module is connected to the first control terminal of the first output module at the first node, and the second control module is configured to control the potential of the first node based at least on a first clock signal; The first output module is configured to output a first voltage signal based on the potential control of the first node; A first control module and a second output module are connected at their first control terminals to a second node. The first control module is configured to control the potential of the second node based at least on the first clock signal, and the second output module is configured to control the output of a second voltage signal based on the potential of the second node.

12. The gate driving circuit according to claim 11, wherein, The second control module is configured to maintain the potential of the first node stably based on at least the first clock signal during the period when the first output module outputs the first voltage signal; Alternatively, the second control module is configured to couple and control the potential of the first node based on the first clock signal, the second clock signal, and the input signal, and based on the transition from the second level to the first level of the second clock signal, so that the first output module outputs the first voltage signal; Alternatively, the second control module is configured to transmit the first level of the input signal to the third node of the second control module in response to the first clock signal being at the first level, and to couple the potential of the third node to the first node in response to the second clock signal changing from the second level to the first level, and transmit the coupled potential to the first node.

13. The gate driving circuit according to claim 11, wherein, The first control module is configured to respond to the input signal changing from a first level to a second level and the first clock signal changing from a second level to a first level, control the potential of the second node to the first level, so that the second output module is turned on and outputs the second voltage signal.

14. The gate driving circuit according to claim 11, wherein, The second control module includes: an input unit, a first control unit, a coupling unit, and a switching unit; The control terminal of the input unit is connected to the first clock signal, the first terminal of the input unit is connected to the input signal, the second terminal of the input unit is connected to the third node, and the input unit is configured to respond to the first clock signal at a first level and transmit the first level of the input signal to the third node. The control terminal of the first control unit is connected to the third node, the first terminal of the first control unit is connected to the second clock signal, the second terminal of the first control unit is connected to the second terminal of the coupling unit to the fourth node, the first terminal of the coupling unit is connected to the third node, and the first control unit is configured to couple the potential of the third node in response to the second clock signal changing from the second level to the first level. The control terminal and the first terminal of the switching unit are both connected to the third node, and the second terminal of the switching unit is connected to the first node. The switching unit is configured to transmit the potential of the third node to the first node in response to the potential difference between the first node and the third node satisfying the conduction condition of the switching unit. The input unit includes an eighth transistor and a ninth transistor. The control electrode of the eighth transistor is connected to the first clock signal, the first electrode of the eighth transistor is connected to the input signal, the control electrode of the ninth transistor is connected to the first voltage signal, the first electrode of the ninth transistor and the second electrode of the eighth transistor are electrically connected to the seventh node, and the second electrode of the ninth transistor is electrically connected to the third node. The first control unit includes a tenth transistor, the control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is connected to the second clock signal, and the second electrode of the tenth transistor is connected to the second terminal of the coupling unit to the fourth node; The coupling unit includes a third capacitor, the first terminal of the third capacitor is the first end of the coupling unit, and the second terminal of the third capacitor is the second end of the coupling unit. The switching unit includes an eleventh transistor, the control electrode of the eleventh transistor is electrically connected to the third node, the first electrode of the eleventh transistor is electrically connected to the third node, and the second electrode of the eleventh transistor is electrically connected to the first node. The second control module further includes a second control unit. The control terminal of the second control unit is connected to the second node. The first terminal of the second control unit is connected to the second voltage signal. The second terminal of the second control unit is connected to the second terminal of the coupling unit to the fourth node. The second control unit is configured to transmit the second voltage signal to the fourth node in response to the potential of the second node being at a first level. The second control unit includes a twelfth transistor, the control electrode of which is electrically connected to the second node, the first electrode of which is connected to the second voltage signal, and the second electrode of which is connected to the second end of the coupling unit to the fourth node.

15. The gate drive circuit according to claim 11, wherein, The first output module includes a second control terminal, the second control terminal of the first output module is connected to a third voltage signal, the first terminal of the first output module is connected to the first voltage signal, and the second terminal of the first output module is connected to the output terminal of the gate driving circuit. The first output module includes a first dual-gate transistor; The first gate of the first dual-gate transistor is connected to the first node, the second gate of the first dual-gate transistor is connected to the third voltage signal, the first terminal of the first dual-gate transistor is connected to the first voltage signal, and the second terminal of the first dual-gate transistor is connected to the output terminal of the gate driving circuit. The second output module includes a second dual-gate transistor; The first gate of the second dual-gate transistor is connected to the second node, the second gate of the second dual-gate transistor is connected to the third voltage signal, the first terminal of the second dual-gate transistor is connected to the second voltage signal, and the second terminal of the second dual-gate transistor is connected to the output terminal of the gate driving circuit. The third voltage signal is less than the second voltage signal.

16. The gate drive circuit according to claim 15 further includes an adjustment module; The first terminal of the adjustment module is connected to the third voltage signal, the second terminal of the adjustment module is connected to the eighth node along with the second control terminal of the first output module, the third terminal of the adjustment module is connected to the first control signal, the fourth terminal of the adjustment module is connected to the first clock signal, and the fifth terminal of the adjustment module is connected to the second clock signal. The adjustment module is configured to: adjust the voltage of the eighth node based on the second clock signal in response to the first control signal, or adjust the voltage of the eighth node based on the third voltage signal in response to the first clock signal; The first control signal is at the same potential as the first node.

17. The gate drive circuit according to claim 16, wherein, The adjustment module includes a third transistor, a fourth transistor, and a first capacitor; The control electrode of the third transistor is connected to the first clock signal, the first electrode of the third transistor is connected to the third voltage signal, and the second electrode of the third transistor is connected to the eighth node; The control electrode of the fourth transistor is connected to the first control signal, the first electrode of the fourth transistor is connected to the second clock signal, the second electrode of the fourth transistor is connected to the first electrode of the first capacitor, and the second electrode of the first capacitor is connected to the eighth node.

18. The gate driving circuit according to claim 11, further comprising: The node interconnection module is connected to the first node and the second node respectively, and is configured to transmit the second voltage signal to the second node in response to the potential of the first node; The node mutual control module includes a thirteenth transistor. The control electrode of the thirteenth transistor is connected to the first node, the first electrode of the thirteenth transistor is connected to a second voltage signal, and the second electrode of the thirteenth transistor is connected to the second node.

19. The gate drive circuit according to claim 12, wherein, The input module includes a fifth transistor; The control electrode of the fifth transistor is connected to the first clock signal, the first electrode of the fifth transistor is connected to the input signal, and the second electrode of the fifth transistor is connected to the first node; The first control module includes a sixth transistor, a seventh transistor, and a second capacitor; The control electrode of the sixth transistor is connected to the input signal, the first electrode of the sixth transistor is connected to the second voltage signal, the second electrode of the sixth transistor and the control electrode of the seventh transistor are connected to the sixth node, the first electrode of the seventh transistor is connected to the first clock signal, and the second electrode of the seventh transistor is connected to the second node; The second capacitor is connected between the control electrode of the seventh transistor and the first electrode of the seventh transistor; The gate drive circuit further includes a protection module, which is connected between the input module and the first node, and the control terminal of the protection module is connected to a first voltage signal. The protection module includes a fourteenth transistor, the first terminal of which is connected to the first node, the second terminal of which is connected to the input module at the fifth node, and the control terminal of which is connected to a first voltage signal. The gate drive circuit further includes a sustaining module, a first terminal of which is connected to the second node, and a second terminal of which is connected to the second voltage signal. The sustaining module is configured to maintain the potential of the second node. The sustaining module includes a fourth capacitor, the first terminal of which is electrically connected to the second node, and the second terminal of which is connected to the second voltage signal.

20. A display panel, comprising: Multiple pixel circuits and multiple cascaded gate drive circuits; The gate driving circuit is the gate driving circuit according to any one of claims 1-19, and the plurality of pixel circuits are arranged in an array, with each level of the gate driving circuit connected to at least one row of pixel circuits.

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