Chip package structure and radio frequency front-end module

Abstract

Provided in the present application are a chip package structure and a radio frequency front-end module. The chip package structure comprises a substrate, a solder mask layer, a filter chip, a first barrier portion, a molding layer and a second barrier portion, a solder mask layer, an attachment portion and an adhesive material portion. The first barrier portion covers at least part of a side surface of the filter chip, and is at least partially in contact with the surface of the solder mask layer facing away from the substrate, such that a cavity structure is formed between the filter chip and the substrate. The chip package structure and the radio frequency front-end module provided in the present application can effectively improve the packaging yield and packaging performance of chip packaging.

Description

Chip packaging structure and radio frequency front-end module

[0001] The present application is based on two Chinese applications with the application number 202410838990.X and the title "Chip packaging structure and radio frequency front-end module" filed on June 26, 2024, and the application number 202411994715.3 and the title "Chip packaging structure and radio frequency front-end module" filed on December 31, 2024, and claims priority thereto. TECHNICAL FIELD

[0002] The present application relates to the field of packaging technology, in particular to a chip packaging structure and a radio frequency front-end module. BACKGROUND

[0003] Some Surface Acoustic Wave (SAW) chips, Bulk Acoustic Wave (BAW) chips or non-filter chips, etc. need to have a cavity structure between the substrate during the packaging process to meet their functions, performance or other special requirements. When packaging the chip, a plastic encapsulation layer is usually formed on the side of the chip away from the substrate by injection molding process under a certain injection pressure to avoid the influence of the external environment on the chip. However, in the related art, the plastic encapsulation material of the plastic encapsulation layer easily penetrates into the cavity structure under pressure during injection molding, thereby affecting the performance of the filter chip and even causing the chip to fail. SUMMARY

[0004] Embodiments of the present application provide a chip packaging structure and a radio frequency front-end module, which aims to reduce the probability of the plastic encapsulation material of the plastic encapsulation layer entering the cavity structure under pressure during injection molding.

[0005] Embodiments of the present application provide a chip packaging structure, comprising:

[0006] a substrate; a solder resist layer disposed on the substrate and formed with a first opening window; a filter chip mounted on the substrate through the first opening window; a first blocking portion covering at least part of the side surface of the filter chip and at least partially contacting the surface of the solder resist layer away from the substrate, so as to form a cavity structure between the filter chip and the substrate; a plastic encapsulation layer covering the filter chip, the first blocking portion and the solder resist layer; a second blocking portion disposed on the filter chip and located at a first surface of the filter chip, the first surface facing the substrate; wherein part of the first blocking portion is located between the second blocking portion and the solder resist layer; the projection of the second blocking portion on the substrate at least partially overlaps the projection of the solder resist layer on the substrate.

[0007] Embodiments of the present application also provide a chip packaging structure, comprising:

[0008] A substrate; a solder resist layer disposed on the substrate and having a first opening window formed therein; a filter chip mounted on the substrate through the first opening window; a first blocking portion covering at least part of a side surface of the filter chip and at least partially in contact with a surface of the solder resist layer away from the substrate, so that a cavity structure is formed between the filter chip and the substrate; a plastic encapsulation layer covering the filter chip, the first blocking portion and the solder resist layer; and a second blocking portion disposed on the filter chip, wherein part of the first blocking portion is located between the second blocking portion and the solder resist layer; the filter chip, the second blocking portion and the substrate are arranged in a thickness direction, and the second blocking portion and the substrate have a gap in the thickness direction of the substrate.

[0009] The embodiment of the present application further provides a chip packaging structure, comprising:

[0010] A substrate comprising at least a bonding pad; a packaging chip electrically disposed on the substrate; a protective layer covering the packaging chip, and part of the protective layer disposed on the substrate, the protective layer, the packaging chip and the substrate forming a cavity, the protective layer comprising a first outer side surface disposed in a first direction, a second outer side surface disposed in a second direction intersecting the first direction, and a plastic encapsulation layer disposed on a side of the protective layer away from the substrate;

[0011] The chip packaging structure further comprises a bonding portion disposed on the protective layer and a bonding point, the plastic encapsulation layer covering the bonding portion, and the number of the bonding pads being greater than or equal to the number of the bonding points; the first outer side surface is disposed around the packaging chip, the bonding portion is disposed on the first outer side surface and the second outer side surface, and at least the protective layer or the bonding portion is an insulating member.

[0012] The embodiment of the present application provides a radio frequency front end module, which comprises the chip packaging structure provided in the embodiment of the present application.

[0013] The chip packaging structure and the radio frequency front end module provided by the embodiments of the present application, the first blocking part can form a sealed cavity structure between the filter chip and the substrate, the first blocking part can block the plastic encapsulation material of the plastic encapsulation layer during the plastic encapsulation process, effectively reducing the probability of the plastic encapsulation material of the plastic encapsulation layer entering the cavity structure under pressure during injection molding, and providing protection for the filter chip to have good functions. Since the second blocking part is arranged on the filter chip, the second blocking part is located on the first surface of the filter chip, so that the second blocking part can prevent the material of the first blocking part from flowing along the first surface of the filter chip towards the chip element of the filter chip during the packaging process, effectively reducing the probability that the material of the first blocking part contacts the chip element or the distance between the material of the first blocking part and the chip element is too small to cause the filter chip to fail, thereby reducing the influence of the packaging process on the performance of the filter chip, and facilitating to improve the packaging yield of the chip packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0015] FIG. 1 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0016] FIG. 2 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0017] FIG. 3 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0018] FIG. 4 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0019] FIG. 5 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0020] FIG. 6 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0021] FIG. 7 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0022] FIG. 8 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0023] FIG. 9 is a chip packaging structure provided in an embodiment of the present application;

[0024] FIG. 10 is another schematic diagram of a filter chip packaging structure provided in an embodiment of the present application;

[0025] FIG. 11 is a schematic cross-sectional view of another chip package structure according to embodiments of the present application;

[0026] FIG. 12 is a schematic cross-sectional view of a bonding portion according to embodiments of the present application;

[0027] FIG. 13 is a schematic view of another chip package structure according to embodiments of the present application;

[0028] FIG. 14 is a schematic top view of a chip package structure according to embodiments of the present application;

[0029] FIG. 15 is a schematic view of yet another chip package structure according to embodiments of the present application;

[0030] FIG. 16 is a schematic view of still another chip package structure according to embodiments of the present application;

[0031] FIG. 17 is a schematic view of another chip package structure according to embodiments of the present application. DETAILED DESCRIPTION

[0032] The technical solutions in embodiments of the present application will be described clearly and completely below with reference to the drawings in embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of the present application.

[0033] In the description of the present application, it should be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “upper”, “lower”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, “clockwise”, “counterclockwise”, and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be understood as a limitation on the present application. In addition, the terms “first” and “second” are only for the purpose of description, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features limited by “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of “multiple” is two or more, unless otherwise specifically limited.

[0034] Referring to FIG. 1, an embodiment of the present application provides a chip packaging structure 100, comprising a substrate 10, a solder resist layer 20, a filter chip 30, a first blocking part 40, a plastic packaging layer 50 and a second blocking part 60. The solder resist layer 20 is arranged on the substrate 10, and the solder resist layer 20 is formed with a first window 21; the filter chip 30 is mounted on the substrate 10 through the first window 21; the first blocking part 40 covers at least part of a side surface 35 of the filter chip 30, and the first blocking part 40 at least partially contacts a surface of the solder resist layer 20 away from the substrate 10, so that a cavity structure 70 is formed between the filter chip 30 and the substrate 10; the plastic packaging layer 50 covers the filter chip 30, the first blocking part 40 and the solder resist layer 20.

[0035] In some embodiments, the second blocking part 60 is arranged on the filter chip 30, and the second blocking part 60 is located on a first surface 31 of the filter chip 30, the first surface 31 being directed towards the substrate 10. Part of the first blocking part 40 is located between the second blocking part 60 and the solder resist layer 20; a projection of the second blocking part 60 on the substrate 10 at least partially overlaps a projection of the solder resist layer 20 on the substrate 10.

[0036] The chip packaging structure 100 of the above embodiment, the arrangement of the first blocking part 40 can form a sealed cavity structure 70 between the filter chip 30 and the substrate 10, and the first blocking part 40 can block the plastic packaging material of the plastic packaging layer 50 during the plastic packaging process, effectively reducing the probability of the plastic packaging material of the plastic packaging layer 50 entering the cavity structure 70 under pressure during injection molding, thereby providing a guarantee for the good function of the filter chip 30. The first blocking part 40 covers at least part of the side surface 35 of the filter chip 30, which can also relieve the stress on the side surface of the filter chip 30, avoid damage to the filter chip 30, and help to prolong the service life of the chip packaging structure 100. Since the second blocking part 60 is arranged on the filter chip 30, and the second blocking part 60 is located on the first surface 31 of the filter chip 30, the second blocking part 60 can prevent the material of the first blocking part 40 from flowing along the first surface 31 of the filter chip 30 towards the chip elements of the filter chip 30 during the packaging process, effectively reducing the probability of the material of the first blocking part 40 contacting the chip elements or being too close to the chip elements to cause the filter chip 30 to fail, thereby reducing the impact of the packaging process on the performance of the filter chip 30, and helping to improve the packaging yield of the chip packaging structure 100.

[0037] Secondly, in the process of forming the plastic sealing layer 50 by the injection molding process, if the plastic sealing material of the plastic sealing layer 50 applies a force to the first barrier portion 40, the second barrier portion 60 can also support the first barrier portion 40 to a certain extent, increasing the difficulty of the plastic sealing material of the plastic sealing layer 50 breaking through the first barrier portion 40 in the plastic sealing process. In addition, even if the plastic sealing material of the plastic sealing layer 50 breaks through part of the first barrier portion 40 (such as the first portion 41 of the first barrier portion 40), the second barrier portion 60 and the first barrier portion 40 between the second barrier portion 60 and the solder mask layer 20 can further block the plastic sealing material of the plastic sealing layer 50 from entering the cavity structure 70, increasing the difficulty of the plastic sealing material of the plastic sealing layer 50 entering the cavity structure 70, thereby providing a guarantee for the filter chip 30 to achieve good filtering function. In addition, the second barrier portion 60 can be at least partially in contact with the bottom surface of the filter chip 30, so that the second barrier portion 60 can support the filter chip 30, so that the second barrier portion 60 can buffer or release the stress received by the filter chip 30 to a certain extent, thereby reducing the probability of the filter chip 30 collapsing or tilting and causing failure, improving the connection reliability of the filter chip 30 and the substrate 10, and being conducive to improving the reliability of the chip packaging structure 100. Part of the first barrier portion 40 is located between the second barrier portion 60 and the solder mask layer 20, so that the first barrier portion 40 can buffer the stress between the second barrier portion 60 and the solder mask layer 20, which is conducive to prolonging the service life of the filter chip 30 and the chip packaging structure 100.

[0038] Thirdly, the projection of the second barrier portion 60 and the solder mask layer 20 on the substrate 10 at least partially overlaps, which is conducive to reducing the use amount of the material of the first barrier portion 40 and more conducive to forming a sealed cavity structure 70 under the condition of ensuring that the cavity structure 70 has the same sealing effect.

[0039] Exemplarily, the substrate 10 only contains metal wires, but the scope of the present application is not limited thereto. In some embodiments of the present application, one or more metal layer circuits and dielectric layers can be deposited on both sides of the substrate 10 by lithography, TSV and other substrate 10 technologies according to the connection needs of at least one of the filter chip 30 and other elements. The substrate 10 can be a resin substrate, a ceramic substrate, a glass substrate, a quartz substrate or other types of substrates. Optionally, the substrate 10 is a resin substrate.

[0040] Exemplarily, the material of the solder resist layer 20 comprises at least one of resin, solder resist green paint, dry film, and other insulating materials. It can be understood that the solder resist layer 20 can protect the substrate 10 and avoid short circuit of the metal wires in the substrate 10. The material of the solder resist layer 20 has good solder resist performance. Exemplarily, in the area where no metal wires are arranged on the surface of the substrate 10, the solder resist layer 20 is arranged between two adjacent metal wires; in the area where metal wires are arranged on the surface of the substrate 10, the solder resist layer 20 covers the metal wires.

[0041] It can be understood that the solder resist layer 20 is arranged on the surface of the substrate 10, in some cases, the solder resist layer 20 can be regarded as two independent structures with the substrate 10, or as a part of the substrate 10, which is not limited in the present application.

[0042] Exemplarily, the filter chip 30 comprises a surface acoustic wave filter chip, a bulk acoustic wave filter chip, or other chips with filtering function. Exemplarily, the filter chip 30 can be mounted on the substrate 10 in a flip-chip manner.

[0043] The number of the filter chips 30 can be designed according to actual needs, such as one, two, three or more. When the number of the filter chips 30 comprises multiple, at least one of the functions, sizes, shapes, structures and distances to the substrate 10 of different filter chips 30 can be different or the same. When the number of the filter chips 30 comprises multiple, the multiple filter chips 30 are arranged at intervals. Different filter chips 30 can be arranged on the same side of the substrate 10, or on different sides of the substrate 10.

[0044] Referring to FIG. 2, the filter chip 30 includes a first chip body 32 and a first protrusion 33 protruding from a side of the first chip body 32 facing the substrate 10, the first chip body 32 is electrically connected to the substrate 10 through the first protrusion 33, a cavity structure 70 is formed between the first chip body 32 and the substrate 10, and the first blocking portion 40 can seal the cavity structure 70. The first chip body 32 has a first surface 31, a second surface 34, and a side surface 35, the first surface 31 and the second surface 34 are oppositely arranged, the side surface 35 connects the first surface 31 and the second surface 34, and the first surface 31 is closer to the substrate 10 than the second surface 34. The second blocking portion 60 is arranged on the first chip body 32 and located on the first surface 31, and can prevent the material of the first blocking portion 40 from flowing along the first surface 31 of the first chip body 32 towards the chip elements close to the filter chip 30 during packaging, thereby effectively reducing the probability of the material of the first blocking portion 40 contacting or being too close to the chip elements to cause the failure of the filter chip 30, and facilitating to improve the packaging yield of the chip packaging structure 100. In addition, the second blocking portion 60 is arranged on the first surface 31, and after packaging, the second blocking portion 60 can buffer or release the stress received by the first chip body 32 to a certain extent, thereby protecting the first protrusion 33 of the filter chip 30 for connecting to the substrate 10 and reducing the probability of the first protrusion 33 collapsing to cause poor contact between the filter chip 30 and the substrate 10. The material of the first protrusion 33 can include at least one of copper, tin, gold, alloy, etc., and can also be a commonly used bump type (for conductive connection) such as a metal bump, and the filter chip 30 is connected to the substrate 10 through the first protrusion 33 and a first pad on the substrate 10.

[0045] In some embodiments, the first window 21 can expose the first pad of the substrate 10, so that the first protrusion 33 of the filter chip 30 can be connected with the first pad of the substrate 10, thereby realizing the connection between the filter chip 30 and the substrate 10; the setting of the first window 21 can also reduce the weight of the solder resist layer 20, thereby facilitating the lightweight design of the chip packaging structure 100. The first pad can be disposed on the surface of the substrate 10 and disposed in the same layer as the solder resist layer 20, or can be embedded or semi-embedded in the substrate, without limitation. Exemplarily, the size of the first window 21 is smaller than the size of the filter chip 30. In other embodiments, the size of the first window 21 can also be greater than or equal to the size of the filter chip 30. Understandably, the first protrusion 33 of the filter chip 30 is connected with the first pad of the substrate 10. The first window 21 can be opened at a position where the first pad needs to be exposed, and the remaining positions of the area of the substrate 10 opposite to the filter chip 30 are covered by the solder resist layer 20, in which case one filter chip 30 corresponds to a plurality of first windows 21, and each first window 21 corresponds to one first protrusion 33. The first window 21 can also be opened at the bottom of the entire filter chip 30, in which case one filter chip 30 corresponds to one first window 21.

[0046] The setting of the plastic sealing layer 50 can be used to isolate the chip packaging structure 100 from the external environment, avoid the influence of humidity, temperature, particles and the like of the external environment on the chip packaging structure 100, and protect the chip packaging structure 100.

[0047] The plastic sealing material used by the plastic sealing layer 50 can include insulating resin material or other conventional plastic sealing material. Optionally, the plastic sealing material is a resin material containing particles; the particles can be silicon dioxide particles or aluminum trioxide particles, and the present embodiment is not limited thereto. Understandably, it can also be other insulating materials that have good fluidity or are in liquid state at high temperature, or other materials that can realize the sealing function.

[0048] Please refer to FIG. 1, in some embodiments, the second barrier 60 is projected on the solder mask 20 on the substrate 10, that is, the second barrier 60 overlaps the solder mask 20 in the thickness direction of the substrate 10. In this way, in the process of forming the plastic package layer 50 by the injection molding process, even if the first barrier 40 (such as the first part 41 of the first barrier 40) outside the second barrier 60 is broken by the plastic package material of the plastic package layer 50, the second barrier 60 and the first barrier 40 between the second barrier 60 and the solder mask 20 can further block the plastic package material of the plastic package layer 50 from entering the cavity structure 70, effectively increasing the difficulty of the plastic package material of the plastic package layer 50 entering the cavity structure 70, thereby providing protection for the filter chip 30 to achieve good filtering function. In addition, the second barrier 60 is projected on the solder mask 20 on the substrate 10, and after packaging, the second barrier 60 and the first barrier 40 between the solder mask 20 and the second barrier 60 can better support the filter chip 30, which is conducive to buffering or releasing the stress suffered by the filter chip 30, thereby effectively reducing the probability of failure of the filter chip 30 due to collapse or tilt, and improving the reliability of the chip packaging structure 100.

[0049] Please refer to FIG. 2, in some embodiments, the second barrier 60 includes an overlapping part 61 and a non-overlapping part 62 connected to the overlapping part 61, the non-overlapping part 62 extends from the overlapping part 61 towards the cavity structure 70, the projection of the overlapping part 61 on the substrate 10 overlaps the projection of the solder mask 20 on the substrate 10, and the projection of the non-overlapping part 62 on the substrate 10 is located outside the projection of the solder mask 20 on the substrate 10. In this way, while ensuring that the first barrier 40 can block the plastic package material of the plastic package layer 50 from entering the cavity structure 70 and ensuring that the second barrier 60 can block the material of the first barrier 40 from flowing along the first surface 31 to the chip elements of the filter chip 30, it is conducive to reducing the amount of material used by the solder mask 20, and there is no need to set the solder mask 20 below the non-overlapping part 62. For example, the projection of the overlapping part 61 on the plane where the solder mask 20 is located overlaps the solder mask 20, and the projection of the non-overlapping part 62 on the plane where the solder mask 20 is located is located at the first window 21. It can be understood that the non-overlapping part 62 is a part of the second barrier 60 other than the overlapping part 61.

[0050] Referring to FIG. 1 or FIG. 2, in some embodiments, the distance between the second barrier 60 and the solder mask 20 along the thickness direction of the substrate 10 is in the range of 1 um to 10 um, such as 1 um, 2 um, 5 um, 8 um, 10 um, or any other suitable range between 1 um and 10 um, to ensure that the second barrier 60 can effectively block the material of the first barrier 40 and ensure that the first barrier 40 can effectively block the encapsulation material of the encapsulation layer 50. Within this range, the first barrier 40 can partially enter the gap between the second barrier 60 and the solder mask 20, which can buffer the stress between the second barrier 60 and the solder mask 20, and avoid damage to the solder mask 20 or the second barrier 60. For example, the distance between the surface of the solder mask 20 away from the substrate 10 and the second barrier 60 along the thickness direction of the substrate 10 is in the range of 1 um to 10 um. For example, the distance between the surface of the solder mask 20 away from the substrate 10 and the second barrier 60 along the thickness direction of the substrate 10 is in the range of 1 um to 10 um in some areas of the surface of the solder mask 20 away from the substrate 10. Some areas of the surface of the solder mask 20 away from the substrate 10 can be in contact with the second barrier 60, such as point contact, surface contact, or line contact.

[0051] In some embodiments, the sum of the height of the second barrier 60 and the height of the solder mask 20 along the thickness direction of the substrate 10 is less than or equal to the height of the first protrusion 33 of the filter chip 30. This ensures that the first protrusion 33 can be reliably connected to the substrate 10, and prevents the first protrusion 33 from being difficult to make good contact with the first pad of the substrate 10 due to the sum of the height of the second barrier 60 and the height of the solder mask 20 being too large, which can cause a virtual weld.

[0052] In some embodiments, the modulus of the second barrier 60, the solder mask 20, and the first barrier 40 are all less than the modulus of the filter chip 30, and the modulus of the first barrier 40 is less than the modulus of the encapsulation layer 50. In this way, the second barrier 60, the solder mask 20, and the first barrier 40 can buffer the stress of at least one of the filter chip 30 and the encapsulation layer 50, and buffer the stress of at least one of the encapsulation layer 50 and the substrate 10, which is beneficial to prolong the service life of the filter chip 30 and the chip packaging structure 100.

[0053] In some embodiments, the modulus of the first barrier 40 is less than at least one of the modulus of the second barrier 60 and the modulus of the solder mask 20. In this way, the first barrier 40 located between the second barrier 60 and the solder mask 20 can buffer the stress of at least one of the second barrier 60 and the solder mask 20, which is beneficial to prolong the service life of the filter chip 30 and the chip packaging structure 100.

[0054] Referring to FIG. 3, in some embodiments, the first barrier portion 40 includes a first portion 41 and a second portion 42. The first portion 41 is located outside the cavity structure 70, covers at least part of the side surface 35 of the filter chip 30, and is at least partially in contact with the surface of the solder resist layer 20 away from the substrate 10. The second portion 42 is at least partially located between the second barrier portion 60 and the solder resist layer 20. In this way, in the process of forming the plastic package layer 50 by the injection molding process, the first portion 41 can block the plastic package material of the plastic package layer 50. Even if the first portion 41 is broken, the second barrier portion 60 and the second portion 42 located between the second barrier portion 60 and the solder resist layer 20 can further block the plastic package material of the plastic package layer 50. Thus, the first barrier portion 40 can effectively block the plastic package material of the plastic package layer 50 from entering the cavity structure 70, thereby providing a guarantee for the filter chip 30 to achieve good filtering function. Exemplarily, the first portion 41 is located outside the second barrier portion 60. The first portion 41 is located outside the second portion 42.

[0055] In some embodiments, the surface of the solder resist layer 20 in contact with the second portion 42 is roughened, which is advantageous for reducing the difficulty of processing the solder resist layer 20, and thus for reducing the difficulty of packaging the chip packaging structure 100. It can be understood that, when forming the solder resist layer 20, if the surface of the solder resist layer 20 in contact with the second portion 42 is processed as a flat surface, the processing difficulty is high and the requirement for the processing equipment is high. In the present embodiment, the surface of the solder resist layer 20 in contact with the second portion 42 is roughened, i.e., the surface of the solder resist layer 20 in contact with the second portion 42 is an uneven surface. Thus, after the filter chip 30 is connected to the substrate 10, a gap exists between the solder resist layer 20 and the second barrier portion 60. When the first barrier portion 40 is formed, the material of the first barrier portion 40 can fill the gap, so that, in the process step of forming the plastic encapsulation layer 50, even if the first barrier portion 40 located outside the second barrier portion 60 is broken, the second barrier portion 60 and the first barrier portion 40 located in the gap can further block the plastic encapsulation material of the plastic encapsulation layer 50 from entering the cavity structure 70, further increasing the difficulty of the plastic encapsulation material of the plastic encapsulation layer 50 from entering the cavity structure 70. On the other hand, for example, in the case where the modulus of the first barrier portion 40 is less than at least one of the modulus of the second barrier portion 60 and the modulus of the solder resist layer 20, the first barrier portion 40 enters the gap between the second barrier portion 60 and the solder resist layer 20, which plays a role of buffering the stress between the second barrier portion 60 and the solder resist layer 20 to a certain extent. The gap can be formed by spacing the surface of the solder resist layer 20 away from the substrate 10 and the surface of the second barrier portion 60 toward the substrate 10. Alternatively, the gap can be formed by contacting one part of the surface of the solder resist layer 20 away from the substrate 10 with the second barrier portion 60, and spacing another part of the surface of the solder resist layer 20 away from the substrate 10 from the second barrier portion 60. Exemplarily, the surface of the second barrier portion 60 toward the substrate 10 can be a flat surface or a roughened surface, which is not limited herein.

[0056] Referring to FIG. 3, in some embodiments, the inner side wall 63 of the second barrier portion 60 is closer to the chip element of the filter chip 30 relative to the second portion 42, so as to reduce the probability of the material of the first barrier portion 40 contaminating the first protrusion 33, the chip element or the first pad of the substrate 10 as much as possible, thereby providing a guarantee for the filter chip 30 to have good performance. In other embodiments, the second portion 42 extends into the cavity structure 70, and the innermost side of the second portion 42 can also be closer to the chip element of the filter chip 30 relative to the inner side wall 63 of the second barrier portion 60, as long as the second portion 42 does not contact the first protrusion 33 or the chip element.

[0057] In some embodiments, the second portion 42 extends into the cavity structure 70, and the chip package structure 100 has at least one of the following features: the second portion 42 extending into the cavity structure 70 is located at the side of the solder resist layer 20 at the first opening 21; the second portion 42 extending into the cavity structure 70 is in contact with the substrate 10 at the cavity structure 70. In this way, the material of the first barrier 40 can be allowed to sufficiently fill the gap between the second barrier 60 and the solder resist layer 20. Exemplarily, the second portion 42 extends into the cavity structure 70, and the second portion 42 extending into the cavity structure 70 is located at the side of the solder resist layer 20 at the first opening 21. Exemplarily, the second portion 42 extends into the cavity structure 70, and the second portion 42 extending into the cavity structure 70 is in contact with the substrate 10 at the cavity structure 70.

[0058] Referring to FIG. 4, in some embodiments, the shape of the second barrier 60 includes a ring shape, so that in the process step of forming the first barrier 40, the second barrier 60 can form a full barrier to the material of the first barrier 40 in the circumferential direction of the second barrier 60, thereby preventing the material of the first barrier 40 from flowing along the first surface 31 of the filter chip 30 towards the chip elements of the filter chip 30 in all directions, reducing the impact of the packaging process on the performance of the filter chip 30, and facilitating improvement of the packaging yield of the chip package structure 100. The outer side of the second barrier 60 can be aligned with the edge of the filter chip 30, or can have a certain distance from the edge of the filter chip 30, which is not limited.

[0059] In some embodiments, the material of the first barrier 40 includes at least one of the following: glue material, green oil, etc. Exemplarily, the glue material can include an insulating liquid polymer material. In at least one embodiment, the glue material can use fast-curing glue (for example: ultraviolet light-curing glue). It can be understood that in other embodiments, the glue material can also use other commonly used glue materials or materials with similar properties to glue materials (insulation, curable) to achieve. The first barrier 40 can be formed by processes such as dip, brush, spray coating, jetting dispense, needle dispense, or printing.

[0060] In some embodiments, the material of the second barrier 60 includes at least one of the following: dry film, polyimide (PI), etc. Exemplarily, the second barrier 60 includes a barrier structure made of non-conductive material.

[0061] Referring to FIG. 3, in some embodiments, the chip package structure 100 further comprises a non-filter chip 80, which is spaced apart from the filter chip 30 on the substrate 10, and the plastic encapsulation layer 50 covers the non-filter chip 80. The non-filter chip 80 is configured to increase the functionality of the chip package structure 100. For example, the first blocking portion 40 is spaced apart from the non-filter chip 80, and the first blocking portion 40 does not need to cover the non-filter chip 80, which is beneficial to reduce the package size of the chip package structure 100.

[0062] For example, the non-filter chip 80 comprises a power amplifier, a low noise amplifier, a radio frequency switch, a capacitor, an inductor, or a resistor, etc. The non-filter chip 80 can be mounted on the substrate 10 in a flip-chip manner or in a wire-bonding manner. It should be noted that, in the case that the non-filter chip 80 is mounted on the substrate 10 in a flip-chip manner, the plastic encapsulation material used in the plastic encapsulation filling process of the plastic encapsulation layer 50 needs to enter the gap between the non-filter chip 80 and the substrate 10 to realize encapsulation, so as to ensure the reliability of the encapsulation of the non-filter chip 80. In the case that the non-filter chip 80 is mounted on the substrate 10 in a wire-bonding manner, compared with the method of forming a cavity structure on the filter chip 30 by coating a film, the non-filter chip 80 can be reliably encapsulated and encapsulated on the same side as the filter chip 30, and the encapsulation layout is more flexible. The filter chip 30 and the non-filter chip 80 can be disposed on the same side of the substrate 10. In other embodiments, the filter chip 30 and part of the non-filter chip 80 can be disposed on the same side of the substrate 10, and the other part of the non-filter chip 80 can be disposed on the other side of the substrate 10, which is not limited in the present application.

[0063] The number of the non-filter chip 80 can be designed according to actual needs, such as one, two, three or more. When the number of the non-filter chip 80 comprises multiple, at least one of the functions, sizes, shapes, structures and distances to the substrate 10 of different non-filter chips 80 can be different or the same. When the number of the non-filter chip 80 comprises multiple, the multiple non-filter chips 80 are spaced apart. Different non-filter chips 80 can be disposed on the same side of the substrate 10 or on different sides of the substrate 10. When the number of the non-filter chip 80 comprises multiple, each non-filter chip 80 can be mounted on the substrate 10 in a flip-chip manner or in a wire-bonding manner; or at least one of the multiple non-filter chips 80 is mounted on the substrate 10 in a flip-chip manner, and the remaining non-filter chips 80 are mounted on the substrate 10 in a wire-bonding manner. In other embodiments, the non-filter chip 80 can also be omitted.

[0064] Please refer to FIG. 3, exemplarily, the non-filter chip 80 is spaced apart from the first blocking part 40, and part of the first blocking part 40 is located at the periphery of the non-filter chip 80. In the scenario of the co-packaging of the filter chip 30 and the non-filter chip 80, if the non-filter chip 80 is mounted on the substrate 10 by means of the bonding wire, in the process step of processing the first blocking part 40, since the wire has been welded with the pad for connecting to the non-filter chip 80, even if the material of the first blocking part 40 flows to the pad, it will not affect the electrical connection between the wire and the pad, and the first blocking part 40 located at the pad can also protect the pad to some extent, so that the connection between the pad and the influence is more reliable, and the probability of the connection between the pad and the wire being broken or loosened is reduced.

[0065] Please refer to FIG. 5, exemplarily, in the scenario of the co-packaging of the filter chip 30 and the non-filter chip 80, if the non-filter chip 80 is mounted on the substrate 10 by means of the flip, in order to ensure that the plastic encapsulation material used by the plastic encapsulation layer 50 can smoothly fill the gap between the non-filter chip 80 and the substrate 10, the plastic encapsulation pressure will be increased in the plastic encapsulation process. The non-filter chip 80 is spaced apart from the first blocking part 40, and part of the first blocking part 40 is located at the periphery of the non-filter chip 80, which can ensure that the plastic encapsulation material used by the plastic encapsulation layer 50 can completely fill the bottom of the non-filter chip 80 in the plastic encapsulation process, and can also ensure that the plastic encapsulation material of the plastic encapsulation layer 50 is not easy to break through the first blocking part 40 and the second blocking part 60 and enter the cavity structure 70.

[0066] Please refer to FIG. 5, exemplarily, the non-filter chip 80 includes a second chip body 81 and a second protrusion 82, the second protrusion 82 is protruded from the side of the second chip body 81 facing the substrate 10, and the second chip body 81 is electrically connected to the substrate 10 through the second protrusion 82. The plastic encapsulation layer 50 filled in the gap between the non-filter chip 80 and the substrate 10 can support the non-filter chip 80, thereby buffering or releasing the stress suffered by the non-filter chip 80, protecting the second protrusion 82 in the non-filter chip 80 for connecting to the substrate 10, reducing the probability of the second protrusion 82 collapsing to cause the non-filter chip 80 to be in poor contact with the substrate 10, and improving the reliability of the chip packaging structure 100.

[0067] Exemplarily, the solder resist layer 20 is formed with a second opening window (not labeled), and the non-filter chip 80 is mounted on the substrate 10 through the second opening window. In some embodiments, the second opening window can expose a second pad of the substrate 10, so that a second protrusion 82 of the non-filter chip 80 can be connected with the second pad, thereby realizing the connection between the non-filter chip 80 and the substrate 10; in addition, the arrangement of the second opening window can also reduce the weight of the solder resist layer 20, thereby facilitating the lightweight design of the chip packaging structure 100. Exemplarily, the second protrusion 82 includes at least one of a tin ball and a metal bump. Exemplarily, the size of the second opening window is greater than the size of the non-filter chip 80.

[0068] Referring to FIG. 2, the embodiment of the present application further provides a chip packaging structure 100, which includes a substrate 10, a solder resist layer 20, a filter chip 30, a first blocking part 40, a plastic packaging layer 50, and a second blocking part 60. The solder resist layer 20 is arranged on the substrate 10, and the solder resist layer 20 is formed with a first opening window 21. The filter chip 30 is mounted on the substrate 10 through the first opening window 21. The first blocking part 40 covers at least part of a side surface 35 of the filter chip 30, and the first blocking part 40 at least partially contacts a surface of the solder resist layer 20 away from the substrate 10, so as to form a cavity structure 70 between the filter chip 30 and the substrate 10. The plastic packaging layer 50 covers the filter chip 30, the first blocking part 40, and the solder resist layer 20. The second blocking part 60 is arranged on the filter chip 30. Part of the first blocking part 40 is located between the second blocking part 60 and the solder resist layer 20. The filter chip 30, the second blocking part 60, and the substrate 10 are arranged in a thickness direction, and the second blocking part 60 has a gap with the substrate 10 in the thickness direction of the substrate 10.

[0069] The chip packaging structure 100 of the above embodiment can form a sealed cavity structure 70 between the filter chip 30 and the substrate 10 through the arrangement of the first blocking part 40. The first blocking part 40 can block the plastic packaging material of the plastic packaging layer 50 during the plastic packaging process, effectively reducing the probability of the plastic packaging material of the plastic packaging layer 50 entering the cavity structure 70 under pressure during injection molding, thereby providing a guarantee for the filter chip 30 to have good functions. Since the second blocking part 60 is arranged on the filter chip 30, the filter chip 30, the second blocking part 60, and the substrate 10 are arranged in a thickness direction, so that the second blocking part 60 can prevent the material of the first blocking part 40 from flowing along the surface of the filter chip 30 close to the substrate 10 towards the chip elements of the filter chip 30 during the packaging process, effectively reducing the probability that the material of the first blocking part 40 contacts the chip elements or the distance between the material of the first blocking part 40 and the chip elements is too small, thereby causing the filter chip 30 to fail, thereby reducing the influence of the packaging process on the performance of the filter chip 30, and facilitating the improvement of the packaging yield of the chip packaging structure 100.

[0070] Secondly, since part of the first barrier portion 40 is located between the second barrier portion 60 and the solder resist layer 20, in the process of forming the plastic sealing layer 50 by the injection molding process, if the plastic sealing material of the plastic sealing layer 50 applies a force to the first barrier portion 40, the second barrier portion 60 can also support the first barrier portion 40 to a certain extent, increasing the difficulty of the plastic sealing material of the plastic sealing layer 50 breaking through the first barrier portion 40 in the plastic sealing process. In addition, even if the plastic sealing material of the plastic sealing layer 50 breaks through part of the first barrier portion 40 (such as the first portion 41 of the first barrier portion 40), the second barrier portion 60 and the first barrier portion 40 located between the second barrier portion 60 and the solder resist layer 20 can further block the plastic sealing material of the plastic sealing layer 50 from entering the cavity structure 70, increasing the difficulty of the plastic sealing material of the plastic sealing layer 50 entering the cavity structure 70, thereby providing a guarantee for the filter chip 30 to achieve good filtering function. In addition, the second barrier portion 60 is arranged on the filter chip 30, and the filter chip 30, the second barrier portion 60 and the substrate 10 are arranged in the thickness direction of the substrate 10. The second barrier portion 60 can support the filter chip 30, so that the second barrier portion 60 can buffer or release the stress received by the filter chip 30 to a certain extent, thereby reducing the probability of failure caused by the collapse or inclination of the filter chip 30, improving the connection reliability of the filter chip 30 and the substrate 10, and being conducive to improving the reliability of the chip packaging structure 100.

[0071] Thirdly, the second barrier portion 60 is arranged on the filter chip 30, and the second barrier portion 60 and the substrate 10 have a gap in the thickness direction of the substrate 10. The existence of the gap can make the filter chip 30 and the substrate 10 easier to assemble when they are connected, thereby reducing the packaging difficulty of the chip packaging structure 100.

[0072] Please refer to FIG. 2. In some embodiments, the projection of the second barrier portion 60 on the substrate 10 at least partially overlaps the projection of the solder resist layer 20 on the substrate 10, which is conducive to reducing the amount of material used for the first barrier portion 40 and forming a sealed cavity structure 70.

[0073] Please refer to FIG. 6. In some embodiments, the projection of the second barrier portion 60 on the substrate 10 is staggered with the projection of the solder resist layer 20 on the substrate 10, which can reduce the amount of material used for the solder resist layer 20.

[0074] Please refer to FIG. 6. In some embodiments, the area of the first window 21 is smaller than the projection area of the filter chip 30 on the substrate 10, so as to reduce the size of the chip packaging structure 100 as much as possible and make the structure of the chip packaging structure 100 more compact.

[0075] Referring to FIG. 7 and FIG. 8, in some embodiments, the area of the first window 21 is greater than or equal to the projected area of the filter chip 30 on the substrate 10. The area of the first window 21 being greater than or equal to the projected area of the filter chip 30 on the substrate 10 can have a certain fault-tolerant effect on the position offset of the filter chip 30, which is conducive to reducing the difficulty of assembling and connecting the filter chip 30 and the substrate 10, and reducing the packaging difficulty of the chip packaging structure 100. In addition, the area of the first window 21 being greater than or equal to the projected area of the filter chip 30 on the substrate 10 can also increase the minimum distance between the second blocking part 60 and the solder resist layer 20, so that the amount of material in the spacing space between the two is increased, thereby better buffering or releasing the stress received by the filter chip 30, and further avoiding damage to the filter chip 30 due to stress.

[0076] In some embodiments, the minimum distance between the second blocking part 60 and the solder resist layer 20 is greater than 10 um, so that the material of the first blocking part 40 can be reduced to flow to the outside of the filter chip 30, thereby reducing the occupied area of a single filter chip 30 and reducing the distance between adjacent chips.

[0077] In some embodiments, the distance between the second blocking part 60 and the solder resist layer 20 is less than or equal to 100 um, that is, the distance between the second blocking part 60 and the solder resist layer 20 in the plane perpendicular to the thickness direction of the substrate 10 is less than or equal to 100 um, so as to ensure that the first blocking part 40 can better block the plastic encapsulation material of the plastic encapsulation layer 50 during the formation of the plastic encapsulation layer 50, and is conducive to the miniaturization design of the chip packaging structure 100. Exemplarily, the distance between the second blocking part 60 and the solder resist layer 20 is less than or equal to 80 um.

[0078] Exemplarily, the substrate 10 includes the substrate 10 of any one of the embodiments of the present application without conflict. Exemplarily, the solder resist layer 20 includes the solder resist layer 20 of any one of the embodiments of the present application without conflict. Exemplarily, the filter chip 30 includes the filter chip 30 of any one of the embodiments of the present application without conflict. Exemplarily, the first blocking part 40 includes the first blocking part 40 of any one of the embodiments of the present application without conflict. Exemplarily, the plastic encapsulation layer 50 includes the plastic encapsulation layer 50 of any one of the embodiments of the present application without conflict. Exemplarily, the second blocking part 60 includes the second blocking part 60 of any one of the embodiments of the present application without conflict. Exemplarily, the chip packaging structure 100 includes the chip packaging structure 100 of any one of the embodiments of the present application without conflict.

[0079] Referring to FIG. 7, the embodiment of the present application further provides a chip packaging structure 100, comprising a substrate 10, a solder resist layer 20, a filter chip 30, a first blocking part 40, a plastic packaging layer 50 and a second blocking part 60, the solder resist layer 20 is arranged on the substrate 10, and the solder resist layer 20 is formed with a first window 21; the filter chip 30 is mounted on the substrate 10 through the first window 21; the first blocking part 40 covers at least part of a side surface 35 of the filter chip 30, and the first blocking part 40 at least partially contacts a surface of the solder resist layer 20 away from the substrate 10, so that a cavity structure 70 is formed between the filter chip 30 and the substrate 10; the plastic packaging layer 50 covers the filter chip 30, the first blocking part 40 and the solder resist layer 20; the second blocking part 60 is arranged on the filter chip 30; and an area of the first window 21 is greater than or equal to a projection area of the filter chip 30 on the substrate 10.

[0080] The chip packaging structure 100 in the above embodiment, the first blocking part 40 can form a sealed cavity structure 70 between the filter chip 30 and the substrate 10, and the first blocking part 40 can block the plastic packaging material of the plastic packaging layer 50 during the plastic packaging process, effectively reducing the probability of the plastic packaging material of the plastic packaging layer 50 entering the cavity structure 70 under pressure during injection molding, and providing a guarantee for the filter chip 30 to have good functions. Secondly, the second blocking part 60 is arranged on the filter chip 30, and the second blocking part 60 can support the filter chip 30, so that the second blocking part 60 can buffer or release the stress received by the filter chip 30 to a certain extent, thereby reducing the probability of the filter chip 30 collapsing or tilting and causing failure, improving the connection reliability of the filter chip 30 and the substrate 10, and being beneficial to improving the reliability of the chip packaging structure 100.

[0081] In addition, the area of the first window 21 is greater than or equal to the projection area of the filter chip 30 on the substrate 10, which can have a certain fault tolerance effect on the position offset of the filter chip 30, is beneficial to reducing the difficulty of connecting the filter chip 30 and the substrate 10, and reducing the packaging difficulty of the chip packaging structure 100. In addition, the area of the first window 21 is greater than or equal to the projection area of the filter chip 30 on the substrate 10, which can also increase the minimum distance between the second blocking part 60 and the solder resist layer 20, so that the amount of material in the spacing space between the two is increased, thereby better buffering or releasing the stress received by the filter chip 30, and further avoiding damage to the filter chip 30 caused by stress.

[0082] In some embodiments, the partial first barrier 40 is located between the second barrier 60 and the solder resist layer 20. In the process of forming the plastic encapsulation layer 50, a part of the first barrier 40 (such as the first part 41 of the first barrier 40) can first block the plastic encapsulation material of the plastic encapsulation layer 50. Even if this part is broken, the second barrier 60 and the first barrier 40 located between the second barrier 60 and the solder resist layer 20 can further block the plastic encapsulation material of the plastic encapsulation layer 50, thereby effectively preventing the plastic encapsulation material of the plastic encapsulation layer 50 from entering the cavity structure 70, thereby ensuring that the filter chip 30 can achieve good filtering function.

[0083] In some embodiments, the minimum distance between the second barrier 60 and the solder resist layer 20 is greater than 10 um, so that the material of the first barrier 40 can flow to the outside of the filter chip 30, thereby reducing the area occupied by a single filter chip 30 and reducing the distance between adjacent chips.

[0084] In some embodiments, the filter chip 30, the second barrier 60 and the substrate 10 are arranged along the thickness direction of the substrate 10, and the second barrier 60 has a gap with the substrate 10 in the thickness direction of the substrate 10. The second barrier 60 is arranged on the filter chip 30, and the second barrier 60 has a gap with the substrate 10 in the thickness direction of the substrate 10, so that when the filter chip 30 and the substrate 10 are connected, they are easier to assemble, thereby reducing the packaging difficulty of the chip packaging structure 100.

[0085] Exemplarily, the substrate 10 includes the substrate 10 of any one of the above embodiments without conflict. The solder resist layer 20 includes the solder resist layer 20 of any one of the above embodiments without conflict. The filter chip 30 includes the filter chip 30 of any one of the above embodiments without conflict. The first barrier 40 includes the first barrier 40 of any one of the above embodiments without conflict. The plastic encapsulation layer 50 includes the plastic encapsulation layer 50 of any one of the above embodiments without conflict. The second barrier 60 includes the second barrier 60 of any one of the above embodiments without conflict. The chip packaging structure 100 includes the chip packaging structure 100 of any one of the above embodiments without conflict.

[0086] The embodiments of the present application also provide a radio frequency front-end module, which includes the chip packaging structure 100 of any one of the above embodiments.

[0087] As shown in FIG. 9, FIG. 9 is a chip packaging structure provided in the embodiments of the present application. The chip packaging structure provided in the embodiments of the present application includes a substrate 10, an insulating layer 102, a protective layer 103, a plastic encapsulation layer 50, an encapsulated chip 108 and a bonding part 301.

[0088] Specifically, the substrate 10 can adopt a conventional circuit substrate, and driving traces are arranged in the substrate 10 to achieve the signal transmission purpose. In the substrate 10 provided in the embodiment, different specifications of circuit substrates can be selected according to the product requirements, so as to ensure the normal operation of the device.

[0089] In the embodiment, the substrate 10 includes pads 105, which can be arranged in multiple numbers. When the pads 105 are arranged, the positions and numbers of the pads 105 correspond to the package chips 108 above. Specifically, when the pads on the package chips 108 are symmetrically arranged, the pads 105 on the substrate 10 are also symmetrically arranged. When the package chips 108 are packaged, the pads 105 and the pads on the package chips 108 are correspondingly matched and adhered.

[0090] Specifically, the package chips 108 are arranged on one side of the substrate 10, and the package chips 108 can be arranged in the flip region 222 of the substrate 10. When the package chips 108 are installed, the pads 106 on the package chips 108 are opposite to the pads 105. In the embodiment, the upper surfaces of the pads 105 can be flush with the upper surface of the substrate 10, or the upper surfaces of the pads 105 are located in the substrate 10. When the pads 105 are arranged, different pads 105 can be arranged at different positions of the substrate 10. As shown in FIG. 9, only the pads 105 corresponding to the filter chips are shown. Alternatively, other pads 105 can be arranged at other positions. Meanwhile, the pads 106 can be arranged as tin balls or other conductive materials to ensure the normal transmission of signals. When connected, the pads 106 can be opposite to the corresponding pads 105. In the embodiment, the number of the pads 105 is greater than or equal to the number of the pads 106, so as to ensure the connection effect and the connection between the substrate 10 and different components.

[0091] As shown in FIG. 10, which is another schematic diagram of a filter chip packaging structure provided in the embodiment, in combination with the structure shown in FIG. 9, when the substrate 10 is arranged, the pads 105 on the substrate 10 are exposed to the upper surface of the substrate 10, and the pads 105 protrude a certain height from the upper surface of the substrate 10. At this time, the pads 106 on the package chips 108 are aligned with the pads 105 when packaging and aligning. The packaging structure in the embodiment is suitable for the above two different substrates.

[0092] In the following embodiments, the packaging structure corresponding to the substrate provided in FIG. 9 is taken as an example for specific description, and other types of substrates 10 are within the protection scope of the application.

[0093] In the setting of the packaging chip 108, the packaging chip 108 includes a filter chip or other functional chip. Specifically, the functional chip includes at least one or more of a passive element and a non-filter chip. The passive element can include an inductor, a capacitor, etc. The non-filter chip can be one or more of a power amplifier, a low-noise amplifier, a radio frequency switch, a coupler, a matching circuit, etc. The passive element can be one or more, and the non-filter chip can be one or more. The above types and quantities of the packaging chip 108 can be set according to product requirements, thereby packaging different chips and meeting the use requirements.

[0094] Further, in the embodiment of the application, the insulating layer 102 is further arranged on the substrate 10. The insulating layer 102 can be directly arranged on the surface of the substrate 10. The insulating layer 102 avoids the flip area 222 and the corresponding pad 105. For example, the insulating layer 102 is arranged on one side of the pad 105. Specifically, the insulating layer 102 can be laid on the surface of the substrate 10 according to requirements. For example, the insulating layer 102 can be arranged on the upper surface or the lower surface of the substrate 10.

[0095] In the setting of the insulating layer 102, the material of the insulating layer 102 includes insulating green paint, resin, and other insulating materials. In the following embodiment, the insulating green paint is taken as an example for illustration. Other types of insulating layer materials are within the protection scope of the application. In preparation, the insulating green paint or resin is sprayed on the surface of the substrate 10, and the above material is cured to form the insulating layer 102 provided in the embodiment of the application. In this way, by arranging the insulating layer 102 on the surface of the substrate 10, on the one hand, the short circuit problem of different components can be avoided. On the other hand, the insulating layer 102 also has a certain thickness and strength. When other film layer structures are arranged on the insulating layer 102, the insulating layer 102 can support the film layer structures, thereby ensuring the stacking or transition between different film layers.

[0096] In the embodiment of the application, in the setting of the insulating layer 102, the thickness of the insulating layer 102 can be set to 10 um to 30 um. Optionally, the thickness of the insulating layer 102 can be set to any one of 10 um, 15 um, 20 um, 25 um, or 30 um. Alternatively, the thickness of the insulating layer 102 can be set to other thickness values according to the specifications of the substrate 10 and the size of the packaged chip. Here, the details are not described again.

[0097] Further, a protection layer 103 is arranged on the side of the insulation layer 102 away from the substrate 10. In the embodiment of the present application, the protection layer 103 is arranged at least partially on the insulation layer 102. When the packaged chip 108 is packaged, the protection layer 103 is first coated, and then the protection layer 103 is pressed to achieve the purpose of sealing. Specifically, the protection layer 103 is formed on the first surface of the substrate 10 and covers the packaged chip 108, such as covering the sidewall and the surface away from the substrate 10 of the surface acoustic wave filter chip. In this way, part of the inner side of the protection layer 103 and the bottom surface of the packaged chip 108, the side surface of the insulation layer 102, and the upper surface of the substrate 10 form a cavity 201. The cavity 201 is a closed cavity 201, thereby achieving the sealing of the packaged chip 108.

[0098] In the embodiment of the present application, when the protection layer 103 is arranged, the protection layer 103 is arranged as an insulation material layer, such as a high molecular or polymer film material. Specifically, in the embodiment of the present application, the protection layer 103 includes one or a combination of epoxy resin, polyimide resin, benzocyclobutene resin, polyurethane, polyethylene, polypropylene, polyolefin, polyamide, polyurethane, and polyvinyl alcohol. In the embodiment of the present application, the protection layer 103 is arranged as a plastic material. The plastic material has good fluidity. On the one hand, the adhesion between the protection layer 103 and the surface acoustic wave filter chip can be ensured when the packaged chip 108 is sealed. On the other hand, the plastic material is easier to form during the packaging and pressing process, thereby reducing the process difficulty.

[0099] Further, when the protection layer 103 is arranged, the film thickness of the protection layer 103 is set to 10-30 um. Specifically, the thickness of the protection layer 103 is set to one of 10 um, 15 um, 20 um, 25 um, and 30 um, or is set according to the specifications of the product and the size of the substrate to ensure that the device has high working performance after the packaging process is completed.

[0100] In the embodiment of the present application, the surface of the protective layer 103 away from the substrate 10 is further provided with a bonding portion 301. As shown in FIG. 9, the bonding portion 301 is bonded to the upper surface of the protective layer 103. When the bonding portion 301 is provided, the bonding portion 301 is arranged near the periphery of the cavity 201, for example, at least part of the bonding portion 301 is arranged near the edge of the encapsulated chip 108. Alternatively, the bonding portion 301 is arranged at the position of the bending area 21 of the protective layer 103, which is the area where the horizontal side of the protective layer 103 intersects with the vertical side, i.e., the position where the protective layer 103 gradually transitions from the horizontal plane to the vertical plane or the inclined plane. In the embodiment of the present application, the bonding portion 301 is arranged in the bending area 21. By arranging the bonding portion 301 in the area, on the one hand, the height difference between the film layers can be effectively reduced, and the transition is more gradual; on the other hand, by arranging more material in the bending area 21, the thickness of the protective layer 103 at the position relative to the cavity 201 is increased, and when the pressure is applied to the protective layer 103, the pressure threshold that the protective layer 103 can withstand is improved, thereby avoiding the risk of rupture of the protective layer 103 during the packaging process.

[0101] Further, when the protective layer 103 is arranged, the thickness of the protective layer 103 in the bending area 21 is greater than or equal to the thickness of the protective layer 103 in other areas. In this way, the performance of the film layer in the bending area 21 can be further improved, and the problem of material flowing into the cavity 201 due to rupture during the packaging process can be avoided, thereby avoiding the problem of contamination of the encapsulated chip 108.

[0102] Further, in the embodiment of the present application, the bonding portion 301 can be made of a plastic material, for example, the bonding portion 301 includes non-conductive glue, green paint, silicone, polyurethane, polyethylene, polypropylene, polyolefin, polyamide, polyurethane, or other polymer materials.

[0103] In the embodiment of the present application, when the protective layer 103 and the bonding portion 301 are arranged, at least the protective layer 103 or the bonding portion 301 is arranged as an insulating member. Alternatively, the protective layer 103 is arranged as a polymer film, and the bonding portion 301 is arranged as a silicone material. In this way, by arranging the protective layer 103 and the bonding portion 301 as polymer materials with good plasticity, on the one hand, the process difficulty during packaging can be reduced, and on the other hand, the plastic insulating material can better form a sealing effect, thereby improving the performance of the device. At the same time, in the present application, the bonding portion 301 is arranged in the bending area 21 of the protective layer 103, and the bonding portion 301 can effectively protect the protective layer 103 in the area, thereby avoiding the problem of material flowing into the cavity 201 due to rupture of the film layer in the area during the film coating and packaging processes, and causing contamination of the encapsulated chip 108.

[0104] As shown in FIG. 9, the protective layer 103 is arranged along the second direction X and the first direction Y. In some embodiments, the second direction X can be defined as a horizontal direction, for example, the surface of the substrate 10 corresponds to the horizontal direction as the second direction X, and the direction intersecting with the second direction X is defined as the first direction Y. Optionally, the first direction Y can be a vertical direction, for example, along the thickness direction of the film layer.

[0105] As shown in FIG. 9, in some embodiments, the protective layer 103 includes a second outer side surface 1031 and a first outer side surface 1032 connected with the second outer side surface 1031. The second outer side surface 1031 is arranged along the second direction X, and the first outer side surface 1032 is arranged along the first direction Y. Both the second outer side surface 1031 and the first outer side surface 1032 are away from one side of the substrate 10. Specifically, the second outer side surface 1031 can be arranged parallel to the surface of the substrate 10, and the first outer side surface 1032 is arranged obliquely relative to the second outer side surface 1031, for example, vertically relative to the second outer side surface 1031. In some embodiments, the first outer side surface 1032 is actually four side surfaces in different directions, for example, when the packaged chip 108 is in a rectangular structure, one of the first outer side surfaces 1032 is arranged in each of the four different directions of the packaged chip 108. Similarly, the second outer side surface 1031 is the upper surface of the protective layer 103, which will not be described here.

[0106] In some embodiments, the bonding part 301 is bonded with both the second outer side surface 1031 and the first outer side surface 1032. The bonding part 301 is arranged at least in the bending area 21. In this way, the bonding part 301 can be closely bonded with the second outer side surface 1031, and the second outer side surface 1031 can support and fix the bonding part 301. In addition, the first outer side surface 1032 can also strengthen the protective layer 103 in the area opposite to the cavity 201, so as to prevent the first outer side surface 1032 from being broken during the packaging process, and to prevent the chip in the cavity 201 from being contaminated, thereby improving the packaging effect.

[0107] Further, along the second direction X, the thickness of the bonding part 301 close to the packaged chip is greater than the thickness of the bonding part 301 away from the packaged chip. In this way, the bonding part 301 close to the cavity 201 has a certain thickness, thereby better preventing the film layer from being broken.

[0108] In an embodiment of the present application, as shown in the structure of FIG. 9, when the bonding part 301 is arranged, the bonding part 301 has a bonding length H1 on the second outer side 1031 in the second direction X, and has a bonding length H2 on the first outer side 1032 in the first direction Y, where H2≤H1. Alternatively, the bonding lengths of the two are arranged as the same length. In this way, the length of the coverage area of the bonding part 301 on the first outer side 1032 can be ensured, so as to ensure the protection of the protective layer 103 in this direction and avoid the breakage of the protective layer 103.

[0109] As shown in FIG. 11, which is a schematic cross-sectional view of another chip packaging structure provided in an embodiment of the present application, in combination with the structure of FIG. 9-2, in the present application, when the insulating layer 102 is arranged, the insulating layer 102 is arranged on the surface of the substrate 10, and part of the insulating layer 102 is located in the cavity 201, and part of the protective layer 103 is arranged on the insulating layer 102.

[0110] Further, in combination with FIG. 9, in an embodiment of the present application, the height between the bottom surface of the packaged chip 108 and the surface of the substrate 10 is defined as the cavity height, which is arranged as H3. Meanwhile, the thickness of the insulating layer 102 in the first direction is arranged as H4, the thickness of the protective layer arranged on the insulating layer 102 is arranged as H5, and the height of the bonding part 301 in the first direction is arranged as H6.

[0111] In an embodiment of the present application, H4+H5<H3. Alternatively, in an embodiment, the cavity height H3=40um, and the corresponding H4=18um and H5=15um. At this time, with the same plane as the reference, the top of the cavity exceeds the sum of the heights of the insulating layer 102 and the protective layer 103. In the first direction Y, the protective layer 103 will have a spacing D with the top of the cavity 201. Due to the existence of the spacing D, when a large pressure is applied in the chip packaging process, the protective layer 103 corresponding to the spacing D is prone to breakage, thereby causing the material of the outer layer to flow into the cavity 201 through the spacing D, resulting in pollution.

[0112] Further, when the heights of the above-mentioned parts are arranged, |H5+H4+H2-H3|≤10um, and in an embodiment, H3≤H2+H4+H5. At this time, as shown in FIG. 9, the height of the bonding part 301 is higher, which can completely cover the spacing D.

[0113] In the embodiment of the present application, the bonding portion 301 is arranged outside the protective layer 103, and in an embodiment, the bonding portion 301 completely covers the interval D. At this time, the height of the bonding portion 301 is greater than D, that is, in the first direction Y, the plane where the top end of the bonding portion 301 is located is higher than the bottom surface of the packaged chip 108. Alternatively, the plane where the top end of the bonding portion is located is between the bottom surface of the packaged chip 108 and the top surface of the packaged chip 108. For details, see the height of the bonding portion 108 in FIG. 9. In this way, the bonding portion 301 can completely cover the protective layer 103 corresponding to the interval D and protect it to prevent the film layer in this region from being broken and avoid contamination in the chip.

[0114] In another embodiment, as shown in FIG. 11, in the first direction, H3≥H2+H4+H5. At this time, the height of the bonding portion 301 is small, and the bonding portion 301 cannot completely cover the protective layer 103 corresponding to the interval D.

[0115] Alternatively, 0.5H3≤H2+H4+H5≤H3, at this time, the height of the top end of the bonding portion 301 in the first direction Y is controlled to be at least greater than 0.5H3, such as H2+H4+H5=0.75H3, which can effectively ensure that the protective layer 103 in the interval D region will not be broken during packaging, so that the material flows into the cavity 201. Thus, the packaging performance of the device is ensured.

[0116] Further, in the embodiment of the present application, when the bonding portion 301 is arranged, the cross-sectional shape of the bonding portion 301 can be arranged as any one of an arc shape, a triangular shape, a trapezoidal shape, and a polygonal shape, such as the cross-sectional shape of the bonding portion 301 arranged as an arc shape in FIG. 11, and the arc shape can be arranged according to actual needs. The shape in the present application is only an example. Alternatively, the curvature of the arc-shaped cross section gradually decreases from the top to the bottom of the bonding portion 301, so that the surface of the bonding portion 301 has a gradually transitioned arc-shaped structure. In this way, when other film layers are prepared on the bonding portion 301 subsequently, the internal stress formed can be avoided, and thus the performance of the packaged chip is improved.

[0117] For details, see FIG. 11, in the embodiment of the present application, when the height of the top end of the bonding portion 301 does not exceed the height of the top of the cavity 201, the bonding portion 301 further comprises at least one recessed portion 302, wherein the recessed portion 302 can be arranged at the middle position of the bonding portion 301.

[0118] At this time, the bonding part 301 comprises the recessed part 302, and on both sides of the recessed part 302, the bonding part 301 comprises a first sub-section 3011 and a second sub-section 3012. The first sub-section 3011 is arranged on the side away from the cavity 201, and the first sub-section 3011 is arranged on the first side of the protective layer 103. The second sub-section 3012 is arranged at a position between the first sub-section 3011 and the cavity, and the second sub-section 3012 is at least partially arranged on the first outer side of the protective layer 103. In the embodiment of the present application, since the second sub-section 3012 is closer to the side of the cavity 201, the film thickness of the second sub-section 3012 is greater than or equal to the film thickness of the first sub-section 3011, so that the second sub-section 3012 can better protect the protective film 103 to prevent the cavity 201 from being contaminated.

[0119] In this way, when the plastic sealing layer 50 is continuously arranged on the protective layer 103 and the bonding part 301, the recessed part 302 is recessed towards the surface of the protective layer 103. When pressure is applied during packaging, the material of the plastic sealing layer 50 flows to a certain extent, which first tends to flow near the recessed part 302 and fill it, and the recessed part 302 can also play a role in distributing pressure during the pressing process, effectively sharing the film layer pressure at the position not bonded by the bonding part 301, so that the uncovered protective layer 103 at the top end region of the bonding part 301 bears less pressure. In this way, in the embodiment of the present application, the problem of rupture of the protective layer 103 at the cavity 201 is avoided by redistributing the pressure.

[0120] Further, in the embodiment of the present application, since the recessed part 302 is arranged on the bonding part 301, the recessed part 302 further enhances the contact and packaging effect of the plastic sealing layer 50, and under the same packaging pressure, the length and area of the insulating layer 102 can be effectively reduced. In this way, the volume occupied by each packaged chip can be further reduced, thereby realizing the miniaturization of the packaged chip.

[0121] In the embodiment of the present application, by means of the above-mentioned recessed part 302, the protective layer 103 can be effectively prevented from being ruptured under the premise of reducing the amount of the bonding part 301, thereby improving the packaging effect and performance.

[0122] As shown in FIG. 12, FIG. 12 is a cross-sectional view of a bonding part provided in an embodiment of the present application. In combination with the film layer structure in FIGS. 9-11, the bonding part 301 further comprises a micropore 404 in the embodiment of the present application. The micropore 404 is arranged on at least the first sub-section 3011 or the second sub-section 3012.

[0123] Specifically, the micropores 404 can include first micropores 1041 and second micropores 1042, the first micropores 1041 are arranged on the first sub-section 3011, and the second micropores 1042 are arranged on the second sub-section 3012. The first micropores 1041 can be arranged along the side away from the cavity 201, and the second micropores 1042 can be arranged obliquely relative to the first micropores 1041, such as the second micropores 1042 arranged along the thickness direction of the packaged chip corresponding to the first direction Y.

[0124] In the embodiments of the present application, the first micropores 1041 and the second micropores 1042 can be arranged separately, such as arranging only the first micropores 1041 on the bonding portion 301, or arranging only the second micropores 1042 on the bonding portion 301, or arranging both micropores on the bonding portion 301. In the following examples, both micropores are arranged as an example, and other examples are within the protection scope of the present application.

[0125] As shown in FIG. 12, in the embodiments of the present application, at least part of the micropores 404 penetrates the bonding portion 301. Specifically, part of the micropores 404 penetrates from the top of the bonding portion 301 to the bottom, thereby forming a penetrating micropore inside the bonding portion 301. At the same time, there are a certain number of micropores that do not penetrate in the bonding portion 301. When pressure is applied during packaging and a plastic encapsulation layer 50 is arranged on the bonding portion 301, the micropores 404 will form flow channels, and part of the plastic encapsulation material will flow under the guidance of the micropores 404. In the embodiments of the present application, at least part of the micropores 404 has an opening away from the cavity side, such as the micropore structure in FIG. 12. When the plastic encapsulation material flows along the micropores under the action of pressure, the micropores 404 will decompose or disperse the force originally acting in the direction of the cavity, thereby changing the stress on the protective layer 103 in the area not covered by the bonding portion 301, avoiding the protective layer 103 in this area from being broken and causing the material to flow into the cavity due to the large pressure during the packaging process. In the embodiments of the present application, the bonding portion 301 can effectively improve the pressure threshold applied during packaging, thereby improving the packaging effect.

[0126] In the embodiment of the present application, when the micropores 404 are arranged, the top of the bonding part 301 does not completely cover the corresponding protective layer 103 at the cavity area, so the protective layer 103 near the top of the bonding part 301 is more likely to be broken under the action of pressure. In the embodiment of the present application, when the second micropores 1042 on the second sub-section 1042 of the bonding part 301 are arranged, the second sub-section 1042 includes an inclined side surface 308, wherein the inclined side surface 308 is arranged near the top of the side surface 308. The first height of the inclined side surface 308 is used as a reference line, and the micropores and the corresponding openings are not arranged on the inclined side surface 308 above the reference line, while the micropores and the corresponding openings are arranged on the inclined side surface 308 below the reference line. In this way, there is no second micropore 1042 facing the side wall direction, and when pressure is applied, there is no pressure acting on the side of the cavity 201, thereby reducing the pressure on the membrane layer on the side wall of the cavity 201, and avoiding the breakage of the membrane layer.

[0127] Further, in the embodiment of the present application, when the micropores 404 are arranged, the aperture of the second micropore 1042 is greater than or equal to the aperture of the first micropore 1041. In this way, the second micropore 1042 with a larger aperture can better share the side pressure of the membrane layer on the second sub-section 3012, thereby reducing the force acting on the protective layer 103, and preventing the breakage of the protective layer 103.

[0128] In the embodiment of the present application, when the micropores 404 are arranged, the second micropore 1042 can be one-to-one corresponding to the first micropore 1041, or multiple first micropores 1041 are connected to the same second micropore 1042, and the number of the first micropores 1041 is greater than or equal to the number of the second micropores 1042. In this way, the material flowing into the second micropore 1042 will continue to flow from the multiple first micropores 1041, thereby reducing the flow resistance of the material in the micropore, and further improving the pressure at the bonding part 301 and the side wall of the cavity 201, thereby avoiding the breakage of the membrane layer in the stress-weak area, and preventing the problem of the encapsulation material flowing into the cavity and polluting the chip, thereby causing the chip to fail.

[0129] Further, as shown in FIG. 12, when the second micropore 1042 is arranged, the second micropore 1042 is arranged obliquely relative to the first micropore 1041, and the outlet of the second micropore 1042 can be arranged on the top surface of the second sub-section 3012. In this way, the material can directly flow downward through the second micropore 1042, or the lateral force during plastic packaging can be directed downward, so as to avoid the pressure on the side wall of the cavity 201.

[0130] In the embodiment of the present application, when the micropores 404 are arranged, the number of micropores on each bonding part is not specifically limited. The micropore structure is used to improve the pressure distribution in the film layer during packaging, thereby effectively avoiding the problem that the film layer in the stress-weak area of the cavity 201 is prone to rupture, and thereby improving the packaging effect and performance.

[0131] Optionally, in the embodiment of the present application, the bonding part 301 can also be arranged as a three-dimensional mesh hole structure. The three-dimensional mesh hole structure is distributed with a plurality of mesh holes in different directions, and the mesh holes in each direction are cross-linked with each other, thereby forming a cross-linked structure. When other plastic packaging materials are arranged above the three-dimensional mesh hole structure, the plastic packaging materials will flow in the three-dimensional mesh hole structure, and the three-dimensional mesh hole structure can further improve or redistribute the pressure in the film layer, thereby effectively avoiding the problem that the film layer in the stress-weak area is prone to rupture. At the same time, since the bonding part 301 is arranged with a plurality of micropores, the micropores can also play an adsorption role. When other plastic packaging layers 50 are continuously arranged on the bonding part 301, the micropores can increase the contact area between the plastic packaging layer 50 and the bonding part 301, thereby improving the bonding effect of the two, and at the same time, since the bonding part 301 can also protect the outer side of the protective layer 103 from direct contact, the micropores can also effectively improve the bonding effect between the bonding part 301 and the protective layer 103, thereby preventing the problem that the film layers are prone to warping or packaging failure after packaging.

[0132] As shown in FIG. 13, which is a schematic diagram of another chip packaging structure provided in the embodiment of the present application, in combination with the film layer in FIG. 9-4, when the packaging structure is arranged, compared with the first sub-section 3011 and the second sub-section 3012 in FIG. 12, the first sub-section 3011 and the second sub-section 3012 in FIG. 12 are not arranged in a stacked manner, and in the embodiment of the present application, the bonding part 301 can also be arranged as a stacked structure, as shown in detail in FIG. 13, the bonding part 301 further includes a third sub-section 3013 and a fourth sub-section 3014. Among them, the third sub-section 3013 and the fourth sub-section 3014 are partially arranged in a stacked manner, that is, at least part of the fourth sub-section 3014 is arranged on the third sub-section 3013 in the first direction Y.

[0133] Specifically, in the setting, the third sub-section 3013 is arranged on the side close to the packaged chip 108, and the third sub-section 3013 is simultaneously attached to the first outer side surface 1032 and the second outer side surface 1031, the bottom surface of part of the fourth sub-section 3014 is arranged on the first outer side surface 1032, and part of the fourth sub-section 3014 is arranged on the side wall of the third sub-section 3013, so that the two are partially laminated. In the embodiment of the present application, since the fourth sub-section 3014 and the third sub-section 3013 are at least partially laminated, the thickness or height of the attachment part 301 is increased, and when the plastic packaging layer 50 is continuously arranged, the laminated structure can further improve the protection effect of the protection layer 103 corresponding to the region of the cavity 201, thereby avoiding the protection layer 103 in this region from being broken during the packaging process, so as to improve the packaging effect. In the embodiment of the present application, the number of laminations can be set according to actual needs, and is not limited to two layers of structure, and other numbers of laminated structures are within the protection scope of the present application. When the third sub-section 3013 and the fourth sub-section 3014 are arranged, corresponding micropore structures can be arranged in at least one sub-section. Optionally, micropore structures are arranged in the third sub-section 3013 and the fourth sub-section 3014, and the micropores in the third sub-section 3013 and the fourth sub-section 3014 are in communication with each other, so as to improve the flow and pressure of the material in the two different sub-sections through the micropore structures in the two different sub-sections, and improve the packaging effect. Further, or no micropore structure is arranged in the two sub-sections, and the above different structures are within the protection scope of the present application.

[0134] Further, in the embodiment of the present application, when the third sub-section 3013 and the fourth sub-section 3014 are arranged, the fourth sub-section 3014 can also completely wrap the third sub-section 3013, at this time, the height of the fourth sub-section 3014 in the first direction Y can be greater than or equal to the height of the third sub-section 3013, so as to further improve the reliability of the packaging by arranging laminated multiple attachment parts.

[0135] As shown in FIG. 14, FIG. 14 is a top view of a chip packaging structure provided in the embodiment of the present application. In combination with the structures in FIGS. 9-12, in the embodiment of the present application, when the attachment part 301 is arranged, the attachment part 301 can be arranged at least one circle around the packaged chip 108. As shown in FIG. 14, a circle of attachment parts 301 is arranged around the packaged chip 108, and the attachment part 301 is simultaneously attached to the second outer side surface 1031 and the first outer side surface 1032 of the protection layer 103.

[0136] In the setting, the width of the bonding part 301 on different outer sides can be set according to the above examples, which will not be repeated here. At the same time, in the setting of the bonding part 301, it can be set by the dispensing process or the spraying process. The adhesive material is coated at the corresponding position of the protective layer 103 by the dispensing process, and finally a ring of the bonding part 103 is formed. As shown in FIG. 14, the bonding part 301 is arranged around the periphery of the package chip 108, and is arranged as a continuous ring. FIG. 14 is a top view, and the specific structure can be set according to the above description of the bonding part.

[0137] Further, in the setting of the bonding part 301, two rings can also be set. At this time, the bonding part 301 includes a first inner ring 3031 and a first outer ring 3032. The first inner ring 3031 is arranged on the side close to the cavity 201, and the first outer ring 3032 is arranged on the side away from the cavity of the first inner ring 3031. At this time, the first inner ring 3031 is arranged on the second outer side and the first outer side, and the first outer ring 3032 is arranged on the second outer side. In this way, by setting two rings of the bonding part, and the height of the bonding part of the first outer ring 3032 is less than or equal to the height of the first inner ring 3031, so that a height difference is formed between the two bonding parts of different heights, which improves the bonding effect of the plastic sealing layer 50, and further improves the packaging performance.

[0138] In the embodiment of the application, the first inner ring 3031 can be arranged as a continuous ring, the first outer ring 3032 can be arranged as a continuous ring, or the first outer ring 3032 is arranged as a separated multi-segment structure with gaps between the multi-segment structure. At this time, the first outer ring 3032 includes a plurality of discontinuous sub-segments, and the distance between the adjacent two sub-segments can be set as the same distance value. When the plastic sealing layer 50 is arranged on the protective layer 103 and the bonding part 301, the plastic sealing layer 50 will cover the first inner ring 3031 and the first outer ring 3032, and because the gaps are arranged between the sub-segments of the first outer ring 3032, the corresponding material of the plastic sealing layer 50 will be bonded to the protective layer 103 through the gap, thereby increasing the bonding effect between the two layers.

[0139] Further, in the embodiment of the application, the bonding part 301 can also include a transition ring. In combination with the structure in FIG. 14, the transition ring is not specifically shown, and the transition ring is arranged in the blank area between the first inner ring 3031 and the first outer ring 3032, and the transition ring is arranged around the first inner ring 3031. Optionally, the transition ring can be continuously arranged, or the transition ring is arranged as a separated multi-segment.

[0140] In the embodiment of the present application, since the first inner ring 3031, the transition ring and the first outer ring 3032 are directly arranged on the protection layer 103, in order to improve the bonding effect and sealing performance of the subsequent plastic sealing layer 50 and the protection layer 103 and the bonding part 301, the bonding parts at different positions are differentially arranged in the embodiment of the present application: the height of the transition ring is less than the height of the first inner ring 3031 and the first outer ring 3032, and the height of the first inner ring 3031 is greater than the height of the first outer ring 3032. In this way, the bonding parts at different regions are arranged at different heights, which can improve the material flow of the plastic sealing layer on one hand, so that it has better fixing effect and does not shift, and on the other hand, the fixing effect of the bottom protection layer can also be improved by arranging multiple bonding parts 301 at different positions.

[0141] Further, the plastic sealing layer 50 is further arranged on the protection layer 103 and the bonding part 301, wherein the plastic sealing layer 50 can be prepared by injection molding or other film coating process, and the plastic sealing layer 50 can be made of one or more of resin materials such as epoxy resin, polybutylene terephthalate, polyimide resin, benzocyclobutene resin, polyamide or high molecular plastic material. In the embodiment of the present application, the thickness of the plastic sealing layer 50 can be set to 80-150 um, and optionally, the thickness of the plastic sealing layer 50 is set to 85 um according to the requirements of different products.

[0142] As shown in FIG. 15, FIG. 15 is another packaging structure provided in the embodiment of the present application. In combination with the above-mentioned other drawings, in the embodiment of the present application, when the bonding part 301 is arranged, the bonding part 301 further comprises an extension branch 1033. The extension branch 1033 is arranged in the second direction away from the cavity 201, and the extension branch 1033 is arranged on the second outer side. In the embodiment of the present application, the extension branch 1033 can be arranged in a strip structure or a wave structure. Preferably, the extension branch 1033 is arranged in a wave structure, so that the extension branch has a longer length. When the plastic sealing layer 50 is further arranged on the extension branch 1033, the first inner ring 1031 and the first outer ring 1032, the wave-shaped extension branch 1033 can further increase the contact area with the two side film layers, thereby improving the packaging effect.

[0143] Further, when the extension branch 1033 is arranged, one end of the extension branch 1033 can be connected with the first inner ring 1031, and the other end can be connected with or not connected with the first outer ring 1032, and the extension branch 1033 can be arranged on the side of the first inner ring 1031 away from the cavity 201. Optionally, the two ends of the extension branch 1033 are respectively connected with the first inner ring 1031 and the first outer ring 1032.

[0144] Meanwhile, in order to improve the packaging effect and further reduce the pressure on the film layer on the side wall of the cavity during packaging, the third micropore is further arranged in the extension branch 1033, which is not shown in the figure. The third micropore structure can be arranged by referring to the structure of the first micropore 1041 and the second micropore 1042, which will not be described here. Some of the third micropores are in communication with the second micropore 1042 or the first micropore 1041, so that the pressure distribution on the film layer is improved through the micropore during the packaging process, thereby avoiding the problem that the protective layer on the side wall of the cavity is easily broken, and improving the packaging effect.

[0145] In the embodiment of the application, when the fitting part 301 is arranged, the modulus of the fitting part 301 is less than or equal to the modulus of the protective layer 103, or the strength or hardness of the fitting part 301 is less than or equal to the strength or hardness of the protective layer 103. Thus, since the strength of the fitting part 301 is lower than that of the protective layer 103, the fitting part 301 will not damage the protective layer after being pressed, and at the same time, the packaging effect and performance of the chip can be effectively improved or enhanced.

[0146] Further, in the embodiment of the application, the first sub-section has a first viscosity, and the second sub-section has a second viscosity, wherein the first viscosity is less than the second viscosity. Thus, the first sub-section 1041 can be more closely fitted with the protective layer 103, and displacement and other problems will not occur during the pressing process, thereby ensuring the packaging effect of the chip provided in the embodiment of the application.

[0147] As shown in FIG. 16, which is a schematic diagram of another packaging structure provided in the embodiment of the application. In combination with other figures, in the embodiment of the application, when the fitting part 301 is arranged, in addition to the fitting part 301 arranged on the first outer side surface 1032 and the second outer side surface 1031, the fitting part 301 can also be arranged on other outer side surfaces of the protective layer 103, such as the fitting part 301 arranged on the upper surface 206 of the protective layer 103. At this time, the protective layer 103 can be arranged at least at the edge of the upper surface 206, and when arranged, a plurality of different fitting parts 301 can be arranged on the upper surface 206 according to product requirements. The above different distribution structures are within the protection scope of the application.

[0148] Optionally, a plurality of adjacent fitting parts 301 are arranged on the upper surface 206, and the spacing between the adjacent two fitting parts 301 is the same, and the height of the fitting part 301 near the edge of the upper surface 206 is greater than or equal to the height of the fitting part 301 in other regions. Thus, by arranging a plurality of fitting parts 301 on the upper surface 206, the fitting effect of the protective layer 103 can be further enhanced, and the plastic packaging effect and the stability after packaging can be further improved when the plastic packaging layer 50 is prepared.

[0149] As shown in FIG. 17, FIG. 17 is another schematic diagram of the packaging structure provided in the embodiments of the present application. In combination with FIGS. 9-15, the packaging structure further comprises a functional chip 109 when the packaging structure is set. The functional chip 109 is arranged on one side of the packaging chip 108, for example, on at least one side of the surface acoustic wave filter chip. In the embodiments of the present application, a protective layer 103 can be arranged on or around the functional chip 109 when the functional chip 109 is set, or the protective layer 103 can not be arranged according to the requirement. When the protective layer 103 is not arranged, the plastic encapsulation layer 50 is directly arranged on the functional chip 109 to seal the functional chip 109.

[0150] Further, in the embodiments of the present application, when the surface acoustic wave filter chip and the non-filter functional chip 109 are arranged in the packaging structure at the same time, the functional chip 109 will have an adverse effect on the packaging of the packaging chip 108 in the packaging process, for example, the packaging chip 108 region will be prone to have a problem of loose packaging after the packaging. In the embodiments of the present application, the volume of the bonding portion 301 on the side close to the functional chip 109 is greater than the volume of the bonding portion on the side far from the functional chip 109.

[0151] Specifically, the height of the bonding portion 301 on the side close to the functional chip 109 can be greater than the height of the bonding portion 301 on the side far from the functional chip 109. For example, in the structure shown in FIG. 15, the bonding portions are arranged on the four side edges of the packaging chip 108, and the side edge close to the functional chip 109 is the first side edge. The heights of the bonding portions arranged on the other three side edges are the same and are less than the height of the bonding portion 301 on the first side edge. In this way, by increasing the height of the bonding portion on the side close to the functional chip 109, the problem of the effect of the arrangement of the functional chip 109 on the packaging effect in the region is reduced, and the packaging chip 108 has the same packaging effect at different positions around the packaging chip 108.

[0152] Further, when the functional chip 109 is arranged, the functional chip 109 and the packaging chip 108 can be arranged on the same side of the substrate 10, or the functional chip 109 and the packaging chip 108 can be arranged on the two sides of the substrate 10. Specifically, the arrangement can be set according to the use requirement of different products, which is not limited herein.

[0153] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed in the present application, and these modifications or replacements should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that, include: substrate; A solder resist layer is disposed on the substrate and has a first opening; The filter chip is mounted on the substrate through the first window; A first blocking portion covers at least a portion of the side surface of the filter chip and is in at least partial contact with the surface of the solder resist layer opposite to the substrate, thereby forming a cavity structure between the filter chip and the substrate; a molding compound layer covers the filter chip, the first blocking portion, and the solder resist layer; The second blocking portion is disposed on the filter chip and located on the first surface of the filter chip, the first surface facing the substrate; Wherein, a portion of the first blocking portion is located between the second blocking portion and the solder resist layer; the projection of the second blocking portion on the substrate at least partially overlaps with the projection of the solder resist layer on the substrate.

2. The chip packaging structure according to claim 1, characterized in that, The projection of the second blocking portion onto the substrate is located at the projection of the solder resist layer onto the substrate.

3. The chip packaging structure according to claim 1, characterized in that, The second blocking portion includes an overlapping portion and a non-overlapping portion connected to the overlapping portion. The non-overlapping portion extends from the overlapping portion toward the cavity structure. The projection of the overlapping portion onto the substrate overlaps with the projection of the solder resist layer onto the substrate. The projection of the non-overlapping portion onto the substrate is located outside the projection of the solder resist layer onto the substrate.

4. The chip packaging structure according to claim 1, characterized in that, The distance between the second blocking portion and the solder resist layer along the thickness direction of the substrate ranges from 1µm to 10µm.

5. The chip packaging structure according to claim 1, characterized in that, The sum of the heights of the second blocking portion and the solder resist layer along the thickness direction of the substrate is less than or equal to the height of the first protrusion of the filter chip.

6. The chip packaging structure according to claim 1, characterized in that, The modulus of the second blocking portion, the solder resist layer, and the first blocking portion is all less than the modulus of the filter chip, and the modulus of the first blocking portion is less than the modulus of the molding compound layer; or the modulus of the first blocking portion is less than at least one of the modulus of the second blocking portion and the modulus of the solder resist layer.

7. The chip packaging structure according to claim 1, characterized in that, The first blocking part includes: The first part is located outside the cavity structure, covers at least a portion of the side surface of the filter chip, and is in at least partial contact with the surface of the solder mask layer opposite to the substrate; The second part is at least partially disposed between the second blocking portion and the solder resist layer, and the inner sidewall of the second blocking portion is closer to the chip element of the filter chip than the second part.

8. The chip packaging structure according to claim 7, characterized in that, The surface of the solder resist layer that contacts the second part is a rough surface.

9. The chip packaging structure according to claim 7, characterized in that, The inner wall of the second blocking portion is closer to the chip element of the filter chip than the second portion.

10. The chip packaging structure according to claim 7, characterized in that, The second portion extends into the cavity structure, and the chip packaging structure has at least one of the following features: The second portion extending into the cavity structure is located on the side of the solder resist layer at the first opening; The second portion extending into the cavity structure contacts the substrate at the cavity structure.

11. The chip packaging structure according to any one of claims 1-10, characterized in that, The second blocking portion has an annular shape.

12. The chip packaging structure according to any one of claims 1-10, characterized in that, The material of the first blocking part includes at least one of the following: adhesive material, green oil; the material of the second blocking part includes at least one of the following: dry film, polyimide.

13. The chip packaging structure according to any one of claims 1-10, characterized in that, Also includes: A non-filter chip is disposed on the substrate at a distance from the filter chip, and the molding layer covers the non-filter chip.

14. A chip packaging structure, characterized in that, include: substrate; A solder resist layer is disposed on the substrate and has a first opening; The filter chip is mounted on the substrate through the first window; A first blocking portion covers at least a portion of the side surface of the filter chip and is in at least partial contact with the surface of the solder resist layer opposite to the substrate, thereby forming a cavity structure between the filter chip and the substrate; a molding compound layer covers the filter chip, the first blocking portion, and the solder resist layer; The second blocking part is disposed on the filter chip; In this configuration, a portion of the first blocking portion is located between the second blocking portion and the solder resist layer; the filter chip, the second blocking portion, and the substrate are arranged in the thickness direction, and the second blocking portion and the substrate have a gap in the thickness direction of the substrate.

15. The chip packaging structure according to claim 14, characterized in that, The projection of the second blocking portion on the substrate at least partially overlaps with the projection of the solder resist layer on the substrate.

16. The chip packaging structure according to claim 15, characterized in that, The projection of the second blocking portion on the substrate is offset from the projection of the solder resist layer on the substrate.

17. The chip packaging structure according to claim 15, characterized in that, The area of ​​the first window is smaller than the projected area of ​​the filter chip on the substrate.

18. The chip packaging structure according to claim 17, characterized in that, The area of ​​the first window is greater than or equal to the projected area of ​​the filter chip on the substrate.

19. A chip packaging structure, characterized in that, include: A substrate, including at least pads; a packaged chip, electrically disposed on the substrate; A protective layer, the protective layer covering the packaged chip, and a portion of the protective layer being disposed on the substrate, the protective layer, the packaged chip, and the substrate forming a cavity, the protective layer including a first outer side disposed along a first direction, a second outer side disposed along a second direction intersecting the first direction, and a molding layer disposed on the side of the protective layer away from the substrate; The chip packaging structure further includes a bonding portion and solder joints. The bonding portion is disposed on the protective layer, the molding layer covers the bonding portion, and the number of solder pads is greater than or equal to the number of solder joints. The first outer side is correspondingly disposed around the packaged chip, the bonding portion is disposed on the first outer side and the second outer side, and at least the protective layer or the bonding portion is configured as an insulating element.

20. The chip packaging structure according to claim 19, characterized in that, In the second direction, the bonding length of the bonding portion on the second outer side is H1, and in the first direction, the bonding length of the bonding portion on the first outer side is H2. Wherein, H2≤H1, and the second direction intersects with the first direction.

21. The chip packaging structure according to claim 19, characterized in that, The bonding portion includes a first inner ring and a first outer ring disposed on the side of the first inner ring away from the cavity; wherein, the bonding portion corresponding to the first inner ring is disposed on the second outer side surface and the first outer side surface of the protective layer, and the first outer ring is disposed on the second outer side surface; wherein, the first inner ring is continuously disposed around the packaged chip, and the first outer ring is disposed in multiple separate segments around the first inner ring.

22. The chip packaging structure according to claim 21, characterized in that, The fitting portion further includes a transition ring disposed between the first inner ring and the first outer ring; The transition ring is segmented, and the height of the transition ring is less than the height of the first inner ring and the first outer ring, while the height of the first inner ring is greater than the height of the first outer ring.

23. The chip packaging structure according to any one of claims 19-22, characterized in that, The chip packaging structure further includes an insulating layer disposed on the surface of the substrate, and a portion of the insulating layer is located within the cavity; Wherein, along the first direction, the cavity height is set to H3, the insulation layer height is set to H4, and the thickness of the protective layer disposed on the insulation layer is H5; Wherein, H5+H4<H3, and |H5+H4+H2-H3|≤10um.

24. The chip packaging structure according to claim 19, characterized in that, Along the first direction, the plane containing the top end of the bonding portion is located between the bottom surface and the top surface of the packaged chip; Wherein, 0.5H3≤H2+H4+H5≤H3.

25. The chip packaging structure according to claim 19, characterized in that, The fitting portion further includes a first sub-segment and a second sub-segment, wherein the first sub-segment is disposed on the side away from the cavity, and the second sub-segment is disposed between the cavity and the first sub-segment; Micropores are provided on at least the first sub-segment or the second sub-segment.

26. The chip packaging structure according to claim 25, characterized in that, The thickness of the first sub-segment is less than or equal to the thickness of the second sub-segment, and the first micro-hole is also provided on the side of the first sub-segment away from the packaged chip.

27. The chip packaging structure according to claim 25, characterized in that, The second sub-segment is provided with a second micro-hole, wherein the second micro-hole is disposed toward the thickness direction of the packaged chip, and at least a portion of the second micro-hole is in communication with the first micro-hole.

28. The chip packaging structure according to claim 19, characterized in that, The fitting portion further includes a plurality of extension branches, which are disposed on the second outer side surface along a second direction away from the cavity; The extension branch is provided with a third micropore, and part of the third micropore is in communication with the second micropore.

29. The chip packaging structure according to claim 19, characterized in that, The bonding portion further includes a third sub-segment and a fourth sub-segment stacked together; The third sub-segment is disposed on the side close to the cavity, and the fourth sub-segment is disposed on the side of the third sub-segment away from the cavity, and the third sub-segment and the fourth sub-segment are partially stacked in the first direction.

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