Array substrate, display panel and display apparatus

Abstract

The present disclosure provides an array substrate, a display panel and a display apparatus. The array substrate comprises: a base substrate; a plurality of binding terminals, located on the base substrate; a plurality of first adapter structures, located on the side of a layer, where said binding terminals are located, away from the base substrate, said first adapter structures being electrically connected to said binding terminals; and a plurality of signal lines, located on the side of said layer away from the base substrate, wherein orthographic projections of said signal lines on the base substrate intersect with orthographic projections of said binding terminals on the base substrate, and the orthographic projections of said signal lines on the base substrate do not overlap orthographic projections of connection positions of said first adapter structures and said binding terminals on the base substrate.

Description

Array substrate, display panel and display device

[0001] Cross-reference to Related Applications

[0002] This application claims priority to the Chinese Patent Application No. 202410831123.3, filed on June 25, 2024, and entitled "Array substrate, display panel and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to an array substrate, a display panel and a display device. BACKGROUND

[0004] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high picture quality, no radiation and portability, and has developed rapidly in recent years. It has gradually replaced the traditional Cathode Ray Tube display (CRT) and dominates the current flat panel display market. Currently, TFT-LCD has been widely used in various large, medium and small size products, and almost covers the main electronic products in today's information society, such as liquid crystal televisions, high-definition digital televisions, computers (desktop and notebook), mobile phones, tablet computers, navigation instruments, vehicle-mounted displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, instruments, public displays and virtual reality displays, etc. SUMMARY

[0005] The array substrate, the display panel and the display device provided by the present disclosure have the following specific solutions:

[0006] In one aspect, the present disclosure provides an array substrate, comprising:

[0007] a substrate substrate;

[0008] a plurality of binding terminals located on the substrate substrate;

[0009] a plurality of first adapter structures located on a side of the layer where the plurality of binding terminals are located away from the substrate substrate, and the plurality of first adapter structures are electrically connected with the plurality of binding terminals;

[0010] A plurality of signal lines are located on a side of the layer where the plurality of bonding terminals are located away from the substrate, a projection of the plurality of signal lines on the substrate and a projection of the plurality of bonding terminals on the substrate intersect each other, and a projection of the plurality of signal lines on the substrate and a projection of the connection positions of the plurality of first transfer structures and the plurality of bonding terminals on the substrate do not overlap each other.

[0011] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the layer where the plurality of signal lines are located is between the layer where the plurality of bonding terminals are located and the layer where the plurality of first transfer structures are located.

[0012] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, a first insulating layer is located between the layer where the plurality of signal lines are located and the layer where the plurality of bonding terminals are located, and a second insulating layer is located between the layer where the plurality of signal lines are located and the layer where the plurality of first transfer structures are located.

[0013] The first insulating layer and the second insulating layer include a plurality of through holes, and the plurality of bonding terminals are electrically connected to the plurality of first transfer structures through the plurality of through holes.

[0014] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, a plurality of resistance reduction electrodes are located in the same layer as the plurality of signal lines, the extension direction of the resistance reduction electrodes is substantially the same as the extension direction of the bonding terminals, and the plurality of resistance reduction electrodes are electrically connected to the plurality of bonding terminals through the plurality of first transfer structures at the plurality of through holes.

[0015] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the plurality of bonding terminals include a ground terminal, and the plurality of signal lines are electrically connected to the ground terminal.

[0016] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, a ground line electrically connected to the ground terminal and a resistance reduction line electrically connected to the ground line are further included, and a projection of the resistance reduction line on the substrate and a projection of the ground line on the substrate substantially coincide with each other.

[0017] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the resistance reduction line is located in the same layer as the plurality of signal lines.

[0018] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, a second transfer structure located in the same layer as the plurality of first transfer structures is further included, and the ground line is electrically connected to the resistance reduction line through the second transfer structure.

[0019] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the second adapter structure is a block-shaped electrode covering the position where it is electrically connected with the ground line and the resistance-reducing line.

[0020] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the second adapter structure is a strip-shaped electrode covering the ground line.

[0021] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the layer where the plurality of binding terminals are located is a gate metal layer, the layer where the plurality of signal lines are located is a source-drain metal layer, and the layer where the plurality of first adapter structures are located is a transparent electrode layer farthest from the substrate.

[0022] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the first adapter structure is a block-shaped electrode covering the position where it is electrically connected with the binding terminal.

[0023] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the first adapter structure is a strip-shaped electrode covering the binding terminal.

[0024] In another aspect, the embodiments of the present disclosure provide a display panel, comprising an array substrate and a counter substrate opposite to each other; wherein,

[0025] The array substrate is the array substrate provided by the embodiments of the present disclosure;

[0026] The orthogonal projection of the counter substrate on the substrate substrate does not overlap with the orthogonal projection of the plurality of binding terminals on the substrate substrate.

[0027] In another aspect, the embodiments of the present disclosure provide a display device, comprising the display panel provided by the embodiments of the present disclosure, and a driving circuit electrically connected with the plurality of binding terminals. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1 is a structural schematic diagram of an array substrate provided by the embodiments of the present disclosure;

[0029] FIG. 2 is a structural schematic diagram of part of a binding terminal of a binding area BD in FIG. 1;

[0030] FIG. 3 is a sectional view along line I-I' in FIG. 2;

[0031] FIG. 4 is a sectional view along line II-II' in FIG. 2;

[0032] FIG. 5 is another structural schematic diagram of part of a binding terminal of a binding area BD in FIG. 1;

[0033] FIG. 6 is a sectional view along line III-III' in FIG. 5;

[0034] Fig. 7 is a schematic view of another structure of a partial binding terminal of a binding area BD in Fig. 1;

[0035] Fig. 8 is a schematic view of a partial structure of a ground line in Fig. 1;

[0036] Fig. 9 is a sectional view along line IV-IV' in Fig. 8;

[0037] Fig. 10 is a schematic view of a structure of a display panel according to an embodiment of the present disclosure;

[0038] Fig. 11 is a schematic view of another structure of a display panel according to an embodiment of the present disclosure;

[0039] Fig. 12 is a schematic view of a structure of a display device according to an embodiment of the present disclosure;

[0040] Fig. 13 is a schematic view of another structure of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] To make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It should be noted that, in the drawings, the thicknesses of layers, films, panels, regions and the like are exaggerated for clarity. In the present disclosure, the exemplary embodiments are described with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described in the present disclosure are not to be construed as being limited to the particular shapes of regions as illustrated in the drawings but are to include deviations in shapes that result from, for example, manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features; an illustrated sharp corner can typically be rounded; etc. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and do not reflect true scales and proportions. The purpose of the figures is to illustrate the concepts of the present disclosure and the division of the regions is not intended to reflect the division of the regions in a real device. Like numbers refer to like or similar elements throughout. To keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and known devices is omitted from the present disclosure.

[0042] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning to those of a person skilled in the art to which this disclosure belongs. The terms "first", "second", and similar terms in the description and in the claims are used to distinguish one element from another, and are not necessarily used to describe a sequential or chronological order. The terms "comprises", "comprising", "includes", "including" and the like are meant to encompass the elements listed thereafter, as well as other elements not specifically listed. The terms "connected", "coupled", and the like, are meant to encompass a direct connection or coupling between the elements connected or coupled, as well as an indirect connection or coupling between the elements connected or coupled, through one or more intermediate elements. The terms "inner", "outer", "upper", "lower", and the like, are used to describe relative positions of the elements, and can change when the absolute positions of the elements are changed.

[0043] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. When an element or layer is referred to as being "disposed on a side of" another element or layer, it can be directly on the side of the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there is no intervening element or layer present. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] In some embodiments, an outer lead bonding (OLB) region (also referred to as a bonding area) of an array substrate is provided with a bonding lead, and an indium tin oxide layer is disposed on the bonding lead for attaching a terminal of a chip on film (COF). A metal trace can be arranged on the array substrate and connected to a display area AA, and a portion of the metal trace extending to the bonding area is the bonding lead. The bonding lead is electrically connected to the indium tin oxide layer via a via, so that a signal of the COF can be conducted from the indium tin oxide layer to the metal trace. However, static electricity (ESD) is easily accumulated during the bonding process, and when the static electricity strikes above the COF, the bonding lead at the via is prone to be fused, which reduces the effective connection area of the bonding lead at the via, increases the resistance of the metal trace, and reduces the yield and reliability of the product.

[0045] In order to at least improve the above technical problems, the array substrate provided by the embodiments of the present disclosure, Fig. 1 is a structural schematic diagram of the array substrate provided by the embodiments of the present disclosure, Fig. 2 is a structural schematic diagram of a part of the binding terminals of one binding area BD in Fig. 1, Fig. 3 is a sectional view along the line I-I' in Fig. 2, and Fig. 4 is a sectional view along the line II-II' in Fig. 2. As shown in Figs. 1 to 4, the array substrate provided by the embodiments of the present disclosure comprises:

[0046] The substrate 101, optionally, the substrate 101 comprises a display area AA1, a first non-display area BB1 comprising at least one binding area BD on one side of the display area AA1, a second non-display area BB2 opposite to the first non-display area BB1, and two third non-display areas BB3 connecting the first non-display area BB1 and the second non-display area BB2, wherein at least one third non-display area BB3 can be provided with a gate drive circuit area (GOA); in some embodiments, the display area AA comprises arrayed red sub-pixel areas, green sub-pixel areas, blue sub-pixel areas and the like, and the substrate 101 is a substrate allowing visible light to pass through, for example, a glass, quartz, plastic or the like.

[0047] A plurality of binding terminals 102 are located in the binding area BD of the substrate 101; optionally, to simplify the process, the structure, size and number of the binding terminals 102 in each binding area BD are the same; it should be understood that, due to the limitation of process conditions or the influence of other factors such as measurement, the "same size" may be exactly the same or may have some deviation (for example, with a deviation of ±2μm). In some embodiments, the binding terminal 102 can be located in the gate metal layer (Gate), and the material of the gate metal layer can comprise at least one metal such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni) and the like, and the gate metal layer can be a single-layer structure or a laminated structure, for example, a single-layer structure composed of a molybdenum metal layer.

[0048] A plurality of first switching structures 103 are located on the side of the layer where the plurality of binding terminals 102 are away from the substrate 101, and the plurality of first switching structures 103 are electrically connected with the plurality of binding terminals 102. In some embodiments, in order to facilitate the binding and bonding of the first switching structure 103 with the driving circuit (for example, a flexible circuit board FPC, or a driving circuit of a binding data chip source IC and the like), the first switching structure 103 can be arranged on the layer where the transparent electrode of the top layer of the array substrate is located; for example, in the case where the transparent conductive layer of the array substrate is only the pixel electrode layer, the first switching structure 103 is located on the pixel electrode layer; for another example, the array substrate simultaneously comprises a pixel electrode and a common electrode, two transparent electrode layers, and the first switching structure 103 is located on the transparent electrode layer far away from the substrate 101.

[0049] A plurality of signal lines 104 are located on the side of the layer where the plurality of bonding terminals 102 are away from the substrate 101. The signal lines 104 can be ground signal lines or floating signal lines. Optionally, the orthogonal projection of the plurality of signal lines 104 on the substrate 101 intersects with the orthogonal projection of the plurality of bonding terminals 102 on the substrate 101. For example, the bonding terminals 102 extend along a first direction Y, and the signal lines 104 extend along a second direction X which is perpendicular to the first direction Y. In order to avoid affecting the attachment of the first conversion structure 103 and the driving circuit (such as a chip on film (COF), a flexible printed circuit (FPC), a data chip (source IC), etc.), the orthogonal projection of the plurality of signal lines 104 on the substrate 101 does not overlap with the orthogonal projection of the connection positions (i.e., the positions of the first vias V1) of the plurality of first conversion structures 103 and the plurality of bonding terminals 102 on the substrate 101. Referring to FIG. 2, optionally, the plurality of signal lines 104 can be connected together at the periphery of the plurality of bonding terminals 102 corresponding to one COF region to form an integrated structure. Thus, when the plurality of signal lines 104 supply the same signal, it is easier. When the plurality of signal lines 104 are floating, the area of the overall signal line 104 is larger, the electrostatic discharge path is increased, and the electrostatic problem is improved.

[0050] In the array substrate provided in the embodiments of the present disclosure, the signal lines 104 are arranged on the side of the layer where the bonding terminals 102 are away from the substrate 101, so that the static electricity accumulated in the bonding area BD during the bonding process can be timely dispersed on the signal lines 104, avoiding the induction of electric charges on the layer where the bonding terminals 102 are located, thereby achieving the electrostatic protection of the bonding terminals 102, and improving the yield and reliability of the product.

[0051] In some embodiments, the layer where the plurality of signal lines 104 are located can be between the layer where the plurality of bonding terminals 102 are located and the layer where the plurality of first conversion structures 103 are located, as shown in FIG. 3. In some embodiments, the signal lines 104 can be located on a source-drain metal layer (SD) or other metal layer (such as a touch metal layer TPM), thereby sharing the source-drain metal layer or other metal layer, without the need to separately increase the layer where the signal lines 104 are located, which is conducive to the lightweight and thin design. Optionally, the material of the source-drain metal layer or other metal layer can include at least one metal such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The source-drain metal layer or other metal layer can be a single-layer structure or a laminated structure. For example, the source-drain metal layer is a laminated structure composed of a titanium metal layer, an aluminum metal layer, and a titanium metal layer, and the other metal layer is a single-layer structure composed of a copper metal layer. Optionally, the source-drain metal layer (SD) of the signal lines 104 and the transistor source-drain metal layer (SD) of the display area are of the same layer and the same material.

[0052] It should be noted that in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 2 to 4, the first adapter structure 103 can be a strip-shaped electrode covering the binding terminal 102, at this time, the signal line 104 between the layer where the binding terminal 102 is located and the layer where the first adapter structure 103 is located crosses the first adapter structure 103. In other embodiments, the first adapter structure 103 can be a block-shaped electrode covering only the connection position (i.e., the position of the first via V1) of the corresponding binding terminal 102, in this case: the layer where the signal line 104 is located can be between the layer where the first adapter structure 103 is located and the layer where the binding terminal 102 is located; or, the signal line 104 and the first adapter structure 103 can be arranged in the same layer and made of the same material, and the signal line 104 and the first adapter structure 103 are insulated from each other by a gap to avoid the signal line 104 from electrically connecting the first adapter structures 103 corresponding to different binding terminals 102 together to cause signal crosstalk. Since the material of the layer where the first adapter structure 103 is located is a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), etc., the conductive performance of these transparent conductive materials is poorer than that of the source-drain metal layer material, therefore, in specific implementation, the signal line 104 can be arranged in the source-drain metal layer, and the present disclosure takes the signal line 104 located in the source-drain metal layer as an example for illustrative description.

[0053] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 3 and 4, a first insulating layer 105 located between the layer where the plurality of signal lines 104 are located and the layer where the plurality of binding terminals 102 are located, and a second insulating layer 106 located between the layer where the plurality of signal lines 104 are located and the layer where the plurality of first adapter structures 103 are located can also be included; wherein the first insulating layer 105 and the second insulating layer 106 include a plurality of first vias V1 arranged in a penetrating manner, and the plurality of binding terminals 102 are electrically connected to the plurality of first adapter structures 103 through the plurality of first vias V1. In some embodiments, the first insulating layer 105 and the second insulating layer 106 can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or made of aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., and can be a single layer or a laminated layer, which is not limited by the present disclosure.

[0054] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, FIG. 5 is a schematic view of another structure of part of the binding terminals of one binding area BD in FIG. 1, and FIG. 6 is a sectional view along the line III-III' in FIG. 5. As shown in FIG. 5 and FIG. 6, a plurality of resistance reduction electrodes 107 can also be arranged in the same layer and of the same material as the plurality of signal lines 104, the extension direction of the resistance reduction electrodes 107 is substantially the same as the extension direction of the binding terminals 102 (for example, both extend along the first direction Y), and the plurality of resistance reduction electrodes 107 are electrically connected with the plurality of binding terminals 102 through the plurality of first transfer structures 103 at the plurality of first vias V1. In this way, on the one hand, the OLB metal thickness is increased, the resistance is reduced, and the anti-static capability is improved; on the other hand, since the OLB has two layers of metal, even if one layer is damaged in the color film substrate cutting process, the other layer can still be used to transmit signals, thereby avoiding the damage of the color film substrate cutting process to the peripheral circuit on the array substrate and improving the product yield.

[0055] It should be understood that in FIG. 5 and FIG. 6, the resistance reduction electrodes 107 are electrically connected with the binding terminals 102, and one signal line 104 intersects with a plurality of binding terminals 102. Therefore, in order to avoid signal crosstalk of different binding terminals 102, the same layer resistance reduction electrodes 107 need to be arranged to be insulated from the signal lines 104 through a gap. In addition, in some embodiments, FIG. 7 is a schematic view of another structure of part of the binding terminals of one binding area BD in FIG. 1. As shown in FIG. 7, the present disclosure can also only arrange the resistance reduction electrodes 107 without arranging the signal lines 104, so as to improve the anti-static capability and the product yield by using the resistance reduction electrodes 107.

[0056] It should be noted that in the present disclosure, "same layer and same material" means that the film layer used for manufacturing a specific pattern is formed by using the same film forming process, and then the layer structure is formed by using the same mask plate through one patterning process. That is, one patterning process corresponds to one mask plate (also referred to as a photomask). According to different specific patterns, one patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns can be at the same height or have the same thickness, or can be at different heights or have different thicknesses.

[0057] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the plurality of binding terminals 102 can include a ground terminal (GND), and the plurality of signal lines 104 can be electrically connected with the ground terminal (GND) to discharge static electricity on the signal lines 104 in time, thereby further improving the anti-static capability.

[0058] In some embodiments, FIG. 8 is a schematic diagram of a partial structure of the ground line in FIG. 1, and FIG. 9 is a sectional view along the line IV-IV' in FIG. 8. As shown in FIGS. 1, 8 and 9, in the array substrate provided in the embodiments of the present disclosure, a ground line 108 electrically connected to the ground terminal (GND) and a resistance reduction line 109 electrically connected to the ground line 108 can also be included, and the orthogonal projection of the resistance reduction line 109 on the substrate 101 substantially coincides with the orthogonal projection of the ground line 108 on the substrate 101, so that the thickness of the GND metal is increased, the resistance is reduced, and the anti-static capability is improved. It should be noted that in the embodiments provided in the present disclosure, due to the limitation of process conditions or the influence of other factors such as measurement, the "substantial coincidence" can be exact coincidence or can have some deviation (for example, with a deviation of ±2 μm), and therefore the "substantial coincidence" between the related features is within the protection scope of the present disclosure as long as the error is allowed.

[0059] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the resistance reduction line 109 can be arranged in the same layer and of the same material as the plurality of signal lines 104 (for example, in the source-drain metal layer), and the ground line 108 can be arranged in the same layer and of the same material as the binding terminal 102 (for example, in the gate metal layer). In some embodiments, the resistance reduction line 109 can be electrically connected to the ground line 108 through a via hole penetrating through the first insulating layer 105. In other embodiments, as shown in FIGS. 8 and 9, a second transfer structure 110 arranged in the same layer as the plurality of first transfer structures 103 can also be included, and the ground line 108 is electrically connected to the resistance reduction line 109 through the second transfer structure 110. The second transfer structure 110 can be a block electrode covering the position (i.e., the position of the second via hole V2) where the ground line 108 and the resistance reduction line 109 are electrically connected, or the second transfer structure 110 can be a strip electrode covering the ground line 108. In some embodiments, the first insulating layer 105 and the second insulating layer 106 include a second via hole V2 arranged therethrough, and the second transfer structure 110 is electrically connected to the resistance reduction line 109 and the ground line 108 at the same time at the second via hole V2. Since the second via hole V2 can be completed through a one-time mask process together with the first via hole V1, the mask process for manufacturing the via hole penetrating through the first insulating layer 105 is avoided, so that the process flow is reduced and the manufacturing cost is saved.

[0060] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG. 8, a test line (add) 111, a feedback line (feed) 112, a common electrode bus (com) 113, a frame start signal line (STV1A, STV1B) 114 and the like can also be included. It should be understood by those skilled in the art that other essential components in the array substrate are also included, and therefore will not be described herein and should not be regarded as a limitation on the present disclosure.

[0061] Based on the same inventive concept, the display panel provided by the embodiments of the present disclosure is provided, and FIG. 10 is a structural schematic diagram of the display panel provided by the embodiments of the present disclosure, and FIG. 11 is another structural schematic diagram of the display panel provided by the embodiments of the present disclosure. As shown in FIG. 10 and FIG. 11, the display panel of the present disclosure comprises the array substrate 001 provided by the embodiments of the present disclosure, and a counter substrate 002 opposite to the array substrate 001, and the counter substrate 002 does not cover the binding area BD where the plurality of binding terminals 102 are located. Since the principle of solving the problem of the display panel is similar to the principle of solving the problem of the array substrate, the implementation of the display panel can refer to the embodiments of the array substrate, and the repeated parts will not be described herein.

[0062] In some embodiments, as shown in FIG. 11, the display panel provided by the embodiments of the present disclosure can further comprise a liquid crystal layer 003 between the array substrate 001 and the counter substrate 002, a first polarizer 004 can be arranged on the side of the array substrate 001 away from the counter substrate 002, a second polarizer 005 can be arranged on the side of the counter substrate 002 away from the array substrate 001, and the polarization direction of the first polarizer 004 is perpendicular to the polarization direction of the second polarizer 005. It should be understood by those skilled in the art that other essential components in the display panel are understood, and will not be described herein, and should not be regarded as a limitation on the present disclosure.

[0063] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure is provided, and FIG. 12 is a structural schematic diagram of the display device provided by the embodiments of the present disclosure, and FIG. 13 is another structural schematic diagram of the display device provided by the embodiments of the present disclosure. As shown in FIG. 12 and FIG. 13, the display device of the present disclosure comprises the display panel PNL provided by the embodiments of the present disclosure, and a driving circuit DC electrically connected with the binding terminals of the binding area BD, and the driving circuit DC can be a flexible circuit board FPC, a driving circuit of a binding data chip source IC, etc. Since the principle of solving the problem of the display device is similar to the principle of solving the problem of the array substrate, the implementation of the display device can refer to the embodiments of the array substrate, and the repeated parts will not be described herein.

[0064] In some embodiments, in the display device provided in the embodiments of the present disclosure, as shown in FIG. 13, a backlight module BLU can also be included on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or a side-lit backlight module. Optionally, the side-lit backlight module can include a lamp bar, a reflector sheet, a light guide plate, a diffusion sheet, a prism group, and the like, and the lamp bar is located on one side of the light guide plate in the thickness direction. The direct-lit backlight module can include a matrix light source, a reflector sheet, a diffusion plate, and a brightness enhancement film, and the like, which are stacked on the light-incident side of the matrix light source, and the reflector sheet includes apertures arranged opposite to the positions of the lamp beads in the matrix light source. The lamp beads in the lamp bar and the lamp beads in the matrix light source can be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0065] In some embodiments, the lamp beads can also be micro light-emitting devices (such as Mini LED, Micro LED), and the like. The micro light-emitting devices in the order of sub-millimeter or even micrometer are as self-luminous devices as organic light-emitting devices (OLEDs). Like the organic light-emitting devices, the micro light-emitting devices have a series of advantages such as high brightness, ultra-low delay, and ultra-large viewing angle. In addition, because the inorganic light-emitting devices emit light based on metal semiconductors with more stable properties and lower resistance, the inorganic light-emitting devices have the advantages of lower power consumption, longer service life, and better resistance to high and low temperatures compared with the organic light-emitting devices based on organic substances. When the micro light-emitting devices are used as backlight sources, more precise dynamic backlight effects can be achieved, which can effectively improve the screen brightness and contrast, and also solve the glare phenomenon caused by the traditional dynamic backlight between the bright and dark areas of the screen, thereby optimizing the visual experience.

[0066] In some embodiments, the display device provided by the embodiments of the present disclosure can be any product or component with display function, such as a display, a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigation device, a smart watch, a fitness wristband, a personal digital assistant, and the like. Optionally, the display device provided by the embodiments of the present disclosure includes, but is not limited to, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip, and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like. For example, the control chip can further include a memory, and can further include a power module, and the like, and the power supply and signal input and output functions are realized through wires, signal lines, and the like arranged additionally. For example, the control chip can further include hardware circuitry and computer executable code, and the like. The hardware circuitry can include conventional very large scale integration (VLSI) circuitry or gate array, and existing semiconductors or other discrete elements such as logic chips, transistors, and the like; the hardware circuitry can also include field programmable gate array, programmable array logic, programmable logic device, and the like. In addition, the above structure does not constitute a limitation on the display device provided by the embodiments of the present disclosure, in other words, the display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or arrange different components.

[0067] Although the preferred embodiments of the present disclosure have been described, those skilled in the art who are informed of the basic inventive concept can make additional changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0068] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, include: Substrate; Multiple bonding terminals are located on the substrate. Multiple first adapter structures are located on the side of the layer containing the multiple bonding terminals away from the substrate, and the multiple first adapter structures are electrically connected to the multiple bonding terminals; Multiple signal lines are located on the side of the layer where the multiple bonding terminals are located, away from the substrate. The orthographic projections of the multiple signal lines on the substrate and the orthographic projections of the multiple bonding terminals on the substrate intersect each other, and the orthographic projections of the multiple signal lines on the substrate and the orthographic projections of the connection positions of the multiple first adapter structures and the multiple bonding terminals on the substrate do not overlap.

2. The array substrate as claimed in claim 1, wherein, The layer containing the multiple signal lines is located between the layer containing the multiple bonding terminals and the layer containing the multiple first adapter structures.

3. The array substrate as described in claim 2, wherein, It also includes a first insulating layer located between the layer containing the plurality of signal lines and the layer containing the plurality of bonding terminals, and a second insulating layer located between the layer containing the plurality of signal lines and the layer containing the plurality of first adapter structures; The first insulating layer and the second insulating layer include a plurality of through-holes, and the plurality of bonding terminals are electrically connected to the plurality of first adapter structures through the plurality of through-holes.

4. The array substrate as claimed in claim 3, wherein, It also includes multiple resistance-reducing electrodes disposed on the same layer as the multiple signal lines, the extension direction of the resistance-reducing electrodes being approximately the same as the extension direction of the bonding terminals, and the multiple resistance-reducing electrodes being electrically connected to the multiple bonding terminals through the multiple first adapter structures at the multiple vias.

5. The array substrate according to any one of claims 1 to 4, wherein, The plurality of bonding terminals include a grounding terminal, and the plurality of signal lines are electrically connected to the grounding terminal.

6. The array substrate as claimed in claim 5, wherein, It also includes a grounding wire electrically connected to the grounding terminal and a resistance-reducing wire electrically connected to the grounding wire, wherein the orthogonal projection of the resistance-reducing wire on the substrate generally coincides with the orthogonal projection of the grounding wire on the substrate.

7. The array substrate as claimed in claim 6, wherein, The reduced resistance line is arranged on the same layer as the multiple signal lines.

8. The array substrate as claimed in claim 6 or 7, wherein, It also includes a second transition structure disposed on the same layer as the plurality of first transition structures, wherein the grounding wire is electrically connected to the resistance-reducing wire through the second transition structure.

9. The array substrate as claimed in claim 8, wherein, The second adapter structure is a block electrode covering the location where it is electrically connected to the grounding wire and the resistance-reducing wire.

10. The array substrate as claimed in claim 8, wherein, The second adapter structure is a strip electrode that covers the grounding wire.

11. The array substrate according to any one of claims 1 to 10, wherein, The layer containing the plurality of bonding terminals is a gate metal layer, the layer containing the plurality of signal lines is a source / drain metal layer, and the layer containing the plurality of first transition structures is a transparent electrode layer furthest from the substrate.

12. The array substrate according to any one of claims 1 to 11, wherein, The first adapter structure is a block electrode covering the location where it is electrically connected to the bonding terminal.

13. The array substrate according to any one of claims 1 to 11, wherein, The first adapter structure is a strip electrode covering the bonding terminal.

14. A display panel, wherein, It includes an array substrate and a counter substrate placed opposite each other; wherein, The array substrate is the array substrate as described in any one of claims 1 to 13; The orthographic projection of the opposing substrate on the substrate and the orthographic projection of the plurality of bonding terminals on the substrate do not overlap.

15. A display device, wherein, It includes the display panel as described in claim 14, and a drive circuit electrically connected to the plurality of bonding terminals.

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