Display substrate and manufacturing method therefor, and display device

Abstract

Disclosed in the present disclosure are a display substrate and a manufacturing method therefor, and a display device. The display substrate (100) comprises a pixel definition layer (15) and a plurality of sub-pixels (10P), wherein each sub-pixel (10P) comprises a light-emitting device (OEL), the light-emitting device (OEL) comprising a light-emitting functional layer (16); the pixel definition layer (15) comprises a partition structure layer (15A) and a first definition layer (15B) disposed on the side of the partition structure layer (15A) away from a substrate (11), the first definition layer (15B) being made of an organic material; and a pixel definition structure (151) between at least two adjacent sub-pixels (10P) comprises a first partition structure (10g1) formed by the partition structure layer (15A) on at least one side of a pixel opening (15K1), and at least part of at least one film layer in the light-emitting functional layer (16) is disconnected at the first partition structure (10g1).

Description

Display substrate, manufacturing method thereof, and display device Cross-reference to Related Applications

[0001] The present disclosure claims priority to Chinese Patent Application No. 202410841429.7, filed on June 26, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to the technical field of display, and relates to a display substrate, a manufacturing method thereof, and a display device. BACKGROUND

[0002] An organic light-emitting diode (OLED) display panel, as a new generation of light-emitting display technology after a liquid crystal display panel, has advantages of wide visual angle, high contrast, bright colors, flexible display, and the like, and has been widely applied to various mobile phones, notebook computers, wearable devices, and the like.

[0003] However, in the related art, there is a crosstalk problem between adjacent sub-pixels. SUMMARY

[0004] Some embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which can solve the problem of crosstalk between adjacent sub-pixels.

[0005] In a first aspect of some embodiments of the present disclosure, a display substrate is provided, comprising a substrate, a pixel defining layer disposed on one side of the substrate, and a plurality of sub-pixels, the pixel defining layer comprising a plurality of pixel defining structures, and a plurality of pixel openings defined by the plurality of pixel defining structures, the pixel openings being configured to define a light-emitting area of the sub-pixel; the sub-pixel comprising a light-emitting device, the light-emitting device comprising a first electrode and a second electrode located on a side of the first electrode away from the substrate, and a light-emitting functional layer located between the first electrode and the second electrode, the light-emitting functional layer comprising a plurality of film layers; wherein the pixel defining layer comprises a partition structure layer and a first defining layer disposed on a side of the partition structure layer away from the substrate, the partition structure layer comprising at least one film layer, and the first defining layer being an organic material; wherein the pixel defining structure between at least two adjacent sub-pixels comprises a first partition structure formed by the partition structure layer on at least one side of the pixel opening, and at least part of at least one film layer in the light-emitting functional layer is disconnected at the first partition structure.

[0006] In some embodiments, the first partition structure is formed by the partition structure layer inwardly recessing towards at least one side of the pixel opening; and the material of the partition structure layer is an inorganic material.

[0007] In some embodiments, the partition structure layer comprises a first sub-film layer and a second sub-film layer stacked in sequence in a direction away from the substrate, the first sub-film layer is at least partially disposed on a side of the first electrode away from the substrate, and the first partition structure is formed by inwardly recessing an edge of the first sub-film layer relative to the second sub-film layer.

[0008] In some embodiments, the pixel defining structure between at least two adjacent sub-pixels further comprises a second partition structure between the two adjacent sub-pixels, and at least part of at least one film layer in the light-emitting functional layer is broken at the second partition structure.

[0009] In some embodiments, the height of the first partition structure is different from that of the second partition structure in a direction perpendicular to the plane on which the substrate lies.

[0010] In some embodiments, at least part of the pixel defining structure further comprises a first partition groove, the first partition groove at least penetrates the first defining layer and at least part of the film layer of the partition structure layer, and the first partition groove exposes the second partition structure.

[0011] In some embodiments, the partition structure layer comprises a third sub-film layer, a first sub-film layer and a second sub-film layer stacked in sequence in a direction away from the substrate, the first sub-film layer is at least partially disposed on a side of the first electrode away from the substrate, the first partition structure is formed by inwardly recessing an edge of the first sub-film layer relative to the second sub-film layer, the second partition structure is formed by inwardly recessing an edge of the first sub-film layer relative to the second sub-film layer, and the thickness of the third sub-film layer at the first partition groove in a direction perpendicular to the plane on which the substrate lies is greater than 0.

[0012] In some embodiments, the partition structure layer further comprises a fourth sub-film layer disposed between the third sub-film layer and the first sub-film layer, and the second partition structure is formed by inwardly recessing an edge of the first sub-film layer and the fourth sub-film layer relative to the second sub-film layer.

[0013] In some embodiments, the first sub-film layer and the fourth sub-film layer are made of the same material.

[0014] In some embodiments, the material of the first sub-film layer and the fourth sub-film layer comprises silicon oxide, and the material of the third sub-film layer and the second sub-film layer comprises silicon nitride.

[0015] In some embodiments, the orthographic projection of the third sub-film layer on the substrate and the orthographic projection of the fourth sub-film layer on the substrate do not overlap with the orthographic projection of the first electrode on the substrate.

[0016] In some embodiments, the plurality of sub-pixels comprises red sub-pixels, green sub-pixels and blue sub-pixels; the pixel defining structure comprises the first partition structure in the red sub-pixels, the green sub-pixels and the blue sub-pixels; and at least one of the two adjacent sub-pixels on both sides of the second partition structure is a red sub-pixel or a green sub-pixel.

[0017] In some embodiments, the first partition structure has a closed loop shape in the orthographic projection on the substrate; and the second partition structure has a non-closed loop shape in the orthographic projection on the substrate.

[0018] In some embodiments, the first limiting layer has a first ramping portion on the edge of the first limiting layer towards the side of the pixel opening, and the slope angle of the first ramping portion is less than or equal to 42 degrees, the slope angle being the included angle between the tangent of the first ramping portion and the plane parallel to the substrate.

[0019] In some embodiments, the pixel defining layer further comprises a second limiting layer disposed on the side of the first limiting layer away from the substrate, and the second limiting layer is an inorganic material; and at least part of the pixel defining structure further comprises a second partition groove between the two adjacent sub-pixels, the second partition groove penetrating the second limiting layer, and the thickness of the first limiting layer at the second partition groove is greater than 0 in the direction perpendicular to the plane of the substrate.

[0020] In some embodiments, the display substrate comprises a display area and a non-display area at least on one side of the display area, and at least part of the sub-pixels are located in the display area; the display substrate further comprises at least one first part in the non-display area, and the first part is at least composed of the partition structure layer; the display substrate further comprises a first conductive layer disposed between the substrate and the pixel defining layer, and the first conductive layer comprises a first wire in the non-display area, the second electrode is connected to the first wire on the side of the first part in the plane parallel to the plane of the substrate; and the first limiting layer comprises a first slope, the first slope is located at the connection between the second electrode and the first wire, and the second electrode is connected to the first wire after extending on the first slope.

[0021] In some embodiments, the display substrate further comprises a first insulating layer disposed between the first electrode and the substrate, the first insulating layer is an organic material, the partition structure layer comprises at least one gas release hole in the non-display area, the gas release hole at least penetrates the partition structure layer, the partition structure layer is filled with an organic material, and the first limiting layer is connected to the first insulating layer through the organic material in the gas release hole.

[0022] In a second aspect, the present disclosure provides a method for manufacturing a display substrate, comprising: providing a substrate; forming a plurality of first electrodes on one side of the substrate; forming a pixel defining layer on a side of the first electrodes away from the substrate, the pixel defining layer comprising a plurality of pixel defining structures and a plurality of pixel openings defined by a plurality of sub-pixels, the pixel openings exposing the first electrodes; wherein the pixel defining layer comprises a partition structure layer and a first limiting layer disposed on a side of the partition structure layer away from the substrate, the partition structure layer comprising at least one film layer, and the first limiting layer being an organic material; wherein the pixel defining structure between at least two adjacent sub-pixels comprises a first partition structure formed by the partition structure layer on at least one side of the pixel opening; forming a light-emitting functional layer on a side of the first electrodes away from the substrate, the light-emitting functional layer comprising a plurality of film layers, at least part of at least one film layer in the light-emitting functional layer being broken at the first partition structure; and forming a second electrode on a side of the light-emitting functional layer away from the substrate.

[0023] In some embodiments, the step of forming the pixel defining layer on a side of the first electrodes away from the substrate comprises: forming a third sub-film layer of the partition structure layer on the substrate, forming a fourth sub-film layer of the partition structure layer on a side of the third sub-film layer away from the substrate, patterning the third sub-film layer and the fourth sub-film layer by a same patterning process, the orthographic projection of the third sub-film layer on the substrate and the orthographic projection of the fourth sub-film layer on the substrate do not overlap with the orthographic projection of the first electrodes on the substrate; forming a first sub-film layer of the partition structure layer on a side of the fourth sub-film layer and the first electrodes away from the substrate, forming a second sub-film layer of the partition structure layer on a side of the first sub-film layer away from the substrate; forming the first limiting layer on a side of the second sub-film layer away from the substrate and patterning the first limiting layer; and patterning the first sub-film layer and the second sub-film layer by the same patterning process to form the first partition structure.

[0024] In some embodiments, in the step of patterning the first sub-film layer and the second sub-film layer by the same patterning process, a second partition structure in the pixel defining structure between at least two adjacent sub-pixels is also formed; and at least part of at least one film layer in the light-emitting functional layer is broken at the second partition structure.

[0025] In some embodiments, in the step of forming the light-emitting functional layer on the side of the first electrode away from the substrate, a charge generation layer in the light-emitting functional layer is formed; after the charge generation layer is formed and before the step of forming the second electrode on the side of the light-emitting functional layer away from the substrate, the method further comprises: baking the display substrate, wherein, after the display substrate is baked, the first limiting layer has a first ramping portion on the edge of the first limiting layer on the side of the pixel opening, and the slope angle of the first ramping portion is less than or equal to 42 degrees, and the slope angle is the included angle between the tangent of the first ramping portion and the plane parallel to the substrate.

[0026] In some embodiments, in the step of forming the pixel limiting layer on the side of the first limiting layer away from the substrate, a second limiting layer is further formed on the side of the first limiting layer away from the substrate, the second limiting layer is an inorganic material, and at least part of the pixel limiting structure further comprises a second partition groove between two adjacent sub-pixels, the second partition groove penetrates the second limiting layer, and the thickness of the first limiting layer at the second partition groove is greater than 0 in the direction perpendicular to the plane of the substrate.

[0027] In some embodiments, the display substrate comprises a display area and a non-display area at least on one side of the display area, and at least part of the sub-pixels are located in the display area; the display substrate further comprises at least one first part in the non-display area, and the first part is at least composed of the partition structure layer; before the step of forming the pixel limiting layer on the side of the first electrode away from the substrate, a first conductive layer is further formed, and the first conductive layer comprises a first trace in the non-display area; in the step of forming the pixel limiting layer on the side of the first electrode away from the substrate, the first limiting layer forms a first slope; after the step of forming the second electrode on the side of the light-emitting functional layer away from the substrate, on the plane parallel to the plane of the substrate, the second electrode is connected to the first trace on the side of the first part, the first slope is located at the connection between the second electrode and the first trace, and the second electrode extends on the first slope and is connected to the first trace.

[0028] In a third aspect, some embodiments of the present disclosure provide a display device, comprising the display substrate described in any one of the above. BRIEF DESCRIPTION OF DRAWINGS

[0029] FIG. 1 is a schematic diagram of a problem existing in a related technology according to some embodiments of the present disclosure;

[0030] FIG. 2 is a schematic diagram of a display substrate according to some embodiments of the present disclosure;

[0031] FIG. 3 is a first partial top view of a display substrate according to some embodiments of the present disclosure;

[0032] FIG. 4 is a first cross-sectional view of a display substrate according to some embodiments of the present disclosure;

[0033] FIG. 5 is a second cross-sectional view of a display substrate according to some embodiments of the present disclosure;

[0034] FIG. 6 is a third cross-sectional view of a display substrate according to some embodiments of the present disclosure;

[0035] FIG. 7 is a fourth cross-sectional view of a display substrate according to some embodiments of the present disclosure;

[0036] FIG. 8 is a first cross-sectional view of a non-display area of a display substrate according to some embodiments of the present disclosure;

[0037] FIG. 9 is a second cross-sectional view of a non-display area of a display substrate according to some embodiments of the present disclosure;

[0038] FIG. 10 is a third cross-sectional view of a non-display area of a display substrate according to some embodiments of the present disclosure;

[0039] FIG. 11 is a first verification result according to some embodiments of the present disclosure;

[0040] FIG. 12 is a second verification result according to some embodiments of the present disclosure;

[0041] FIG. 13 is a fifth cross-sectional view of a display substrate according to some embodiments of the present disclosure;

[0042] FIG. 14 is a sixth cross-sectional view of a display substrate according to some embodiments of the present disclosure;

[0043] FIG. 15 is a third verification result according to some embodiments of the present disclosure;

[0044] FIG. 16 is a second partial top view of a display substrate according to some embodiments of the present disclosure;

[0045] FIG. 17 is a third partial top view of a display substrate according to some embodiments of the present disclosure;

[0046] FIG. 18 is a seventh cross-sectional view of a display substrate according to some embodiments of the present disclosure;

[0047] FIG. 19 is a first flow chart of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0048] FIG. 20 is a first intermediate process diagram of a display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0049] FIG. 21 is a first intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0050] FIG. 22 is a second intermediate process diagram of a display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0051] FIG. 23 is a second intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0052] FIG. 24 is a third intermediate process diagram of a display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0053] FIG. 25 is a third intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0054] FIG. 26 is a fourth intermediate process diagram of a display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0055] FIG. 27 is a fourth intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0056] FIG. 28 is a fifth intermediate process diagram of a display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0057] FIG. 29 is a fifth intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0058] FIG. 30 is a sixth intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0059] FIG. 31 is a seventh intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0060] FIG. 32 is a second flow diagram of a manufacturing method of a display substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0061] In order to better understand the technical solutions provided by the embodiments of the present specification, the technical solutions of the embodiments of the present specification will be described in detail below through the accompanying drawings and specific embodiments. It should be understood that the specific features in the embodiments of the present specification and the embodiments are detailed descriptions of the technical solutions of the present specification, and are not limitations of the technical solutions of the present specification. In the case of no conflict, the technical features in the embodiments of the present specification and the embodiments can be combined with each other.

[0062] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element. The term "two or more" includes two or more than two.

[0063] In the related art, there is a problem of crosstalk between adjacent sub-pixels, for example, when a sub-pixel is lit, the current in the lit sub-pixel will flow horizontally to the adjacent sub-pixel, causing the adjacent sub-pixel to appear abnormal lighting. In the related art, some isolation structures are provided to prevent the problem of crosstalk between adjacent sub-pixels, but these isolation structures have the problems of occupying a large area (layout) or not being suitable for stacked light-emitting devices or not being able to well isolate different color sub-pixels.

[0064] In the related art, as shown in FIG. 1, FIG. 1 is a schematic diagram of a problem existing in a related technology provided by some embodiments of the present disclosure. As shown in FIG. 1, the display panel includes a substrate 11, a first insulating layer 13 (the first insulating layer 13 can be a flat layer) disposed on the substrate 11, a first conductive layer (the first conductive layer can be a first electrode layer 14 including a plurality of first electrodes 141 of a plurality of light emitting devices located in a display area AA) disposed on the first insulating layer 13, a pixel defining layer 15 disposed on the first conductive layer, a light emitting functional layer 16 disposed on the pixel defining layer, a second electrode 17 disposed on the light emitting functional layer 16, and an encapsulation layer 19 disposed on the second electrode 17. FIG. 1 schematically shows a cross-sectional structure of part of the film layers of a non-display area BB of the display panel. FIG. 1 exemplarily shows that the first conductive layer is the first electrode layer 14, and the first conductive layer includes a first trace 142. The display panel includes a first part 101D. FIG. 1 exemplarily shows that the first part 101D is formed by part of the pixel defining layer 15. In FIG. 1, at the first dashed line circle 101X1 in a plane parallel to the substrate 11, the second electrode 17 is connected to the first trace 142 on one side of the first part 101D. The inventors have found that in the related art, disconnection defects are prone to occur at the connection between the second electrode 17 and the first trace 142. In particular, when the material of the pixel defining layer 15 is an inorganic material, such disconnection defects are particularly serious.

[0065] Therefore, the present disclosure provides a display substrate and a manufacturing method thereof, and a display device, which can solve or improve at least one of the above problems.

[0066] The present disclosure provides a display substrate, including a substrate, a pixel defining layer disposed on one side of the substrate, and a plurality of sub-pixels, the pixel defining layer including a plurality of pixel defining structures, and a plurality of pixel openings defined by the plurality of pixel defining structures, the pixel openings being configured to define light emitting areas of the sub-pixels.

[0067] The sub-pixel includes a light emitting device, the light emitting device including a first electrode and a second electrode located on a side of the first electrode away from the substrate, and a light emitting functional layer located between the first electrode and the second electrode, the light emitting functional layer including a plurality of film layers.

[0068] The pixel defining layer includes a partition structure layer and a first defining layer disposed on a side of the partition structure layer away from the substrate, the partition structure layer including at least one film layer, and the first defining layer being an organic material.

[0069] At least one film layer of the light emitting functional layer is disconnected at the first partition structure between at least two adjacent sub-pixels.

[0070] The present disclosure also provides a manufacturing method of the display substrate.

[0071] The present disclosure also provides a display panel comprising the display substrate.

[0072] The present disclosure also provides a display device comprising the display substrate.

[0073] Please refer to FIG. 2 to FIG. 7, FIG. 2 is a schematic diagram of a display substrate according to some embodiments of the present disclosure, FIG. 3 is a first partial top view of a display substrate according to some embodiments of the present disclosure; FIG. 4 is a first cross-sectional structure schematic diagram of a display substrate according to some embodiments of the present disclosure; FIG. 5 is a second cross-sectional structure schematic diagram of a display substrate according to some embodiments of the present disclosure; FIG. 6 is a third cross-sectional structure schematic diagram of a display substrate according to some embodiments of the present disclosure; FIG. 7 is a fourth cross-sectional structure schematic diagram of a display substrate according to some embodiments of the present disclosure. FIG. 4 illustrates the cross-sectional structure at the C-C dotted line in FIG. 3, or FIG. 4 illustrates that the display substrate only comprises the first partition structure. FIG. 5 and FIG. 6 illustrate the cross-sectional structure at the D-D dotted line in FIG. 3, or FIG. 5 and FIG. 6 illustrate that the display substrate comprises both the first partition structure and the second partition structure. The structures in FIG. 5 and FIG. 6 are the same or similar, and the difference is that FIG. 6 further illustrates the partial film layer on the side of the pixel definition layer away from the substrate.

[0074] Please refer to FIG. 8 to FIG. 9, FIG. 8 is a first cross-sectional structure schematic diagram of a non-display area of a display substrate according to some embodiments of the present disclosure; FIG. 9 is a second cross-sectional structure schematic diagram of a non-display area of a display substrate according to some embodiments of the present disclosure; FIG. 10 is a third cross-sectional structure schematic diagram of a non-display area of a display substrate according to some embodiments of the present disclosure. The structures in FIG. 8 and FIG. 9 are the same, and the difference is that some labels or numbers are added in FIG. 9.

[0075] The display substrate 100 includes a substrate 11, a pixel defining layer 15 disposed on one side of the substrate 11, and a plurality of sub-pixels 10P, the pixel defining layer 15 includes a plurality of pixel defining structures 151, and a plurality of pixel openings 15K1 defined by the plurality of pixel defining structures 151, the pixel openings 15K1 are configured to define a light-emitting area of the sub-pixel 10P; the sub-pixel 10P includes a light-emitting device OEL, the light-emitting device OEL includes a first electrode 141 and a second electrode 17 located on a side of the first electrode 141 away from the substrate 11, and a light-emitting functional layer 16 located between the first electrode 141 and the second electrode 17, the light-emitting functional layer 16 includes a plurality of film layers; wherein the pixel defining layer 15 includes a partition structure layer 15A and a first defining layer 15B disposed on a side of the partition structure layer 15A away from the substrate 11, the partition structure layer 15A includes at least one film layer, and the first defining layer 15B is an organic material; wherein the pixel defining structure 151 between at least two adjacent sub-pixels 10P includes a first partition structure 10g1 formed by the partition structure layer 15A on at least one side of the pixel opening 15K1, and at least part of at least one film layer in the light-emitting functional layer 16 is disconnected at the first partition structure 10g1.

[0076] For example, the substrate 11 can be glass or a flexible substrate 11, and the flexible substrate 11 can be polyimide, which is not limited herein.

[0077] For example, the film layer structure of the display substrate 100 can include: the substrate 11, a driving circuit layer disposed on one side of the substrate 11, a first electrode layer 14 disposed on a side of the driving circuit layer away from the substrate 11, and a pixel defining layer 15 disposed on a side of the first electrode layer 14 away from the substrate 11. The first electrode layer 14 includes a plurality of first electrodes 141 arranged in an array, the pixel defining layer 15 includes a plurality of pixel defining structures 151 and a plurality of pixel openings 15K1, and the pixel openings 15K1 expose corresponding first electrodes 141.

[0078] For example, in some embodiments, the display substrate 100 can include a plurality of light-emitting devices OEL, and each light-emitting device OEL includes: a first electrode 141 disposed on one side of the substrate 11, a light-emitting functional layer 16 disposed on a side of the first electrode 141 away from the substrate 11, and a second electrode 17 disposed on a side of the light-emitting functional layer 16 away from the substrate 11. One of the first electrode 141 and the second electrode 17 is an anode, and the other is a cathode. In the present disclosure, the first electrode 141 is taken as an example of the anode, and the second electrode 17 is taken as an example of the cathode.

[0079] For example, in some embodiments, the driving circuit layer can include a plurality of pixel driving circuits, the first electrode 141 is electrically connected to a corresponding pixel driving circuit, and the pixel driving circuit is used to drive the light-emitting device OEL to emit light.

[0080] For example, referring to FIG. 6 and FIG. 8, a film layer structure of a display substrate 100 is exemplarily illustrated, which includes a substrate 11, a first metal layer 12 disposed on the substrate 11, a first insulating layer 13 disposed on the first metal layer 12, a first electrode layer 14 disposed on the first insulating layer 13, a pixel defining layer 15 disposed on the first electrode layer 14, a light emitting functional layer 16 disposed at least in the pixel opening 15K1, a second electrode 17 disposed on the light emitting functional layer 16, and an encapsulation layer 19 disposed on the second electrode 17. The encapsulation layer 19 is formed by at least one inorganic material layer and at least one organic material layer, for example, the encapsulation layer 19 includes a first inorganic material sub-layer 191 disposed on the second electrode 17, a first organic material sub-layer 192 disposed on the first inorganic material sub-layer 191, and a second inorganic material sub-layer 193 disposed on the first organic material sub-layer 192.

[0081] For example, in FIG. 6, the first metal layer 12 includes a plurality of drain electrodes 121 (or source electrodes), which can be part of a pixel driving circuit, and the first electrode 141 is connected to a corresponding drain electrode 121.

[0082] For example, the light emitting device OEL can be a tandem light emitting device (Tandem, series light emitting device), or a single layer light emitting device.

[0083] For example, FIG. 6 illustrates that the light emitting device OEL is a tandem light emitting device, and FIG. 6 illustrates that the light emitting functional layer 16 includes a first light emitting unit 161, a charge generation layer 162 (CGL), and a second light emitting unit 163, which are disposed in a stack on the first electrode 141. The light emitting functional layer 16 can also include any one of a hole transport layer HTL, a hole injection layer HIL, an electron injection layer EIL, an electron transport layer ETL, a hole blocking layer HBL, and an electron blocking layer EBL. The light emitting functional layer 16 can also include other numbers of light emitting units or / and charge generation layers.

[0084] For example, the charge generation layer 162 (CGL) can include an N-type charge generation layer and a P-type charge generation layer. The main function of the charge generation layer 162 (CGL) is to provide electron carriers for the lower light emitting unit and to provide hole carriers for the upper light emitting unit.

[0085] For example, the charge generation layer 162 (CGL), the hole transport layer HTL, the hole injection layer HIL, the electron injection layer EIL, the electron transport layer ETL, the hole blocking layer HBL, and the electron blocking layer EBL are common film layers of a plurality of sub-pixels 10P, which can be referred to as common layers, and the light emitting device OEL includes at least one of these common layers.

[0086] For example, at least part of at least one film layer in the light-emitting functional layer 16 is disconnected at the first partition structure 10g1. For example, the charge generation layer 162 (CGL) is disconnected at the first partition structure 10g1. For example, any one of the hole transport layer HTL, the hole injection layer HIL, the electron injection layer EIL, the electron transport layer ETL, the hole blocking layer HBL, and the electron blocking layer EBL is disconnected at the first partition structure 10g1.

[0087] For example, the charge generation layer 162 (CGL) has a relatively large conductivity. When the charge generation layer 162 (CGL) is a full-film layer, the charge generation layers 162 (CGL) of two adjacent light-emitting devices OEL are continuous film layers, and there is a charge lateral migration phenomenon, which causes spectral crosstalk of the display substrate 100 at a low gray scale, such as causing crosstalk between adjacent subpixels, resulting in color deviation of the display substrate 100. For example, the charge generation layer 162 (CGL) can cause crosstalk between subpixels of different colors at a low brightness, resulting in low gray scale color deviation. In some embodiments of the present disclosure, at least part of at least one film layer in the light-emitting functional layer 16 is disconnected at the first partition structure 10g1, which can improve or avoid the charge lateral migration phenomenon between adjacent subpixels 10P, thereby improving or solving the problem of crosstalk between adjacent subpixels.

[0088] For example, in some other embodiments, when the second electrode 17 is a full-film layer in the display substrate 100, there is a charge lateral migration phenomenon, which causes spectral crosstalk of the display substrate 100 at a low gray scale, resulting in uneven color of the display substrate 100, which has a great impact on the uniformity of the display product. In some embodiments of the present disclosure, at least part of the second electrode 17 is disconnected at the first partition structure 10g1, which can improve or avoid the charge lateral migration phenomenon between adjacent subpixels 10P, thereby improving or solving the problem of crosstalk between adjacent subpixels.

[0089] In some embodiments, please refer to FIG. 2 and FIG. 8, the display substrate 100 includes a display area AA and a non-display area BB located at least on one side of the display area AA, and at least part of the subpixels 10P is located in the display area AA; the display substrate 100 further includes at least one first part 101D located in the non-display area BB, and the first part 101D is at least composed of the partition structure layer 15A; the display substrate 100 further includes a first conductive layer arranged between the substrate 11 and the pixel definition layer 15, and the first conductive layer includes a first trace 142 located in the non-display area BB. In a plane parallel to the substrate 11, the second electrode 17 is connected to the first trace 142 on one side of the first part 101D; the first definition layer 15B includes a first slope 15XP, and the first slope 15XP is located at the connection between the second electrode 17 and the first trace 142. The second electrode 17 extends on the first slope 15XP and is then connected to the first trace 142.

[0090] For example, the first region 101D can be a transition region located in the non-display region BB, and the first conductive layer can be the first electrode layer 14, which includes a plurality of first electrodes 141 located in the display region AA and a first wire 142 located in the non-display region.

[0091] For example, in some embodiments, the display substrate 100 or the display panel 1000 can include a pad region electrically connected to a circuit board or a driving chip, the first wire 142 is connected between the pad region and the second electrode 17, and the display substrate 100 or the display panel 1000 can supply signals to the second electrode 17 through the first wire 142.

[0092] For example, in some embodiments, as shown in FIG. 8, the display substrate 100 or the display panel 1000 can include a pad region electrically connected to a circuit board or a driving chip, the display substrate 100 includes a second wire 122, for example, the second wire 122 is patterned from the first metal layer 12, the second wire 122 is connected to the first wire 142, the first wire 142 is connected to the second electrode 17, the second wire 122 is connected between the pad region and the first wire 142, and the display substrate 100 or the display panel 1000 can supply signals to the second electrode 17 through the second wire 122 and the first wire 142 in sequence.

[0093] For example, the pixel definition layer 15 includes a partition structure layer 15A and a first definition layer 15B disposed on a side of the partition structure layer 15A away from the base 11, the first definition layer 15B is an organic material, a first slope 15XP is formed at a connection between the second electrode 17 and the first wire 142, the first definition layer 15B of the organic material can form a transitionally gentle slope, the first slope 15XP can carry the second electrode 17, the second electrode 17 extends on the first slope 15XP and then connects the first wire 142, so that the second electrode 17 can be prevented from being broken at this position, and thus the pixel definition layer 15 of some embodiments of the present disclosure can prevent the problem of breakage of the connection between the conductive layers on the upper and lower sides of the pixel definition layer 15.

[0094] For example, in some embodiments, an edge of the orthographic projection of the first electrode 141 on the base 11 is located within the range of the orthographic projection of the first definition layer 15B of the pixel definition structure 151 on the base 11, and the thickness of the partition structure layer 15A is small, which can avoid the problem of short circuit between the first electrode 141 and the second electrode 17 caused by abnormality of the partition structure layer 15A wrapping the edge of the first electrode 14 (abnormality of the first sub-film layer 15A1 covering the first electrode 141).

[0095] In some embodiments of the present disclosure, by setting the partition structure layer 15A, the pixel defining structure 151 between at least two adjacent sub-pixels 10P includes a first partition structure 10g1 formed by the partition structure layer 15A on at least one side of the pixel opening 15K1, and at least part of at least one film layer in the light-emitting functional layer 16 is disconnected at the first partition structure 10g1, which can improve or avoid the phenomenon of lateral migration of charges between adjacent sub-pixels 10P, thereby improving or solving the problem of crosstalk between adjacent sub-pixels. At the same time, the side of the partition structure layer 15A away from the substrate 11 is provided with a first limiting layer 15B, and the first limiting layer 15B is an organic material. In a plane parallel to the substrate 11, the first limiting layer 15B fills the side of the pattern of the partition structure layer 15A (the side of the first limiting layer 15B covering the first part 101D) to form a gentle slope (the first slope 15XP). The gentle slope (the first slope 15XP) can well bear the second electrode 17 at the connection between the second electrode 17 and the first trace 142. After the second electrode 17 extends on the gentle slope (the first slope 15XP), it is connected to the first trace 142, so that the second electrode 17 can be prevented from breaking at this point. That is, the pixel defining layer 15 of some embodiments of the present disclosure has the problem of preventing the connection between the conductive layers on the upper and lower sides of the pixel defining layer 15 from breaking.

[0096] In some embodiments of the present disclosure, by setting the first limiting layer 15B, the thickness of the partition structure layer 15A is small, which avoids the problem of short circuit between the first electrode 141 and the second electrode 17 caused by the abnormality of the partition structure layer 15A wrapping the edge of the first electrode 14 (the abnormality of the first sub-film layer 15A1 covering the first electrode 141). That is, when the partition structure layer 15A wraps the edge of the first electrode 14 abnormally, the first limiting layer 15B also covers the first electrode 141, thereby preventing the first electrode 141 and the second electrode 17 from short circuiting.

[0097] In some embodiments, the first partition structure 10g1 is formed by the partition structure layer 15A inwardly shrinking towards at least one side of the pixel opening 15K1; and the material of the partition structure layer 15A is an inorganic material.

[0098] For example, as shown in FIG. 4, the first partition structure 10g1 is an undercut structure.

[0099] For example, when the material of the partition structure layer 15A is an inorganic material, the first partition structure 10g1 with a preset shape can be well formed. The size of the first partition structure 10g1 is small, so that the first partition structure 10g1 occupies a small area (layout), which is suitable for a stacked light-emitting device and a high-resolution display panel.

[0100] For example, when the material of the partition structure layer 15A is an inorganic material, the side of the pattern of the partition structure layer 15A (the side of the first part 101D) is steeper, and when the pixel definition layer 15 does not include the first definition layer 15B, the second electrode 17 is more likely to break at the connection with the first wiring 142. In some embodiments of the present disclosure, the first definition layer 15B is provided to improve or prevent the breaking of the second electrode 17 at the connection with the first wiring 142.

[0101] In some embodiments, the partition structure layer 15A includes a first sub-film layer 15A1 and a second sub-film layer 15A2 which are sequentially stacked in a direction away from the substrate 11, the first sub-film layer 15A1 is at least partially disposed on a side of the first electrode 141 away from the substrate 11, and the first partition structure 10g1 is formed by the edge of the first sub-film layer 15A1 being inwardly recessed relative to the second sub-film layer 15A2.

[0102] For example, the first partition structure 10g1 is formed by the edge of the first sub-film layer 15A1 being inwardly recessed relative to the second sub-film layer 15A2, i.e., at the first partition structure 10g1, the edge of the second sub-film layer 15A2 extends beyond the edge of the first sub-film layer 15A1 by a certain distance.

[0103] For example, in a plane parallel to the substrate 11, the width of the first partition structure 10g1 (i.e., the width of the edge of the first sub-film layer 15A1 being inwardly recessed relative to the second sub-film layer 15A2) is 0.5 microns to 4 microns, and the width of the first partition structure 10g1 can be any of 0.5 microns, 1 micron, 1.5 microns, 2 microns, 2.5 microns, 3 microns, 3.5 microns, and 4 microns.

[0104] For example, in a plane parallel to the substrate 11, the width of the second partition structure 10g2 (i.e., the width of the edge of the first sub-film layer 15A1 being inwardly recessed relative to the second sub-film layer 15A2) is 0.5 microns to 4 microns, and the width of the second partition structure 10g2 can be any of 0.5 microns, 1 micron, 1.5 microns, 2 microns, 2.5 microns, 3 microns, 3.5 microns, and 4 microns.

[0105] For example, the first sub-film layer 15A1 is at least partially disposed on a side of the first electrode 141 away from the substrate 11, i.e., the first sub-film layer 15A1 at least partially covers the first electrode 141, avoiding the side end of the first electrode 141 being exposed and causing display defects.

[0106] In some embodiments, as shown in FIGS. 5 and 6, the pixel definition structure 151 between at least two adjacent sub-pixels 10P further includes a second partition structure 10g2 between the two adjacent sub-pixels 10P, and at least part of at least one film layer in the light-emitting functional layer 16 is broken at the second partition structure 10g2.

[0107] For example, at least part of at least one film layer in the light-emitting functional layer 16 is disconnected at the second partition structure 10g2, which can improve or avoid the charge lateral migration phenomenon between adjacent sub-pixels 10P, thereby improving or solving the problem of crosstalk between adjacent sub-pixels.

[0108] For example, the display substrate 100 simultaneously includes the first partition structure 10g1 and the second partition structure 10g2, which can better improve or avoid the charge lateral migration phenomenon between adjacent sub-pixels 10P, thereby improving or solving the problem of crosstalk between adjacent sub-pixels.

[0109] For example, the display substrate 100 simultaneously includes the first partition structure 10g1 and the second partition structure 10g2, and the first partition structure 10g1 or / and the second partition structure 10g2 is arranged at different positions, which can adapt to the spacing between sub-pixels of different colors.

[0110] For example, the display substrate 100 simultaneously includes the first partition structure 10g1 and the second partition structure 10g2, and the first partition structure 10g1 or / and the second partition structure 10g2 is arranged in the corresponding sub-pixel of different colors, which can better improve or avoid the charge lateral migration phenomenon between adjacent sub-pixels 10P, thereby improving or solving the problem of crosstalk between adjacent sub-pixels.

[0111] For example, in other embodiments, at least part of the second electrode 17 is disconnected at the second partition structure 10g2, which can improve or avoid the charge lateral migration phenomenon between adjacent sub-pixels 10P, thereby improving or solving the problem of crosstalk between adjacent sub-pixels.

[0112] For example, the light-emitting device OEL is a stacked light-emitting device as shown in FIG. 6, and the light-emitting functional layer 16 includes a first light-emitting unit 161, a charge generation layer 162 (CGL), and a second light-emitting unit 163 which are stacked on the first electrode 141 as an example shown in FIG. 6.

[0113] For example, please refer to FIG. 3, the plurality of sub-pixels 10P includes a red sub-pixel 10P2, a green sub-pixel 10P3, and a blue sub-pixel 10P1.

[0114] For example, in some embodiments, the red sub-pixel 10P2 includes a red light-emitting device including the first light-emitting unit 161, the charge generation layer 162 (CGL), and the second light-emitting unit 163, in which the first light-emitting unit 161 and the second light-emitting unit 163 both emit red light. In some embodiments, the green sub-pixel 10P3 includes a green light-emitting device including the first light-emitting unit 161, the charge generation layer 162 (CGL), and the second light-emitting unit 163, in which the first light-emitting unit 161 and the second light-emitting unit 163 both emit green light. In some embodiments, the blue sub-pixel 10P1 includes a blue light-emitting device including the first light-emitting unit 161, the charge generation layer 162 (CGL), and the second light-emitting unit 163, in which the first light-emitting unit 161 and the second light-emitting unit 163 both emit blue light. The microcavity lengths in the red light-emitting device, the green light-emitting device, and the blue light-emitting device are different in the direction perpendicular to the plane in which the substrate 11 lies, so that the distance from the charge generation layer 162 (CGL) to the first electrode 141 in the red light-emitting device, the distance from the charge generation layer 162 (CGL) to the first electrode 141 in the green light-emitting device, and the distance from the charge generation layer 162 (CGL) to the first electrode 141 in the blue light-emitting device are different. By simultaneously providing the first partition structure 10g1 and the second partition structure 10g2, at least one light-emitting functional layer 16 outside the light-emitting device of different colors can be effectively disconnected, respectively.

[0115] For example, in some embodiments, the distance from the charge generation layer 162 (CGL) to the first electrode 141 in the red light-emitting device and the distance from the charge generation layer 162 (CGL) to the first electrode 141 in the green light-emitting device are both greater than the distance from the charge generation layer 162 (CGL) to the first electrode 141 in the blue light-emitting device. The first partition structure 10g1 can disconnect the charge generation layer 162 (CGL) in the blue light-emitting device, and the second partition structure 10g2 can disconnect the charge generation layer 162 (CGL) in the red light-emitting device and the charge generation layer 162 (CGL) in the green light-emitting device. By simultaneously providing the first partition structure 10g1 and the second partition structure 10g2, different microcavity lengths of different color sub-pixels / different color light-emitting devices can be adapted, and the phenomenon of lateral migration of charges between adjacent sub-pixels 10P of multiple colors can be improved or avoided, thereby improving or solving the crosstalk problem existing in the display substrate with multiple color sub-pixels.

[0116] In some embodiments, as shown in FIGS. 5 and 6, the height of the first partition structure 10g1 is different from the height of the second partition structure 10g2 in the direction perpendicular to the plane in which the substrate 11 lies.

[0117] For example, as shown in FIG. 5, the height of the first partition structure 10g1 is the distance between the surface of the substrate 11 far away from the inner recessed region and the surface of the substrate 11 close to the inner recessed region.

[0118] For example, as shown in FIG. 5, the height of the second partition structure 10g2 is the distance between the surface of the substrate 11 far away from the inner recessed region and the surface of the substrate 11 close to the inner recessed region.

[0119] For example, as shown in FIG. 5, in the direction perpendicular to the plane where the substrate 11 is located, the height of the first partition structure 10g1 is the first height h1, the height of the second partition structure 10g2 is the second height h2, and the height of the first partition structure 10g1 is different from the height of the second partition structure 10g2, so that the first partition structure 10g1 and the second partition structure 10g2 can adapt to the needs of sub-pixels of different colors.

[0120] For example, in the direction perpendicular to the plane where the substrate 11 is located, the height of the first partition structure 10g1 is different from the height of the second partition structure 10g2, which can adapt to different microcavity lengths of sub-pixels of different colors / different color light emitting devices, and can improve or avoid the phenomenon of lateral migration of charges between adjacent sub-pixels 10P of multiple colors, thereby improving or solving the crosstalk problem existing in the display substrate with multiple color sub-pixels.

[0121] For example, as shown in FIG. 5 and FIG. 6, it is illustrated that in the direction perpendicular to the plane where the substrate 11 is located, the first height h1 of the first partition structure 10g1 is less than the second height h2 of the second partition structure 10g2, when the distance from the charge generation layer 162 (CGL) to the first electrode 141 in the red light emitting device and the distance from the charge generation layer 162 (CGL) to the first electrode 141 in the green light emitting device are both greater than the distance from the charge generation layer 162 (CGL) to the first electrode 141 in the blue light emitting device, the first partition structure 10g1 can make the charge generation layer 162 (CGL) in the blue light emitting device disconnected, and the second partition structure 10g2 can make the charge generation layer 162 (CGL) in the red light emitting device and the charge generation layer 162 (CGL) in the green light emitting device disconnected, by simultaneously setting the first partition structure 10g1 and the second partition structure 10g2, different microcavity lengths of sub-pixels of different colors / different color light emitting devices can be adapted, and the phenomenon of lateral migration of charges between adjacent sub-pixels 10P of multiple colors can be improved or avoided, thereby improving or solving the crosstalk problem existing in the display substrate with multiple color sub-pixels.

[0122] In some embodiments, as shown in FIG. 5 and FIG. 6, the at least partial pixel defining structure 151 further comprises a first partition groove 15K2, the first partition groove 15K2 at least penetrating the first defining layer 15B and at least partial membrane layer of the partition structure layer 15A, and the first partition groove 15K2 exposing the second partition structure 10g2.

[0123] For example, the first partition groove 15K2 exposes the second partition structure 10g2, and at least one membrane layer in the light-emitting functional layer 16 and at least partial part of the second electrode 17 are disconnected at the second partition structure 10g2 through the first partition groove 15K2.

[0124] It should be noted that FIG. 6 shows that the light-emitting functional layer 16 is disconnected at the first partition structure 10g1 and the second partition structure 10g2, and the actual morphology of the light-emitting functional layer 16 disconnected at the first partition structure 10g1 and the second partition structure 10g2 can also be other shapes.

[0125] In some embodiments, as shown in FIG. 5 and FIG. 6, the partition structure layer 15A comprises a third sub-membrane layer 15A3, a first sub-membrane layer 15A1 and a second sub-membrane layer 15A2 which are sequentially stacked in a direction away from the substrate 11, the first sub-membrane layer 15A1 is at least partially disposed on a side of the first electrode 141 away from the substrate 11; the first partition structure 10g1 is formed by the edge of the first sub-membrane layer 15A1 inwardly recessed relative to the second sub-membrane layer 15A2; the second partition structure 10g2 is at least formed by the edge of the first sub-membrane layer 15A1 inwardly recessed relative to the second sub-membrane layer 15A2; in a direction perpendicular to the plane in which the substrate 11 lies, the thickness of the third sub-membrane layer 15A3 at the first partition groove 15K2 is greater than 0.

[0126] For example, as shown in FIG. 5 and FIG. 6, at the edge of the pixel opening 10, the first sub-membrane layer 15A1 partially covers the surface of the first electrode 141 away from the substrate 11, which has the effect of protecting the first electrode 141 and preventing the side end surface of the first electrode 141 from being exposed.

[0127] For example, as shown in FIG. 5 and FIG. 6, in a direction perpendicular to the plane in which the substrate 11 lies, the thickness of the third sub-membrane layer 15A3 at the first partition groove 15K2 is greater than 0, that is, during the etching process of forming the first partition groove 15K2 or the second partition structure 10g2, etching to the first insulating layer 13 (the first insulating layer 13 can be a flat layer disposed between the substrate 11 and the first electrode layer 14) can be avoided, which has the effect of protecting the first insulating layer 13.

[0128] In some embodiments, as shown in FIGS. 5 and 6, the partition structure layer 15A further comprises a fourth sub-film layer 15A4 disposed between the third sub-film layer 15A3 and the first sub-film layer 15A1; the second partition structure 10g2 is formed by inwardly recessing the edge of the first sub-film layer 15A1 and the fourth sub-film layer 15A4 relative to the second sub-film layer 15A2.

[0129] For example, the first partition structure 10g1 is formed by inwardly recessing the edge of the first sub-film layer 15A1 relative to the second sub-film layer 15A2, and the second partition structure 10g2 is formed by inwardly recessing the edge of the first sub-film layer 15A1 and the fourth sub-film layer 15A4 relative to the second sub-film layer 15A2, so that the second height h2 of the second partition structure 10g2 is greater than the first height h1 of the first partition structure 10g1.

[0130] For example, in the direction perpendicular to the plane where the substrate 11 is located, the thickness of the second sub-film layer 15A2 ranges from 5 nanometers to 50 nanometers, for example, the thickness of the second sub-film layer 15A2 can be any value among 5 nanometers, 10 nanometers, 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, and 40 nanometers.

[0131] For example, in the direction perpendicular to the plane where the substrate 11 is located, the thickness of the first sub-film layer 15A1 ranges from 5 nanometers to 200 nanometers, for example, the thickness of the first sub-film layer 15A1 can be any value among 5 nanometers, 40 nanometers, 50 nanometers, 100 nanometers, 150 nanometers, and 200 nanometers.

[0132] For example, in the direction perpendicular to the plane where the substrate 11 is located, the thickness of the fourth sub-film layer 15A4 ranges from 5 nanometers to 200 nanometers, for example, the thickness of the fourth sub-film layer 15A4 can be any value among 5 nanometers, 30 nanometers, 50 nanometers, 100 nanometers, 150 nanometers, and 200 nanometers.

[0133] For example, in the direction perpendicular to the plane where the substrate 11 is located, the thickness of the third sub-film layer 15A3 is less than or equal to 1000 nanometers.

[0134] For example, the first limiting layer 15B can adopt a photosensitive resin or a photoresist type material, and in the direction perpendicular to the plane where the substrate 11 is located, the thickness of the first limiting layer 15B is less than or equal to 3 micrometers.

[0135] For example, the first metal layer 12 adopts a titanium / aluminum / titanium laminated structure, and in the direction perpendicular to the plane where the substrate 11 is located, the first metal layer can be a laminated structure of titanium with a thickness of 50 nanometers, aluminum with a thickness of 400 nanometers, and titanium with a thickness of 50 nanometers.

[0136] For example, the first electrode layer 14 or the first electrode 141 can adopt a stack structure of indium tin oxide / silver / indium tin oxide (ITO / Ag / ITO), and in a direction perpendicular to a plane on which the substrate 11 lies, the first electrode layer 14 or the first electrode 141 can be a stack structure of 8-nanometer-thick indium tin oxide, 100-nanometer-thick silver, and 8-nanometer-thick indium tin oxide.

[0137] In some embodiments, the first sub-film layer 15A1 and the fourth sub-film layer 15A4 are of the same material, as shown in FIGS. 5 and 6.

[0138] For example, the first sub-film layer 15A1 and the fourth sub-film layer 15A4 are of the same material, and the first sub-film layer 15A1 and the fourth sub-film layer 15A4 can form the second partition structure 10g2 through the same etching process, thereby reducing the manufacturing process steps.

[0139] In some embodiments, the first sub-film layer 15A1 and the fourth sub-film layer 15A4 are of silicon oxide, and the third sub-film layer 15A3 and the second sub-film layer 15A2 are of silicon nitride.

[0140] For example, the first sub-film layer 15A1 partially covers the first electrode 141 disposed on a side surface of the first electrode 141 away from the substrate 11, and the first sub-film layer 15A1 adopting silicon nitride can maintain the surface flatness of the first electrode 141, avoiding the surface unevenness of the first electrode 141 caused by silicon oxide.

[0141] In some embodiments, the third sub-film layer 15A3 and the fourth sub-film layer 15A4 do not overlap with the first electrode 141 in orthographic projection on the substrate 11, as shown in FIGS. 5 and 6.

[0142] For example, the third sub-film layer 15A3 and the fourth sub-film layer 15A4 do not overlap with the first electrode 141 in orthographic projection on the substrate 11, and in combination with the first partition structure 10g1 formed by the edge of the first sub-film layer 15A1 inwardly retracted relative to the second sub-film layer 15A2, the first partition structure 10g1 formed by the edge of the first sub-film layer 15A1 inwardly retracted relative to the second sub-film layer 15A2 makes the second height h2 of the second partition structure 10g2 greater than the first height h1 of the first partition structure 10g1.

[0143] In some embodiments, as shown in FIG. 3, FIG. 5 and FIG. 6, the plurality of sub-pixels 10P includes a red sub-pixel 10P2, a green sub-pixel 10P3 and a blue sub-pixel 10P1; in the red sub-pixel 10P2, the green sub-pixel 10P3 and the blue sub-pixel 10P1, the pixel defining structure 151 includes the first partition structure 10g1; among the two adjacent sub-pixels 10P located on both sides of the second partition structure 10g2, at least one is the red sub-pixel 10P2 or the green sub-pixel 10P3.

[0144] For example, in some embodiments, the display substrate 100 simultaneously includes the first partition structure 10g1 and the second partition structure 10g2.

[0145] For example, in some embodiments, the display substrate 100 simultaneously includes the first partition structure 10g1 and the second partition structure 10g2, each side of the pixel defining structure 151 towards the pixel opening 15K1 is provided with the first partition structure 10g1, the pixel defining structure 151 between a red sub-pixel 10P2 and other sub-pixel 10P (the other sub-pixel 10P can be another red sub-pixel 10P2) is provided with the second partition structure 10g2, and the pixel defining structure 151 between a green sub-pixel 10P3 and other sub-pixel 10P (the other sub-pixel 10P can be another green sub-pixel 10P3) is provided with the second partition structure 10g2.

[0146] For example, in some other embodiments, the display substrate 100 only includes the first partition structure 10g1, and in the pixel defining structure 151 defining the red sub-pixel 10P2, the green sub-pixel 10P3 and the blue sub-pixel 10P1, the pixel defining structure 151 includes the first partition structure 10g1.

[0147] For example, in some other embodiments, the display substrate 100 only includes the second partition structure 10g2, and among the two adjacent sub-pixels 10P located on both sides of the second partition structure 10g2, can be any one of the red sub-pixel 10P2, the green sub-pixel 10P3 and the blue sub-pixel 10P1.

[0148] For example, in some other embodiments, when one blue sub-pixel 10P1 is arranged adjacent to another blue sub-pixel 10P1, the pixel defining structure 151 between the two adjacent blue sub-pixels 10P1 can not include the second partition structure 10g2.

[0149] In some embodiments, as shown in FIG. 3, FIG. 5 and FIG. 6, the first partition structure 10g1 has a closed ring shape in the orthographic projection on the base 11; and the second partition structure 10g2 has a non-closed ring shape in the orthographic projection on the base 11.

[0150] For example, the orthographic projection of the first partition structure 10g1 on the substrate 11 is a closed ring, that is, the first partition structure 10g1 is arranged around the pixel opening 15K1, which can better disconnect at least one film layer in the light-emitting functional layer 16, and the length of the disconnected at least one film layer in the light-emitting functional layer 16 is greater, which can better improve or avoid the phenomenon of lateral migration of charges between adjacent sub-pixels 10P, thereby improving or solving the problem of crosstalk between adjacent sub-pixels.

[0151] For example, the orthographic projection of the second partition structure 10g2 on the substrate 11 is a non-closed ring, which can avoid the second electrode 17 being disconnected into an island at the second partition structure 10g2, maintain the electrical connection of the second electrode 17 in each sub-pixel 10P, and maintain the uniformity of the electrical signal supply and the electrical signal in the second electrode 17 in each sub-pixel 10P.

[0152] For example, as shown in FIG. 3, it can be understood that a second partition structure 10g2 is arranged around the red sub-pixel 10P2, and the second partition structure 10g2 includes a plurality of second partition structure segments, and adjacent second partition structure segments have a connecting portion 10g21, which can maintain the electrical connection of the second electrode 17 in the red sub-pixel 10P2 with other sub-pixels.

[0153] For example, as shown in FIG. 3, it can be understood that a plurality of second partition structures 10g2 are arranged around the red sub-pixel 10P2, and adjacent two second partition structures 10g2 have a connecting portion 10g21, which can maintain the electrical connection of the second electrode 17 in the red sub-pixel 10P2 with other sub-pixels.

[0154] For example, as shown in FIG. 3, through the arrangement of the second partition structure 10g2 and the connecting portion 10g21, the second electrode 17 in each sub-pixel 10P is in a grid shape, which can maintain the uniformity of the electrical signal in the second electrode 17 in each sub-pixel 10P.

[0155] In some embodiments, as shown in FIG. 5, in at least part of the pixel defining structure 151, the edge of the first limiting layer 15B toward the side of the pixel opening 15K1 has a first ramp portion 15BP1, and the slope angle θ of the first ramp portion 15BP1 is less than or equal to 42 degrees. The slope angle is the angle between the tangent of the first ramp portion 15BP1 and the plane parallel to the substrate 11.

[0156] For example, since the pixel defining layer 15 includes the partition structure layer 15A and the first defining layer 15B disposed on the side of the partition structure layer 15A away from the substrate 11, the slope angle θ of the first ramp portion 15BP1 is less than or equal to 42 degrees, and in the direction perpendicular to the substrate 11, the thickness of the light emitting functional layer 16 is matched with the thickness of the pixel defining layer and the slope angle θ of the first ramp portion 15BP1, so that the light extraction efficiency of the light emitting device OEL is improved.

[0157] In some embodiments, as shown in FIG. 7, the pixel defining layer 15 further includes a second defining layer 15C disposed on the side of the first defining layer 15B away from the substrate 11, and the second defining layer 15C is an inorganic material; at least part of the pixel defining structure 151 further includes a second partition groove 15K3 between the two adjacent sub-pixels 10P, and the second partition groove 15K3 penetrates the second defining layer 15C, and in the direction perpendicular to the plane where the substrate 11 is located, the thickness of the first defining layer 15B at the second partition groove 15K3 is greater than 0.

[0158] For example, the first defining layer 15B is an organic material, and in the case of incomplete curing, the first defining layer 15B will release gas under the physical conditions such as heating or UV irradiation during the manufacturing process, which will cause the light emitting functional layer 16 to bubble, break or peel off, etc. The trace gas released by the first defining layer 15B can have chemical or physical reactions with the film layers in the light emitting functional layer 16, thereby damaging the integrity of the light emitting functional layer 16, reducing the mobility of the lateral migration of the charge between the adjacent sub-pixels 10P, and thus improving or solving the problem of crosstalk between adjacent sub-pixels.

[0159] For example, the second partition groove 15K3 penetrates the second defining layer 15C, and the thickness of the first defining layer 15B at the second partition groove 15K3 is greater than 0, so that the light emitting functional layer 16 can contact the first defining layer 15B through the second partition groove 15K3.

[0160] For example, the second partition groove 15K3 can be in the shape of a slit or a strip,

[0161] In some embodiments, as shown in FIG. 2 and FIG. 8, the display substrate 100 includes a display area AA and a non-display area BB located at least at one side of the display area AA, and at least part of the sub-pixel 10P is located in the display area AA; the display substrate 100 further includes at least one first part 101D located in the non-display area BB, and the first part 101D is at least composed of the partition structure layer 15A; the display substrate 100 further includes a first conductive layer arranged between the base 11 and the pixel defining layer 15, and the first conductive layer includes a first wire 142 located in the non-display area BB, and the second electrode 17 is connected to the first wire 142 at one side of the first part 101D in a plane parallel to the base 11; the first limiting layer 15B includes a first slope 15XP, and the first slope 15XP is located at the connection between the second electrode 17 and the first wire 142, and the second electrode 17 is connected to the first wire 142 after extending on the first slope 15XP.

[0162] For example, the pixel defining layer 15 includes the partition structure layer 15A and the first limiting layer 15B arranged on the side of the partition structure layer 15A away from the base 11, the first limiting layer 15B is an organic material, and the first limiting layer 15B forms a first slope 15XP at the connection between the second electrode 17 and the first wire 142; the first limiting layer 15B of the organic material can form a transition slope, the first slope 15XP can carry the second electrode 17, and the second electrode 17 is connected to the first wire 142 after extending on the first slope 15XP, so that the second electrode 17 can be prevented from being broken at this position. Therefore, the pixel defining layer 15 of some embodiments of the present disclosure can prevent the connection between the conductive layers on the upper and lower sides of the pixel defining layer 15 from being broken.

[0163] In some embodiments, as shown in FIG. 2 and FIG. 8, the display substrate 100 further includes a first insulating layer 13 arranged between the first electrode 141 and the base 11, and the first insulating layer 13 is an organic material; the partition structure layer 15A includes at least one gas release hole 15AA1 located in the non-display area BB, and the gas release hole 15AA1 at least penetrates the partition structure layer 15A; the partition structure layer 15A is filled with an organic material, and the first limiting layer 15B is connected to the first insulating layer 13 through the organic material in the gas release hole 15AA1.

[0164] For example, the partition structure layer 15A filled with the organic material can be the first limiting layer 15B.

[0165] For example, the first limiting layer 15B is connected to the first insulating layer 13 through the organic material in the outgassing hole 15AA1. The first insulating layer 13 is an organic material. The first insulating layer 13 may, under the condition of incomplete curing, under the physical condition of temperature rise or UV irradiation during manufacturing, etc., appear outgassing phenomenon. The isolation structure layer 15A is an inorganic material. The isolation structure layer 15A has good gas barrier performance. The first limiting layer 15B is connected to the first insulating layer 13 through the organic material in the outgassing hole 15AA1. The first limiting layer 15B can make the gas released by the first insulating layer 13 escape from the first limiting layer 15B, avoiding the problems such as bubbling, fracture or peeling of the inorganic material in the isolation structure layer 15A and other film layers.

[0166] Please refer to FIG. 11 to FIG. 12, FIG. 11 is a first verification result schematic diagram provided by some embodiments of the present disclosure; FIG. 12 is a second verification result schematic diagram provided by some embodiments of the present disclosure.

[0167] Please refer to FIG. 3, FIG. 6 and FIG. 11. The brightness of each part on the display substrate or display panel is measured on the same straight line. The same color sub-pixel is located on the measurement straight line. FIG. 11(a) illustrates the measurement result of the related art, and FIG. 11(b) illustrates the measurement result of the present disclosure (with the first isolation structure 10g1 and the second isolation structure 10g2 of the present disclosure). In FIG. 11(a) and FIG. 11(b), the horizontal coordinate represents the measurement distance or length (the measuring instrument moves and measures according to a certain measurement step, and the unit of the horizontal coordinate is micrometer), and the vertical coordinate represents the light intensity (unit: candela). In FIG. 11(a) and FIG. 11(b), the dotted box 101k represents the light intensity or brightness of the area between the adjacent two light emitting devices, and the dotted circle 101q represents the light intensity or brightness in the light emitting device. As can be seen from FIG. 11(a), in the related art, since the charge generation layer 162 (CGL) or other film layer of the adjacent two light emitting devices OEL is a continuous film layer, there is a charge lateral migration phenomenon, which causes the display substrate 100 to have spectral crosstalk, and also causes the area between the adjacent two light emitting devices OEL to emit light. As can be seen from FIG. 11(b), in the present disclosure, since the first isolation structure 10g1 and the second isolation structure 10g2 make the charge generation layer 162 (CGL) or other film layer of the adjacent two light emitting devices OEL be a discontinuous film layer, the charge lateral migration phenomenon between the adjacent sub-pixels 10P is improved or avoided, the crosstalk of the display substrate 100 is improved, and the light emission in the area between the adjacent two light emitting devices OEL is also improved or avoided.

[0168] In addition, the inventors measured the luminance of each part of the display substrate or display panel on different straight lines using the measurement method shown in FIG. 11. The same color sub-pixels are located on the measurement straight line, or different color sub-pixels are located on the measurement straight line. Compared with the related art, some embodiments of the present disclosure greatly improve the crosstalk phenomenon between adjacent sub-pixels 10P, and also improve or avoid the light emission effect between the two adjacent light emitting devices OEL.

[0169] Please refer to FIGS. 3, 6 and 12. The spectrum of different pure color pictures is measured, and the spectrum of different gray scales or different luminances under the pure color picture is also measured. For example, the spectrum of red picture, green picture and blue picture is measured. FIG. 11 shows the spectrum under 413 nit and 111 nit of the red picture. In FIG. 12, the abscissa represents the wavelength (unit: nanometer), and the ordinate represents the light intensity (unit: candela). It can be seen from FIG. 12 that in the case of high gray scale (413 nit) or low gray scale (111 nit), there is no light intensity in the green wavelength and blue wavelength range. This shows that in the red picture, the green sub-pixel and the blue sub-pixel adjacent to the red sub-pixel do not emit light and do not have crosstalk phenomenon by using the technical solution of the present disclosure.

[0170] In addition, the inventors measured the spectrum of different gray scales or different luminances under the green picture, and found that in the green picture, the red sub-pixel and the blue sub-pixel adjacent to the green sub-pixel do not emit light and do not have crosstalk phenomenon by using the technical solution of the present disclosure. The inventors measured the spectrum of different gray scales or different luminances under the blue picture, and found that in the blue picture, the red sub-pixel and the green sub-pixel adjacent to the blue sub-pixel do not emit light and do not have crosstalk phenomenon by using the technical solution of the present disclosure.

[0171] In addition, the inventors measured in a display panel with a color gamut design value of DCIP3 (98%) that the charge generation layer 162 (CGL) or other film layers of the two adjacent light emitting devices OEL are discontinuous film layers due to the first partition structure 10g1 and the second partition structure 10g2 by using the technical solution of the present disclosure, which improves or avoids the charge lateral migration phenomenon between adjacent sub-pixels 10P, improves the spectrum crosstalk of the display substrate 100, and also improves or avoids the light emission between the two adjacent light emitting devices OEL, so that the color gamut value of the display panel is improved to 102.39%. Therefore, by using the technical solution of the present disclosure, the spectrum crosstalk of the display substrate 100 is improved, the light emission between the two adjacent light emitting devices OEL is improved or avoided, and the color gamut (color saturation) is also improved.

[0172] Please refer to FIG. 13 to FIG. 15, FIG. 13 is a fifth cross-sectional structure schematic diagram of a display substrate provided by some embodiments of the present disclosure; FIG. 14 is a sixth cross-sectional structure schematic diagram of a display substrate provided by some embodiments of the present disclosure; and FIG. 15 is a third verification result schematic diagram provided by some embodiments of the present disclosure. Among them, FIG. 11 is a cross-sectional structure before forming the charge generation layer 162, FIG. 12 is a cross-sectional structure formed after forming the charge generation layer 162 and after a baking process, and FIG. 12 is also the final cross-sectional structure of the display substrate 100 or the cross-sectional structure of the display panel 1000.

[0173] For example, before forming the charge generation layer 162, by controlling the curing temperature and time and other processes, the slope angle θ of the first ramp part 15BP1 is large, when the charge generation layer 162 is formed, it is easy to make the formed charge generation layer 162 disconnected at or near the first ramp part 15BP1, which can reduce the mobility of the lateral migration of charges between adjacent sub-pixels 10P, thereby improving or solving the problem of crosstalk between adjacent sub-pixels. After forming the charge generation layer 162, or after forming all the film layers of the light-emitting functional layer 16, a baking process is performed, so that the slope angle θ of the first ramp part 15BP1 is small, and when the second electrode 17 is formed again, the second electrode 17 is not easy to disconnect at or near the first ramp part 15BP1, thereby improving the voltage uniformity on the second electrode 17; At the same time, in the direction perpendicular to the substrate 11, the thickness of the light-emitting functional layer 16 is matched with the thickness of the pixel defining layer and the slope angle θ of the first ramp part 15BP1, so that the light-emitting efficiency of the light-emitting device OEL is improved.

[0174] For example, in some embodiments, as shown in FIG. 5 or 14, in the direction perpendicular to the plane where the substrate 11 is located, the thickness of the first defining layer 15B is 5 microns to 15 microns, for example, the thickness of the first defining layer 15B is any one of 5 microns, 6 microns, 7 microns, 8 microns, 9 microns, 10 microns, 11 microns, 12 microns, 13 microns, 14 microns and 15 microns. By setting a thicker first defining layer 15B, the slope angle θ of the first ramp part 15BP1 is less than or equal to 42 degrees, which can better improve the light-emitting efficiency of the display substrate or the display panel. At the same time, by setting a thicker first defining layer 15B, the slope angle θ of the first ramp part 15BP1 is large, when the charge generation layer 162 is formed, it is easy to make the formed charge generation layer 162 disconnected at or near the first ramp part 15BP1, which can reduce the mobility of the lateral migration of charges between adjacent sub-pixels 10P, thereby improving or solving the problem of crosstalk between adjacent sub-pixels.

[0175] For example, before forming the charge generation layer 162, the slope angle θ of the first ramp portion 15BP1 is set to be greater than or equal to 80 degrees, for example, the slope angle θ of the first ramp portion 15BP1 is set to be any one of 80 degrees, 81 degrees, 82 degrees, 83 degrees, 84 degrees, and 85 degrees.

[0176] For example, after forming the charge generation layer 162, and in the cross-sectional structure formed after the baking process, or in the final cross-sectional structure of the display substrate 100 or the cross-sectional structure of the display panel 1000, the slope angle θ of the first ramp portion 15BP1 is set to be less than or equal to 42 degrees, for example, the slope angle θ of the first ramp portion 15BP1 is set to be any one of 42 degrees, 41 degrees, 40 degrees, 39 degrees, 38 degrees, and 35 degrees.

[0177] For example, the slope angle θ of the first ramp portion 15BP1 is set to be less than or equal to 42 degrees (or at the same time, the thickness of the first confinement layer 15B in the direction perpendicular to the plane where the base 11 is located is set to be 5 microns to 15 microns), and in the direction perpendicular to the base 11, the thickness of the light-emitting functional layer 16 is set to match the thickness of the pixel confinement layer and the slope angle θ of the first ramp portion 15BP1. Due to the setting of the first confinement layer 15B, the reflection of light emitted at a large angle can be increased, the forward (normal viewing angle) light emission in the sub-pixel can be increased, and the light emission efficiency of the light-emitting device can be improved.

[0178] For example, as shown in FIGS. 13 and 14, in some embodiments, the pixel confinement layer 15 only includes the first confinement layer 15B and does not include the partition structure layer 15A, that is, the pixel confinement layer 15 only includes an organic material. After forming the charge generation layer 162, and in the cross-sectional structure formed after the baking process, or in the final cross-sectional structure of the display substrate 100 or the cross-sectional structure of the display panel 1000, the slope angle θ of the first ramp portion 15BP1 is set to be less than or equal to 42 degrees.

[0179] For example, as shown in FIG. 4, in some embodiments, the pixel confinement layer 15 includes the first confinement layer 15B and other film layers in addition to the first confinement layer 15B, for example, the pixel confinement layer 15 further includes the partition structure layer 15A. After forming the charge generation layer 162, and in the cross-sectional structure formed after the baking process, or in the final cross-sectional structure of the display substrate 100 or the cross-sectional structure of the display panel 1000, the slope angle θ of the first ramp portion 15BP1 is set to be less than or equal to 42 degrees.

[0180] Please refer to FIG. 14 and FIG. 15, FIG. 15 illustrates the effect of luminance gain at normal viewing angle (or represents the light extraction efficiency gain at different slope angles θ) under the condition of different slope angles θ, the horizontal coordinate in FIG. 15 represents the slope angle θ of the first climbing part 15BP1 (the slope angle θ is from 35 degrees to 85 degrees), and the vertical coordinate represents the luminance gain or light extraction efficiency gain, the luminance gain at normal viewing angle is the ratio of the luminance at a slope angle θ to the luminance of the related art display panel. As can be seen from FIG. 15, when the slope angle θ of the first climbing part 15BP1 is less than or equal to 42 degrees, the luminance gain at normal viewing angle increases (or the light extraction efficiency increases), for example, when the slope angle θ is 40 degrees, the luminance gain at normal viewing angle is 124.04%.

[0181] Please refer to FIG. 16 to FIG. 18, FIG. 16 is a second partial top view of a display substrate provided by some embodiments of the present disclosure; FIG. 17 is a third partial top view of a display substrate provided by some embodiments of the present disclosure; FIG. 18 is a seventh cross-sectional structure schematic view of a display substrate provided by some embodiments of the present disclosure. Among them, FIG. 16 and FIG. 17 illustrate different shapes of the second partition groove 15K3.

[0182] For example, in some embodiments, as shown in FIG. 7, the pixel defining layer 15 includes a first defining layer 15B and a second defining layer 15C arranged on the side of the first defining layer 15B away from the substrate 11, the first defining layer 15B is an organic material, and the second defining layer 15C is an inorganic material; at least part of the pixel defining structure 151 further includes a second partition groove 15K3 between two adjacent sub-pixels 10P, the second partition groove 15K3 penetrates the second defining layer 15C, and the thickness of the first defining layer 15B at the second partition groove 15K3 is greater than 0 in the direction perpendicular to the plane where the substrate 11 is located.

[0183] For example, the first defining layer 15B is an organic material, and in the case of incomplete curing, the first defining layer 15B will release gas under physical conditions such as heating or UV irradiation during manufacturing, which will cause the light emitting functional layer 16 to blister, break or peel off, etc. A small amount of gas released by the first defining layer 15B can chemically or physically react with the film layer in the light emitting functional layer 16, thereby damaging the integrity of the light emitting functional layer 16 and reducing the mobility of the lateral migration of charges between adjacent sub-pixels 10P, thereby improving or solving the problem of crosstalk between adjacent sub-pixels.

[0184] For example, the second partition groove 15K3 penetrates the second defining layer 15C, and the thickness of the first defining layer 15B at the second partition groove 15K3 is greater than 0, so that the light emitting functional layer 16 can contact the first defining layer 15B through the second partition groove 15K3.

[0185] For example, compared with the example of FIG. 7, the pixel defining layer 15 in the example of FIG. 18 includes the first defining layer 15B, and the second defining layer 15C disposed on the side of the first defining layer 15B away from the substrate 11, and the pixel defining layer 15 does not include the partition structure layer 15A.

[0186] For example, in the example of FIG. 7 and FIG. 18, in some embodiments, the display substrate 1000 can only include the second partition groove 15K3, and the display substrate 1000 can also simultaneously include the first partition structure 10g1 and the second partition groove 15K3.

[0187] For example, in the example of FIG. 7 and FIG. 18, in some embodiments, the second partition groove 15K3 can be disposed on the pixel defining structure 151 between any two adjacent sub-pixels 10P.

[0188] For example, in the example of FIG. 7 and FIG. 18, as shown in FIG. 16 and FIG. 17, in some embodiments, due to the incomplete curing of the first defining layer 15B, the first defining layer 15B can release gas under the physical conditions such as heating or UV irradiation during the manufacturing process, and the released gas does not have chemical or physical reaction with the second electrode 17. The orthogonal projection of the first partition structure 10g1 on the substrate 11 can be a closed ring, which can better improve or avoid the phenomenon of lateral migration of charges between adjacent sub-pixels 10P, thereby improving or solving the problem of crosstalk between adjacent sub-pixels.

[0189] It should be noted that in some embodiments, the features in the examples of FIG. 14 and FIG. 18 can be combined, for example, the pixel defining layer 15 includes the first defining layer 15B and the second defining layer 15C.

[0190] It should be noted that in some embodiments, the pixel defining layer 15 includes the first defining layer 15B and the second defining layer 15C, and at least part of the pixel defining structure 151 further includes the second partition groove 15K3 between the adjacent two sub-pixels 10P.

[0191] It should be noted that in some other embodiments, the pixel defining layer 15 includes the first defining layer 15B and the second defining layer 15C, and the edge of the first defining layer 15B towards the side of the pixel opening 15K1 has the first ramp portion 15BP1, and the slope angle of the first ramp portion 15BP1 is less than or equal to 42 degrees, and the slope angle is the included angle between the tangent of the first ramp portion 15BP1 and the plane parallel to the substrate 11.

[0192] It should be noted that in some other embodiments, the pixel definition layer 15 includes a first definition layer 15B and a second definition layer 15C, the slope angle of the first ramp 15BP1 is less than or equal to 42 degrees, and the at least partial pixel definition structure 151 further includes a second partition groove 15K3 between two adjacent sub-pixels 10P.

[0193] Please refer to FIGS. 8-10, which illustrate that the non-display area BB of the display substrate 100 includes a crack prevention area 103, a dam area 104, a cathode overlap area 105, and a light-emitting functional layer 16 excess area. The light-emitting functional layer 16 excess area is used to provide an error area for the manufacturing process of the light-emitting functional layer 16, and ensure that the light-emitting functional layer 16 is uniformly formed in the display area. The cathode overlap area 105 is located on the side of the light-emitting functional layer 16 excess area away from the display area AA, and in the cathode overlap area 105, the second electrode 17 is connected to the first trace 142 on the side surface of the first part 101D. The dam area 104 is located on the side of the cathode overlap area 105 away from the display area AA, and the dam area 104 includes a plurality of dams 201, which are at least composed of one layer of organic material. FIG. 8 illustrates that the dam 201 is composed of part of the first insulating layer 13, part of the first definition layer 15B, and part of the support column layer 18. The dam 201 is used to block the diffusion of the organic material in the encapsulation layer 19 to the edge of the display substrate 100. The crack prevention area 103 is located on the side of the dam area 104 away from the display area AA, and the crack prevention area 103 is used to block the cutting crack. The display substrate 100 includes a plurality of crack prevention units 1031 in the crack prevention area 103, and the crack prevention units 1031 have a crack prevention groove 1032 between two adjacent crack prevention units 1031. The crack prevention unit 1031 can be patterned from a plurality of inorganic material film layers.

[0194] For example, FIG. 8 illustrates that at least one gas release hole 15AA1 is provided in the first trace 142, and at least one gas release hole 15AA1 is provided in the first part 101D.

[0195] For example, FIG. 10 illustrates that the display substrate 100 further includes at least one pad terminal 15HP provided between the crack prevention unit 1031 and the dam 201. Part of the first insulating layer 13 (the first pattern 131 of the first insulating layer 13) covers both ends of the pad terminal 15HP, and the first insulating layer 13 (the first pattern 131 of the first insulating layer 13) exposes the pad terminal 15HP through the opening. The pad terminal 15HP is used to be connected to a circuit board or a driving chip.

[0196] For example, the non-display area BB of the display substrate 100 or the display panel 1000 includes a plurality of frame areas, and at least one frame area can be provided with a pad terminal 15HP. FIGS. 8 and 9 illustrate the cross-sectional structure of the frame area without the pad terminal 15HP, and FIG. 10 illustrates the cross-sectional structure of the frame area with the pad terminal 15HP.

[0197] For example, in FIG. 10, the second trace 122 connects the corresponding

[0198] For example, as shown in FIGS. 8 and 9, in a plane parallel to the plane on which the substrate 11 lies, the distance A1 from the edge of the display area AA to the edge of the light-emitting functional layer 16 is 50 micrometers to 2000 micrometers, for example, any one of 50 micrometers, 100 micrometers, 200 micrometers, 300 micrometers, 400 micrometers, 500 micrometers, 600 micrometers, 700 micrometers, 800 micrometers, 900 micrometers, 1000 micrometers, 1100 micrometers, and 1200 micrometers.

[0199] For example, as shown in FIGS. 8 and 9, in a plane parallel to the plane on which the substrate 11 lies, the distance B1 from the edge of the display area AA to the edge of the second electrode 17 is 500 micrometers to 8000 micrometers, for example, any one of 500 micrometers, 1000 micrometers, 2000 micrometers, 3000 micrometers, 4000 micrometers, 5000 micrometers, 6000 micrometers, 7000 micrometers, and 8000 micrometers.

[0200] For example, as shown in FIGS. 8 and 9, in a plane parallel to the plane on which the substrate 11 lies, the width of the connection site C1 of the second electrode 17 and the first trace 142 is 200 micrometers to 3000 micrometers, for example, any one of 200 micrometers, 400 micrometers, 600 micrometers, 800 micrometers, 1000 micrometers, 1200 micrometers, 1400 micrometers, 1600 micrometers, 1800 micrometers, 2000 micrometers, 2200 micrometers, 2400 micrometers, and 3000 micrometers.

[0201] For example, as shown in FIGS. 8 and 9, in a plane parallel to the plane on which the substrate 11 lies, the width of the connection site D1 of the first trace 142 and the second trace 122 is 200 micrometers to 3000 micrometers, for example, any one of 200 micrometers, 500 micrometers, 800 micrometers, 1100 micrometers, 1400 micrometers, 1700 micrometers, 2000 micrometers, 2300 micrometers, and 2600 micrometers.

[0202] For example, as shown in FIGS. 8 and 9, in a plane parallel to the plane on which the substrate 11 lies, the width E1 of the second trace 122 is 50 micrometers to 4000 micrometers, for example, any one of 50 micrometers, 100 micrometers, 300 micrometers, 600 micrometers, 900 micrometers, 1200 micrometers, 1500 micrometers, 1800 micrometers, 2100 micrometers, 2400 micrometers, and 2700 micrometers.

[0203] For example, as shown in FIGS. 8 and 9, the width of the edge of the dam 201 farthest from the display area AA to the edge of the encapsulation layer H1 in the plane parallel to the plane on which the substrate 11 lies can be 10 to 500 micrometers, for example, can be any one of 10 micrometers, 30 micrometers, 40 micrometers, 60 micrometers, 80 micrometers, 100 micrometers, 120 micrometers, 140 micrometers, 160 micrometers, 180 micrometers, 210 micrometers, 230 micrometers, 260 micrometers, and 280 micrometers.

[0204] For example, as shown in FIGS. 8 and 9, the distance between the adjacent two dams 201 (the distance J1 between the first dam and the second dam, the distance J2 between the second dam and the third dam) in the plane parallel to the plane on which the substrate 11 lies can be 2 to 500 micrometers, for example, can be any one of 2 micrometers, 5 micrometers, 10 micrometers, 20 micrometers, 30 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, 110 micrometers, 120 micrometers, 130 micrometers, and 150 micrometers.

[0205] For example, as shown in FIGS. 8 and 9, the width of the dam 201 (the width K1 of the first dam, the width K2 of the second dam, the width K3 of the third dam) in the plane parallel to the plane on which the substrate 11 lies can be 2 to 500 micrometers, for example, can be any one of 2 micrometers, 5 micrometers, 10 micrometers, 20 micrometers, 30 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, 110 micrometers, 120 micrometers, 130 micrometers, and 150 micrometers.

[0206] For example, as shown in FIGS. 8 and 9, the distance M1 from the edge of the crack prevention groove 1032 closest to the display area AA to the dam 201 farthest from the display area AA in the plane parallel to the plane on which the substrate 11 lies can be 50 to 1500 micrometers, for example, can be any one of 50 micrometers, 100 micrometers, 200 micrometers, 300 micrometers, 400 micrometers, 500 micrometers, 600 micrometers, 700 micrometers, 800 micrometers, and 900 micrometers.

[0207] For example, as shown in FIGS. 8 and 9, the distance N1 from the edge of the crack prevention groove 1032 closest to the display area AA to the edge of the encapsulation layer 19 in the plane parallel to the plane on which the substrate 11 lies can be 10 to 1500 micrometers, for example, can be any one of 10 micrometers, 50 micrometers, 100 micrometers, 200 micrometers, 300 micrometers, 400 micrometers, 500 micrometers, 600 micrometers, 700 micrometers, 800 micrometers, and 900 micrometers.

[0208] For example, as shown in FIGS. 8 and 9, the width S1 of the anti-cracking unit 1031 and the width W1 of the anti-cracking groove 1032 in parallel to the plane where the substrate 11 is located can be any one of 0.5 microns, 2 microns, 4 microns, 6 microns, 8 microns, 10 microns, 12 microns, 14 microns, 16 microns, 20 microns, 30 microns, 40 microns, 50 microns, and 100 microns.

[0209] For example, as shown in FIGS. 8 and 9, the total width P1 of the anti-cracking unit 1031 and the anti-cracking groove 1032 in parallel to the plane where the substrate 11 is located can be any one of 2 microns, 10 microns, 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns, 100 microns, 110 microns, and 150 microns.

[0210] For example, as shown in FIGS. 8 and 9, the distance Q1 from the edge of the display substrate 100 to the anti-cracking groove 1032 farthest from the display area AA in parallel to the plane where the substrate 11 is located can be any one of 10 microns, 20 microns, 40 microns, 50 microns, 100 microns, 200 microns, 300 microns, 400 microns, 500 microns, 600 microns, 700 microns, 800 microns, and 900 microns.

[0211] For example, as shown in FIGS. 8 and 9, the width R1 of the non-display area BB of the display substrate 100 in parallel to the plane where the substrate 11 is located can be any one of 100 microns, 500 microns, 1000 microns, 2000 microns, 3000 microns, 4000 microns, 5000 microns, 6000 microns, 7000 microns, 8000 microns, and 9000 microns.

[0212] For example, as shown in FIGS. 8 and 9, the width T1 of the air release hole 15AA1 in the first wire 142 in parallel to the plane where the substrate 11 is located can be any one of 2 microns, 10 microns, 15 microns, 20 microns, 25 microns, 30 microns, 35 microns, 40 microns, 45 microns, and 50 microns.

[0213] For example, as shown in FIGS. 8 and 9, the distance from the first organic material sub-layer 192 to the edge of the second electrode 17 in the encapsulation layer 19 in parallel to the plane where the substrate 11 is located can be any one of 10 microns, 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns, 100 microns, 200 microns, 300 microns, 400 microns, and 500 microns.

[0214] For example, as shown in FIG. 10, in parallel to the plane on which the substrate 11 lies, the distance M2 from the edge of the pad terminal to the dam 201 farthest from the display area AA is 50 to 1500 micrometers, for example, can be any of 50 micrometers, 100 micrometers, 200 micrometers, 300 micrometers, 400 micrometers, 500 micrometers, 600 micrometers, 700 micrometers, 800 micrometers, 900 micrometers, 1000 micrometers, 1100 micrometers, 1200 micrometers, 1300 micrometers, 1400 micrometers, and 1500 micrometers.

[0215] For example, as shown in FIG. 10, in parallel to the plane on which the substrate 11 lies, the distance M2 from the edge of the pad terminal to the dam 201 farthest from the display area AA is 50 to 1500 micrometers, for example, can be any of 50 micrometers, 100 micrometers, 200 micrometers, 300 micrometers, 400 micrometers, 500 micrometers, 600 micrometers, 700 micrometers, 800 micrometers, 900 micrometers, 1000 micrometers, 1100 micrometers, 1200 micrometers, 1300 micrometers, 1400 micrometers, and 1500 micrometers.

[0216] Referring to FIGS. 19-31, FIG. 19 is a first flow diagram of a manufacturing method of a display substrate according to some embodiments of the present disclosure; FIG. 20 is a first intermediate process diagram of a display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure; FIG. 21 is a first intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure; FIG. 22 is a second intermediate process diagram of a display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure; FIG. 23 is a second intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure; FIG. 24 is a third intermediate process diagram of a display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure; FIG. 25 is a third intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure; FIG. 26 is a fourth intermediate process diagram of a display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure; FIG. 27 is a fourth intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure; FIG. 28 is a fifth intermediate process diagram of a display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure; FIG. 29 is a fifth intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure; FIG. 30 is a sixth intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure; and FIG. 31 is a seventh intermediate process diagram of a non-display area of a manufacturing method of a display substrate according to some embodiments of the present disclosure.

[0217] The present disclosure also provides a manufacturing method of a display substrate, which can be used to manufacture the display substrate 100 of any one of the above, and the manufacturing method of the display substrate comprises the following steps: step S100, step S200, step S300, step S400 and step S500.

[0218] In step 100, a substrate is provided.

[0219] For example, as shown in FIG. 20, a substrate 11 is provided, which can be a glass or a flexible substrate 11, and the flexible substrate 11 can be a polyimide, which is not limited herein.

[0220] In step 200, a plurality of first electrodes are formed on one side of the substrate.

[0221] For example, as shown in FIGS. 20 and 21, a driving circuit layer is formed on one side of the substrate 11, which can include a plurality of pixel driving circuits, and the first electrode 141 is electrically connected to a corresponding pixel driving circuit, and the pixel driving circuit is used to drive the light emitting device OEL to emit light.

[0222] For example, as shown in FIGS. 20 and 21, the manufacturing method of the display substrate includes: forming the first metal layer 12 on one side of the base 11, the first metal layer 12 includes a plurality of drain electrodes 121 (or source electrodes) in the display area AA; forming the first insulating layer 13 on the side of the first metal layer 12 away from the base 11, the first insulating layer 13 can be an organic material, and the first insulating layer 13 can be a planar layer; forming the first electrode layer 14 on the side of the first insulating layer 13 away from the base 11, the first electrode layer 14 includes a plurality of first electrodes 141 in the display area AA, and the first electrodes 141 are connected to the corresponding drain electrodes 121 through the via holes in the first insulating layer 13.

[0223] For example, as shown in FIGS. 20 and 21, in the non-display area BB, the first metal layer 12 includes a second trace 122, and the first electrode layer 14 includes a first trace 142, and the first trace 142 is connected to the second trace 122 through the via hole in the first insulating layer 13.

[0224] For example, as shown in FIGS. 20 and 21, in the non-display area BB, when the first insulating layer 13 is formed, the first insulating layer 13 is also patterned to form a plurality of dam 201 first sub-layer parts 13D.

[0225] For example, as shown in FIG. 8, in some embodiments, at least one first sub-layer part 13D is covered by a dam inorganic material layer 15AD, the dam inorganic material layer 15AD is patterned from the inorganic material film layer such as the partition structure layer 15A, and at least one gas release hole 15AA1 can be provided in the dam inorganic material layer 15AD to communicate the organic material film layers in the dam 201 at different film layers so as to release the gas in the organic material film layers.

[0226] For example, as shown in FIGS. 20 and 21, in the non-display area BB, when the first electrode layer 14 is patterned, a gas release hole 15AA1 is also formed in the film layer part of the first electrode layer 14 such as the first trace 141, so as to communicate the organic material film layers on the upper and lower sides of the first electrode layer 14.

[0227] Step 300, forming a pixel defining layer on the side of the first electrode away from the base, the pixel defining layer includes a plurality of pixel defining structures and a plurality of pixel openings of a plurality of sub-pixels defined by the plurality of pixel defining structures, and the pixel opening exposes the first electrode; wherein the pixel defining layer includes a partition structure layer and a first defining layer provided on the side of the partition structure layer away from the base, the partition structure layer includes at least one film layer, and the first defining layer is an organic material; wherein the pixel defining structure between at least two adjacent sub-pixels includes a first partition structure formed by the partition structure layer on at least one side of the pixel opening.

[0228] For example, as shown in FIGS. 22-30, the pixel defining layer 15 is formed on the side of the first electrode 141 away from the substrate 11, the pixel defining layer 15 includes a plurality of pixel defining structures 151, and a plurality of pixel openings 15K1 of a plurality of sub-pixels 10P defined by the plurality of pixel defining structures 151, the pixel openings 15K1 exposing the first electrode 141; wherein the pixel defining layer 15 includes a partition structure layer 15A and a first defining layer 15B disposed on the side of the partition structure layer 15A away from the substrate 11, the partition structure layer 15A includes at least one film layer, and the first defining layer 15B is an organic material; wherein the pixel defining structure 151 between at least two adjacent sub-pixels 10P includes a first partition structure 10g1 formed by the partition structure layer 15A on at least one side of the pixel opening 15K1.

[0229] Step 400, forming a light-emitting functional layer on the side of the first electrode away from the substrate, the light-emitting functional layer including a plurality of film layers, at least part of at least one film layer in the light-emitting functional layer being broken at the first partition structure.

[0230] For example, as shown in FIG. 31, the light-emitting functional layer 16 is formed on the side of the first electrode 141 away from the substrate 11, the light-emitting functional layer 16 includes a plurality of film layers, and at least part of at least one film layer in the light-emitting functional layer 16 is broken at the first partition structure 10g1.

[0231] Step 500, forming a second electrode on the side of the light-emitting functional layer away from the substrate.

[0232] For example, as shown in FIG. 31, the second electrode 17 is formed on the side of the light-emitting functional layer 16 away from the substrate 11.

[0233] In some embodiments, the step of forming the pixel defining layer 15 on the side of the first electrode 141 away from the substrate 11 (step S300) includes steps S301, S302, S303, and S304.

[0234] Step S301, as shown in FIGS. 22 and 23, forming a third sub-film layer 15A3 of the partition structure layer 15A on the substrate 11, forming a fourth sub-film layer 15A4 of the partition structure layer 15A on the side of the third sub-film layer 15A3 away from the substrate 11, patterning the third sub-film layer 15A3 and the fourth sub-film layer 15A4 by the same patterning process, and the orthographic projection of the third sub-film layer 15A3 on the substrate 11 and the orthographic projection of the fourth sub-film layer 15A4 on the substrate 11 do not overlap with the orthographic projection of the first electrode 141 on the substrate 11.

[0235] For example, patterning the third sub-film layer 15A3 and the fourth sub-film layer 15A4 by the same patterning process can reduce the number of manufacturing process steps.

[0236] At step S302, as shown in FIGS. 24 and 25, a first sub-film layer 15A1 of the partition structure layer 15A is formed on the fourth sub-film layer 15A4 and the first electrode 141 away from the substrate 11, and a second sub-film layer 15A2 of the partition structure layer 15A is formed on the first sub-film layer 15A1 away from the substrate 11.

[0237] At step S303, as shown in FIGS. 26 and 27, a first limiting layer 15B is formed on the second sub-film layer 15A2 away from the substrate 11, and the first limiting layer 15B is patterned.

[0238] For example, after the first limiting layer 15B is patterned, the first limiting layer 15B includes a plurality of pixel defining structures 151 located in the display area AA, and a plurality of second sub-layer parts 15BD of the plurality of dams 201 located in the non-display area BB.

[0239] For example, as shown in FIGS. 28 and 29, between step S303 and step S304, a support column layer 18 can also be formed on the first limiting layer 15B away from the substrate 11, and the support column layer 18 includes a plurality of support columns 181 located in at least the display area AA, and a plurality of third sub-layer parts 182D of the plurality of dams 201 located in the non-display area BB.

[0240] At step S304, as shown in FIG. 30, the first sub-film layer 15A1 and the second sub-film layer 15A2 are patterned by the same patterning process to form the first partition structure 10g1.

[0241] For example, by patterning the first sub-film layer 15A1 and the second sub-film layer 15A2 by the same patterning process, the number of process steps can be reduced.

[0242] For example, by first patterning the first limiting layer 15B at step S303, the first limiting layer 15B can be used as a mask for patterning the first sub-film layer 15A1 and the second sub-film layer 15A2, thereby reducing the number of masks and saving costs.

[0243] In some embodiments, as shown in FIGS. 28 and 30, in the step of patterning the first sub-film layer 15A1 and the second sub-film layer 15A2 by the same patterning process (step S304), a second partition structure 10g2 located between at least two adjacent sub-pixels 10P in the pixel defining structure 151 is also formed; at least part of at least one film layer in the light emitting functional layer 16 is disconnected at the second partition structure 10g2.

[0244] For example, since the material of the first sub-film layer 15A1 and the fourth sub-film layer 15A4 is the same, after etching the first sub-film layer 15A1, the fourth sub-film layer 15A4 is also etched, that is, when the first sub-film layer 15A1 and the second sub-film layer 15A2 are patterned in the same patterning process, the fourth sub-film layer 15A4 is also etched to form the second partition structure 10g2.

[0245] In some embodiments, please refer to FIG. 13 and FIG. 14, in the step of forming the light-emitting functional layer 16 on the side of the first electrode 141 away from the substrate 11 (step S400), the method for manufacturing the display substrate 100 further comprises: forming a charge generation layer 162 in the light-emitting functional layer 16; after forming the charge generation layer 162, and before the step of forming the second electrode 17 on the side of the light-emitting functional layer 16 away from the substrate 11, the method for manufacturing the display substrate 100 further comprises: baking the display substrate 100, wherein after baking the display substrate 100, in at least part of the pixel defining structure 151, the first limiting layer 15B has a first ramp portion 15BP1 on the edge of the side of the first limiting layer 15B facing the pixel opening 15K1, and the slope angle of the first ramp portion 15BP1 is less than or equal to 42 degrees, and the slope angle is the included angle between the tangent of the first ramp portion 15BP1 and the plane parallel to the substrate 11.

[0246] In some embodiments, please refer to FIG. 7 and FIG. 18, in the step of forming the pixel defining layer 15 on the side of the first electrode 141 away from the substrate 11, the method for manufacturing the display substrate 100 further comprises: forming a second limiting layer 15C on the side of the first limiting layer 15B away from the substrate 11, the second limiting layer 15C is an inorganic material, and the at least part of the pixel defining structure 151 further comprises a second partition groove 15K3 between two adjacent sub-pixels 10P, the second partition groove 15K3 penetrates the second limiting layer 15C, and the thickness of the first limiting layer 15B at the second partition groove 15K3 in the direction perpendicular to the plane where the substrate 11 is located is greater than 0.

[0247] In some embodiments, the display substrate 100 comprises a display area AA and a non-display area BB located at least at one side of the display area AA, and at least part of the sub-pixels 10P are located in the display area AA; the display substrate 100 further comprises at least one first part 101D located in the non-display area BB, and the first part 101D is at least composed of the partition structure layer 15A; before the step of forming the pixel defining layer 15 on the side of the first electrode 141 away from the substrate 11, the method further comprises: forming a first conductive layer (the first electrode layer 14 is the first conductive layer as shown in FIG. 8), and the first conductive layer comprises a first trace 142 located in the non-display area BB; in the step of forming the pixel defining layer 15 on the side of the first electrode 141 away from the substrate 11, the first defining layer 15B forms a first slope 15XP (as shown in FIG. 29); after the step of forming the second electrode 17 on the side of the light-emitting functional layer 16 away from the substrate 11, the second electrode 17 is connected to the first trace 142 on the side of the first part 101D in a plane parallel to the plane where the substrate 11 is located, the first slope 15XP is located at the connection between the second electrode 17 and the first trace 142, and the second electrode 17 extends on the first slope 15XP and is connected to the first trace 142 (please refer to FIGS. 8-10).

[0248] Please refer to FIG. 32, which is a second flowchart of a method for manufacturing a display substrate according to some embodiments of the present disclosure; FIG. 32 illustrates another method for manufacturing a display substrate according to the present disclosure, and the display substrates shown in FIGS. 4-7 and FIG. 14 can be manufactured by using the method for manufacturing a display substrate, and the method for manufacturing a display substrate comprises steps K100, K200, K300, K400, K500 and K600.

[0249] K100, providing a substrate.

[0250] K200, forming a plurality of first electrodes on one side of the substrate.

[0251] K300, forming a pixel defining layer on the side of the first electrode away from the substrate, the pixel defining layer comprises a plurality of pixel defining structures, and a plurality of pixel openings of a plurality of sub-pixels defined by the plurality of pixel defining structures, and the pixel openings expose the first electrode; wherein the pixel defining layer comprises a first defining layer, and the first defining layer is an organic material.

[0252] K400, forming a charge generation layer in a light-emitting functional layer on the side of the first electrode away from the substrate.

[0253] K500, baking the substrate, after baking the display substrate, in at least part of the pixel defining structure, the first defining layer has a first ramping portion towards the edge of the side of the pixel opening, the slope angle of the first ramping portion is less than or equal to 42 degrees, and the slope angle is the included angle between the tangent of the first ramping portion and the plane parallel to the base.

[0254] For example, when the charge generation layer 162 is formed (before the substrate is baked), the slope angle θ of the first ramping portion 15BP1 is large, and the slope angle θ of the first ramping portion 15BP1 is greater than or equal to 80 degrees, for example, the slope angle θ of the first ramping portion 15BP1 is any one of 80 degrees, 81 degrees, 82 degrees, 83 degrees, 84 degrees and 85 degrees. When the charge generation layer 162 is formed (before the substrate is baked), the slope angle θ of the first ramping portion 15BP1 is large, which is easy to make the formed charge generation layer 162 break at the first ramping portion 15BP1 or near the first ramping portion 15BP1, which can reduce the mobility of the lateral migration of charges between adjacent sub-pixels 10P, thereby improving or solving the problem of crosstalk between adjacent sub-pixels.

[0255] For example, after the charge generation layer 162 is formed, and in the cross-sectional structure formed after the baking process, or in the final cross-sectional structure of the display substrate 100 or the cross-sectional structure of the display panel 1000, the slope angle θ of the first ramping portion 15BP1 is set to be less than or equal to 42 degrees, for example, the slope angle θ of the first ramping portion 15BP1 is any one of 42 degrees, 41 degrees, 40 degrees, 39 degrees, 38 degrees and 35 degrees.

[0256] For example, the slope angle θ of the first ramping portion 15BP1 is set to be less than or equal to 42 degrees (or at the same time, the thickness of the first defining layer 15B in the direction perpendicular to the plane where the base 11 is located is 5 microns to 15 microns), in the direction perpendicular to the base 11, the thickness of the light-emitting functional layer 16 is matched with the thickness of the pixel defining layer, and the slope angle θ of the first ramping portion 15BP1, and due to the setting of the first defining layer 15B, the reflection of light emitted at a large angle can be increased, the forward (normal viewing angle) light emission in the sub-pixel can be increased, and the light-emitting device light emission efficiency can be improved.

[0257] For example, as shown in FIGS. 13 and 14, in some embodiments, the pixel defining layer 15 only includes the first defining layer 15B and does not include the partition structure layer 15A, that is, the pixel defining layer 15 only includes organic material, after the charge generation layer 162 is formed, and in the cross-sectional structure formed after the baking process, or in the final cross-sectional structure of the display substrate 100 or the cross-sectional structure of the display panel 1000, the slope angle θ of the first ramping portion 15BP1 is set to be less than or equal to 42 degrees.

[0258] For example, as shown in FIG. 4, in some embodiments, the pixel defining layer 15 includes the first defining layer 15B, and other film layers outside the first defining layer 15B, for example, the pixel defining layer 15 further includes the partition structure layer 15A or / and the second defining layer 15C, and the slope angle θ of the first ramp portion 15BP1 is less than or equal to 42 degrees in the cross-sectional structure formed after the baking process after forming the charge generation layer 162, or in the final cross-sectional structure of the display substrate 100 or the cross-sectional structure of the display panel 1000.

[0259] For example, in some embodiments, as shown in FIG. 5 or 14, the thickness of the first defining layer 15B is 5 microns to 15 microns in the direction perpendicular to the plane where the substrate 11 is located, for example, the thickness of the first defining layer 15B is any one of 5 microns, 6 microns, 7 microns, 8 microns, 9 microns, 10 microns, 11 microns, 12 microns, 13 microns, 14 microns and 15 microns. By setting a thicker first defining layer 15B, the slope angle θ of the first ramp portion 15BP1 is less than or equal to 42 degrees, which can better improve the light extraction efficiency of the display substrate or the display panel. At the same time, by setting a thicker first defining layer 15B, the slope angle θ of the first ramp portion 15BP1 is larger, which makes it easier to make the formed charge generation layer 162 break at the first ramp portion 15BP1 or near the first ramp portion 15BP1 when forming the charge generation layer 162, which can reduce the mobility of the charge lateral migration between adjacent sub-pixels 10P, thereby improving or solving the problem of crosstalk between adjacent sub-pixels.

[0260] K600, a second electrode is formed on the side of the light-emitting functional layer away from the substrate.

[0261] The present disclosure also provides a display panel, which includes the display substrate 100 of any one of the above, or the display panel includes the display substrate 100 combined by any one of the above, or the display panel is manufactured by the manufacturing method of the display substrate of any one of the above.

[0262] The present disclosure also provides a display device, which includes the display substrate 100 of any one of the above, or the display device includes the display substrate 100 combined by any one of the above, or the display device is manufactured by the manufacturing method of the display substrate of any one of the above.

[0263] For example, in some embodiments, the display device can be a display panel.

[0264] For example, the display device can be a mobile phone, a notebook computer, a television, etc.

[0265] In some embodiments of the present disclosure, by setting the partition structure layer, the pixel defining structure between at least two adjacent sub-pixels includes a first partition structure formed by the partition structure layer on at least one side of the pixel opening, and at least part of at least one film layer in the light-emitting functional layer is disconnected at the first partition structure, which can improve or avoid the phenomenon of lateral migration of charges between adjacent sub-pixels, thereby improving or solving the problem of crosstalk between adjacent sub-pixels. At the same time, the first limiting layer is arranged on the side of the partition structure layer away from the substrate, the first limiting layer is an organic material, and in a plane parallel to the substrate, the first limiting layer fills the side of the pattern of the partition structure layer (the first limiting layer covers the side of the first part) to form a gentle slope (the first slope). The gentle slope (the first slope) can well bear the second electrode at the connection between the second electrode and the first trace, and the second electrode extends on the gentle slope (the first slope) and then connects the first trace, so that the second electrode can be prevented from being broken at this position. That is, the pixel defining layer of some embodiments of the present disclosure has the problem of preventing the connection between the conductive layers on the upper and lower sides of the pixel defining layer from being broken.

[0266] In some embodiments of the present disclosure, by setting the first limiting layer, the thickness of the partition structure layer is small, and the problem of short circuit between the first electrode and the second electrode caused by the abnormality of the partition structure layer wrapping the edge of the first electrode (the abnormality of the first sub-film layer covering the first electrode) is avoided. That is, when the abnormality of the partition structure layer wrapping the edge of the first electrode occurs, the first limiting layer also covers the first electrode, thereby preventing the short circuit between the first electrode and the second electrode.

[0267] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0268] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

[0269] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they understand the basic creative concept. Therefore, the appended claims are intended to include the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0270] Obviously, many modifications and variations of the present teachings are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the present teachings can be practiced otherwise than as specifically described.

Claims

1. A display substrate, comprising a substrate, a pixel defining layer disposed on one side of the substrate, and a plurality of sub-pixels, wherein the pixel defining layer includes a plurality of pixel defining structures and a plurality of pixel openings defined by the plurality of pixel defining structures, and the pixel openings are configured to define the light-emitting areas of the sub-pixels; The sub-pixel includes a light-emitting device, the light-emitting device includes a first electrode and a second electrode located on the side of the first electrode away from the substrate, and a light-emitting functional layer located between the first electrode and the second electrode, the light-emitting functional layer including multiple film layers; in, The pixel defining layer includes a partition structure layer and a first defining layer disposed on the side of the partition structure layer away from the substrate. The partition structure layer includes at least one film layer, and the first defining layer is an organic material. The pixel defining structure between at least two adjacent sub-pixels includes a first partition structure formed by the partition structure layer on at least one side of the pixel opening, wherein at least a portion of at least one film layer in the light-emitting functional layer is broken at the first partition structure.

2. The display substrate according to claim 1, wherein, The first partition structure is formed by the partition structure layer being recessed inward on at least one side facing the pixel opening; The material of the partition structure layer is an inorganic material.

3. The display substrate according to claim 2, wherein, The isolation structure layer includes a first sub-film layer and a second sub-film layer stacked sequentially in a direction away from the substrate. The first sub-film layer is at least partially disposed on the side of the first electrode away from the substrate. The first isolation structure is formed by the inward indentation of the edge of the first sub-film layer relative to the second sub-film layer.

4. The display substrate according to claim 1, wherein, The pixel-defining structure between at least two adjacent sub-pixels further includes a second partition structure located between the two adjacent sub-pixels, wherein at least a portion of at least one film layer in the light-emitting functional layer is broken at the second partition structure.

5. The display substrate according to claim 4, wherein, The first partition structure and the second partition structure have different heights in a direction perpendicular to the plane of the base.

6. The display substrate according to claim 4, wherein, At least a portion of the pixel defining structure further includes a first partition groove that penetrates at least the first defining layer and at least a portion of the film layer of the partition structure layer, the first partition groove exposing the second partition structure.

7. The display substrate according to claim 6, wherein, The isolation structure layer includes a third sub-film layer, a first sub-film layer and a second sub-film layer stacked sequentially in a direction away from the substrate, wherein the first sub-film layer is at least partially disposed on the side of the first electrode away from the substrate; The first partition structure is formed by the inward recess of the edge of the first sub-film layer relative to the second sub-film layer; The second partition structure is formed by the first sub-film layer being recessed at its edge relative to the second sub-film layer; In a direction perpendicular to the plane of the substrate, the thickness of the third sub-film layer at the first partition groove is greater than 0.

8. The display substrate according to claim 7, wherein, The partition structure layer further includes a fourth sub-membrane layer disposed between the third sub-membrane layer and the first sub-membrane layer; The second partition structure is formed by the inward recess of the first sub-membrane layer and the fourth sub-membrane layer relative to the edge of the second sub-membrane layer.

9. The display substrate according to claim 8, wherein, The first sub-film layer is made of the same material as the fourth sub-film layer.

10. The display substrate according to claim 9, wherein, The first sub-film layer and the fourth sub-film layer are made of silicon oxide, and the third sub-film layer and the second sub-film layer are made of silicon nitride.

11. The display substrate according to claim 8, wherein, The orthographic projections of the third sub-film layer and the fourth sub-film layer on the substrate do not overlap with the orthographic projection of the first electrode on the substrate.

12. The display substrate according to claim 4, wherein, The plurality of said sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels; In the red sub-pixel, the green sub-pixel, and the blue sub-pixel, the pixel defining structure includes the first partition structure; Of the two adjacent sub-pixels located on both sides of the second partition structure, at least one is a red sub-pixel or a green sub-pixel.

13. The display substrate according to claim 4, wherein, The first partition structure, when projected onto the substrate, forms a closed loop. The second partition structure has a non-closed ring shape when projected onto the substrate.

14. The display substrate according to claim 1, wherein, In at least a portion of the pixel-defining structure, the edge of the first defining layer facing the pixel opening has a first ramp, the ramp angle of which is less than or equal to 42 degrees, the ramp angle being the angle between the tangent of the first ramp and a plane parallel to the substrate.

15. The display substrate according to claim 1, wherein, The pixel defining layer further includes a second defining layer disposed on the side of the first defining layer away from the substrate, the second defining layer being an inorganic material; At least a portion of the pixel-defining structure further includes a second partition groove located between two adjacent sub-pixels, the second partition groove penetrating the second defining layer, and the thickness of the first defining layer at the second partition groove being greater than 0 in a direction perpendicular to the plane of the substrate.

16. The display substrate according to any one of claims 1 to 15, wherein, The display substrate includes a display area and a non-display area located at least on one side of the display area, and at least a portion of the sub-pixels are located in the display area; The display substrate further includes at least one first portion located in the non-display area, the first portion being at least composed of the partition structure layer; The display substrate further includes a first conductive layer disposed between the substrate and the pixel defining layer. The first conductive layer includes a first trace located in the non-display area. On a plane parallel to the substrate, a second electrode is connected to the first trace on one side of the first portion. The first limiting layer includes a first ramp located at the connection between the second electrode and the first trace, and the second electrode extends on the first ramp and connects to the first trace.

17. The display substrate according to claim 16, wherein, The display substrate further includes a first insulating layer disposed between the first electrode and the substrate. The first insulating layer is an organic material. The partition structure layer includes at least one vent hole located in the non-display area. The vent hole penetrates at least through the partition structure layer. The partition structure layer is filled with organic material. The first limiting layer is connected to the first insulating layer through the organic material in the vent hole.

18. A method for manufacturing a display substrate, comprising: Provide a base; A plurality of first electrodes are formed on one side of the substrate; A pixel defining layer is formed on the side of the first electrode away from the substrate. The pixel defining layer includes a plurality of pixel defining structures and a plurality of pixel openings of a plurality of sub-pixels defined by the plurality of pixel defining structures, the pixel openings exposing the first electrode. The pixel defining layer includes a partition structure layer and a first defining layer disposed on the side of the partition structure layer away from the substrate. The partition structure layer includes at least one film layer, and the first defining layer is an organic material. The pixel defining structure between at least two adjacent sub-pixels includes a first partition structure formed by the partition structure layer on at least one side of the pixel opening. A light-emitting functional layer is formed on the side of the first electrode away from the substrate. The light-emitting functional layer includes a plurality of film layers, and at least a portion of at least one of the film layers is broken at the first partition structure. A second electrode is formed on the side of the light-emitting functional layer away from the substrate.

19. The method for manufacturing a display substrate according to claim 18, wherein, The step of forming a pixel-defining layer on the side of the first electrode away from the substrate includes: A third sub-film layer of the isolation structure layer is formed on the substrate, and a fourth sub-film layer of the isolation structure layer is formed on the side of the third sub-film layer away from the substrate. The third sub-film layer and the fourth sub-film layer are patterned by the same patterning process. The orthographic projection of the third sub-film layer on the substrate and the orthographic projection of the fourth sub-film layer on the substrate do not overlap with the orthographic projection of the first electrode on the substrate. A first sub-film layer of the isolation structure layer is formed on the side of the fourth sub-film layer and the first electrode away from the substrate, and a second sub-film layer of the isolation structure layer is formed on the side of the first sub-film layer away from the substrate. The first defining layer is formed on the side of the second sub-film layer away from the substrate, and the first defining layer is patterned; The first sub-film layer and the second sub-film layer are patterned using the same patterning process to form the first partition structure.

20. The method for manufacturing a display substrate according to claim 19, wherein, In the step of patterning the first sub-film layer and the second sub-film layer using the same patterning process, a second partition structure is also formed between at least partially adjacent sub-pixels in the pixel definition structure. At least a portion of at least one of the films in the light-emitting functional layer is broken at the second partition structure.

21. The method for manufacturing a display substrate according to claim 18, wherein, The step of forming a light-emitting functional layer on the side of the first electrode away from the substrate includes forming a charge-generating layer in the light-emitting functional layer; After forming the charge-generating layer and before forming the second electrode on the side of the light-emitting functional layer away from the substrate, the method of manufacturing the display substrate further includes baking the display substrate, wherein, after baking the display substrate, in at least a portion of the pixel defining structure, the edge of the first defining layer facing the pixel opening has a first ramp portion, the ramp portion having a slope angle less than or equal to 42 degrees, the slope angle being the angle between the tangent of the first ramp portion and a plane parallel to the substrate.

22. The method for manufacturing a display substrate according to claim 18, wherein, The step of forming a pixel-defining layer on the side of the first electrode away from the substrate further includes: A second defining layer is formed on the side of the first defining layer away from the substrate. The second defining layer is an inorganic material. At least a portion of the pixel defining structure also includes a second partition groove located between two adjacent sub-pixels. The second partition groove penetrates the second defining layer. In a direction perpendicular to the plane of the substrate, the thickness of the first defining layer at the second partition groove is greater than 0.

23. The method for manufacturing a display substrate according to any one of claims 18 to 22, wherein, The display substrate includes a display area and a non-display area located at least on one side of the display area, and at least a portion of the sub-pixels are located in the display area; the display substrate also includes at least one first portion located in the non-display area, the first portion being at least composed of the partition structure layer; Before the step of forming a pixel defining layer on the side of the first electrode away from the substrate, the method further includes: forming a first conductive layer, the first conductive layer including a first trace located in the non-display area; In the step of forming a pixel defining layer on the side of the first electrode away from the substrate, the first defining layer forms a first slope; After the step of forming the second electrode on the side of the light-emitting functional layer away from the substrate, the second electrode is connected to the first trace on one side of the first portion on a plane parallel to the substrate. The first slope is located at the connection between the second electrode and the first trace, and the second electrode extends on the first slope and connects to the first trace.

24. A display device comprising a display substrate as claimed in any one of claims 1 to 17.

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