Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a display area (AA) and a non-display area (NA) surrounding the display area (AA). The display panel comprises: a first base substrate (31); a plurality of conductive layers (32), which are stacked in sequence on one side of the first base substrate (31) in the normal direction of the first base substrate (31); and a dimming structure (33), which is arranged on the side of at least one conductive layer (32) facing away from the first base substrate (31), wherein the dimming structure (33) is configured to transmit linearly-polarized light, the polarization direction of which is a first direction (f1).

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to the Chinese patent application No. 202410834135.1, filed on June 25, 2024, and entitled “Display panel and display device”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0004] The current meta-universe technology promotes the rapid development of virtual reality (VR), augmented reality (AR) and mixed reality (MR) display technology. AR, VR and MR technologies require display panels to have ultra-high resolution, ultra-high refresh rate, ultra-fast response and other characteristics.

[0005] SUMMARY

[0006] The present disclosure provides a display panel, comprising a display area and a non-display area surrounding the display area, the display panel comprising:

[0007] a first substrate;

[0008] a plurality of conductive layers, sequentially stacked on one side of the first substrate along the normal direction of the first substrate; and

[0009] a light modulation structure, disposed on the side of at least one of the conductive layers away from the first substrate, the light modulation structure being configured to transmit linearly polarized light with a polarization direction being a first direction.

[0010] In some embodiments, the display area comprises a plurality of sub-pixels, the sub-pixels comprising an opening area configured to transmit light;

[0011] A projection of the light modulation structure on the first substrate covers the display area, and a projection of the opening area of the sub-pixel on the first substrate is at least partially located outside the projection range of the light modulation structure on the first substrate.

[0012] In some embodiments, the light modulation structure comprises at least one light modulation pattern, a projection contour line of the light modulation pattern on the first substrate being parallel or perpendicular to the first direction.

[0013] In some embodiments, a projection of the light-adjusting structure on the first substrate covers the display area.

[0014] In some embodiments, the display panel comprises an array substrate, a counter substrate, and a liquid crystal layer between the array substrate and the counter substrate, the first substrate and the plurality of conductive layers are on the array substrate, and the counter substrate comprises a second substrate.

[0015] The light-adjusting structure comprises at least one of:

[0016] a first light-adjusting structure disposed on the array substrate and between one or more of the conductive layers and the liquid crystal layer; and

[0017] a second light-adjusting structure disposed on the counter substrate and between the second substrate and the liquid crystal layer.

[0018] In some embodiments, the conductive layers comprise scan lines and data lines disposed in different layers, and the first light-adjusting structure is disposed on a side of the scan lines and the data lines away from the first substrate.

[0019] A projection of the first light-adjusting structure on the first substrate covers a projection of the scan lines and the data lines on the first substrate.

[0020] In some embodiments, the conductive layers comprise first conductive patterns and second conductive patterns disposed in different layers, and the first conductive patterns and the second conductive patterns are connected by first vias.

[0021] The first light-adjusting structure is disposed on a side of the first conductive patterns and the second conductive patterns away from the first substrate, and a projection of the first light-adjusting structure on the first substrate covers a projection of the first vias on the first substrate.

[0022] In some embodiments, the plurality of conductive layers further comprises third conductive patterns, along a normal direction of the first substrate, the second conductive patterns are between the first conductive patterns and the third conductive patterns, and the second conductive patterns and the third conductive patterns are connected by second vias.

[0023] The first light-adjusting structure is disposed on a side of the third conductive patterns away from the first substrate, and a projection of the first light-adjusting structure on the first substrate further covers a projection of the second vias on the first substrate.

[0024] In some embodiments, the counter substrate further comprises:

[0025] A spacer column is disposed on a side of the second light-adjusting structure facing away from the second substrate, and a projection of the second light-adjusting structure on the second substrate covers a projection of the spacer column on the second substrate.

[0026] In some embodiments, the display area includes a plurality of sub-pixels, and the sub-pixels include an opening area for transmitting light;

[0027] The opposite substrate further includes: a light-blocking matrix disposed on a side of the second light-adjusting structure facing away from the second substrate, a projection of the light-blocking matrix on the second substrate is disposed around the opening area, and a contour line of the projection of the light-blocking matrix on the second substrate includes an arc line; and

[0028] A projection of the second light-adjusting structure on the second substrate covers the arc line.

[0029] In some embodiments, the display panel further includes:

[0030] A first polarizer is disposed on a side of the first substrate facing away from the plurality of conductive layers, and the first polarizer is configured to transmit linearly polarized light having a polarization direction of the first direction.

[0031] In some embodiments, the light-adjusting structure includes a plurality of bars arranged at equal intervals along a second direction, and the second direction is perpendicular to the first direction.

[0032] In some embodiments, the display area includes a plurality of sub-pixels, and the plurality of sub-pixels includes first sub-pixels and second sub-pixels, the first sub-pixels are configured to transmit first color light, and the second sub-pixels are configured to transmit second color light.

[0033] The display panel further includes:

[0034] A filter layer is disposed between the first substrate and the conductive layer, and the filter layer includes a plurality of filter patterns, the plurality of filter patterns includes a first filter pattern, in a projection of the first substrate, the first filter pattern overlaps the opening area of the first sub-pixel and does not overlap the opening area of the second sub-pixel, the first filter pattern is configured to transmit the first color light and reflect the second color light.

[0035] In some embodiments, the plurality of filter patterns further includes:

[0036] A second filter pattern, in an orthographic projection on the first substrate, the second filter pattern has an overlap with the opening area of the second sub-pixel and has no overlap with the opening area of the first sub-pixel, the second filter pattern is configured to transmit the second color light and reflect the first color light.

[0037] In some embodiments, the display panel further comprises:

[0038] A first planar layer disposed on the first substrate and a side of the filter layer close to the conductive layer, an orthographic projection of the first planar layer on the first substrate entirely covers the first substrate, and a surface of the first planar layer away from the first substrate is planar; or

[0039] A second planar layer filled in a gap between the plurality of filter patterns, a surface of the second planar layer away from the first substrate is substantially flush with a surface of the filter pattern away from the first substrate.

[0040] In some embodiments, the conductive layer comprises:

[0041] A semiconductor layer disposed on a side of the filter layer away from the first substrate, the semiconductor layer comprises a transistor active layer of different sub-pixels; and

[0042] In an orthographic projection on the first substrate, the filter pattern entirely covers the transistor active layer of the same sub-pixel.

[0043] In some embodiments, the first sub-pixel comprises a red sub-pixel and a green sub-pixel, the first color light comprises red light and green light, the second sub-pixel comprises a blue sub-pixel, and the second color light comprises blue light.

[0044] In some embodiments, the plurality of conductive layers comprise a scan line and a data line disposed in different layers, the scan line is disposed on a side of the filter layer away from the first substrate, and the data line is disposed on a side of the filter layer away from or close to the first substrate.

[0045] In some embodiments, the filter pattern comprises a high-refractive layer and a low-refractive layer stacked and alternately arranged, the refractive index of the high-refractive layer is greater than the refractive index of the low-refractive layer.

[0046] The present disclosure provides a display device comprising:

[0047] The display panel as provided in any of the embodiments; and

[0048] A driving assembly connected to the display panel, configured to drive the display panel to emit light.

[0049] The above description is only a summary of the technical solutions of the present disclosure. In order to enable one skilled in the art to better understand the technical means of the present disclosure, the contents of the specification can be implemented, and in order to enable the above and other purposes, features and advantages of the present disclosure to be more apparent and easy to understand, the specific embodiments of the present disclosure are described below.

[0050] Brief Description of the Drawings

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the drawings needed to be used in the embodiments or related art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creative labor. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0052] FIG. 1 shows the bad pictures of several display panels in the related art;

[0053] FIG. 2 shows a planar structure schematic diagram of a display panel provided by the present disclosure;

[0054] FIG. 3 shows a structure schematic diagram of a first array substrate provided by the present disclosure;

[0055] FIG. 4 shows a structure schematic diagram of a second array substrate provided by the present disclosure;

[0056] FIG. 5 shows a structure schematic diagram of a third array substrate provided by the present disclosure;

[0057] FIG. 6 shows a structure schematic diagram of a first opposite substrate provided by the present disclosure;

[0058] FIG. 7 shows a structure schematic diagram of a second opposite substrate provided by the present disclosure;

[0059] FIG. 8 shows a cross-sectional structure schematic diagram of a display panel provided by the present disclosure;

[0060] FIG. 9 shows a structure schematic diagram of a fourth array substrate provided by the present disclosure;

[0061] FIG. 10 shows a structure schematic diagram of a fifth array substrate provided by the present disclosure;

[0062] FIG. 11 shows structure schematic diagrams of a sixth and a seventh array substrate provided by the present disclosure;

[0063] FIG. 12 shows a structure schematic diagram of an eighth array substrate provided by the present disclosure;

[0064] FIG. 13 schematically shows a plan structure of an array substrate;

[0065] FIG. 14 schematically shows a structure of a ninth array substrate provided by the present disclosure;

[0066] FIG. 15 schematically shows a process flow of preparing a filter layer.

[0067] DETAILED DESCRIPTION

[0068] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0069] An AR / VR / MR product needs to use a display panel with an ultra-high pixel density unit (Pixels Per Inch, PPI) to achieve a better display effect. However, the ultra-high PPI display panel encounters great challenges in design and process.

[0070] As the pixels of the ultra-high PPI display panel become smaller, the shielding structures such as the traces, transistors, and spacers in the pixels are difficult to be reduced in size in proportion to the pixels due to the limitations of equipment and material capabilities, resulting in a very small pixel aperture ratio of the ultra-high PPI display panel. For example, the pixel aperture ratio of a 500PPI display panel is 50% to 65%, and the transmittance is about 4%. The pixel size of a 1200PPI display panel is 3 to 20 microns, and the pixel aperture ratio can only be 20%, and the transmittance is only about 1.5%. As can be seen, the transmittance of the ultra-high PPI display panel is low.

[0071] In order to improve the pixel aperture ratio, the main solution adopted by the related art is to reduce the trace width and via size, etc. However, this brings a series of technical problems such as pattern distortion and diffraction light leakage.

[0072] Referring to FIG. 1, a diagram a shows a design pattern of a data line, and a diagram b shows an actual preparation pattern of the data line. By comparing the diagrams a and b in FIG. 1, it can be found that the actual prepared data line has a serious pattern distortion problem.

[0073] The diffraction light leakage phenomenon is shown with reference to c to f in FIG. 1. According to the principle of diffraction optics, when the size of the shielding structure (such as a wire, a via, and a spacer) is close to the wavelength of light, diffraction is obvious. Diffraction causes the light to be depolarized, producing light with a chaotic vibration direction. The depolarized light passing through the liquid crystal will form a very obvious light leakage defect, which in turn leads to a reduction in contrast.

[0074] In order to improve the contrast, the related art reduces diffraction light leakage by setting a shielding layer. However, the setting of the shielding layer further reduces the pixel aperture ratio and the transmittance.

[0075] In the present disclosure, a transistor refers to an element including at least three terminals of a gate, a drain, and a source. The transistor has a channel region between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0076] In the present disclosure, the transistor can be a thin film transistor or a field effect transistor, etc. The present disclosure is described by taking a thin film transistor as an example.

[0077] In the present disclosure, the first electrode can be a drain, and the second electrode can be a source, or the first electrode can be a source, and the second electrode can be a drain. In the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation, the functions of the "source" and the "drain" are sometimes exchanged with each other. Therefore, in the present disclosure, the "source" and the "drain" can be exchanged with each other.

[0078] In the related art, a pixel circuit of a liquid crystal display panel (LCD) includes one or two transistors, and is relatively simple, and therefore can achieve an ultra-high pixel density (PPI), that is, a number of pixels per inch. The liquid crystal display panel has various display modes, such as an ADS (Advanced Super Dimension Switch) mode, a TN (twisted nematic) mode, and a VA (Vertical Alignment) mode. In the ADS mode, a pixel electrode and a common electrode are both located on one side of a liquid crystal layer. In the TN mode and the VA mode, the pixel electrode and the common electrode are respectively arranged on opposite sides of the liquid crystal layer, the pixel electrode is located on one side of an array substrate, and the common electrode is located on one side of a counter substrate. The working principle of the ADS mode is that liquid crystal molecules are in a plane parallel to a substrate. When no voltage is applied, light passing through a lower polarizer forms linear polarization parallel to a short axis of the liquid crystal molecules. The polarization direction cannot be rotated, and therefore is absorbed by an upper polarizer and cannot be emitted. When a voltage is applied, a horizontal electric field is formed to the left and right of the liquid crystal, and the liquid crystal molecules are arranged along the direction of the electric field. Light passing through the lower polarizer and the liquid crystal layer is in an elliptical polarization state, and can be emitted through the upper polarizer. The working principle of the TN mode is that, in a no-voltage state, liquid crystal molecules are twisted by 90° under the action of an alignment film, and light passing through the lower polarizer and the liquid crystal molecules is emitted from the upper polarizer. When a voltage is applied, most of the liquid crystal molecules are arranged vertically, except for the liquid crystal near the upper and lower alignment films, and light passing through the lower polarizer is not deflected through the liquid crystal layer. Since the light is parallel to the polarization axis of the upper polarizer, the light is absorbed and cannot be emitted. The working principle of the VA mode is that liquid crystal molecules are arranged vertically to the substrate. When no voltage is applied, light passing through the lower polarizer forms linear polarization parallel to the short axis of the liquid crystal molecules. The polarization direction cannot be rotated, and therefore is absorbed by the upper polarizer and cannot be emitted. When a voltage is applied, the liquid crystal molecules are deflected along the direction of the electric field, and light passing through the lower polarizer and the liquid crystal layer is in an elliptical polarization state, and can be emitted through the upper polarizer.

[0079] The structure of the display panel is described below by taking the ADS mode as an example.

[0080] To solve the problem of diffraction light leakage, the display panel provided by the present disclosure includes a display area AA and a non-display area NA surrounding the display area AA, as shown in FIG. 2.

[0081] The display area AA includes a plurality of sub-pixels PX, the sub-pixel PX includes an opening area TA and a non-opening area NTA, the opening area TA is used for transmitting light, and the non-opening area NTA cannot transmit light. The non-light-transmitting shielding structures such as thin film transistors, vias, traces, and post spacers PS can be arranged in the non-opening area NTA. The ratio of the area of the opening area TA to the area of the sub-pixel PX is the aperture ratio, and the area of the sub-pixel PX is the sum of the area of the opening area TA and the area of the non-opening area NTA.

[0082] Exemplarily, the plurality of sub-pixels PX are arranged in an array along the row direction and the column direction. Adjacent two rows of sub-pixels PX can be arranged in alignment (as shown in a of FIG. 2) or can be arranged in misalignment (as shown in b of FIG. 2). The misaligned arrangement is conducive to realizing super-high PPI, but since the data line DL is a bent structure, it is more prone to cause pattern distortion and diffraction light leakage problems.

[0083] As shown in FIG. 3, the display panel includes: a first substrate 31; a plurality of conductive layers 32, which are sequentially stacked on one side of the first substrate 31 along the normal direction of the first substrate 31; and a light adjustment structure 33, which is arranged on the side of at least one conductive layer 32 away from the first substrate 31, and the light adjustment structure 33 is used for transmitting linearly polarized light with a polarization direction of a first direction f1.

[0084] By arranging the light adjustment structure 33 inside the display panel, among the light incident on the light adjustment structure 33, only the linearly polarized light with the polarization direction of the first direction f1 can be transmitted, and other polarized light cannot be transmitted. Therefore, the light adjustment structure 33 can shield the stray polarized light generated by diffraction, thereby reducing diffraction light leakage and improving contrast. Moreover, by arranging the light adjustment structure 33 to reduce or eliminate diffraction light leakage, the size of the shielding layer for shielding the diffraction light leakage can be reduced, which is conducive to improving the pixel aperture ratio and the transmittance of the display panel and realizing super-high PPI technology.

[0085] Exemplarily, as shown in FIG. 3, the conductive layer 32 can include at least one of: a semiconductor layer 35, a first conductive layer 321, a second conductive layer 322, a pixel electrode EP layer, and a common electrode EC layer. The semiconductor layer 35 includes an active layer ACT of a thin film transistor, the first conductive layer 321 includes a scan line GL, the second conductive layer 322 includes a data line DL, the pixel electrode EP layer includes a plurality of pixel electrodes EP located at different sub-pixels PX, and the common electrode EC layer includes a common electrode EC, and the common electrodes EC of the plurality of sub-pixels PX are in communication with each other.

[0086] Exemplarily, as shown in FIG. 3, the display panel can further include: a first polarizer POL1 arranged on the side of the first substrate 31 away from the plurality of conductive layers 32, and the first polarizer POL1 is used for transmitting linearly polarized light with a polarization direction of a first direction f1.

[0087] In a specific implementation, the light incident on the first polarizer POL1 is natural light with a random vibration direction, for example, and linearly polarized light with a polarization direction of the first direction f1 is transmitted through the first polarizer POL1. The linearly polarized light can be diffractively depolarized in the process of passing through the first substrate 31 and the conductive layer 32, and the depolarized light is filtered by the light adjustment structure 33 to become linearly polarized light with a polarization direction of the first direction f1 again.

[0088] For example, as shown in any one of FIGS. 3 to 7, the light adjustment structure 33 includes a plurality of slats SL arranged at equal intervals along the second direction f2, which is perpendicular to the first direction f1.

[0089] In this example, the light adjustment structure 33 is a wire grid structure. Of course, the light adjustment structure 33 can also be a coatable polarizer or the like, as long as it can transmit linearly polarized light with a polarization direction of the first direction f1 and block other polarized light.

[0090] In some embodiments, as shown in FIG. 3, the orthographic projection of the light adjustment structure 33 on the first substrate 31 covers the entire display area AA.

[0091] In this embodiment, as shown in FIG. 3, the orthographic projection of the light adjustment structure 33 on the first substrate 31 covers the opening area TA and the non-opening area NTA of the sub-pixel PX. By arranging the light adjustment structure 33 throughout the display area AA, this embodiment can comprehensively shield the diffractive light leakage at each position in the display area AA, and can further improve the contrast of the display panel.

[0092] In other embodiments, as shown in any one of FIGS. 4 to 7, the orthographic projection of the light adjustment structure 33 on the first substrate 31 partially covers the display area AA, and the orthographic projection of the opening area TA of the sub-pixel PX on the first substrate 31 is at least partially located outside the orthographic projection range of the light adjustment structure 33 on the first substrate 31.

[0093] In this embodiment, as shown in any one of FIGS. 4 to 7, the orthographic projection of the light adjustment structure 33 on the first substrate 31 covers at least part of the non-opening area NTA of the sub-pixel PX, and can also cover part of the opening area TA of the sub-pixel PX or not cover the opening area TA of the sub-pixel PX. In this way, the light adjustment structure 33 is arranged only in the area of the display area AA where diffractive light leakage is likely to occur, which not only can effectively shield the diffractive light leakage and improve the contrast, but also can improve the transmittance of the opening area TA.

[0094] For example, as shown in any one of FIGS. 4 to 7, the light adjustment structure 33 includes one light adjustment pattern PT (as shown in FIG. 4) that is interconnected or a plurality of light adjustment patterns PT (as shown in any one of FIGS. 5 to 7) that are separated from each other.

[0095] The inventors find that when the included angle between the orthographic profile line of the light-adjusting pattern PT on the first substrate 31 and the first direction f1 is not 0° or 90°, the diffraction light leakage phenomenon is more serious.

[0096] In order to further improve the diffraction light leakage phenomenon, for example, as shown in any one of FIGS. 4 to 7, the orthographic profile line of the light-adjusting pattern PT on the first substrate 31 is parallel or perpendicular to the first direction f1.

[0097] As shown in FIG. 4, the profile line L1 is parallel to the first direction f1, and the profile line L2 is perpendicular to the first direction f1.

[0098] For example, as shown in FIGS. 5 to 7, the orthographic shape of the light-adjusting pattern PT on the first substrate 31 is a rectangle, and the side of the rectangle is parallel or perpendicular to the first direction f1.

[0099] For example, the light-adjusting structure 33 can be made of a metal material such as aluminum, molybdenum, etc., and can also be made of a transparent conductive material such as ITO, IZO, IGZO, IGO, ZTO, etc. The transmittance of the transparent conductive material to visible light is higher than that of the metal material.

[0100] For example, as shown in FIG. 8, the display panel includes an array substrate 81, a counter substrate 82, and a liquid crystal layer 83 between the array substrate 81 and the counter substrate 82, the first substrate 31 and the plurality of conductive layers 32 are located on the array substrate 81, and the counter substrate 82 includes a second substrate 61.

[0101] The display panel provided by the present example is a liquid crystal display panel, which is beneficial to realize ultra-high PPI (such as 2000+PPI) and high resolution (such as 4K), improve the AR / VR display immersion, reduce the influence of screen door effect, and realize a field of view angle of 100° and a pixel per degree (PPD) of more than 40.

[0102] For example, the display panel can include one light-adjusting structure 33. The light-adjusting structure 33 can be located in the array substrate 81 (as shown in FIGS. 3 to 5) or in the counter substrate 82 (as shown in FIGS. 6 and 7).

[0103] For example, as shown in any one of FIGS. 3 to 5, the light-adjusting structure 33 includes a first light-adjusting structure 331 disposed on the array substrate 81. The first light-adjusting structure 331 is located between the one or more conductive layers 32 and the liquid crystal layer 83.

[0104] By disposing the first light-adjusting structure 331 in the array substrate 81, it is beneficial to prevent color crosstalk interference between different color sub-pixels PX and further improve the display effect.

[0105] Exemplarily, as shown in FIG. 6 or FIG. 7, the light-adjusting structure 33 comprises: a second light-adjusting structure 332, disposed on the opposite substrate 82, between the second substrate 61 and the liquid crystal layer 83.

[0106] By disposing the second light-adjusting structure 332 in the opposite substrate 82, the diffraction leakage light generated between the first light-adjusting structure 331 and the first substrate 31 can be completely shielded, which is conducive to improving the contrast.

[0107] Exemplarily, the display panel can further comprise a plurality of light-adjusting structures 33. As shown in FIG. 8, the light-adjusting structure 33 comprises: a first light-adjusting structure 331, disposed on the array substrate 81, between the plurality of conductive layers 32 and the liquid crystal layer 83; and a second light-adjusting structure 332, disposed on the opposite substrate 82, between the second substrate 61 and the liquid crystal layer 83.

[0108] In order to further shield the diffraction leakage light, exemplarily, as shown in FIG. 3 to FIG. 5, the first light-adjusting structure 331 can be disposed close to the liquid crystal layer 83 in the array substrate 81, that is, all the conductive layers 32 in the array substrate 81 are located between the first light-adjusting structure 331 and the first substrate 31, so that the first light-adjusting structure 331 can shield the diffraction leakage light generated by all the film layers between the first substrate 31 and the first light-adjusting structure 331.

[0109] Exemplarily, as shown in FIG. 3, the array substrate 81 can further comprise a first polarized insulating layer 34, disposed on the side of the first light-adjusting structure 331 away from the first substrate 31, for protecting the first light-adjusting structure 331, which can improve the reliability of the display panel.

[0110] As shown in FIG. 4, the conductive layer 32 comprises a scan line GL and a data line DL disposed in different layers, and the first light-adjusting structure 331 is located on the side of the scan line GL and the data line DL away from the first substrate 31.

[0111] Exemplarily, as shown in FIG. 4, the orthographic projection of the first light-adjusting structure 331 on the first substrate 31 covers the orthographic projection of the scan line GL and the data line DL on the first substrate 31. In this way, the first light-adjusting structure 331 can shield the diffraction leakage light generated by the scan line GL and the data line DL.

[0112] Exemplarily, the thickness of the scan line GL and the data line DL is greater than or equal to 300 angstroms.

[0113] Exemplarily, in the orthographic projection on the first substrate 31, the edge of the first light-adjusting structure 331 is extended outward relative to the edge of the scan line GL and the data line DL by a first distance, for example, greater than or equal to 0 microns and less than or equal to 1 micron or 1.5 microns.

[0114] Exemplarily, in the width direction of the data line DL (perpendicular to the extension direction of the data line DL), the line width of the data line DL is 2.5 microns, the pattern width of the first light-adjusting structure 331 overlapping with the data line DL can be greater than or equal to 2.5 microns and less than or equal to 5.5 microns, for example, 3.5 microns.

[0115] Exemplarily, in the orthographic projection on the first substrate 31, the edge of the first light-adjusting structure 331 is outwardly extended from the edge of the scan line GL and the data line DL by 0 microns, that is, the edge of the first light-adjusting structure 331 is flush with the edge of the scan line GL and the data line DL. In this way, the pixel aperture ratio and the transmittance can be further improved.

[0116] As shown in FIG. 5, the conductive layer 32 includes a first conductive pattern 51 and a second conductive pattern 52 arranged in different layers, the first conductive pattern 51 and the second conductive pattern 52 are connected through a first via hole H1, and the first light-adjusting structure 331 is arranged on the side of the first conductive pattern 51 and the second conductive pattern 52 away from the first substrate 31.

[0117] Exemplarily, as shown in FIG. 5, the orthographic projection of the first light-adjusting structure 331 on the first substrate 31 covers the orthographic projection of the first via hole H1 on the first substrate 31. In this way, the first light-adjusting structure 331 can shield the diffraction light leakage generated by the first via hole H1.

[0118] Exemplarily, in the orthographic projection on the first substrate 31, the edge of the first light-adjusting structure 331 is outwardly extended from the edge of the first via hole H1 by a first distance, for example, greater than or equal to 0 microns and less than or equal to 1 micron or 1.5 microns.

[0119] Exemplarily, in the orthographic projection on the first substrate 31, the edge of the first light-adjusting structure 331 is outwardly extended from the edge of the first via hole H1 by 0 microns, that is, the edge of the first light-adjusting structure 331 is flush with the edge of the first via hole H1. In this way, the pixel aperture ratio and the transmittance can be further improved.

[0120] As shown in FIG. 5, the plurality of conductive layers 32 further include a third conductive pattern 53, in the normal direction of the first substrate 31, the second conductive pattern 52 is located between the first conductive pattern 51 and the third conductive pattern 53, the second conductive pattern 52 and the third conductive pattern 53 are connected through a second via hole H2, and the first light-adjusting structure 331 is arranged on the side of the third conductive pattern 53 away from the first substrate 31.

[0121] Exemplarily, as shown in FIG. 5, the orthographic projection of the first light-adjusting structure 331 on the first substrate 31 also covers the orthographic projection of the second via hole H2 on the first substrate 31. In this way, the first light-adjusting structure 331 can shield the diffraction light leakage generated by the second via hole H2.

[0122] Exemplarily, in the orthographic projection on the first substrate 31, the edge of the first light-adjusting structure 331 is outwardly extended from the edge of the second via hole H2 by a first distance, for example, greater than or equal to 0 microns and less than or equal to 1 micron or 1.5 microns.

[0123] Exemplarily, in the orthographic projection on the first substrate 31, the edge of the first light-adjusting structure 331 is outwardly extended from the edge of the second via hole H2 by 0 microns, i.e., the edge of the first light-adjusting structure 331 is flush with the edge of the second via hole H2. In this way, the pixel aperture ratio and the transmittance can be further improved.

[0124] Exemplarily, the first conductive pattern 51 can include at least one of a metal, a metal oxide, a semiconductor and the like, and can be arranged in the same layer as the active layer ACT of the thin film transistor, the scan line GL, the data line DL, the pixel electrode EP or the common electrode EC.

[0125] Exemplarily, the second conductive pattern 52 can include at least one of a metal, a metal oxide, a semiconductor and the like, and can be arranged in the same layer as the active layer ACT of the thin film transistor, the scan line GL, the data line DL, the pixel electrode EP or the common electrode EC.

[0126] Exemplarily, the third conductive pattern 53 can include at least one of a metal, a metal oxide, a semiconductor and the like, and can be arranged in the same layer as the active layer ACT of the thin film transistor, the scan line GL, the data line DL, the pixel electrode EP or the common electrode EC.

[0127] Exemplarily, as shown in FIG. 5, the first conductive pattern 51 is the active layer ACT of the thin film transistor, and correspondingly, the second conductive pattern 52 is the transfer electrode EZ, and the third conductive pattern 53 is the pixel electrode EP.

[0128] Exemplarily, the transfer electrode EZ can be a transparent conductive material, and in a direction perpendicular to the first substrate 31, the transfer electrode EZ can be located between the data line DL and the pixel electrode EP. Of course, the transfer electrode EZ can also be arranged in the same layer as the data line DL.

[0129] As shown in FIG. 6, the counter substrate 82 further includes a spacer PS arranged on the side of the second light-adjusting structure 332 away from the second substrate 61. The spacer PS is conducive to maintaining the liquid crystal thickness between the array substrate 81 and the counter substrate 82, and improving the display uniformity.

[0130] Exemplarily, as shown in FIG. 6, the second light-adjusting structure 332 covers the orthogonal projection of the post spacer PS on the second substrate 61. In this way, the second light-adjusting structure 332 can shield the diffraction light leakage caused by the post spacer PS.

[0131] Exemplarily, in the orthogonal projection on the second substrate 61, the edge of the second light-adjusting structure 332 is outwardly extended from the edge of the post spacer PS by a first distance, which is greater than or equal to 0 microns and less than or equal to 1 micron or 1.5 microns, for example.

[0132] Exemplarily, in the orthogonal projection on the second substrate 61, the edge of the second light-adjusting structure 332 is outwardly extended from the edge of the post spacer PS by 0 microns, i.e., the edge of the second light-adjusting structure 332 is flush with the edge of the post spacer PS. In this way, the pixel aperture ratio and the transmittance can be further improved.

[0133] Exemplarily, the orthogonal projection of the post spacer PS on the first substrate 31 can be a circle (as shown in FIG. 6a), a rectangle (as shown in FIG. 6b), a mesh shape in which the shapes are interconnected, and the like, which are not limited in the present disclosure.

[0134] Exemplarily, the post spacer PS can be made of an organic material or a metal material, and the like.

[0135] As shown in FIG. 7, the counter substrate 82 further comprises a light-blocking matrix BM, which is arranged on the side of the second light-adjusting structure 332 away from the second substrate 61. The orthogonal projection of the light-blocking matrix BM on the second substrate 61 is arranged around the opening area TA, and the profile line of the orthogonal projection of the light-blocking matrix BM on the second substrate 61 comprises an arc line hx. The arc line hx is located on the side of the light-blocking matrix BM close to the opening area TA.

[0136] Exemplarily, as shown in FIG. 7, the orthogonal projection of the second light-adjusting structure 332 on the second substrate 61 covers the arc line hx. In this way, the second light-adjusting structure 332 can shield the diffraction light leakage caused by the arc line hx of the light-blocking matrix BM.

[0137] Exemplarily, in the orthogonal projection on the second substrate 61, the edge of the second light-adjusting structure 332 is outwardly extended from the arc line hx by a first distance, which is greater than or equal to 0 microns and less than or equal to 1 micron or 1.5 microns, for example.

[0138] Exemplarily, as shown in FIG. 6 or FIG. 7, the opposite substrate 82 can further include a color filter layer CF and a protective layer OC which are sequentially stacked between the light shielding matrix BM and the spacers, and the color filter layer CF is arranged close to the light shielding matrix BM. The color filter layer CF includes, for example, a red color filter R for transmitting red light, a green color filter G for transmitting green light, and a blue color filter B for transmitting blue light.

[0139] Exemplarily, as shown in FIG. 6, the opposite substrate 82 can further include a second polarized insulating layer 62 arranged between the second light modulation structure 332 and the spacers PS, for protecting the second light modulation structure 332.

[0140] Exemplarily, as shown in FIG. 8, the display panel can further include a second polarizer POL2 arranged on a side of the second substrate 61 away from the first substrate 31, and the second polarizer POL2 is configured to transmit linearly polarized light with a polarization direction being the second direction f2.

[0141] Exemplarily, the array substrate 81 shown in FIG. 4 can be prepared by the following process flow: sequentially forming a buffer layer buffer, a semiconductor layer 35, a first insulating layer 36, a first conductive layer 321, a second insulating layer 37, a second conductive layer 322, a third insulating layer 38, a pixel electrode EP layer, a fourth insulating layer 39, a common electrode EC layer, a fifth insulating layer 310, and a first light modulation structure 331 on the first substrate 31.

[0142] Exemplarily, the opposite substrate 82 shown in FIG. 7 can be prepared by the following process flow: sequentially forming a second light modulation structure 332, a light shielding matrix BM, a color filter layer CF, a protective layer OC, and spacers PS on the second substrate 61.

[0143] Exemplarily, the light modulation structure 33 can be prepared by the following processes: metal layer film forming, photoresist coating, exposure, photoresist stripping, etching, etc. The light modulation structure 33 can also be prepared by a nanoimprint patterning process, which is not limited in the present disclosure.

[0144] Exemplarily, as shown in FIG. 3, a transparent auxiliary electrode FZ can be further formed between the first insulating layer 36 and the first conductive layer 321. In the orthographic projection on the first substrate 31, the orthographic projection shape of the transparent auxiliary electrode FZ is substantially the same as that of the scan line GL, the transparent auxiliary electrode FZ covers the scan line GL, and the contour line of the transparent auxiliary electrode FZ is outwardly expanded relative to the contour line of the scan line GL. By arranging the transparent auxiliary electrode FZ, the channel size can be increased without increasing the aperture ratio, which is conducive to improving the pixel aperture ratio.

[0145] The transparent auxiliary electrode FZ can be made of a transparent conductive material.

[0146] To further improve the transmittance of the display panel, as shown in FIG. 9, the display area AA includes a plurality of sub-pixels PX, the plurality of sub-pixels PX includes a first sub-pixel PX1 and a second sub-pixel PX2, the first sub-pixel PX1 is configured to transmit first color light, and the second sub-pixel PX2 is configured to transmit second color light.

[0147] The first sub-pixel PX1 can include one or more of a red sub-pixel PXR, a green sub-pixel PXG, and a blue sub-pixel PXB, and the second sub-pixel PX2 can include one or more of a red sub-pixel PXR, a green sub-pixel PXG, and a blue sub-pixel PXB.

[0148] For example, as shown in FIG. 9, the first sub-pixel PX1 includes a red sub-pixel PXR and a green sub-pixel PXG, the first color light includes red light and green light, the second sub-pixel PX2 includes a blue sub-pixel PXB, and the second color light includes blue light.

[0149] For example, as shown in FIG. 9, the display panel further includes a filter layer 91 disposed between the first substrate 31 and the conductive layer 32, the filter layer 91 includes a plurality of filter patterns 91P, the filter patterns 91P are configured to transmit a portion of the incident light and reflect a portion of the incident light.

[0150] For example, as shown in FIG. 9, the plurality of filter patterns 91P includes a first filter pattern 91P1, in the orthographic projection on the first substrate 31, the first filter pattern 91P1 overlaps with the opening area TA of the first sub-pixel PX1 and does not overlap with the opening area TA of the second sub-pixel PX2, the first filter pattern 91P1 is configured to transmit the first color light and reflect the second color light.

[0151] In the case where the first sub-pixel PX1 includes a red sub-pixel PXR and a green sub-pixel PXG, the first color light includes red light and green light, the second sub-pixel PX2 includes a blue sub-pixel PXB, and the second color light includes blue light, as shown in FIG. 9, the first filter pattern 91P1 is disposed at the red sub-pixel PXR and the green sub-pixel PXG, transmits the red light and the green light, and reflects the blue light.

[0152] Since the first filter pattern 91P1 located at the first sub-pixel PX1 can reflect the second color light, the thickness of the color filter layer CF disposed at the first sub-pixel PX1 can be thinned, thereby improving the transmittance of the first sub-pixel PX1.

[0153] Exemplarily, the thickness of the first filter pattern 91P1 is 0.58 microns, and the thickness of the color filter layer CF arranged on the first sub-pixel PX1 can be reduced by 1 micron, and the transmittance is increased by 16% while maintaining the same color gamut.

[0154] Exemplarily, as shown in FIG. 10, the plurality of filter patterns 91P further include a second filter pattern 91P2, in the orthographic projection on the first substrate 31, the second filter pattern 91P2 overlaps with the opening area TA of the second sub-pixel PX2, and does not overlap with the opening area TA of the first sub-pixel PX1, the second filter pattern 91P2 is used for transmitting the second color light and reflecting the first color light.

[0155] In the case that the first sub-pixel PX1 includes a red sub-pixel PXR and a green sub-pixel PXG, the first color light includes red light and green light, the second sub-pixel PX2 includes a blue sub-pixel PXB, and the second color light includes blue light, as shown in FIG. 10, the second filter pattern 91P2 is arranged on the blue sub-pixel PXB, transmits the blue light, and reflects the red light and the green light.

[0156] Since the second filter pattern 91P2 located in the second sub-pixel PX2 can reflect the first color light, the thickness of the color filter layer CF arranged on the second sub-pixel PX2 can be reduced, thereby improving the transmittance of the second sub-pixel PX2.

[0157] Exemplarily, as shown in FIG. 9, the filter pattern 91P includes high-refraction layers and low-refraction layers which are stacked and arranged alternately, the refractive index of the high-refraction layer is greater than the refractive index of the low-refraction layer.

[0158] Exemplarily, the high-refraction layer includes one or more of TiO2, Nb2O5, Y2O3, TaO2, SiN, etc., and the low-refraction layer includes one or more of SiO2, MgF2, LiF, etc. The greater the difference between the refractive index of the high-refraction layer and the low-refraction layer, the thinner the thickness of the filter pattern 91P.

[0159] Exemplarily, the high-refraction layer uses TiO2, the low-refraction layer uses SiO2, TiO2 and SiO2 are alternately stacked to obtain the first filter pattern 91P1, the transmittance of the first filter pattern 91P1 to red and green light is more than 90%, and the reflectivity of the first filter pattern 91P1 to blue light is more than 90%.

[0160] Exemplarily, as shown in FIG. 11a, the display panel can further include a first planar layer PLN1 arranged on the side of the first substrate 31 and the filter layer 91 close to the conductive layer 32, the orthographic projection of the first planar layer PLN1 on the first substrate 31 covers the first substrate 31 entirely, and the surface of the first planar layer PLN1 away from the first substrate 31 is planar.

[0161] As shown in a of FIG. 11, the first planar layer PLN1 is not only disposed in the gaps between the first filter patterns 91P1, but also disposed on the side of the first filter patterns 91P1 away from the first substrate 31, i.e., the first planar layer PLN1 is disposed on both the first sub-pixel PX1 and the second sub-pixel PX2, and the surface of the first planar layer PLN1 away from the first substrate 31 is higher than the surface of the filter layer 91 away from the first substrate 31.

[0162] By disposing the first planar layer PLN1, the subsequent film layer can be formed on the planarized surface of the first planar layer PLN1, so as to eliminate the step difference and avoid the risk of wire disconnection.

[0163] Exemplarily, as shown in b of FIG. 11, the display panel can further include a second planar layer PLN2 filled in the gaps between the plurality of filter patterns 91P, and the surface of the second planar layer PLN2 away from the first substrate 31 is substantially flush with the surface of the filter pattern 91P away from the first substrate 31.

[0164] By disposing the second planar layer PLN2, the surface of the second planar layer PLN2 away from the first substrate 31 is located in the same plane as the surface of the filter pattern 91P away from the first substrate 31, and the subsequent film layer can be formed on the planarized surface, so as to avoid the risk of wire disconnection.

[0165] In addition, by disposing the second planar layer PLN2 such that the surface of the second planar layer PLN2 away from the first substrate 31 is substantially flush with the surface of the filter pattern 91P away from the first substrate 31, the distance between the filter layer 91 and the color filter layer CF can be reduced, which is beneficial to reduce the risk of color mixing.

[0166] In the case where the filter layer 91 only includes the first filter patterns 91P1 located in the first sub-pixel PX1, as shown in b of FIG. 11, the orthographic projection of the second planar layer PLN2 on the first substrate 31 overlaps with the second sub-pixel PX2 and does not overlap with the first sub-pixel PX1, i.e., the second planar layer PLN2 is disposed in the gaps between the first filter patterns 91P1.

[0167] In order to improve the reliability of the display panel, the temperature resistance of the first planar layer PLN1 or the second planar layer PLN2 is greater than or equal to 350 ℃.

[0168] In order to improve the transmittance of the display panel, the refractive index of the first planar layer PLN1 or the second planar layer PLN2 is, for example, equivalent to the refractive index of the first substrate 31. For example, the first substrate 31 is a glass substrate, and the refractive index of the first planar layer PLN1 or the second planar layer PLN2 is, for example, greater than or equal to 1.4 and less than or equal to 1.5.

[0169] Exemplarily, the first planar layer PLN1 or the second planar layer PLN2 has a transmittance greater than or equal to 99%.

[0170] Exemplarily, the first planar layer PLN1 or the second planar layer PLN2 is made of a high-temperature planar adhesive with high transmittance.

[0171] Exemplarily, as shown in FIG. 9, the conductive layer 32 includes a semiconductor layer 35 disposed on the side of the filter layer 91 facing away from the first substrate 31, and the semiconductor layer 35 includes a transistor active layer ACT located in different sub-pixels PX.

[0172] Exemplarily, the transistor active layer ACT includes an oxide semiconductor material, which is conducive to improving the pixel aperture ratio.

[0173] Exemplarily, the transistor active layer ACT includes a semiconductor material M1OaNb, where M1 is a single metal or a combination of multiple metals, a > 0, and b ≥ 0, O represents an oxygen element, and N represents a nitrogen element, that is, the semiconductor material is a metal oxide material or a metal nitride oxide material.

[0174] Suitable metal oxide materials include, but are not limited to, one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), In-free OS, rare earth doped oxide (Ln-OS, such as rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of the transistor active layer ACT can be in an amorphous, partially crystalline, single crystalline, or polycrystalline state, and can be a single layer or a multi-layer structure.

[0175] Suitable metal nitride oxide materials include, but are not limited to, zinc nitride oxide, indium nitride oxide, gallium nitride oxide, tin nitride oxide, cadmium nitride oxide, aluminum nitride oxide, germanium nitride oxide, titanium nitride oxide, silicon nitride oxide, or a combination thereof. In one example, the material of the transistor active layer ACT includes indium gallium zinc oxide (IGZO).

[0176] Exemplarily, as shown in FIG. 9, in the orthographic projection on the first substrate 31, the filter pattern 91P completely covers the transistor active layer ACT located in the same sub-pixel PX. In this way, the filter pattern 91P can block part of the light for the active layer ACT, improve the stability of the transistor, and improve the problem of threshold voltage drift caused by light.

[0177] Exemplarily, as shown in FIG. 9, in the orthographic projection on the first substrate 31, the first filter pattern 91P1 completely covers the transistor active layer ACT located in the first sub-pixel PX1, so that the refraction of the blue light to the transistor active layer ACT located in the first sub-pixel PX1 can be avoided.

[0178] Exemplarily, as shown in FIG. 9 or FIG. 12, the plurality of conductive layers 32 include the scan lines GL and the data lines DL which are arranged in different layers, the scan lines GL are located on the side of the filter layer 91 away from the first substrate 31, and the data lines DL are located on the side of the filter layer 91 away from the first substrate 31 (as shown in FIG. 9) or on the side of the filter layer 91 close to the first substrate 31 (as shown in FIG. 12).

[0179] By arranging the data lines DL on the side of the filter layer 91 close to the first substrate 31, the diffraction light leakage can be reduced.

[0180] In the case that the data lines DL are arranged on the side of the filter layer 91 close to the first substrate 31, the data lines DL can be arranged in the same layer as the alignment marks and made of the same material.

[0181] Exemplarily, as shown in FIG. 9, the data lines DL can be located on the side of the semiconductor layer 35 away from the first substrate 31, in this case, the active layer ACT is connected to the data lines DL in an upper overlap manner; as shown in FIG. 12, the data lines DL can also be located on the side of the semiconductor layer 35 close to the first substrate 31, in this case, the active layer ACT is connected to the data lines DL in a lower overlap manner.

[0182] Exemplarily, the data lines DL can also be arranged on the surface of the first planar layer PLN1 away from the first substrate 31, and the data lines DL can also be arranged on the surface of the second planar layer PLN2 and the filter layer 91 away from the first substrate 31.

[0183] Exemplarily, as shown in FIG. 13, the rectangular frame k is the boundary of the orthographic projection of the filter layer 91 on the first substrate 31, and the orthographic projection of the filter pattern 91P on the first substrate 31 completely covers the orthographic projection of the scan lines GL on the first substrate 31.

[0184] Since the line width of the data lines DL is small (such as 1.3 microns), in the case that the surface of the filter layer 91 away from the first substrate 31 has a large step, in order to avoid the line break defect of the data lines DL, exemplarily, as shown in a and b in FIG. 13, in the orthographic projection on the first substrate 31, the boundary of the filter layer 91 along the column direction does not overlap with the data lines DL, and the spacing between the boundary of the filter layer 91 along the column direction and the data lines DL is greater than or equal to 0.7 microns.

[0185] Exemplarily, in the orthographic projection on the first substrate 31, the boundary of the first filter pattern 91P1 in the column direction can be located on the side of the data line DL close to the second sub-pixel PX2 (as shown in a of FIG. 13) or the side away from the second sub-pixel PX2 (as shown in a of FIG. 13).

[0186] In the case where the surface of the filter layer 91 is planarized away from the first substrate 31, in the orthographic projection on the first substrate 31, the boundary of the filter layer 91 in the column direction can overlap with the data line DL (as shown in c of FIG. 13) or have no overlap, in c of FIG. 13, the boundary of the filter layer 91 in the column direction is flush with the center line of the data line DL in the column direction.

[0187] Exemplarily, the transistor can adopt a top gate structure, i.e., the scan line GL is located on the side of the active layer ACT away from the first substrate 31. Of course, the transistor can also adopt a bottom gate structure, i.e., the scan line GL is located on the side of the active layer ACT close to the first substrate 31, which is not limited in the present disclosure.

[0188] Exemplarily, the color filter layer CF can be located on the opposite substrate 82.

[0189] Exemplarily, the color filter layer CF can be located on the array substrate 81, as shown in FIG. 14, the color filter layer CF can be located between the transistor and the pixel electrode EP and the common electrode EC, which can improve the problem of cross-color between pixels caused by the deviation of the array substrate 81 and the opposite substrate 82.

[0190] As shown in FIG. 14, the pixel electrode EP and the transistor are connected through the via hole provided on the color filter layer CF, and due to the provision of the filter layer 91, the thickness of the color filter layer CF can be thinned, the thinner thickness of the color filter layer CF can reduce the via hole depth and aperture, and thus the risk of climbing disconnection and the light leakage problem caused by the oversized via hole can be reduced.

[0191] Exemplarily, the thickness of the color filter layer CF is greater than or equal to 1.5 microns and less than or equal to 2 microns, for example.

[0192] Referring to FIG. 15, the filter layer 91 shown in FIG. 10 can be prepared according to the following steps:

[0193] Step 1: Forming a filter film 151 on the first substrate 31, as shown in a of FIG. 15.

[0194] Step 2: Etching the filter film 151 located at the second sub-pixel PX2 to obtain the first filter pattern 91P1 located at the first sub-pixel PX1, as shown in b of FIG. 15. The first filter pattern 91P1 can also be located in the non-display area NA.

[0195] Step 3: Form the filter film 152 on the surface of the first filter pattern 91P1 away from the first substrate 31, as shown in FIG. 15C.

[0196] Step 4: Etch the filter film 152 located in the first sub-pixel PX1, and the etching obtains the array substrate as shown in FIG. 15D. Then, the second filter pattern 91P2 located in the second sub-pixel PX2 is obtained by using the ashing process, as shown in FIG. 15E. In this way, the first filter pattern 91P1 and the second filter pattern 91P2 can be tightly prepared.

[0197] The display device provided by the present disclosure comprises: the display panel provided by any one of the embodiments; and a driving assembly connected with the display panel, used for driving the display panel to emit light.

[0198] It can be understood by those skilled in the art that the display device provided by the present disclosure has the advantages of the display panel of any one of the above-mentioned embodiments.

[0199] The display device provided by the present disclosure can be: a display module, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a vehicle-mounted display device, a smart watch, a fitness wristband, a personal digital assistant, or any product or component with a display function.

[0200] In the present disclosure, the meaning of "a plurality of" is two or more, and the meaning of "at least one" is one or more, unless otherwise explicitly and specifically limited.

[0201] In the present disclosure, the terms "upper", "lower", and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0202] In the present disclosure, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, product or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, product or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, product or device including the element.

[0203] As used in the present disclosure, the terms "one embodiment", "some embodiments", "exemplary embodiment", "one or more embodiments", "example", "an example", "some examples" and the like are intended to mean that a particular feature, structure, material, or characteristic is included in at least one embodiment or example of the present disclosure, but that it is not necessarily included in all embodiments or examples. Therefore, the above terms are not necessarily indicative of any particular

[0204] In the present disclosure, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0205] In the present specification, "electrically connected" and "coupled" include cases where constituent elements are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0206] In the present specification, "disposed in the same layer" means structures patterned by the same patterning process, and the materials thereof can be the same or different. For example, the materials of the precursors forming the plurality of structures disposed in the same layer are the same, and the finally formed materials can be the same or different.

[0207] In the present specification, a polygon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and the like, and can be an approximate triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and the like, and can have some small deformation due to a tolerance, and can have a chamfer, a round corner, an arc edge, and a deformation, and the like.

[0208] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0209] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0210] The use of "for" or "configured to" in the present disclosure means open and inclusive language that does not exclude devices that are adapted to perform additional tasks or steps.

[0211] As used in the present disclosure, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0212] As used in the present disclosure, "parallel," "perpendicular," "equal," "flush," includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable range of deviation for near parallel can be, for example, within 10° or 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable range of deviation for near perpendicular can also be, for example, within 10° or 5°. "Equal" includes absolute equality and near equality, where the acceptable range of deviation for near equality can be, for example, a difference between the two that is less than or equal to 5% of either. "Flush" includes absolute flush and near flush, where the acceptable range of deviation for near flush can be, for example, a distance between the two that is less than or equal to 5% of either dimension.

[0213] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate or intervening layers can also be present.

[0214] The present disclosure describes example embodiments with reference to cross-sectional and / or plan view illustrations that are idealized example diagrams. In the interest of clarity, not all of the layer and regions are shown in each diagram can be shown in the drawings for purposes of example. It should be appreciated that in the various diagrams, layers and regions that are depicted in the drawings as single layers can in fact be composed of multiple sub-layers. Similarly, regions that are depicted in the drawings as single regions can in fact be composed of multiple sub-regions. The depiction of layers and regions as single layers and regions is merely intended to simplify the drawings and the description, and is not intended to limit the scope of the example embodiments in any way. Furthermore, layers and regions that are depicted in the drawings as being adjacent can in fact be separated from each other by intermediate layers or regions. The specific materials used to form the layers and regions are not critical unless specifically indicated, and embodiments of the example embodiments can include any suitable material.

[0215] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present disclosure, but not to limit them; although the present disclosure has been described in detail with reference to the foregoing examples, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display panel comprising a display area and a non-display area surrounding the display area, the display panel comprising: a first substrate; a plurality of conductive layers sequentially stacked on one side of the first substrate along a normal direction of the first substrate; and a light adjusting structure disposed on a side of at least one of the conductive layers away from the first substrate, the light adjusting structure being configured to transmit linearly polarized light having a first polarization direction. The display area comprises a plurality of sub-pixels, each of the sub-pixels comprising an opening area configured to transmit light; A projection of the light adjusting structure on the first substrate covers the display area, and a projection of the opening area of the sub-pixel on the first substrate at least partially falls outside a projection range of the light adjusting structure on the first substrate. The light adjusting structure comprises at least one light adjusting pattern, a projection contour line of the light adjusting pattern on the first substrate being parallel or perpendicular to the first direction. The light adjusting structure entirely covers the display area in a projection on the first substrate.

2. The display panel of claim 1, wherein, The display panel comprises an array substrate, a counter substrate, and a liquid crystal layer between the array substrate and the counter substrate, the first substrate and the plurality of conductive layers being located on the array substrate, and the counter substrate comprising a second substrate; The light adjusting structure comprises at least one of:

3. The display panel of claim 2, wherein, a first light adjusting structure disposed on the array substrate between one or more of the conductive layers and the liquid crystal layer; and 4. The display panel of claim 1, wherein, a second light adjusting structure disposed on the counter substrate between the second substrate and the liquid crystal layer.

5. The display panel of claim 1, wherein, The conductive layers comprise scan lines and data lines disposed in different layers, and the first light adjusting structure is located on a side of the scan lines and the data lines away from the first substrate; A projection of the first light adjusting structure on the first substrate covers projections of the scan lines and the data lines on the first substrate. The conductive layers comprise first conductive patterns and second conductive patterns disposed in different layers, the first conductive patterns and the second conductive patterns being connected by first vias; The first light adjusting structure is disposed on a side of the first conductive patterns and the second conductive patterns away from the first substrate, and a projection of the first light adjusting structure on the first substrate covers a projection of the first vias on the first substrate. The plurality of conductive layers further comprise third conductive patterns, the second conductive patterns being located between the first conductive patterns and the third conductive patterns along the normal direction of the first substrate, and the second conductive patterns and the third conductive patterns being connected by second vias; 6. The display panel of claim 5, wherein, The first light adjusting structure is disposed on a side of the third conductive patterns away from the first substrate, and a projection of the first light adjusting structure on the first substrate further covers a projection of the second vias on the first substrate. The counter substrate further comprises:

7. The display panel of claim 5, wherein, ​ ​ 8. The display panel of claim 7, wherein, ​ ​ 9. The display panel of claim 5, wherein, ​ A spacer column is disposed on a side of the second light-adjusting structure facing away from the second substrate, and a projection of the second light-adjusting structure on the second substrate covers a projection of the spacer column on the second substrate.

10. The display panel of claim 5, wherein, The display area includes a plurality of sub-pixels, and the sub-pixels include an opening area for transmitting light; The opposite substrate further includes: a light-blocking matrix disposed on a side of the second light-adjusting structure facing away from the second substrate, a projection of the light-blocking matrix on the second substrate is disposed around the opening area, and a contour line of the projection of the light-blocking matrix on the second substrate includes an arc line; and A projection of the second light-adjusting structure on the second substrate covers the arc line.

11. The display panel of claim 1, wherein, The display panel further includes: A first polarizer is disposed on a side of the first substrate facing away from the plurality of conductive layers, and the first polarizer is used to transmit linearly polarized light with a polarization direction being the first direction.

12. The display panel of claim 1, wherein, The light-adjusting structure includes a plurality of grid bars arranged at equal intervals along a second direction, and the second direction is perpendicular to the first direction.

13. The display panel according to any one of claims 1 to 12, wherein, The display area includes a plurality of sub-pixels, and the plurality of sub-pixels include first sub-pixels and second sub-pixels, the first sub-pixels are used to transmit first color light, and the second sub-pixels are used to transmit second color light; The display panel further includes: A filter layer is disposed between the first substrate and the conductive layer, and the filter layer includes a plurality of filter patterns, the plurality of filter patterns include a first filter pattern, in a projection on the first substrate, the first filter pattern overlaps the opening area of the first sub-pixel and does not overlap the opening area of the second sub-pixel, the first filter pattern is used to transmit the first color light and reflect the second color light.

14. The display panel of claim 13, wherein, The plurality of filter patterns further include: A second filter pattern, in a projection on the first substrate, the second filter pattern overlaps the opening area of the second sub-pixel and does not overlap the opening area of the first sub-pixel, the second filter pattern is used to transmit the second color light and reflect the first color light.

15. The display panel of claim 13, wherein, The display panel further includes: A first planar layer is disposed on a side of the first substrate and the filter layer close to the conductive layer, a projection of the first planar layer on the first substrate covers the first substrate in its entirety, and a surface of the first planar layer facing away from the first substrate is a plane; or A second planar layer is filled in a gap between the plurality of filter patterns, and a surface of the second planar layer facing away from the first substrate is substantially flush with a surface of the filter pattern facing away from the first substrate.

16. The display panel of claim 13, wherein, The conductive layer includes: A semiconductor layer is disposed on a side of the filter layer facing away from the first substrate, and the semiconductor layer includes a transistor active layer in different sub-pixels; and In a projection on the first substrate, the filter pattern completely covers the transistor active layer in the same sub-pixel.

17. The display panel of claim 13, wherein, The first sub-pixel includes a red sub-pixel and a green sub-pixel, the first color light includes red light and green light, the second sub-pixel includes a blue sub-pixel, and the second color light includes blue light.

18. The display panel of claim 13, wherein, The plurality of conductive layers include scan lines and data lines arranged in different layers, the scan lines are located on a side of the filter layer away from the first substrate, and the data lines are located on a side of the filter layer away from or close to the first substrate.

19. The display panel of claim 13, wherein, The filter pattern includes high-refraction layers and low-refraction layers arranged in a stack and alternately, a refractive index of the high-refraction layers is greater than a refractive index of the low-refraction layers.

20. A display device, comprising: the display panel according to any one of claims 1 to 19; and a driving assembly connected with the display panel and configured to drive the display panel to emit light.

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