Pixel driving circuit and driving method therefor, and display device

Abstract

A pixel driving circuit and a driving method therefor, and a display device. The pixel driving circuit comprises a storage sub-circuit, a first control sub-circuit, and a second control sub-circuit, wherein the first control sub-circuit is electrically connected to at least one reset signal line, a first node and a third node, and is configured to connect the first node to the third node under the control of the at least one reset signal line; the second control sub-circuit is electrically connected to a fourth reset signal line, a first power line and a fifth node, and is configured to provide a signal from the first power line to the fifth node on the basis of the fourth reset signal line; and the storage sub-circuit is electrically connected to the first node, a second node, and the fifth node, and is configured to store the voltage difference of signals between the first node, the second node and the fifth node.

Description

Pixel driving circuit and driving method thereof, and display device

[0001] The present application claims priority to the Chinese patent application No. 202410832634.7, filed on June 25, 2024, and entitled “Pixel driving circuit and driving method thereof, and display device”, the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to, but is not limited to, the technical field of display, in particular to a pixel driving circuit and driving method thereof, and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit, comprising: a driving sub-circuit, a light-emitting control sub-circuit, a storage sub-circuit, a first control sub-circuit and a second control sub-circuit;

[0006] The driving sub-circuit is electrically connected with the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of signals of the first node and the second node;

[0007] The light-emitting control sub-circuit is electrically connected with at least one light-emitting signal line, and is configured to output a driving signal under the control of signals of the at least one light-emitting signal line;

[0008] The first control sub-circuit is electrically connected with at least one reset signal line, the first node and the third node respectively, and is configured to connect the first node and the third node under the control of the at least one reset signal line;

[0009] a second control sub-circuit electrically connected with the fourth reset signal line, the first power supply line and the fifth node, and configured to provide a signal of the first power supply line to the fifth node based on the fourth reset signal line;

[0010] a storage sub-circuit electrically connected with the first node, the second node and the fifth node, and configured to store a voltage difference of signals between the first node, the second node and the fifth node.

[0011] In an example embodiment, the storage sub-circuit comprises a first capacitor and a second capacitor.

[0012] a first plate of the first capacitor is electrically connected with the fifth node, and a second plate of the first capacitor is electrically connected with the second node;

[0013] a first plate of the second capacitor is electrically connected with the fifth node, and a second plate of the second capacitor is electrically connected with the first node.

[0014] In an example embodiment, the second control sub-circuit comprises an eighth transistor.

[0015] a control electrode of the fourth transistor is electrically connected with the scan signal line, a first electrode of the fourth transistor is electrically connected with the data signal line, and a second electrode of the fourth transistor is electrically connected with the second node;

[0016] a control electrode of the fifth transistor is electrically connected with the fourth reset signal line, a first electrode of the fifth transistor is electrically connected with the first power supply line, and a second electrode of the fifth transistor is electrically connected with the fifth node.

[0017] In an example embodiment, the first control sub-circuit is further electrically connected with a reference signal line, the second node and a first initial signal line, and configured to provide a signal of the reference signal line to the second node, and provide a signal of the first initial signal line to the first node or the third node under control of a signal of at least one reset signal line.

[0018] In an example embodiment, the at least one reset signal line comprises at least one of a first reset signal line, a second reset signal line and a third reset signal line.

[0019] the first control sub-circuit comprises a first transistor, a second transistor and a ninth transistor;

[0020] a control electrode of the first transistor is electrically connected with the first reset signal line, a first electrode of the first transistor is electrically connected with the first initial signal line, and a second electrode of the first transistor is electrically connected with one of the first node and the third node;

[0021] a control electrode of the second transistor is electrically connected with the third reset signal line, a first electrode of the second transistor is electrically connected with the first node, and a second electrode of the second transistor is electrically connected with the third node.

[0022] The control electrode of the ninth transistor is electrically connected with the second reset signal line, the first electrode of the ninth transistor is electrically connected with the reference signal line, and the second electrode of the ninth transistor is electrically connected with the second node.

[0023] In an example embodiment, the second reset signal line and the third reset signal line are different signal lines, or are the same signal line.

[0024] In an example embodiment, further comprising: a third control sub-circuit;

[0025] The third control sub-circuit is electrically connected with the fifth reset signal line, the second initial signal line and the fourth node respectively, and is configured to provide the signal of the second initial signal line to the fourth node under the control of the signal of the fifth reset signal line.

[0026] The fifth reset signal line is the same signal line as one of the second reset signal line and the fourth reset signal line.

[0027] In an example embodiment, further comprising: a write sub-circuit; the write sub-circuit is electrically connected with the scan signal line, the data signal line and the second node respectively, and is configured to provide the signal of the data signal line to the second node under the control of the signal of the scan signal line.

[0028] The light-emitting control sub-circuit is further electrically connected with the first power supply line, the second node, the third node and the fifth node; the at least one light-emitting signal line comprises a first light-emitting signal line; the driving sub-circuit comprises a third transistor; the write sub-circuit comprises a fourth transistor; and the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor.

[0029] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node.

[0030] The control electrode of the fourth transistor is electrically connected with the scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node.

[0031] The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the second node.

[0032] The control electrode of the sixth transistor is electrically connected with the first light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fourth node.

[0033] In an example embodiment, the at least one reset signal line includes at least one of a first reset signal line and a third reset signal line.

[0034] The first control sub-circuit includes a first transistor and a second transistor.

[0035] The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to one of the first node and the third node.

[0036] The control electrode of the second transistor is electrically connected to the third reset signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

[0037] In an example embodiment, the at least one reset signal line includes a third reset signal line.

[0038] The first control sub-circuit includes a second transistor.

[0039] The control electrode of the second transistor is electrically connected to the third reset signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

[0040] In an example embodiment, further including a third control sub-circuit.

[0041] The third control sub-circuit is electrically connected to a fifth reset signal line, a second initial signal line, and a fourth node, respectively, and is configured to provide a signal of the second initial signal line to the fourth node under control of a signal of the fifth reset signal line.

[0042] The fifth reset signal line is the same signal line as the fourth reset signal line, or is a different signal line from at least one of the first reset signal line, the third reset signal line, and the fourth reset signal line.

[0043] In an example embodiment, further including a write sub-circuit, the write sub-circuit being electrically connected to a scan signal line, a data signal line, and a second node, respectively, and being configured to provide a signal of the data signal line to the second node under control of a signal of the scan signal line.

[0044] The light emission control sub-circuit is further electrically connected to a first power supply line, the second node, the third node, and a fifth node; the at least one light emission signal line includes a first light emission signal line and a second light emission signal line; the drive sub-circuit includes a third transistor; the write sub-circuit includes a fourth transistor; and the light emission control sub-circuit includes a fifth transistor and a sixth transistor.

[0045] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node;

[0046] The control electrode of the fourth transistor is electrically connected with the scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node;

[0047] The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the second node;

[0048] The control electrode of the sixth transistor is electrically connected with the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fourth node.

[0049] In an exemplary embodiment, the display device further comprises a write sub-circuit electrically connected with the scan signal line, and the write sub-circuit comprises a fourth transistor, and the first control sub-circuit comprises a second transistor electrically connected with the first node and the third node, respectively;

[0050] The time period during which the signal of the scan signal line to which the control electrode of the fourth transistor is connected is an effective level signal does not overlap with the time period during which the signal of the reset signal line to which the control electrode of the second transistor is connected is an effective level signal.

[0051] In an exemplary embodiment, the start time of the time period during which the signal of the scan signal line to which the control electrode of the fourth transistor is connected is an effective level signal is later than the end time of the time period during which the signal of the reset signal line to which the control electrode of the second transistor is connected is an effective level signal.

[0052] In an exemplary embodiment, the display device further comprises a biasing sub-circuit;

[0053] The biasing sub-circuit is electrically connected with at least one of the second node and the third node, the first reset signal line, and the biasing signal line, and is configured to provide the signal of the biasing signal line to the at least one of the second node and the third node under the control of the signal of the first reset signal line;

[0054] The biasing sub-circuit comprises a tenth transistor;

[0055] The control electrode of the tenth transistor is electrically connected with the first reset signal line, the first electrode of the tenth transistor is electrically connected with the biasing signal line, and the second electrode of the tenth transistor is electrically connected with the at least one of the second node and the third node.

[0056] In a second aspect, the display device comprises the pixel driving circuit.

[0057] In an example embodiment, further comprising: a substrate; and a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of third reset signal lines, a plurality of fourth reset signal lines, a plurality of scan signal lines, a plurality of reference signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of light-emitting signal lines, a plurality of first power supply lines, a plurality of data signal lines, and a plurality of power connection lines disposed on the substrate, at least one power connection line electrically connected to at least one first power supply line;

[0058] At least one of the first reset signal lines, the second reset signal lines, the third reset signal lines, the fourth reset signal lines, the light-emitting signal lines, the first initial signal lines, the second initial signal lines, the reference signal lines, and the power connection lines extends at least partially along a first direction, and at least one of the first power supply lines and the data signal lines extends at least partially along a second direction, the first direction and the second direction intersecting;

[0059] Orthographic projections of the first initial signal lines, orthographic projections of the first reset signal lines, orthographic projections of the third reset signal lines, orthographic projections of the scan signal lines, orthographic projections of the light-emitting signal lines, orthographic projections of the fourth reset signal lines, orthographic projections of the second reset signal lines, orthographic projections of the reference signal lines, and orthographic projections of the second initial signal lines are arranged in the second direction in order, and orthographic projections of the power connection lines are located between orthographic projections of the light-emitting signal lines and orthographic projections of the fourth reset signal lines.

[0060] In an example embodiment, further comprising: a driving circuit layer, the driving circuit layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, a pixel driving circuit comprising: at least one transistor and at least one capacitor, the transistor comprising: an active pattern, a control electrode, a first electrode, and a second electrode, the capacitor comprising: a first electrode plate and a second electrode plate;

[0061] The semiconductor layer comprises: the first initial signal lines, the second initial signal lines, and the active pattern of the at least one transistor of the at least one pixel driving circuit;

[0062] The first conductive layer comprises: the light-emitting signal lines, the control electrode of the at least one transistor of the at least one pixel driving circuit, and the second electrode plate of the at least one capacitor;

[0063] The second conductive layer comprises: the first electrode plate of the at least one capacitor of the at least one pixel driving circuit;

[0064] The third conductive layer comprises a first reset signal line, a second reset signal line, a third reset signal line, a fourth reset signal line, a scan signal line, a reference signal line, a power connection line, and a first electrode and a second electrode of at least one transistor of the at least one pixel driving circuit.

[0065] The fourth conductive layer comprises a data signal line and a first power line.

[0066] In an example embodiment, further comprising: a shielding electrode on the second conductive layer, the shielding electrode being electrically connected to the first initial signal line.

[0067] A normal projection of the shielding electrode on the substrate at least partially overlaps a normal projection of the first initial signal line, the first reset signal line, the third reset signal line, and the scan signal line on the substrate.

[0068] In a third aspect, the present disclosure further provides a driving method of a pixel driving circuit, configured to drive the pixel driving circuit, the method comprising:

[0069] The driving sub-circuit provides a driving signal to the third node under the control of signals at the first node and the second node;

[0070] The light-emitting control sub-circuit outputs a driving signal under the control of a signal of at least one light-emitting signal line;

[0071] The first control sub-circuit connects the first node and the third node under the control of at least one reset signal line;

[0072] The second control sub-circuit provides a signal of the first power line to the fifth node based on the fourth reset signal line;

[0073] The storage sub-circuit stores a voltage difference of signals between the first node, the second node, and the fifth node.

[0074] Other aspects can be appreciated upon reading and understanding the drawings and detailed description.

[0075] SUMMARY

[0076] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application. The present application is not limited to the embodiments illustrated in the drawings.

[0077] FIG. 1 is a structural schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0078] FIG. 2 is a structural schematic diagram of a pixel driving circuit according to an example embodiment;

[0079] FIG. 3 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0080] Fig. 4 is a second equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0081] Fig. 5 is a third equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0082] Fig. 6 is a fourth equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0083] Fig. 7 is a fifth equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0084] Fig. 8 is a sixth equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0085] Fig. 9 is a seventh equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0086] Fig. 10 is an eighth equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0087] Fig. 11 is a ninth equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0088] Fig. 12 is a first timing diagram of the pixel driving circuit according to Figs. 3 and 4;

[0089] Fig. 13 is a second timing diagram of the pixel driving circuit according to Figs. 3 and 4;

[0090] Fig. 14 is a timing diagram of the pixel driving circuit according to Figs. 5 and 6;

[0091] Fig. 15 is a timing diagram of the pixel driving circuit according to Figs. 7 and 8;

[0092] Fig. 16 is a first timing diagram of the pixel driving circuit according to Figs. 9 and 10;

[0093] Fig. 17 is a second timing diagram of the pixel driving circuit according to Figs. 9 and 10;

[0094] Fig. 18 is a third timing diagram of the pixel driving circuit according to Figs. 9 and 10;

[0095] Fig. 19 is a structural schematic diagram of a display device;

[0096] Fig. 20 is a schematic diagram after forming a semiconductor layer pattern in Fig. 19;

[0097] Fig. 21 is a schematic diagram of a first conductive layer pattern in Fig. 19;

[0098] Fig. 22 is a schematic diagram after forming a first conductive layer pattern in Fig. 19;

[0099] FIG. 23 is a schematic view of the second conductive layer pattern in FIG. 19;

[0100] FIG. 24 is a schematic view of FIG. 19 after the second conductive layer pattern is formed;

[0101] FIG. 25 is a schematic view of FIG. 19 after the fourth insulating layer pattern is formed;

[0102] FIG. 26 is a schematic view of the third conductive layer pattern in FIG. 19;

[0103] FIG. 27 is a schematic view of FIG. 19 after the third conductive layer pattern is formed;

[0104] FIG. 28 is a schematic view of FIG. 19 after the first planar layer pattern is formed;

[0105] FIG. 29 is a schematic view of the fourth conductive layer pattern in FIG. 19;

[0106] FIG. 30 is a schematic view of FIG. 19 after the fourth conductive layer pattern is formed.

[0107] DETAILED DESCRIPTION

[0108] In order to make the objectives, technical solutions, and advantages of the present disclosure clearer, below the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. It is easily understood by those skilled in the art that the embodiments and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other as long as there is no conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the detailed description of some known functions and known components is omitted. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed structures

[0109] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and interval of each film layer, and the width and interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic views of the structures, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0110] The ordinal numbers "first", "second", "third", and the like in the present specification are set in order to avoid confusion of components, and are not intended to be limiting in terms of numbers.

[0111] In this specification, terms of "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or directional relationship of the components are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0112] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0113] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0114] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0115] In this specification, "electrically connected" includes the case where the components are connected together through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit and receive an electrical signal between the components to be connected. Examples of the element having a certain electrical action include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0116] In the present specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and 10° or less, and thus, an angle of -5° or more and 5° or less is also included. In addition, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and 100° or less, and thus, a state in which an angle of 85° or more and 95° or less is also included.

[0117] In the present specification, "film" and "layer" can be replaced with each other. For example, "conductive layer" can be replaced with "conductive film" at times. Similarly, "insulating film" can be replaced with "insulating layer" at times.

[0118] In the present specification, "same layer" refers to structures of two (or more) kinds that are patterned by the same patterning process, and the materials thereof can be the same or different. For example, the materials of the precursors that form the multiple structures in the same layer are the same, and the materials finally formed can be the same or different.

[0119] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly in the sense that they can be approximately a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. There can be some small deformations due to tolerances, there can be inside corners, arc edges, and deformations, etc.

[0120] In the present disclosure, "about" refers to not strictly limited boundaries, allowing values within the range of process and measurement errors.

[0121] The display device includes a plurality of sub-pixels, the sub-pixel includes a pixel driving circuit and a light emitting device, the pixel driving circuit is configured to drive the light emitting device to emit light. The threshold value compensation process in the pixel driving circuit and the data writing process occur together, so that the pixel driving circuit cannot realize high frequency driving.

[0122] To this end, the present disclosure provides a pixel driving circuit.

[0123] FIG. 1 is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure. As shown in FIG. 1, the pixel driving circuit provided by the embodiment of the present disclosure can include a driving sub-circuit, a light-emitting control sub-circuit, a storage sub-circuit, a first control sub-circuit, and a second control sub-circuit. As shown in FIG. 1, the driving sub-circuit is electrically connected to a first node N1, a second node N2, and a third node N3 respectively, and is configured to provide a driving signal to the third node N3 under the control of signals of the first node N1 and the second node N2; the light-emitting control sub-circuit is electrically connected to at least one light-emitting signal line EM, and is configured to output a driving signal under the control of a signal of the at least one light-emitting signal line EM; the first control sub-circuit is electrically connected to at least one reset signal line Reset, the first node N1, and the third node N3 respectively, and is configured to connect the first node N1 and the third node N3 under the control of the at least one reset signal line Reset; the second control sub-circuit is electrically connected to a fourth reset signal line Reset4, a first power supply line VDD, and a fifth node N5 respectively, and is configured to provide a signal of the first power supply line VDD to the fifth node N5 under the control of a signal of the fourth reset signal line Reset4; and the storage sub-circuit is electrically connected to the first node N1, the second node N2, and the fifth node N5 respectively, and is configured to store a voltage difference of signals between the first node N1, the second node N2, and the fifth node N5.

[0124] In an example embodiment, the pixel driving circuit is configured to drive the light-emitting device L to emit light. The light-emitting device L is connected to the fourth node N4 and a second power supply line VSS respectively.

[0125] In an example embodiment, the first power supply line VDD continuously provides a high-level signal, and the second power supply line VSS continuously provides a low-level signal.

[0126] In an example embodiment, the light-emitting device can include a current-driven device, and can adopt a current-type light-emitting diode, such as a Micro Light Emitting Diode (Micro LED) or a Mini Light Emitting Diode (Mini LED) or an Organic Light Emitting Diode (OLED) or a Quantum Light Emitting Diode (QLED). The typical size (e.g., length) of the Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of the Mini LED can be about 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0127] In an exemplary embodiment, the light emitting device can be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0128] In an exemplary embodiment, the first electrode of the light emitting device L is electrically connected to the fourth node N4, and the second electrode of the light emitting device L is electrically connected to the second power supply line VSS.

[0129] In an exemplary embodiment, the organic light emitting layer can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked. In an exemplary embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0130] The present disclosure can achieve independent occurrence of threshold compensation and data writing in a pixel driving circuit, improve the time of threshold compensation in the pixel driving circuit, and thus achieve high-frequency driving of the pixel driving circuit, by mutual cooperation between the driving sub-circuit, the light emitting control sub-circuit, the storage sub-circuit, the first control sub-circuit, and the second control sub-circuit.

[0131] In an exemplary embodiment, the at least one light emitting signal line can include a first light emitting signal line, or can include a first light emitting signal line and a second light emitting signal line.

[0132] In an exemplary embodiment, the at least one reset signal line can include at least two of a first reset signal line, a second reset signal line, a third reset signal line, and a fourth reset signal line.

[0133] The at least one pixel driving circuit includes at least one transistor. According to the characteristic of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. When the transistor is a P-type transistor, the on voltage is a low voltage (for example, 0 V, -5 V, -10 V or other suitable voltage), and the off voltage is a high voltage (for example, 5 V, 10 V or other suitable voltage). When the transistor is an N-type transistor, the on voltage is a high voltage (for example, 5 V, 10 V or other suitable voltage), and the off voltage is a low voltage (for example, 0 V, -5 V, -10 V or other suitable voltage).

[0134] In an example embodiment, the P-type transistor can be a low temperature poly-silicon (LTPS) thin film transistor, and the N-type transistor can be an oxide thin film transistor. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon, and the active layer of the oxide thin film transistor adopts oxide semiconductor. The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature polycrystalline oxide (LTPO) display substrate, which can utilize the advantages of both, can realize low frequency driving, can reduce power consumption, and can improve display quality.

[0135] FIG. 2 is an equivalent circuit diagram of the storage sub-circuit and the second control sub-circuit provided in FIG. 1. In an example embodiment, as shown in FIG. 2, the storage sub-circuit can include a first capacitor C1 and a second capacitor C2. Wherein the first plate of the first capacitor C1 is electrically connected with the fifth node N5, and the second plate of the first capacitor C1 is electrically connected with the second node N2; the first plate of the second capacitor C2 is electrically connected with the fifth node N5, and the second plate of the second capacitor C2 is electrically connected with the first node N1.

[0136] In an example embodiment, as shown in FIG. 2, the second control sub-circuit can include an eighth transistor T8, the control electrode of the eighth transistor T8 is electrically connected with the fourth reset signal line Reset4, the first electrode of the eighth transistor T8 is electrically connected with the first power supply line VDD, and the second electrode of the eighth transistor T8 is electrically connected with the fifth node N5.

[0137] In an example embodiment, as shown in FIG. 1, the pixel driving circuit can further include a writing sub-circuit. Wherein the writing sub-circuit is electrically connected with the scan signal line Gate, the data signal line Data and the second node N2 respectively, and is configured to provide the signal of the data signal line Data to the second node N2 under the control of the signal of the scan signal line Gate.

[0138] In an example embodiment, as shown in FIG. 1, the pixel driving circuit can further include a third control sub-circuit. The third control sub-circuit is electrically connected with the fifth reset signal line Reset5, the first reset signal line Reset1 and the bias signal line BIAS, and is configured to provide the signal of the bias signal line BIAS to one of the second node N2 and the third node N3 under the control of the signal of the first reset signal line Reset1.

[0139] In an example embodiment, as shown in FIG. 1, the pixel driving circuit can further include a bias sub-circuit. The bias sub-circuit is electrically connected with at least one of the second node N2 and the third node N3, the first reset signal line Reset1 and the bias signal line BIAS, and is configured to provide the signal of the bias signal line BIAS to one of the second node N2 and the third node N3 under the control of the signal of the first reset signal line Reset1.

[0140] In an example embodiment, the bias sub-circuit can be configured to adjust the display residual image, so as to ensure the display effect of the display device in which the pixel driving circuit is located.

[0141] In an example embodiment, when the at least one light-emitting signal line includes the first light-emitting signal line EM1, the first control sub-circuit is further electrically connected with the reference signal line REF, the second node N2 and the first initial signal line INIT1, and is configured to provide the signal of the reference signal line REF to the second node N2 and the signal of the first initial signal line INIT1 to the first node N1 or the third node N3 under the control of the signal of the at least one reset signal line.

[0142] FIG. 3 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment of the present disclosure, FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment of the present disclosure, FIG. 5 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment of the present disclosure, FIG. 6 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment of the present disclosure, FIG. 7 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment of the present disclosure, and FIG. 8 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment of the present disclosure. As shown in FIGS. 3 to 8, when the at least one light-emitting signal line includes the first light-emitting signal line EM1, the at least one reset signal line includes at least one of the first reset signal line Reset1, the second reset signal line Reset2 and the third reset signal line Reset3. The first control sub-circuit includes the first transistor T1, the second transistor T2 and the ninth transistor T9.

[0143] The control electrode of the first transistor T1 is electrically connected with the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected with the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected with one of the first node N1 and the third node N3; the control electrode of the second transistor T2 is electrically connected with the third reset signal line Reset3, the first electrode of the second transistor T2 is electrically connected with the first node N1, the second electrode of the second transistor T2 is electrically connected with the third node N3, the control electrode of the ninth transistor T9 is electrically connected with the second reset signal line Reset2, the first electrode of the ninth transistor T9 is electrically connected with the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected with the second node N2.

[0144] In an example embodiment, the third control sub-circuit can include a seventh transistor T7. The control electrode of the seventh transistor T7 is electrically connected with the fifth reset signal line Reset5, the first electrode of the seventh transistor T7 is electrically connected with the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected with the fourth node N4.

[0145] As shown in FIGS. 3-8, when the at least one emitting signal line includes the first emitting signal line EM1, the driving sub-circuit includes a third transistor T3, the writing sub-circuit includes a fourth transistor T4, and the emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3. The control electrode of the fourth transistor T4 is electrically connected with the scanning signal line Gate, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2. The control electrode of the fifth transistor T5 is electrically connected with the first emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2. The control electrode of the sixth transistor T6 is electrically connected with the first emitting signal line EM1, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the fourth node N4. FIGS. 3, 5 and 7 are described by taking the second electrode of the first transistor T1 being electrically connected with the first node N1 as an example, and FIGS. 4, 6 and 8 are described by taking the second electrode of the first transistor T1 being electrically connected with the third node N3 as an example.

[0146] In an example embodiment, the second reset signal line Reset2 and the third reset signal line Reset3 are different signal lines, or are the same signal line.

[0147] In an example embodiment, the fifth reset signal line Reset5 is the same signal line as one of the second reset signal line Reset2 and the fourth reset signal line Reset4.

[0148] FIGS. 3 and 4 are examples in which the second reset signal line Reset2 and the third reset signal line Reset3 are different signal lines, and the fifth reset signal line Reset5 is the same signal line as the second reset signal line Reset2. FIGS. 5 and 6 are examples in which the second reset signal line Reset2, the third reset signal line Reset3, and the fifth reset signal line Reset5 are the same signal line. FIGS. 7 and 8 are examples in which the second reset signal line Reset2 and the third reset signal line Reset3 are the same signal line, and the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are the same signal line.

[0149] In an example embodiment, the pixel driving circuit provided in FIGS. 3 to 8 can further include a bias sub-circuit. The bias sub-circuit includes a tenth transistor T10. The control electrode of the tenth transistor T10 is electrically connected to the first reset signal line Reset1, the first electrode of the tenth transistor T10 is electrically connected to a bias signal line BIAS, and the second electrode of the tenth transistor T10 is electrically connected to one of the second node N2 and the third node N3.

[0150] In an example embodiment, the first transistor T1 to the tenth transistor T10 in at least one of the pixel driving circuits in FIGS. 3 to 8 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the tenth transistor T10 can include P-type transistors and N-type transistors.

[0151] In an example embodiment, FIGS. 3 to 8 are examples in which the first transistor T1 to the tenth transistor T10 are all P-type transistors.

[0152] In an example embodiment, the first transistor T1, the second transistor T2, and the eighth transistor T8 in at least one of the pixel driving circuits in FIGS. 3 to 8 can be N-type transistors, and the third transistor T3 to the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 can be P-type transistors. The first transistor T1, the second transistor T2, and the eighth transistor T8 in at least one of the pixel driving circuits in FIGS. 3 to 8 can be N-type transistors, which can reduce the leakage current of the first node N1, and thus improve the reliability of the pixel driving circuit.

[0153] Fig. 9 is an equivalent circuit diagram seven of the pixel driving circuit provided by the embodiment of the present disclosure, and Fig. 10 is an equivalent circuit diagram eight of the pixel driving circuit provided by the embodiment of the present disclosure. As shown in Fig. 9 and Fig. 10, when the at least one light-emitting signal line includes the first light-emitting signal line EM1 and the second light-emitting signal line EM2, the at least one reset signal line can include at least one of the first reset signal line Reset1 and the third reset signal line Reset3. The first control sub-circuit is further electrically connected with the first initial signal line INIT1. The first control sub-circuit includes the first transistor T1 and the second transistor T2. Wherein, the control electrode of the first transistor T1 is electrically connected with the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected with the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected with one of the first node N1 and the third node N3; the control electrode of the second transistor T2 is electrically connected with the third reset signal line Reset3, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the third node N3. Fig. 9 is an example of the second electrode of the first transistor being electrically connected with the first node N1, and Fig. 10 is an example of the second electrode of the first transistor being electrically connected with the third node N3.

[0154] Fig. 11 is an equivalent circuit diagram nine of the pixel driving circuit provided by the embodiment of the present disclosure. As shown in Fig. 11, when the at least one light-emitting signal line includes the first light-emitting signal line EM1 and the second light-emitting signal line EM2, the at least one reset signal line can include the third reset signal line Reset3. The first control sub-circuit includes the second transistor T2. Wherein, the control electrode of the second transistor T2 is electrically connected with the third reset signal line Reset3, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the third node N3.

[0155] In the example embodiment, the third control sub-circuit can include the seventh transistor T7. Wherein, the control electrode of the seventh transistor T7 is electrically connected with the fifth reset signal line Reset5, the first electrode of the seventh transistor T7 is electrically connected with the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected with the fourth node N4.

[0156] As shown in FIGS. 10-11, when the at least one light-emitting signal line includes the first light-emitting signal line and the second light-emitting signal line, the driving sub-circuit includes the third transistor T3, the writing sub-circuit includes the fourth transistor T4, and the light-emitting control sub-circuit includes the fifth transistor T5 and the sixth transistor T6, wherein the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the scanning signal line Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. FIGS. 3, 5, and 7 are described by way of example with the second electrode of the first transistor T1 electrically connected to the first node N1, and FIGS. 4, 6, and 8 are described by way of example with the second electrode of the first transistor T1 electrically connected to the third node N3.

[0157] In an example embodiment, the fifth reset signal line Reset5 and the fourth reset signal line Reset4 are the same signal line, and can be different from at least one of the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4.

[0158] In an example embodiment, the pixel driving circuit provided in FIGS. 9-11 can further include a biasing sub-circuit. The biasing sub-circuit includes the tenth transistor T10, wherein the control electrode of the tenth transistor T10 is electrically connected to the first reset signal line Reset1, the first electrode of the tenth transistor T10 is electrically connected to the biasing signal line BIAS, and the second electrode of the tenth transistor T10 is electrically connected to one of the second node N2 and the third node N3.

[0159] In an example embodiment, the first transistor T1 to the eighth transistor T8 and the tenth transistor T10 in at least one of the pixel driving circuits in FIGS. 9 and 10 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the eighth transistor T8 and the tenth transistor T10 can include P-type transistors and N-type transistors. FIGS. 9 and 10 are described by taking the first transistor T1 to the eighth transistor T8 and the tenth transistor T10 as P-type transistors as an example.

[0160] In an example embodiment, the first transistor T1, the second transistor T2, and the eighth transistor T8 in FIGS. 9 and 10 can be N-type transistors, and the third transistor T3 to the seventh transistor T7 and the tenth transistor T10 can be P-type transistors.

[0161] The first transistor T1, the second transistor T2, and the eighth transistor T8 in FIGS. 9 and 10 being N-type transistors can reduce the leakage current of the first node N1, and further improve the reliability of the pixel driving circuit.

[0162] In an example embodiment, the second transistor T2 to the eighth transistor T8 and the tenth transistor T10 in at least one of the pixel driving circuits in FIG. 11 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the second transistor T2 to the eighth transistor T8 and the tenth transistor T10 can include P-type transistors and N-type transistors. FIG. 11 is described by taking the second transistor T2 to the eighth transistor T8 and the tenth transistor T10 as P-type transistors as an example.

[0163] In an example embodiment, the second transistor T2 and the eighth transistor T8 in FIG. 11 can be N-type transistors, and the third transistor T3 to the seventh transistor T7 and the tenth transistor T10 can be P-type transistors.

[0164] The second transistor T2 and the eighth transistor T8 in FIG. 11 being N-type transistors can reduce the leakage current of the first node N1, and further improve the reliability of the pixel driving circuit.

[0165] In the example implementation, as shown in FIGS. 2-11, the write sub-circuit includes the fourth transistor T4, and the node control sub-circuit includes the second transistor T2, which is electrically connected with the first node N1 and the third node N3 respectively. The reset signal line to which the control electrode of the second transistor T2 is connected can be the second reset signal line Reset2 or the third reset signal line Reset3. The signal of the scan signal line Gate to which the control electrode of the fourth transistor is connected does not overlap with the signal of the reset signal line to which the control electrode of the second transistor is connected in the time period in which the signal is the effective level signal. The signal of the scan signal line Gate to which the control electrode of the fourth transistor is connected does not overlap with the signal of the reset signal line to which the control electrode of the second transistor is connected in the time period in which the signal is the effective level signal, which can make the time period of threshold compensation and the time period of data writing not overlap, thereby realizing separate occurrence of threshold compensation and data writing.

[0166] In the example implementation, the start time of the time period in which the signal of the scan signal line Gate to which the control electrode of the fourth transistor is connected is the effective level signal is later than the end time of the time period in which the signal of the reset signal line to which the control electrode of the second transistor is connected is the effective level signal.

[0167] In the example implementation, FIG. 12 is a working timing diagram one of the pixel driving circuit provided in FIGS. 3 and 4. As shown in FIGS. 3 and 12, the working process of the pixel driving circuit provided in FIG. 3 can include:

[0168] In the first stage P11, referred to as the initialization stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3 and the fourth reset signal line Reset4 are low level signals, and the signals of the first emission signal line EM1, the scan signal line Gate, the second reset signal line Reset2 and the fifth reset signal line Reset5 are high level signals. The first transistor T1, the second transistor T2 and the eighth transistor T8 are turned on, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0169] The first transistor T1 and the second transistor T2 are turned on, the initial signal of the first initial signal line INIT1 is written to the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed. The eighth transistor T8 is turned on, the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed.

[0170] In this stage, the voltage value V N1 VN1 = Vinit1, the voltage value V of the signal of the third node N3 N3 satisfies V N3 = Vinit1, the voltage value V of the signal of the fifth node N5 N5 satisfies V N5 = Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, and Vdd is the voltage value of the signal of the first power supply line VDD.

[0171] In the second stage P12, referred to as a threshold compensation stage, the signals of the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low-level signals, and the signals of the first emitting signal line EM1, the first reset signal line Reset1 and the scanning signal line Gate are high-level signals. The second transistor T2, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0172] The second transistor T2 and the ninth transistor T9 are turned on, the signal of the reference signal line REF is written to the second node N2, and the first node N1 is charged through the turned-on ninth transistor T9, the turned-on third transistor T3 and the turned-on second transistor T2 until the voltage value V of the signal of the first node N1 N1 satisfies V N1 = Vref + Vth, wherein Vref is the voltage value of the signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4, the first pole of the emitting device is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed. The eighth transistor T8 is turned on, the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed.

[0173] In this stage, the voltage value V of the signal of the first node N1 N1 satisfies V N1 = Vref + Vth, the voltage value V of the signal of the second node N2 N2 satisfies V N2 = Vref, the voltage value V of the signal of the third node N3 N3 satisfies V N3 = Vref + Vth, the voltage value V of the signal of the fourth node N4 N4 satisfies V N4 = Vinit2, the voltage value V of the signal of the fifth node N5 N5 satisfies VN5 =Vdd, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, the charge stored in the first capacitor C1 is Vdd-Vref, and the charge stored in the second capacitor C2 is Vdd-Vref-Vth.

[0174] The third stage, P13, is called the data writing stage. The signals on the scan signal line Gate and the fourth reset signal line Reset4 are low-level signals, while the signals on the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fifth reset signal line Reset5, and the first light-emitting signal line EM1 are high-level signals. The fourth transistor T4 and the eighth transistor T8 are turned on, while the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned off.

[0175] When the fourth transistor T4 is turned on, the data voltage of the data signal line Data is written to the second node N2. When the eighth transistor T8 is turned on, the signal of the first power line VDD is written to the fifth node N5. The fifth node N5 is initialized (reset), and its internal pre-stored voltage is cleared, thus completing the initialization.

[0176] During this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node... N1 Satisfy V N1 =Vref + Vth, the voltage value V of the signal at the second node N2. N2 Satisfy V N2 =Vdata, the voltage value V of the signal at the third node N3. N3 Satisfy V N3 =Vref + Vth, the voltage value V of the signal at the fourth node N4. N4 Satisfy V N4 =Vinit2, the voltage value V of the signal at the fifth node N5. N5 Satisfy V N5 =Vdd, Vdata is the data voltage of the data signal line Data, the charge stored in the first capacitor C1 is Vdd-Vref, and the charge stored in the second capacitor C2 is Vdd-Vref-Vth.

[0177] In the fourth stage P14, referred to as the light emitting stage, the signal of the first light emitting signal line EM1 is a low level signal, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4, the fifth reset signal line Reset5 and the scanning signal line Gate are high level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0178] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power voltage output by the first power supply end VDD is provided to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6 to drive the light emitting device L to emit light.

[0179] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V N1 of the signal of the first node N1 satisfies V N1 =Vref+Vth, the voltage value V N2 of the signal of the second node N2 satisfies V N2 =Vdata, the voltage value V N4 of the signal of the fourth node N4 satisfies V N4 =Voled+Vss, and Voled is the voltage difference applied to the two sides of the light emitting device L, and Vss is the voltage value of the signal of the second power supply line VSS.

[0180] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage value V N1 of the signal of the first node N1 satisfies V N1 =Vref+Vth, and the voltage value V N2 of the signal of the second node N2 satisfies V 2 =Vdata, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*(Vref+Vth-Vdata-Vth) 2

[0181] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3.

[0182] The above is described by taking the first transistor T1 to the ninth transistor T9 included in the pixel driving circuit of FIG. 3 as an example. When the pixel driving circuit of FIG. 2 includes a tenth transistor T10, the tenth transistor T10 is turned on in the first stage and is turned off in the second stage to the fourth stage. The tenth transistor T10 is turned on, and the signal of the bias signal line BIAS is written into the second node N2 or the third node N3.

[0183] The pixel driving circuit of FIG. 4 is different from the pixel driving circuit of FIG. 3 only in the position of the first transistor T1. The first transistor T1 is turned on only in the first stage. Therefore, the working process of the pixel driving circuit of FIG. 4 is the same as that of the pixel driving circuit of FIG. 3, and the disclosure will not be described here.

[0184] In the exemplary embodiment, FIG. 13 is a working timing diagram two of the pixel driving circuit of FIGS. 3 and 4. The difference between FIG. 12 and FIG. 13 is only the signal of the third reset signal line Reset3. The signal of the second reset signal line Reset2 in FIG. 12 is a high-level signal in the first stage and a low-level signal in the second stage. The second reset signal line Reset2 is a low-level signal in the first stage and the second stage. The signal of the second reset signal line Reset2 in FIG. 13 is the same as that of the third reset signal line Reset3. Both are a high-level signal in the first stage and a low-level signal in the second stage. Therefore, the working timing provided in FIG. 13 is different from that provided in FIG. 12 only in the working process in the first stage. The working processes in the other stages are completely the same. The disclosure will only describe the working process in the first stage.

[0185] In combination with FIGS. 3 and 13, the working process of the pixel driving circuit of FIG. 3 can include:

[0186] The first stage P11 is called an initialization stage. The signals of the first reset signal line Reset1 and the fourth reset signal line Reset4 are low-level signals. The signals of the first emission signal line EM1, the scan signal line Gate, the second reset signal line Reset2, the third reset signal line Reset3, and the fifth reset signal line Reset5 are high-level signals. The first transistor T1 and the eighth transistor T8 are turned on. The second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned off.

[0187] The first transistor T1 is turned on, the initial signal of the first initial signal line INIT1 is written to the first node N1, the first node N1 is initialized (reset), the pre-stored voltage in the first node N1 is emptied, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage in the fifth node N5 is emptied, and the initialization is completed.

[0188] In this stage, the voltage value V of the signal of the first node N1 N1 satisfies V N1 = Vinit1, the voltage value V of the signal of the fifth node N5 N5 satisfies V N5 = Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, and Vdd is the voltage value of the signal of the first power supply line VDD.

[0189] The above is described by taking the first transistor T1 to the ninth transistor T9 included in the pixel driving circuit of FIG. 3 as an example. When the pixel driving circuit provided in FIG. 3 includes a tenth transistor T10, the tenth transistor T10 is turned on in the first stage and is turned off in the second stage to the fourth stage. The tenth transistor T10 is turned on, and the signal of the bias signal line BIAS is written to the second node N2 or the third node N3.

[0190] As shown in FIG. 4 and FIG. 13, the working process of the pixel driving circuit provided in FIG. 4 can include:

[0191] The first stage P11 is called the initialization stage, the signals of the first reset signal line Reset1 and the fourth reset signal line Reset4 are low-level signals, and the signals of the first emission signal line EM1, the scan signal line Gate, the second reset signal line Reset2, the third reset signal line Reset3, and the fifth reset signal line Reset5 are high-level signals. The first transistor T1 and the eighth transistor T8 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned off.

[0192] The first transistor T1 is turned on, the initial signal of the first initial signal line INIT1 is written to the third node N3, the third node N3 is initialized (reset), the pre-stored voltage in the third node N3 is emptied, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage in the fifth node N5 is emptied, and the initialization is completed.

[0193] In this stage, the voltage value V of the signal of the third node N3 N3 satisfies V N3 = Vinit1, the voltage value V of the signal of the fifth node N5 N5Vinit1 N5 = Vdd, Vinit1 is a voltage value of a signal of the first initial signal line INIT1, and Vdd is a voltage value of a signal of the first power supply line VDD.

[0194] In the exemplary embodiment, when the first transistor T1, the second transistor T2, and the eighth transistor T8 are N-type transistors, the signal of the first reset signal line Reset1 is a high-level signal in the first stage, the signal of the second reset signal line Reset2 is a high-level signal in the second stage, and the signal of the fourth reset signal line Reset4 is a high-level signal in the first stage, the second stage, and the third stage.

[0195] In the exemplary embodiment, FIG. 14 is a timing chart of the operation of the pixel driving circuit provided in FIGS. 5 and 6. As shown in FIGS. 5 and 14, the operation of the pixel driving circuit provided in FIG. 5 can include:

[0196] In the first stage P21, referred to as an initialization stage, the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4, and the fifth reset signal line Reset5 are low-level signals, and the signals of the first emission signal line EM1 and the scan signal line Gate are high-level signals. The first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0197] The first transistor T1 and the second transistor T2 are turned on, and the initial signal of the first initial signal line INIT1 is written to the first node N1 and the third node N3, so that the first node N1 and the third node N3 are initialized (reset) and the pre-stored voltage in the first node N1 and the third node N3 is emptied, and the initialization is completed. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written to the fourth node N4, so that the first electrode of the light emitting device is initialized (reset) and the pre-stored voltage in the first electrode is emptied, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power supply line VDD is written to the fifth node N5, so that the fifth node N5 is initialized (reset) and the pre-stored voltage in the fifth node N5 is emptied, and the initialization is completed. The ninth transistor T9 is turned on, and the signal of the reference signal line REF is written to the second node N2, so that the second node N2 is initialized (reset) and the pre-stored voltage in the second node N2 is emptied, and the initialization is completed.

[0198] In this stage, the voltage value V N1 Vinit1 N1 = Vinit1, the voltage value V N2 Vinit1 N2 = Vref, the voltage value VN3 V N3 = Vinitl, the voltage value V of the signal of the fourth node N4 N4 V N4 = Vinit2, the voltage value V of the signal of the fifth node N5 N5 V N5 = Vdd, Vinitl is the voltage value of the signal of the first initial signal line INIT1, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, Vref is the voltage value of the signal of the reference signal line REF, and Vdd is the voltage value of the signal of the first power supply line VDD.

[0199] In the second phase P22, referred to as the threshold compensation phase, the signals of the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low-level signals, and the signals of the first emission signal line EM1, the first reset signal line Resetl and the scanning signal line Gate are high-level signals. The second transistor T2, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, and the first transistor Tl, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0200] The second transistor T2 and the ninth transistor T9 are turned on, the signal of the reference signal line REF is written to the second node N2, and the first node Nl is charged through the turned-on ninth transistor T9, the turned-on third transistor T3 and the turned-on second transistor T2 until the voltage value V of the signal of the first node Nl N1 V N1 = Vref + Vth, where Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4, the first electrode of the light emitting device is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed. The eighth transistor T8 is turned on, the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed.

[0201] In this phase, the voltage value V of the signal of the first node Nl N1 V N1 = Vref + Vth, the voltage value V of the signal of the second node N2 N2 V N2 = Vref, the voltage value V of the signal of the fourth node N4 N4 V N4 = Vinit2, the voltage value V of the signal of the fifth node N5 N5 V N5=Vdd, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, the charge stored in the first capacitor C1 is Vdd-Vref, and the charge stored in the second capacitor C2 is Vdd-Vref-Vth.

[0202] The third stage, P23, is called the data writing stage. The signals on the scan signal line Gate and the fourth reset signal line Reset4 are low-level signals, while the signals on the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fifth reset signal line Reset5, and the first light-emitting signal line EM1 are high-level signals. The fourth transistor T4 and the eighth transistor T8 are turned on, while the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned off.

[0203] When the fourth transistor T4 is turned on, the data voltage of the data signal line Data is written to the second node N2. When the eighth transistor T8 is turned on, the signal of the first power line VDD is written to the fifth node N5. The fifth node N5 is initialized (reset), and its internal pre-stored voltage is cleared, thus completing the initialization.

[0204] During this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node... N1 Satisfy V N1 =Vref + Vth, the voltage value V of the signal at the second node N2. N2 Satisfy V N2 =Vdata, the voltage value V of the signal at the third node N3. N3 Satisfy V N3 =Vref + Vth, the voltage value V of the signal at the fourth node N4. N4 Satisfy V N4 =Vinit2, the voltage value V of the signal at the fifth node N5. N5 Satisfy V N5 =Vdd, Vdata is the data voltage of the data signal line Data, the charge stored in the first capacitor C1 is Vdd-Vref, and the charge stored in the second capacitor C2 is Vdd-Vref-Vth.

[0205] The fourth stage, P24, is called the light-emitting stage. The light-emitting signal line EM is at a low level, while the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4, the fifth reset signal line Reset5, and the scan signal line Gate are at a high level. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0206] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T6, driving the light-emitting device L to emit light.

[0207] During this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node... N1 Satisfy V N1 =Vref + Vth, the voltage value V of the signal at the second node N2. N2 Satisfy V N2 =Vdata, the voltage value V of the signal at the fourth node N4. N4 Satisfy V N4 =Voled + Vss, where Voled is the voltage difference applied across the light-emitting device L, and Vss is the voltage value of the signal on the second power line VSS.

[0208] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. This is because the voltage value V of the signal at the first node N1... N1 Satisfy V N1 =Vref+Vth, the voltage value of the signal at the second node N2 satisfies V N2 =Vdata, therefore the drive current of the third transistor T3 is: I = K*(Vgs - Vth) 2 =K*(Vref+Vth-Vdata-Vth) 2 =K*(Vref-Vdata) 2

[0209] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3.

[0210] The above is described by taking the first transistor T1 to the ninth transistor T9 included in FIG. 5 as an example. When the pixel driving circuit provided in FIG. 5 includes a tenth transistor T10, the tenth transistor T10 is turned on in the first stage and is turned off in the second stage to the fourth stage. The tenth transistor T10 is turned on, and the signal of the bias signal line BIAS is written into the second node N2 or the third node N3.

[0211] The pixel driving circuit provided in FIG. 6 is different from the pixel driving circuit provided in FIG. 5 only in the position of the first transistor T1. The first transistor T1 is turned on only in the first stage. Therefore, the working process of the pixel driving circuit provided in FIG. 6 is the same as that of the pixel driving circuit provided in FIG. 5, and the disclosure will not be described here.

[0212] In the exemplary embodiment, when the first transistor T1, the second transistor T2, and the eighth transistor T8 are N-type transistors, the signal of the first reset signal line Reset1 is a high-level signal in the first stage, the signal of the second reset signal line Reset2 is a high-level signal in the first stage and the second stage, and the signal of the third reset signal line Reset3 is a high-level signal in the first stage, the second stage, and the third stage.

[0213] In the exemplary embodiment, FIG. 15 is a working timing diagram of the pixel driving circuit provided in FIG. 7 and FIG. 8. As shown in FIG. 7 and FIG. 15, the working process of the pixel driving circuit provided in FIG. 7 can include:

[0214] The first stage P31 is called an initialization stage. The signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset4, the fourth reset signal line Reset4, and the fifth reset signal line Reset5 are low-level signals, and the signals of the first emission signal line EM1 and the scan signal line Gate are high-level signals. The first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0215] The first transistor T1 and the second transistor T2 are turned on, the initial signal of the first initial signal line INIT1 is written to the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized (reset), the pre-stored voltage in the first node N1 and the third node N3 is emptied, and the initialization is completed. The seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4, the first electrode of the light emitting device is initialized (reset), the pre-stored voltage in the first electrode of the light emitting device is emptied, and the initialization is completed. The eighth transistor T8 is turned on, the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage in the fifth node N5 is emptied, and the initialization is completed. The ninth transistor T9 is turned on, the signal of the reference signal line REF is written to the second node N2, the second node N2 is initialized (reset), the pre-stored voltage in the second node N2 is emptied, and the initialization is completed.

[0216] In this stage, the voltage value V N1 satisfies V N1 = Vinit1, the voltage value V N2 satisfies V N2 = Vref, the voltage value V N3 satisfies V N3 = Vinit1, the voltage value V N4 satisfies V N4 = Vinit2, the voltage value V N5 satisfies V N5 = Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, Vref is the voltage value of the signal of the reference signal line REF, and Vdd is the voltage value of the signal of the first power supply line VDD.

[0217] The second stage P32, referred to as the threshold compensation stage, the signals of the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low level signals, and the signals of the first emission signal line EM1, the first reset signal line Reset1 and the scanning signal line Gate are high level signals. The second transistor T2, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0218] The second transistor T2 and the ninth transistor T9 are turned on, the signal of the reference signal line REF is written to the second node N2, and the first node N1 is charged through the turned-on ninth transistor T9, the turned-on third transistor T3 and the turned-on second transistor T2 until the voltage value V N1 satisfies V N1 = Vref + Vth, where Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4, the first electrode of the light emitting device is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed. The eighth transistor T8 is turned on, the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed.

[0219] At this stage, the voltage value V N1 satisfies V N1 = Vref + Vth, the voltage value V N2 satisfies V N2 = Vref, the voltage value V N4 satisfies V N4 = Vinit2, the voltage value V N5 satisfies V N5 = Vdd, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, the charge amount stored by the first capacitor C1 is Vdd-Vref, and the charge amount stored by the second capacitor C2 is Vdd-Vref-Vth.

[0220] The third stage P33, referred to as a data writing stage, the signals of the scanning signal line Gate, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low signals, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3 and the first light emitting signal line EM1 are high signals. The fourth transistor T4, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the ninth transistor T9 are turned off.

[0221] The fourth transistor T4 is turned on, the data voltage of the data signal line Data is written to the second node N2, the eighth transistor T8 is turned on, the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage in the fifth node N5 is emptied, and the initialization is completed. The seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4, the first electrode of the light emitting device is initialized (reset), the pre-stored voltage in the first electrode of the light emitting device is emptied, and the initialization is completed.

[0222] The voltage value V N1 satisfies V N1 =Vref+Vth, the voltage value V N2 of the signal of the second node N2 satisfies V N2 =Vdata, the voltage value V N3 of the signal of the third node N3 satisfies V N3 =Vref+Vth, the voltage value V N4 of the signal of the fourth node N4 satisfies V N4 =Vinit2, and the voltage value V N5 of the signal of the fifth node N5 satisfies V N5 =Vdd, where Vdata is the data voltage of the data signal line Data, the charge amount stored by the first capacitor C1 is Vdd-Vref, and the charge amount stored by the second capacitor C2 is Vdd-Vref-Vth.

[0223] The fourth stage P34 is called a light emitting stage, the signal of the first light emitting signal line EM1 is a low level signal, the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4, the fifth reset signal line Reset5 and the scanning signal line Gate are high level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0224] The fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output by the first power supply end VDD is provided to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6 to drive the light emitting device L to emit light.

[0225] The voltage value V N1 of the signal of the first node satisfies V N1 =Vref+Vth, the voltage value V N2 of the signal of the second node N2 satisfies VN2 = Vdata, the voltage value V of the signal of the fourth node N4 N4 satisfies V N4 = Voled + Vss, Voled is the voltage difference applied on both sides of the light emitting device L, and Vss is the voltage value of the signal of the second power line VSS.

[0226] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage value V of the signal of the first node N1 N1 satisfies V N1 = Vref + Vth, the voltage value of the signal of the second node N2 satisfies V N2 = Vdata, thus the driving current of the third transistor T3 is: I = K * (Vgs - Vth) 2 = K * (Vref + Vth - Vdata - Vth) 2 = K * (Vref - Vdata) 2

[0227] wherein I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3.

[0228] The above is described by taking the first transistor T1 to the ninth transistor T9 included in FIG. 7 as an example. When the pixel driving circuit provided in FIG. 7 includes a tenth transistor T10, the tenth transistor T10 is turned on in the first stage and is turned off in the second stage to the fourth stage. When the tenth transistor T10 is turned on, the signal of the bias signal line BIAS is written into the second node N2 or the third node N3.

[0229] The pixel driving circuit provided in FIG. 8 is different from the pixel driving circuit provided in FIG. 7 only in the position of the first transistor T1. The first transistor T1 is turned on only in the first stage. Therefore, the working process of the pixel driving circuit provided in FIG. 8 is the same as that of the pixel driving circuit provided in FIG. 7, and the disclosure will not be described here again.

[0230] In the exemplary embodiment, when the first transistor T1, the second transistor T2, and the eighth transistor T8 are N-type transistors, the signal of the first reset signal line Reset1 is a high-level signal in the first stage, the signal of the second reset signal line Reset2 is a high-level signal in the first stage and the second stage, and the signal of the third reset signal line Reset3 is a high-level signal in the first stage, the second stage, and the third stage.

[0231] In an exemplary embodiment, FIG. 16 is a timing diagram of the operation of the pixel driving circuit provided in FIGS. 9 and 10. As shown in FIGS. 9 and 16, the operation of the pixel driving circuit provided in FIG. 9 can include:

[0232] In the first stage P41, referred to as the initialization stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, and the first emission signal line EM1 are low signals, and the signals of the second emission signal line EM2, the scan signal line Gate, and the fifth reset signal line Reset5 are high signals. The first transistor T1, the second transistor T2, the fifth transistor T5, and the eighth transistor T8 are turned on, and the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0233] The first transistor T1 and the second transistor T2 are turned on, the initial signal of the first initial signal line INIT1 is written to the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized (reset), the pre-stored voltage in the first node N1 and the third node N3 is emptied, and the initialization is completed. The fifth transistor T5 is turned on, the signal of the first power supply line VDD is written to the second node N2, the second node N2 is initialized (reset), the pre-stored voltage in the second node N2 is emptied, and the initialization is completed. The eighth transistor T8 is turned on, the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage in the fifth node N5 is emptied, and the initialization is completed.

[0234] In this stage, the voltage value V N1 of the signal of the first node N1 satisfies V N1 = Vinit1, the voltage value V N2 of the signal of the second node N2 satisfies V N2 = Vdd, the voltage value V N3 of the signal of the third node N3 satisfies V N3 = Vinit1, the voltage value V N5 of the signal of the fifth node N5 satisfies V N5 = Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, and Vdd is the voltage value of the signal of the first power supply line VDD.

[0235] In the second stage P42, called threshold compensation stage, the signals of the first light-emitting signal line EM1, the fifth reset signal line Reset5, the third reset signal line Reset3 and the fourth reset signal line Reset4 are low signals, and the signals of the second light-emitting signal line EM2, the first reset signal line Reset1 and the scanning signal line Gate are high signals. The second transistor T2, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, and the first transistor T1, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0236] The second transistor T2 and the fifth transistor T5 are turned on, the signal of the first power supply line VDD is written to the second node N2, and the first node N1 is charged through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on second transistor T2 until the voltage value V N1 satisfies V N1 =Vdd+Vth, where Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4, the first electrode of the light-emitting device is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed. The eighth transistor T8 is turned on, the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed.

[0237] In this stage, the voltage value V N1 satisfies V N1 =Vdd+Vth, the voltage value V N2 satisfies V N2 =Vdd, the voltage value V N3 satisfies V N3 =Vdd+Vth, the voltage value V N4 satisfies V N4 =Vinit2, the voltage value V N5 satisfies V N5 =Vdd, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, the stored charge amount of the first capacitor C1 is 0, and the stored charge amount of the second capacitor C2 is Vth.

[0238] The third stage P43, called a data writing stage, the signals of the scan signal line Gate and the fourth reset signal line Reset4 are low signals, and the signals of the first reset signal line Reset1, the fifth reset signal line Reset5, the third reset signal line Reset3, the first emitting signal line EM1 and the second emitting signal line EM2 are high signals. The fourth transistor T4 and the eighth transistor T8 are turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0239] The fourth transistor T4 is turned on, the data voltage of the data signal line Data is written to the second node N2, the eighth transistor T8 is turned on, and the signal of the first power supply line VDD is written to the fifth node N5, so that the fifth node N5 is initialized (reset) and the internal pre-stored voltage is emptied, and the initialization is completed.

[0240] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V N1 satisfies V N1 =Vdd+Vth, the voltage value V N2 of the signal of the second node N2 satisfies V N2 =Vdata, the voltage value V N3 of the signal of the third node N3 satisfies V N3 =Vdd+Vth, the voltage value V N4 of the signal of the fourth node N4 satisfies V N4 =Vinit2, and the voltage value V N5 of the signal of the fifth node N5 satisfies V N5 =Vdd, Vdata is the data voltage of the data signal line Data, the first capacitor C1 stores 0, and the second capacitor C2 stores Vth.

[0241] The fourth stage P44, called an emitting stage, the signals of the first emitting signal line EM1 and the second emitting signal line EM2 are low signals, and the signals of the first reset signal line Reset1, the fifth reset signal line Reset5, the third reset signal line Reset3, the fourth reset signal line Reset4 and the scan signal line Gate are high signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0242] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply end VDD is provided to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6 to drive the light emitting device L to emit light.

[0243] In this phase, the voltage value V N1 satisfies V N1 =Vref+Vth, the voltage value V N2 of the signal of the second node N2 satisfies V N2 =Vdata, and the voltage value V N4 of the signal of the fourth node N4 satisfies V N4 =Voled+Vss, where Voled is the voltage difference applied to the light-emitting device L, and Vss is the voltage value of the signal of the second power line VSS.

[0244] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage value V N1 of the signal of the first node N1 satisfies V N1 =Vdd+Vth, and the voltage value of the signal of the second node N2 satisfies V N2 =Vdata, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*(Vdd+Vth-Vdata-Vth) 2 =K*(Vdd-Vdata) 2

[0245] where I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3.

[0246] The above is described by taking the pixel driving circuit provided in FIG. 9 including the first transistor T1 to the eighth transistor T8 as an example. When the pixel driving circuit provided in FIG. 8 includes the tenth transistor T10, the tenth transistor T10 is turned on in the first phase and is turned off in the second phase to the fourth phase. When the tenth transistor T10 is turned on, the signal of the bias signal line BIAS is written to the second node N2 or the third node N3.

[0247] The pixel driving circuit provided in FIG. 10 is different from the pixel driving circuit provided in FIG. 9 only in the position of the first transistor T1. The first transistor T1 is turned on only in the first phase. Therefore, the working process of the pixel driving circuit provided in FIG. 10 is the same as that of the pixel driving circuit provided in FIG. 9, and the disclosure will not be described here again.

[0248] For the pixel driving circuit provided in FIG. 11, the first emission signal line EM1 can be a low level signal in the second stage, the second emission signal line EM2 can be a low level signal in the first stage, the first node can be reset through the second initial signal line, the seventh transistor, the sixth transistor and the second transistor, and the signal of the first node can be compensated through the first power supply line, the fifth transistor, the third transistor and the second transistor.

[0249] In an exemplary embodiment, FIG. 17 is a timing diagram two of the working process of the pixel driving circuit provided in FIG. 9 and FIG. 10. As shown in FIG. 9 and FIG. 17, the working process of the pixel driving circuit provided in FIG. 9 can include:

[0250] In the first stage P51, referred to as the initialization stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the fifth reset signal line Reset5 and the first emission signal line EM1 are low level signals, and the signals of the second emission signal line EM2 and the scan signal line Gate are high level signals. The first transistor T1, the second transistor T2, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are turned on, and the fourth transistor T4 and the sixth transistor T6 are turned off.

[0251] The first transistor T1 and the second transistor T2 are turned on, the initial signal of the first initial signal line INIT1 is written to the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized (reset), the pre-stored voltage in the internal thereof is emptied, and the initialization is completed. The seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4, the first electrode of the light emitting device is initialized (reset), the pre-stored voltage in the internal thereof is emptied, and the initialization is completed. The fifth transistor T5 is turned on, the signal of the reference signal line REF is written to the second node N2, the second node N2 is initialized (reset), the pre-stored voltage in the internal thereof is emptied, and the initialization is completed. The eighth transistor T8 is turned on, the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage in the internal thereof is emptied, and the initialization is completed.

[0252] In this stage, the voltage value V N1 of the signal of the first node N1 satisfies V N1 = Vinit1, the voltage value V N2 of the signal of the second node N2 satisfies V N2 = Vdd, the voltage value V N3 of the signal of the third node N3 satisfies V N3 = Vinit1, the voltage value V N4 of the signal of the fourth node N4 satisfies V N4= Vinit2, the voltage value V of the signal of the fifth node N5 N5 satisfies V N5 = Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, and Vdd is the voltage value of the signal of the first power supply line VDD.

[0253] In the second phase P52, referred to as a threshold compensation phase, the signals of the first light-emitting signal line EM1, the third reset signal line Reset3, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low-level signals, and the signals of the second light-emitting signal line EM2, the first reset signal line Reset1 and the scanning signal line Gate are high-level signals. The second transistor T2, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first transistor T1, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0254] The second transistor T2 and the fifth transistor T5 are turned on, the signal of the first power supply line VDD is written to the second node N2, and the first node N1 is charged through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on second transistor T2 until the voltage value V of the signal of the first node N1 N1 satisfies V N1 = Vdd + Vth, where Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4, the first electrode of the light-emitting device is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed. The eighth transistor T8 is turned on, the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed.

[0255] In this phase, the voltage value V of the signal of the first node N1 N1 satisfies V N1 = Vdd + Vth, the voltage value V of the signal of the second node N2 N2 satisfies V N2 = Vdd, the voltage value V of the signal of the fourth node N4 N4 satisfies V N4 = Vinit2, the voltage value V of the signal of the fifth node N5 N5 satisfies V N5 = Vdd, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, the charge amount stored by the first capacitor C1 is 0, and the charge amount stored by the second capacitor C2 is Vth.

[0256] The third stage P53, called a data writing stage, has low signals of the scan signal line Gate and the fourth reset signal line Reset4, and high signals of the first reset signal line Reset1, the third reset signal line Reset3, the fifth reset signal line Reset5, the first emission signal line EM1 and the second emission signal line EM2. The fourth transistor T4 and the eighth transistor T8 are turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off.

[0257] The fourth transistor T4 is turned on, the data voltage of the data signal line Data is written to the second node N2, the eighth transistor T8 is turned on, and the signal of the first power supply line VDD is written to the fifth node N5, so that the fifth node N5 is initialized (reset) and the internal pre-stored voltage is emptied, and the initialization is completed.

[0258] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V N1 satisfies V N1 =Vdd+Vth, the voltage value V N2 of the signal of the second node N2 satisfies V N2 =Vdata, the voltage value V N3 of the signal of the third node N3 satisfies V N3 =Vdd+Vth, the voltage value V N4 of the signal of the fourth node N4 satisfies V N4 =Vinit2, and the voltage value V N5 of the signal of the fifth node N5 satisfies V N5 =Vdd, Vdata is the data voltage of the data signal line Data, the first capacitor C1 stores 0, and the second capacitor C2 stores Vth.

[0259] The fourth stage P54, called an emission stage, has a low signal of the emission signal line EM, and high signals of the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the fifth reset signal line Reset5 and the scan signal line Gate. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0260] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply end VDD is provided to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6 to drive the light emitting device L to emit light.

[0261] In this stage, the voltage value V N1 satisfies V N1 =Vref+Vth, the voltage value V N2 of the signal of the second node N2 satisfies V N2 =Vdata, and the voltage value V N4 of the signal of the fourth node N4 satisfies V N4 =Voled+Vss, where Voled is the voltage difference applied to the light emitting device L, and Vss is the voltage value of the signal of the second power line VSS.

[0262] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage value V N1 of the signal of the first node N1 satisfies V N1 =Vref+Vth, the voltage value of the signal of the second node N2 satisfies V N2 =Vdata, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*(Vref+Vth-Vdata-Vth) 2 =K*(Vref-Vdata) 2

[0263] where I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3.

[0264] For the pixel driving circuit provided in FIGS. 9 and 10, the first light emitting signal line EM1 can be a low-level signal in the second stage, the second light emitting signal line EM2 can be a low-level signal in the first stage, the first node can be reset through the second initial signal line, the seventh transistor, the sixth transistor, and the second transistor, and the signal of the first node can be compensated through the first power line, the fifth transistor, the third transistor, and the second transistor.

[0265] In an exemplary embodiment, FIG. 18 is a timing diagram three of the working process of the pixel driving circuit provided in FIGS. 9 and 10. As shown in FIGS. 9 and 18, the working process of the pixel driving circuit provided in FIG. 9 can include:

[0266] In the first stage P61, referred to as an initialization stage, the signals of the first light-emitting signal line EM1, the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, and the fifth reset signal line Reset5 are low signals, and the signals of the second light-emitting signal line EM2 and the scanning signal line Gate are high signals. The first transistor T1, the second transistor T2, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned on, and the fourth transistor T4 and the sixth transistor T6 are turned off.

[0267] The first transistor T1 and the second transistor T2 are turned on, the initial signal of the first initial signal line INIT1 is written to the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized (reset), the pre-stored voltage in the internal thereof is emptied, and the initialization is completed. The seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4, the first electrode of the light-emitting device is initialized (reset), the pre-stored voltage in the internal thereof is emptied, and the initialization is completed. The fifth transistor T5 is turned on, the signal of the first power supply line VDD is written to the second node N2, the second node N2 is initialized (reset), the pre-stored voltage in the internal thereof is emptied, and the initialization is completed. The eighth transistor T8 is turned on, the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage in the internal thereof is emptied, and the initialization is completed.

[0268] In this stage, the voltage value V N1 of the signal of the first node N1 satisfies V N1 = Vinit1, the voltage value V N2 of the signal of the second node N2 satisfies V N2 = Vdd, the voltage value V N3 of the signal of the third node N3 satisfies V N3 = Vinit1, the voltage value V N4 of the signal of the fourth node N4 satisfies V N4 = Vinit2, the voltage value V N5 of the signal of the fifth node N5 satisfies V N5 = Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, and Vdd is the voltage value of the signal of the first power supply line VDD.

[0269] The second stage, P62, is called the threshold compensation stage. The signals of the first light-emitting signal line EM1, the third reset signal line Reset3, the fourth reset signal line Reset4, and the fifth reset signal line Reset5 are low-level signals, while the signals of the second light-emitting signal line EM2, the first reset signal line Reset1, and the scan signal line Gate are high-level signals. The second transistor T2, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned on, while the first transistor T1, the fourth transistor T4, and the sixth transistor T6 are turned off.

[0270] The second transistor T2 and the fifth transistor T5 are turned on, and the signal of the reference signal line REF is written into the second node N2. The first node N1 is charged through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on second transistor T2 until the voltage value V of the signal at the first node N1 reaches a certain level. N1 Satisfy V N1 = Vdd + Vth, where Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written to the fourth node N4, initializing (resetting) the first electrode of the light-emitting device, clearing its internal pre-stored voltage, and completing the initialization. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written to the fifth node N5, initializing (resetting) the fifth node N5, clearing its internal pre-stored voltage, and completing the initialization.

[0271] In this phase, the voltage value V of the signal at the first node N1 N1 Satisfy V N1 =Vdd + Vth, where V is the voltage value of the signal at the second node N2. N2 Satisfy V N2 =Vdd, the voltage value V of the signal at the fourth node N4. N4 Satisfy V N4 =Vinit2, the voltage value V of the signal at the fifth node N5. N5 Satisfy V N5 =Vdd, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, the charge stored in the first capacitor C1 is 0, and the charge stored in the second capacitor C2 is Vth.

[0272] The third stage, P63, is called the data writing stage. The scan signal line Gate and the fourth reset signal line Reset4 are at low levels, while the first reset signal line Reset1, the fifth reset signal line Reset5, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are at high levels. The fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned on, while the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0273] The fourth transistor T4 is turned on, the data voltage of the data signal line Data is written to the second node N2, the eighth transistor T8 is turned on, the signal of the first power supply line VDD is written to the fifth node N5, the fifth node N5 is initialized (reset), and the pre-stored voltage in the fifth node N5 is emptied, and the initialization is completed. The seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4, the first electrode of the light emitting device is initialized (reset), the pre-stored voltage in the first electrode of the light emitting device is emptied, and the initialization is completed.

[0274] In this phase, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V N1 satisfies V N1 =Vref+Vth, the voltage value V N2 of the signal of the second node N2 satisfies V N2 =Vdata, the voltage value VN3 of the signal of the third node N3 satisfies V N3 =Vdd+Vth, the voltage value V N4 of the signal of the fourth node N4 satisfies V N4 =Vinit2, and the voltage value V N5 of the signal of the fifth node N5 satisfies V N5 =Vdd, where Vdata is the data voltage of the data signal line Data, the first capacitor C1 stores an electric charge of 0, and the second capacitor C2 stores an electric charge of Vth.

[0275] The fourth stage P64 is called the light emitting stage, the signals of the first emitting signal line EM1 and the second emitting signal line EM2 are low signals, and the signals of the first reset signal line Reset1, the fifth reset signal line Reset5, the fourth reset signal line Reset4, and the scanning signal line Gate are high signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0276] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply end VDD is provided to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6 to drive the light emitting device L to emit light.

[0277] In this phase, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V N1 of the signal of the first node satisfies V N1 =Vref+Vth, the voltage value V N2 of the signal of the second node N2 satisfies V N2 =Vdata, and the voltage value VN4 Vref+Vth N4 =Voled+Vss, Voled is the voltage difference applied on both sides of the light emitting device L, and Vss is the voltage value of the signal of the second power line VSS.

[0278] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage value V N1 Vref+Vth N1 =Vref+Vth, the voltage value of the signal of the second node N2 satisfies V N2 =Vdata, thus the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*(Vref+Vth-Vdata-Vth) 2 =K*(Vref-Vdata) 2

[0279] wherein I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3.

[0280] In the exemplary embodiments, the pixel driving circuit provided by FIGS. 3-8 includes the first transistor to the ninth transistor. The threshold compensation path: the reference signal line, the ninth transistor, the third transistor, and the second transistor compensate the first node, the data writing path includes the data signal line and the fourth transistor, and the data voltage of the data signal line is written into the pixel driving circuit. The pixel driving circuit provided by FIGS. 9-17, due to the fifth transistor and the sixth transistor being controlled by the first light emitting signal line and the second light emitting signal line respectively, so that the threshold compensation path: the first power line, the fifth transistor, the third transistor, and the second transistor compensate the first node, and the data writing path includes the data signal line and the fourth transistor, and the data voltage of the data signal line is written into the pixel driving circuit. Therefore, compared with the pixel driving circuit provided by FIGS. 3-8, the pixel driving circuit provided by FIGS. 9-11 occupies a smaller area, and is more conducive to realizing high PPI of the display device.

[0281] The pixel driving circuit provided by any one of the preceding embodiments is also provided. The driving method of the pixel driving circuit can include the following steps:

[0282] The driving sub-circuit provides a driving signal to the third node under the control of the signals of the first node and the second node.

[0283] The light emitting control sub-circuit outputs a driving signal under the control of a signal of at least one light emitting signal line.

[0284] The first control sub-circuit connects the first node and the third node under the control of at least one reset signal line.

[0285] The second control sub-circuit provides a signal of the first power supply line to the fifth node based on the fourth reset signal line.

[0286] The storage sub-circuit stores a voltage difference of a signal between the first node, the second node and the fifth node.

[0287] The display device provided by the embodiments of the present disclosure comprises the pixel driving circuit provided by any one of the embodiments.

[0288] In an example embodiment, FIG. 19 is a structural schematic diagram of a display device. As shown in FIG. 19, the display device further comprises a substrate and a plurality of first reset signal lines Reset1, a plurality of second reset signal lines Reset2, a plurality of third reset signal lines Reset3, a plurality of fourth reset signal lines Reset4, a plurality of scanning signal lines, a plurality of reference signal lines REF, a plurality of first initial signal lines INIT1, a plurality of second initial signal lines INIT2, a plurality of light emitting signal lines, a plurality of first power supply lines VDD and a plurality of data signal lines Data, which are arranged on the substrate.

[0289] In an example embodiment, at least one of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4, the light emitting signal line, the first initial signal line INIT1, the second initial signal line INIT2 and the reference signal line REF extends at least partially along the first direction D1.

[0290] In an example embodiment, at least one of the first power supply line VDD and the data signal line Data extends at least partially along the second direction D2, and the first direction D1 and the second direction D2 intersect. The included angle between the first direction D1 and the second direction D2 can be 70 degrees to 90 degrees. In an example, the included angle between the first direction D1 and the second direction D2 is 90 degrees.

[0291] In an exemplary embodiment, the normal projection of the first initial signal line INIT1 on the substrate, the normal projection of the first reset signal line Reset1 on the substrate, the normal projection of the third reset signal line Reset3 on the substrate, the normal projection of the scan signal line on the substrate, the normal projection of the light-emitting signal line on the substrate, the normal projection of the fourth reset signal line Reset4 on the substrate, the normal projection of the second reset signal line Reset2 on the substrate, the normal projection of the reference signal line REF on the substrate, and the normal projection of the second initial signal line INIT2 on the substrate are arranged in the second direction D2 in sequence.

[0292] In an exemplary embodiment, the display device further comprises a plurality of power supply connection lines VDL located in the third conductive layer, the power supply connection lines VDL extending at least partially in the first direction D1; at least one power supply connection line is electrically connected with at least one first power supply line VDD.

[0293] In an exemplary embodiment, the normal projection of the power supply connection line VDL on the substrate is located between the normal projection of the first light-emitting signal line EM11 on the substrate and the normal projection of the fourth reset signal line Reset4 on the substrate.

[0294] In an exemplary embodiment, the display device further comprises a driving circuit layer, the driving circuit layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, the pixel driving circuit comprising: at least one transistor and at least one capacitor, the transistor comprising: an active pattern, a control electrode, a first electrode, and a second electrode, the capacitor comprising: a first electrode plate and a second electrode plate;

[0295] The semiconductor layer comprises: the first initial signal line INIT1, the second initial signal line INIT2, and the active pattern of the at least one transistor of the at least one pixel driving circuit.

[0296] The first conductive layer comprises: the first light-emitting signal line EM1, and the control electrode of the at least one transistor of the at least one pixel driving circuit, and the second electrode plate of the at least one capacitor.

[0297] The second conductive layer comprises: the first electrode plate of the at least one capacitor of the at least one pixel driving circuit.

[0298] The third conductive layer can comprise: the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4, the scan signal line Gate, the reference signal line REF, the power supply connection line VDL, and the first electrode and the second electrode of the at least one transistor of the at least one pixel driving circuit.

[0299] The fourth conductive layer comprises: the data signal line Data and the first power supply line VDD.

[0300] In an exemplary embodiment, the display device further includes a shielding electrode SL on the second conductive layer, the shielding electrode SL being electrically connected to the first initial signal line INIT1.

[0301] In an exemplary embodiment, a projection of the shielding electrode SL on the substrate at least partially overlaps with projections of the first initial signal line INIT1, the first reset signal line Reset1, the third reset signal line Reset3, and the scan signal line on the substrate.

[0302] The preparation process of the display substrate is exemplarily described below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist, and the like for metal materials, inorganic materials, or transparent conductive materials, and includes coating organic materials, mask exposure, and development, and the like for organic materials. The deposition can adopt any one or more of sputtering, evaporation, and chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating, and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a material on a substrate prepared by deposition, coating, or other processes. If the "thin film" does not need to be patterned during the entire preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire preparation process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The "A and B are disposed in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the projection of B is located within the projection of A" or "the projection of A contains the projection of B" means that the boundary of the projection of B falls within the boundary of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B.

[0303] FIGS. 20 to 30 are schematic diagrams of a preparation process of a display substrate according to an exemplary embodiment. FIGS. 20 to 30 are described by taking one row of three-column pixel driving circuits as an example, and the pixel driving circuit is the pixel driving circuit provided in FIG. 2. The preparation process of the display substrate according to an exemplary embodiment can include:

[0304] In an exemplary embodiment, the at least one transistor includes an active pattern, a gate electrode, a first electrode, and a second electrode.

[0305] (1) forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern can include: depositing a first insulating thin film and a first semiconductor thin film on a substrate, patterning the first insulating thin film and the first semiconductor thin film by a patterning process, forming a first insulating layer pattern and a semiconductor layer pattern formed on the first insulating layer pattern, as shown in FIG. 20, which is a schematic diagram after forming a semiconductor layer pattern of FIG. 19.

[0306] In an exemplary embodiment, the semiconductor layer pattern can include: a first connection line L1, a second connection line L2, and an active pattern T11 of the first transistor to an active pattern T91 of the ninth transistor of the at least one pixel driving circuit.

[0307] In an exemplary embodiment, the active pattern T11 of the first transistor to the active pattern T81 of the eighth transistor are an integrated structure connected to each other. The active pattern T91 of the ninth transistor is separately provided.

[0308] In an exemplary embodiment, in the first direction D1, the active pattern T21 of the second transistor, the active pattern T61 of the sixth transistor, and the active pattern T71 of the seventh transistor can be located on the same side of the active pattern T31 of the third transistor T3, the active pattern T41 of the fourth transistor and the active pattern T51 of the fifth transistor can be located on the same side of the active pattern T31 of the third transistor T3, and the active pattern T21 of the second transistor and the active pattern T41 of the fourth transistor can be located on different sides of the active pattern T31 of the third transistor T3. In the second direction D2, the active pattern T11 of the first transistor, the active pattern T21 of the second transistor, and the active pattern T41 of the fourth transistor in the Mth row of sub-pixels can be located on the side of the active pattern T31 of the third transistor T3 close to the M-1th row of sub-pixels, and the active pattern T51 of the fifth transistor, the active pattern T61 of the sixth transistor, the active pattern T71 of the seventh transistor, the active pattern T81 of the eighth transistor, and the active pattern T91 of the ninth transistor in the Mth row of sub-pixels can be located on the side of the active pattern T31 of the third transistor T3 close to the M+1th row of sub-pixels. The active pattern T91 of the ninth transistor is located between the active pattern T71 of the seventh transistor and the active pattern T81 of the eighth transistor.

[0309] In the exemplary embodiment, the shape of the active pattern T11 of the first transistor, the shape of the active pattern T41 of the fourth transistor, the shape of the active pattern T51 of the fifth transistor, the shape of the active pattern T61 of the sixth transistor, the shape of the active pattern T71 of the seventh transistor, and the shape of the active pattern T91 of the ninth transistor can be an "I" letter shape, the shape of the active pattern T21 of the second transistor can be an "n" letter shape, the shape of the active pattern T31 of the third transistor can be an upside-down "Ω" letter shape, and the shape of the active pattern T81 of the eighth transistor can be an "L" letter shape.

[0310] In the exemplary embodiment, the active pattern of each transistor can include a first region, a second region, and a channel region between the first region and the second region. In the exemplary embodiment, the second region T11-2 of the active pattern T11 of the first transistor can serve as the first region T21-1 of the active pattern T21 of the second transistor, the first region T31-1 of the active pattern T31 of the third transistor can simultaneously serve as the second region T41-2 of the active pattern T41 of the fourth transistor and the second region T51-2 of the active pattern T51 of the fifth transistor, the second region T31-2 of the active pattern T31 of the third transistor can simultaneously serve as the second region T21-2 of the active pattern T21 of the second transistor and the first region T61-1 of the active pattern T61 of the sixth transistor, the first region T51-1 of the active pattern T51 of the fifth transistor can serve as the first region T81-1 of the active pattern T81 of the eighth transistor, the second region T61-2 of the active pattern T61 of the sixth transistor can serve as the second region T71-2 of the active pattern T71 of the seventh transistor, and the first region T41-1 of the active pattern T41 of the fourth transistor, the second region T81-2 of the active pattern T81 of the eighth transistor, the first region T91-1 of the active pattern T91 of the ninth transistor, and the second region T91-2 of the active pattern T91 of the ninth transistor can be separately provided.

[0311] In the exemplary embodiment, the first connection line L1 is located at a side of the active pattern T11 of the first transistor away from the active pattern T31 of the third transistor, the shape of the first connection line L1 can be a linear shape in which a main body portion extends in the first direction D1, and the first connection line L1 and the first region T11-1 of the active pattern T11 of the first transistor are in an integrated structure.

[0312] In the exemplary embodiment, the second connection line L2 is located at a side of the active pattern T71 of the seventh transistor away from the active pattern T31 of the third transistor, the shape of the second connection line L2 can be a linear shape in which a main body portion extends in the first direction D1, and the second connection line L2 and the first region T71-1 of the active pattern T71 of the seventh transistor are in an integrated structure.

[0313] (2) forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the second insulating thin film and the first conductive thin film by a patterning process, forming a second insulating layer pattern and a first conductive layer pattern on the second insulating layer, as shown in FIGS. 21 and 22, wherein FIG. 21 is a schematic view of the first conductive layer pattern in FIG. 19, and FIG. 22 is a schematic view of FIG. 19 after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0314] In an exemplary embodiment, the first conductive layer pattern can include: a first emission signal line EM1, and control electrodes T12 to T92 of the first to ninth transistors of the at least one pixel driving circuit, a second electrode plate C12 of the first capacitor, and a second electrode plate C22 of the second capacitor.

[0315] In an exemplary embodiment, the first emission signal line EM1 can have a linear shape in which a main body portion extends along the first direction D1. The first emission signal line EM1 and the active pattern of the fifth transistor overlap with each other to serve as a control electrode T52 of the fifth transistor. The first emission signal line EM1 and the active pattern of the sixth transistor overlap with each other to serve as a control electrode T62 of the sixth transistor.

[0316] In an exemplary embodiment, the second electrode plate C12 of the first capacitor can have a rectangular shape, and a corner portion of the rectangular shape can be chamfered. The second electrode plate C12 of the first capacitor of the Mth row pixel driving circuit is located on a side of the first emission signal line EM1 connected to the Mth row pixel driving circuit, which is close to the (M-1)th row pixel driving circuit.

[0317] In an exemplary embodiment, the second electrode plate C22 of the second capacitor can have a rectangular shape, and a corner portion of the rectangular shape can be chamfered. The second electrode plate C22 of the second capacitor of the Mth row pixel driving circuit is located on a side of the second electrode plate C12 of the first capacitor of the Mth row pixel driving circuit, which is close to the (M-1)th row pixel driving circuit.

[0318] In an exemplary embodiment, the control electrode T72 of the seventh transistor and the control electrode T92 of the ninth transistor can be an integrated structure connected to each other. The integrated structure of the control electrode T72 of the seventh transistor and the control electrode T92 of the ninth transistor extends along the first direction D1. The integrated structure of the control electrode T72 of the seventh transistor and the control electrode T92 of the ninth transistor of the Mth row pixel driving circuit is located on a side of the control electrode T82 of the eighth transistor in the Mth row pixel driving circuit, which is close to the (M+1)th row pixel driving circuit.

[0319] In the exemplary embodiment, the control electrode T82 of the eighth transistor is separately provided. The control electrode T82 of the eighth transistor extends along the second direction D2. The control electrode T82 of the eighth transistor of the Mth row of pixel driving circuit is located on the side of the first light emitting signal line EM1 connected with the Mth row of pixel driving circuit close to the M+1th row of pixel driving circuit.

[0320] In the exemplary embodiment, the control electrode T12 of the first transistor is arranged across the active pattern of the first transistor, the control electrode T22 of the second transistor is arranged across the active pattern of the second transistor, the control electrode T32 of the third transistor T3 is arranged across the active pattern of the third transistor T3, the control electrode T42 of the fourth transistor is arranged across the active pattern of the fourth transistor, the control electrode T52 of the fifth transistor is arranged across the active pattern of the fifth transistor, the control electrode T62 of the sixth transistor is arranged across the active pattern of the sixth transistor, the control electrode T72 of the seventh transistor is arranged across the active pattern of the seventh transistor, the control electrode T82 of the eighth transistor is arranged across the active pattern of the eighth transistor, and the control electrode T92 of the ninth transistor is arranged across the active pattern of the ninth transistor, that is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0321] In the exemplary embodiment, the present process further includes a conductorization process. The conductorization process is that after the formation of the first conductive layer pattern, the semiconductor layer in the region shielded by the control electrode of the plurality of transistors (i.e., the region where the semiconductor layer overlaps with the control electrode) is treated as the channel region of the transistor, and the semiconductor layer in the region not shielded by the first conductive layer is treated as a conductorized layer. The first connection line can be reused as the first initial signal line INIT1 and the first electrode T13 of the first transistor, the second connection line can be reused as the second initial signal line INIT2 and the first electrode T73 of the seventh transistor, the second region of the active pattern T31 of the third transistor T3 (also the second region of the active pattern of the second transistor and the first region of the active pattern of the sixth transistor) can be used as the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor T3 and the first electrode T63 of the sixth transistor)

[0322] In the exemplary embodiment, the first light emitting signal line EM1 can be a straight line or a broken line, which is not limited in the present disclosure.

[0323] (3) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: sequentially depositing a third insulating thin film and a second conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the third insulating thin film and the second conductive thin film by a patterning process, forming a third insulating layer pattern and a second conductive layer pattern on the third insulating layer, as shown in FIG. 23 and FIG. 24, FIG. 23 is a schematic diagram of the second conductive layer pattern in FIG. 19, and FIG. 24 is a schematic diagram of FIG. 19 after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0324] In an exemplary embodiment, the second conductive layer pattern at least includes: a shielding electrode SL, a first plate C11 of a first capacitor, and a first plate C21 of a second capacitor.

[0325] In an exemplary embodiment, the shielding electrode SL has an "L" shape, and a normal projection of the shielding electrode SL on the substrate at least partially overlaps with a normal projection of the first connection line and the active pattern of the second transistor on the substrate. The shielding electrode SL is configured to effectively shield the influence of data voltage jump on the key nodes in the pixel driving circuit, avoid the influence of data voltage jump on the potential of the key nodes in the pixel driving circuit, and improve the display effect.

[0326] In an exemplary embodiment, the first plate C11 of the first capacitor and the first plate C21 of the second capacitor are an integrated structure. The outline of the integrated structure of the first plate C11 of the first capacitor and the first plate C21 of the second capacitor can be a rectangular shape, and the corners of the rectangular shape can be chamfered. A normal projection of the integrated structure of the first plate C11 of the first capacitor and the first plate C21 of the second capacitor on the substrate at least partially overlaps with a normal projection of the second plate of the first capacitor and the second plate of the second capacitor (also the control electrode of the third transistor T3) on the substrate.

[0327] The integrated structure of the first plate C11 of the first capacitor and the first plate C21 of the second capacitor is provided with a first opening H1 and a second opening H2. The first opening H1 can be rectangular in shape and can be located in the middle of the integrated structure of the first plate C11 of the first capacitor and the first plate C21 of the second capacitor. The first opening H1 exposes the third insulating layer covering the second plate of the second capacitor (also the control electrode of the third transistor T3), and the normal projection of the second plate of the second capacitor (also the control electrode of the third transistor T3) on the substrate contains the normal projection of the first opening H1 on the substrate. The second opening H2 can be rectangular in shape and can be located in the middle of the integrated structure of the first plate C11 of the first capacitor and the first plate C21 of the second capacitor. The second opening H2 exposes the third insulating layer covering the second plate of the first capacitor, and the normal projection of the second plate of the first capacitor on the substrate contains the normal projection of the second opening H2 on the substrate.

[0328] (4) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth insulating thin film, patterning the fourth insulating thin film using a patterning process, forming the fourth insulating layer pattern covering the second conductive layer, the fourth insulating layer pattern being provided with a plurality of vias, as shown in FIG. 25. FIG. 25 is a schematic view after the fourth insulating layer pattern is formed in FIG. 19.

[0329] In an exemplary embodiment, the plurality of vias provided on the fourth insulating layer pattern at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, and an eighteenth via V18.

[0330] In an exemplary embodiment, the first via V1 has a normal projection on the substrate within a range of a normal projection on the substrate of the first initial signal line, the third insulating layer and the second insulating layer within the first via V1 are etched away, exposing a surface of the first initial signal line, and the first via V1 is configured to allow a subsequently formed connection electrode to connect with the first initial signal line through the via.

[0331] In an exemplary embodiment, the second via V2 has a normal projection on the substrate within a range of a normal projection on the substrate of a second region of the active pattern of the first transistor (also a first region of the active pattern of the second transistor), the third insulating layer and the second insulating layer within the second via V2 are etched away, exposing a surface of the second region of the active pattern of the first transistor (also the first region of the active pattern of the second transistor), and the second via V2 is configured to allow a second electrode of the first transistor (also a first electrode of the second transistor) to be subsequently formed to connect with the second region of the active pattern of the first transistor (also the first region of the active pattern of the second transistor) through the via.

[0332] In the example embodiment, the third via V3 is configured such that the first electrode of the third transistor T3 (also the second electrode of the fourth transistor, the second electrode of the fifth transistor, and the second electrode of the ninth transistor) is connected to the first region of the active pattern of the third transistor T3 (also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor) through the via.

[0333] In the example embodiment, the fourth via V4 is configured such that the first electrode of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through the via.

[0334] In the example embodiment, the fifth via V5 is configured such that the power connection line is connected to the first region of the active pattern of the fifth transistor (also the first region of the active pattern of the eighth transistor) through the via.

[0335] In the example embodiment, the sixth via V6 is configured such that the second electrode of the sixth transistor (also the second electrode of the seventh transistor) is connected to the second region of the active pattern of the sixth transistor (also the second region of the active pattern of the seventh transistor) through the via.

[0336] In an example embodiment, the seventh via V7 has a footprint on the substrate within a footprint of the second region of the active pattern of the eighth transistor on the substrate, the third insulating layer and the second insulating layer within the seventh via V7 are etched away to expose a surface of the second region of the active pattern of the eighth transistor, and the seventh via V7 is configured to connect the second pole of the subsequently formed eighth transistor to the second region of the active pattern of the eighth transistor through the via.

[0337] In an example embodiment, the eighth via V8 has a footprint on the substrate within a footprint of the first region of the active pattern of the ninth transistor on the substrate, the third insulating layer and the second insulating layer within the eighth via V8 are etched away to expose a surface of the first region of the active pattern of the ninth transistor, and the eighth via V8 is configured to connect the reference signal line to the first region of the active pattern of the ninth transistor through the via.

[0338] In an example embodiment, the ninth via V9 has a footprint on the substrate within a footprint of the second region of the active pattern of the ninth transistor on the substrate, the third insulating layer and the second insulating layer within the ninth via V9 are etched away to expose a surface of the second region of the active pattern of the ninth transistor, and the ninth via V9 is configured to connect the first pole of the subsequently formed third transistor T3 (also the second pole of the fourth transistor, the second pole of the fifth transistor, and the second pole of the ninth transistor) to the second region of the active pattern of the ninth transistor through the via.

[0339] In an example embodiment, the tenth via V10 has a footprint on the substrate within a footprint of the control pole of the first transistor on the substrate, the third insulating layer within the tenth via V10 is etched away to expose a surface of the control pole of the first transistor, and the tenth via V10 is configured to connect the first reset signal line to the control pole of the first transistor through the via.

[0340] In an example embodiment, the eleventh via V11 has a footprint on the substrate within a footprint of the control pole of the second transistor on the substrate, the third insulating layer within the eleventh via V11 is etched away to expose a surface of the control pole of the second transistor, and the eleventh via V11 is configured to connect the third reset signal line to the control pole of the second transistor through the via.

[0341] In an example embodiment, the twelfth via V12 has a footprint on the substrate within a footprint of the first opening on the substrate, the third insulating layer within the twelfth via V12 is etched away to expose a surface of the second plate of the second capacitor (also the control electrode of the third transistor T3), and the twelfth via V12 is configured to enable a second electrode of a first transistor (also a first electrode of the second transistor) formed subsequently to connect to the second plate of the second capacitor (also the control electrode of the third transistor T3) through the via.

[0342] In an example embodiment, the thirteenth via V13 has a footprint on the substrate within a footprint of the control electrode of the fourth transistor on the substrate, the third insulating layer within the thirteenth via V13 is etched away to expose a surface of the control electrode of the fourth transistor, and the thirteenth via V13 is configured to enable a scan signal line formed subsequently to connect to the control electrode of the fourth transistor through the via.

[0343] In an example embodiment, the fourteenth via V14 has a footprint on the substrate within a footprint of the control electrode of the seventh transistor (also a control electrode of the ninth transistor) on the substrate, the third insulating layer within the fourteenth via V14 is etched away to expose a surface of the control electrode of the seventh transistor (also a control electrode of the ninth transistor), and the fourteenth via V14 is configured to enable a second reset signal line formed subsequently to connect to the control electrode of the seventh transistor (also a control electrode of the ninth transistor) through the via.

[0344] In an example embodiment, the fifteenth via V15 has a footprint on the substrate within a footprint of the control electrode of the eighth transistor on the substrate, the third insulating layer within the fifteenth via V15 is etched away to expose a surface of the control electrode of the eighth transistor, and the fifteenth via V15 is configured to enable a fourth reset signal line formed subsequently to connect to the control electrode of the eighth transistor through the via.

[0345] In an example embodiment, the sixteenth via V16 has a footprint on the substrate within a footprint of the second opening on the substrate, the third insulating layer within the sixteenth via V16 is etched away to expose a surface of the second plate of the first capacitor, and the sixteenth via V16 is configured to enable a first electrode of the third transistor (also a second electrode of the fourth transistor, a second electrode of the fifth transistor, and a second electrode of the ninth transistor) formed subsequently to connect to the second plate of the first capacitor through the via.

[0346] In an exemplary embodiment, the normal projection of the seventeenth via V17 on the substrate is located within the range of the normal projection of the first plate of the first capacitor (also the first plate of the second capacitor) on the substrate, exposing the surface of the first plate of the first capacitor (also the first plate of the second capacitor), and the seventeenth via V17 is configured to connect the second electrode of the eighth transistor formed subsequently therethrough to the first plate of the first capacitor (also the first plate of the second capacitor).

[0347] In an exemplary embodiment, the normal projection of the eighteenth via V18 on the substrate is located within the range of the normal projection of the shielding electrode on the substrate, exposing the surface of the shielding electrode, and the eighteenth via V18 is configured to connect the connection electrode formed subsequently therethrough to the shielding electrode.

[0348] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a third conductive thin film, and patterning the third conductive thin film by using a patterning process, to form a third conductive layer pattern disposed on the fourth insulating layer, as shown in FIG. 26 and FIG. 27, FIG. 26 is a schematic diagram of the third conductive layer pattern in FIG. 19, and FIG. 27 is a schematic diagram of FIG. 19 after forming the third conductive layer pattern. In an exemplary embodiment, the third conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0349] In an exemplary embodiment, the third conductive layer pattern can at least include: a first reset signal line Reset1, a second reset signal line Reset2, a third reset signal line Reset3, a fourth reset signal line Reset4, a scan signal line Gate, a reference signal line REF, a power connection line VDL, and a connection electrode EL of at least one pixel driving circuit, a second electrode T14 of the first transistor, a first electrode T23 of the second transistor, a first electrode T33 of the third transistor T3, a first electrode T43 and a second electrode T44 of the fourth transistor, a first electrode T53 and a second electrode T54 of the fifth transistor, a second electrode T64 of the sixth transistor, a second electrode T74 of the seventh transistor, a first electrode T83 and a second electrode T84 of the eighth transistor, a first electrode T93 and a second electrode T94 of the ninth transistor.

[0350] In an exemplary embodiment, the first reset signal line Reset1, the third reset signal line Reset3, the scan signal line Gate, the power connection line VDL, the fourth reset signal line Reset4, the second reset signal line Reset2, and the reference signal line REF are arranged in the second direction D2 in sequence.

[0351] In an example embodiment, the orthogonal projection of the reference signal line REF on the substrate is located between the orthogonal projection of the second reset signal line Reset2 on the substrate and the orthogonal projection of the second initial signal line on the substrate.

[0352] In an example embodiment, the orthogonal projection of the first reset signal line Reset1 on the substrate is located between the orthogonal projection of the third reset signal line Reset3 on the substrate and the orthogonal projection of the first initial signal line on the substrate.

[0353] In an example embodiment, the orthogonal projection of the light emission signal line on the substrate is located between the orthogonal projection of the scan signal line on the substrate and the orthogonal projection of the power supply connection line VDL on the substrate.

[0354] In an example embodiment, the first reset signal line Reset1 can have a linear shape in which a main body portion extends along the first direction D1, and the first reset signal line Reset1 is connected to the control electrode of the first transistor through the tenth via hole.

[0355] In an example embodiment, the second reset signal line Reset2 can have a linear shape in which a main body portion extends along the first direction D1, and the second reset signal line Reset2 is connected to the control electrode of the seventh transistor (also the control electrode of the ninth transistor) through the fourteenth via hole.

[0356] In an example embodiment, the third reset signal line Reset3 can have a linear shape in which a main body portion extends along the first direction D1, and the third reset signal line Reset3 is connected to the control electrode of the second transistor through the eleventh via hole.

[0357] In an example embodiment, the fourth reset signal line Reset4 can have a linear shape in which a main body portion extends along the first direction D1, and the fourth reset signal line Reset4 is connected to the control electrode of the eighth transistor through the fifteenth via hole.

[0358] In an example embodiment, the scan signal line Gate can have a linear shape in which a main body portion extends along the first direction D1, and the scan signal line Gate is connected to the control electrode of the fourth transistor through the thirteenth via hole.

[0359] In an example embodiment, the power supply connection line VDL can have a linear shape in which a main body portion extends along the first direction D1, and the power supply connection line VDL is connected to the first area of the active pattern of the fifth transistor (also the first area of the active pattern of the eighth transistor) through the fifth via hole. The area in which the power supply connection line VDL overlaps the first area of the active pattern of the fifth transistor (also the first area of the active pattern of the eighth transistor) serves as the first electrode of the fifth transistor (also the first electrode of the eighth transistor)

[0360] In an example embodiment, the reference signal line REF can have a shape of a line shape in which a main body portion extends along the first direction D1, and the reference signal line REF is connected to the first region of the active pattern of the ninth transistor through the eighth via hole. The region in which the reference signal line REF overlaps the first region of the active pattern of the ninth transistor serves as the first electrode T93 of the ninth transistor.

[0361] In an example embodiment, the connection electrode EL is located on the side of the first reset signal line Reset1 away from the third reset signal line Reset3, the first electrode T43 of the fourth transistor is located between the first reset signal line Reset1 and the third reset signal line Reset3, the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T33 of the third transistor T3, the second electrode T44 of the fourth transistor, the second electrode T54 of the fifth transistor, the second electrode T64 of the sixth transistor, the second electrode T74 of the seventh transistor, the second electrode T84 of the eighth transistor, and the second electrode T94 of the ninth transistor are located between the scan signal line Gate and the power connection line VDL.

[0362] In an example embodiment, the second electrode T14 of the first transistor and the first electrode T23 of the second transistor are in an integrated structure. The shape of the integrated structure of the second electrode T14 of the first transistor and the first electrode T23 of the second transistor is a strip shape extending along the second direction D2. The second electrode T14 of the first transistor (also the first electrode T23 of the second transistor) is connected to the second region of the active pattern of the first transistor (also the first region of the active pattern of the second transistor) through the second via hole, and is connected to the second electrode plate of the second capacitor (also the control electrode of the third transistor T3) through the twelfth via hole.

[0363] In an example embodiment, the first electrode T43 of the fourth transistor is separately provided and has a shape of a strip shape extending along the first direction D1. The first electrode T43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through the fourth via hole.

[0364] In an exemplary embodiment, the first electrode T33 of the third transistor T3, the second electrode T44 of the fourth transistor, the second electrode T54 of the fifth transistor, and the second electrode T94 of the ninth transistor are in one structure. The one structure of the first electrode T33 of the third transistor T3, the second electrode T44 of the fourth transistor, the second electrode T54 of the fifth transistor, and the second electrode T94 of the ninth transistor is in the shape of a "┌" character. The first electrode T33 of the third transistor T3 (also the second electrode T44 of the fourth transistor, the second electrode T54 of the fifth transistor, and the second electrode T94 of the ninth transistor) is connected with the first area of the active pattern of the third transistor T3 (also the second area of the active pattern of the fourth transistor and the second area of the active pattern of the fifth transistor) through the third via, connected with the second area of the active pattern of the ninth transistor through the ninth via, and connected with the second plate of the first capacitor through the sixteenth via.

[0365] In an exemplary embodiment, the second electrode T64 of the sixth transistor and the second electrode T74 of the seventh transistor are in one structure. The one structure of the second electrode T64 of the sixth transistor and the second electrode T74 of the seventh transistor is in the shape of extending along the second direction D2. The second electrode T64 of the sixth transistor (also the second electrode T74 of the seventh transistor) is connected with the second area of the active pattern of the sixth transistor (also the second area of the active pattern of the seventh transistor) through the sixth via.

[0366] In an exemplary embodiment, the second electrode T84 of the eighth transistor is separately arranged. The shape of the second electrode T84 of the eighth transistor can be a strip extending along the second direction D2. The second electrode T84 of the eighth transistor is connected with the second area of the active pattern of the eighth transistor through the seventh via, and connected with the first plate of the first capacitor (also the first plate of the second capacitor) through the seventeenth via.

[0367] In an exemplary embodiment, the connection electrode EL is separately arranged. The shape of the connection electrode EL can be a strip extending along the first direction D1. The connection electrode EL is electrically connected with the first initial signal line through the first via, and electrically connected with the shielding electrode through the eighteenth via.

[0368] In an exemplary embodiment, the orthogonal projection of the shielding electrode on the substrate at least partially overlaps with the orthogonal projection of the first reset signal line Reset1, the third reset signal line Reset3, and the scan signal line Gate on the substrate.

[0369] In the example embodiment, the scan signal line Gate, the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4, the reference signal line REF, and the power connection line VDL can be designed with equal width or non-equal width, and can be a straight line or a broken line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0370] (6) Forming a first planar layer pattern. In the example embodiment, forming the first planar layer pattern can include: on the substrate on which the aforementioned pattern is formed, first depositing a fifth insulating thin film, then coating a first planar thin film, and patterning the first planar thin film and the fifth insulating thin film by using a patterning process to form a fifth insulating layer covering the third conductive layer pattern and a first planar layer disposed on the fifth insulating layer, the first planar layer being provided with a plurality of vias, as shown in FIG. 28, which is a schematic diagram after the first planar layer pattern is formed in FIG. 19.

[0371] In the example embodiment, the plurality of vias on the first planar layer pattern at least includes: a nineteenth via V19 to a twenty-first via V21.

[0372] In the example embodiment, the nineteenth via V19 has a projection on the substrate within the range of the first electrode of the fourth transistor, the fifth insulating layer in the nineteenth via V19 is etched away to expose the surface of the first electrode of the fourth transistor, and the nineteenth via V19 is configured to connect the subsequently formed data signal line to the first electrode of the fourth transistor.

[0373] In the example embodiment, the twentieth via V20 has a projection on the substrate within the range of the second electrode of the sixth transistor (also the second electrode of the seventh transistor), the fifth insulating layer in the twentieth via V20 is etched away to expose the surface of the second electrode of the sixth transistor (also the second electrode of the seventh transistor), and the twentieth via V20 is configured to connect the subsequently formed anode connection electrode to the second electrode of the sixth transistor (also the second electrode of the seventh transistor).

[0374] In the example embodiment, the twenty-first via V21 has a projection on the substrate within the range of the power connection line on the substrate, the fifth insulating layer in the twenty-first via V21 is etched away to expose the surface of the power connection line, and the twenty-first via V21 is configured to connect the subsequently formed first power line to the power connection line.

[0375] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern can include: on a substrate on which the aforementioned patterns are formed, depositing a fourth conductive thin film, patterning the fourth conductive thin film using a patterning process, and forming the fourth conductive layer pattern disposed on the fourth insulating layer, as shown in FIG. 29 and FIG. 30, FIG. 29 is a schematic diagram of the fourth conductive layer pattern in FIG. 19, and FIG. 30 is a schematic diagram of FIG. 19 after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0376] In an exemplary embodiment, the fourth conductive layer pattern includes at least: a data signal line Data, a first power supply line VDD, and an anode connection electrode AL located at at least one pixel driving circuit.

[0377] In an exemplary embodiment, the first power supply line VDD can have a shape of a line with a main body portion extending along the second direction D2. The first power supply line VDD is connected to the power supply connection line through the twenty-first via.

[0378] In an exemplary embodiment, the data signal line Data can have a shape of a line with a main body portion extending along the second direction D2. The data signal line Data is connected to the first electrode of the fourth transistor through the nineteenth via.

[0379] In an exemplary embodiment, the line width of the first power supply line VDD is greater than the line width of the data signal line Data.

[0380] In an exemplary embodiment, the anode connection electrode AL can have a shape of a strip with a main body portion extending along the second direction D2. The anode connection electrode AL is connected to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the twentieth via.

[0381] (8) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern can include: on a substrate on which the aforementioned patterns are formed, applying a second planar thin film, patterning the second planar thin film using a patterning process, and forming a second planar layer covering the fourth conductive layer pattern, the second planar layer being provided with a plurality of vias. The anode via on the second planar layer pattern has a range of orthographic projection on the substrate within the range of orthographic projection of the anode connection electrode on the substrate, the second planar layer in the anode via is removed, exposing the surface of the anode connection electrode, and the anode via is configured to allow the subsequently formed anode to be connected to the anode connection electrode through the via.

[0382] So far, the driving circuit layer is prepared on the substrate. In the plane parallel to the display substrate, the driving circuit layer can be connected with the first reset signal line, the second reset signal line, the third reset signal line, the fourth reset signal line, the light-emitting signal line, the first initial signal line, the second initial signal line, the reference signal line, the data signal line and the first power supply line as the pixel driving circuit. In the plane perpendicular to the display substrate, the driving circuit layer can be arranged on the substrate.

[0383] The driving circuit layer can include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first planar layer, a fourth conductive layer and a second planar layer arranged on the substrate in sequence. The semiconductor layer can include at least an active pattern of at least one transistor, the first initial signal line and the second initial signal line, the first conductive layer can include at least the gate electrode of the first transistor to the ninth transistor, the second plate of the first capacitor and the second plate of the third capacitor, and the light-emitting signal line, the second conductive layer can include at least the shielding electrode, the first plate of the first capacitor and the first plate of the second capacitor, the shielding electrode is electrically connected with the first initial signal line, the third conductive layer can include at least the first electrode and the second electrode of the plurality of transistors, the first reset signal line, the second reset signal line, the third reset signal line, the fourth reset signal line, the power supply connection line, the scanning signal line, the reference signal line, the power supply connection line is electrically connected with the first power supply. The fourth conductive layer can include at least the data signal line, the first power supply line and the anode connection electrode.

[0384] In the example embodiment, the semiconductor layer can be an amorphous silicon layer, a polycrystalline silicon layer or a metal oxide layer. Among them, the metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0385] In the example embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0386] In an exemplary embodiment, the first, second, third, fourth, and fifth insulating layers can employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer. The first insulating layer can be referred to as a buffer layer, the second and third insulating layers can be referred to as gate insulating (GI) layers, the fourth insulating layer can be referred to as an interlayer insulating (ILD) layer, and the fifth insulating layer can be referred to as a passivation (PVX) layer.

[0387] In an exemplary embodiment, the first and second planar layers can employ an organic material such as resin, etc.

[0388] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer, and the preparation of the light emitting structure layer can include the following operations.

[0389] The light emitting structure layer is formed. In an exemplary embodiment, forming the light emitting structure layer includes: depositing an anode conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive thin film through a patterning process to form an anode conductive layer pattern, depositing a pixel definition thin film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition thin film through a patterning process to form a pixel definition layer pattern that exposes the anode layer pattern, coating an organic light emitting material on the substrate on which the pixel definition layer pattern is formed, patterning the organic light emitting material through a patterning process to form an organic structure layer pattern, depositing a cathode conductive thin film on the substrate on which the organic material layer pattern is formed, and patterning the cathode conductive thin film through a patterning process to form a cathode conductive layer.

[0390] In an exemplary embodiment, the anode conductive layer pattern can include at least: anodes of a plurality of light emitting devices.

[0391] In an exemplary embodiment, the organic structure layer pattern can include at least: an organic light emitting layer of a light emitting device.

[0392] In an exemplary embodiment, the cathode conductive layer pattern can include at least: cathodes of a plurality of light emitting devices.

[0393] In an exemplary embodiment, the anode conductive layer can employ a transparent conductive material such as any one or more of indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO).

[0394] In an exemplary embodiment, the cathode conductive layer can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material with conductivity, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed by titanium, aluminum, and titanium.

[0395] In an exemplary embodiment, the display device can be any product or component with a display function, such as electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0396] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0397] For the sake of clarity, the thickness and size of a layer or microstructure are exaggerated in the drawings used to describe the embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0398] Although the embodiments disclosed in the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

A pixel driving circuit, comprising: The driving sub-circuit, the light-emitting control sub-circuit, the storage sub-circuit, the first control sub-circuit and the second control sub-circuit are connected to the first node, the second node and the third node. The driving sub-circuit is electrically connected to the first node, the second node and the third node, and is configured to provide a driving signal to the third node under the control of signals of the first node and the second node. The light-emitting control sub-circuit is electrically connected to at least one light-emitting signal line, and is configured to output a driving signal under the control of signals of the at least one light-emitting signal line. The first control sub-circuit is electrically connected to at least one reset signal line, the first node and the third node, and is configured to connect the first node and the third node under the control of signals of the at least one reset signal line. The second control sub-circuit is electrically connected to a fourth reset signal line, a first power supply line and a fifth node, and is configured to provide signals of the first power supply line to the fifth node under the control of signals of the fourth reset signal line. The storage sub-circuit is electrically connected to the first node, the second node and the fifth node, and is configured to store a voltage difference of signals between the first node, the second node and the fifth node. The pixel driving circuit according to claim 1, wherein The storage sub-circuit includes a first capacitor and a second capacitor. The first plate of the first capacitor is electrically connected to the fifth node, and the second plate of the first capacitor is electrically connected to the second node. The first plate of the second capacitor is electrically connected to the fifth node, and the second plate of the second capacitor is electrically connected to the first node. The pixel driving circuit according to claim 1, wherein The second control sub-circuit includes an eighth transistor. The control electrode of the eighth transistor is electrically connected to the fourth reset signal line, the first electrode of the eighth transistor is electrically connected to the first power supply line, and the second electrode of the eighth transistor is electrically connected to the fifth node. The pixel driving circuit according to claim 3, wherein The first control sub-circuit is also electrically connected to a reference signal line, the second node and a first initial signal line, and is configured to provide signals of the reference signal line to the second node, and provide signals of the first initial signal line to the first node or the third node under the control of signals of the at least one reset signal line. The pixel driving circuit according to claim 4, wherein The at least one reset signal line includes at least one of a first reset signal line, a second reset signal line and a third reset signal line. The first control sub-circuit includes a first transistor, a second transistor and a ninth transistor. The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to one of the first node and the third node. The control electrode of the second transistor is electrically connected to the third reset signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the ninth transistor is electrically connected to the second reset signal line, the first electrode of the ninth transistor is electrically connected to the reference signal line, and the second electrode of the ninth transistor is electrically connected to the second node. The pixel driving circuit according to claim 5, wherein The second reset signal line and the third reset signal line are different signal lines, or are the same signal line. The pixel driving circuit according to claim 6, further comprising: The third control sub-circuit is electrically connected to a fifth reset signal line, a second initial signal line and a fourth node, and is configured to provide signals of the second initial signal line to the fourth node under the control of signals of the fifth reset signal line. The third control sub-circuit includes a seventh transistor. ​ The control electrode of the seventh transistor is electrically connected with the fifth reset signal line, the first electrode of the seventh transistor is electrically connected with the second initial signal line, and the second electrode of the seventh transistor is electrically connected with the fourth node; The fifth reset signal line is the same signal line as one of the second reset signal line and the fourth reset signal line. The pixel driving circuit according to claim 4, further comprising: The write sub-circuit; The write sub-circuit is electrically connected with the scan signal line, the data signal line and the second node respectively, and is configured to provide the signal of the data signal line to the second node under the control of the signal of the scan signal line; The light-emitting control sub-circuit is further electrically connected with the first power supply line, the second node, the third node and the fifth node; The at least one light-emitting signal line includes the first light-emitting signal line, the drive sub-circuit includes the third transistor, the write sub-circuit includes the fourth transistor, and the light-emitting control sub-circuit includes the fifth transistor and the sixth transistor; The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node; The control electrode of the fourth transistor is electrically connected with the scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the second node; The control electrode of the sixth transistor is electrically connected with the first light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fourth node. The pixel driving circuit according to claim 3, wherein The at least one reset signal line includes at least one of the first reset signal line and the third reset signal line; The first control sub-circuit includes the first transistor and the second transistor; The control electrode of the first transistor is electrically connected with the first reset signal line, the first electrode of the first transistor is electrically connected with the first initial signal line, and the second electrode of the first transistor is electrically connected with one of the first node and the third node; The control electrode of the second transistor is electrically connected with the third reset signal line, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node. The pixel driving circuit according to claim 3, wherein The at least one reset signal line includes the third reset signal line; The first control sub-circuit includes the second transistor; The control electrode of the second transistor is electrically connected with the third reset signal line, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node. The pixel driving circuit according to claim 9 or 10, further comprising: The third control sub-circuit; The third control sub-circuit is electrically connected with the fifth reset signal line, the second initial signal line and the fourth node respectively, and is configured to provide the signal of the second initial signal line to the fourth node under the control of the signal of the fifth reset signal line; The fifth reset signal line is the same signal line as the fourth reset signal line, or is different from at least one of the first reset signal line, the third reset signal line and the fourth reset signal line. The pixel driving circuit according to claim 11, further comprising: The write sub-circuit; The write sub-circuit is electrically connected with the scan signal line, the data signal line and the second node, and is configured to provide the signal of the data signal line to the second node under the control of the signal of the scan signal line; The light emitting control sub-circuit is further electrically connected with the first power supply line, the second node, the third node and the fifth node; The at least one light emitting signal line includes a first light emitting signal line and a second light emitting signal line, the drive sub-circuit includes a third transistor, the write sub-circuit includes a fourth transistor, and the light emitting control sub-circuit includes a fifth transistor and a sixth transistor; The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node; The control electrode of the fourth transistor is electrically connected with the scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the first light emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the second node; The control electrode of the sixth transistor is electrically connected with the second light emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fourth node. The pixel driving circuit according to claim 1, further comprising: The write sub-circuit is electrically connected with the scan signal line, and includes a fourth transistor, and the first control sub-circuit includes a second transistor, which is electrically connected with the first node and the third node; The time period during which the signal of the scan signal line connected with the control electrode of the fourth transistor is an effective level signal does not overlap with the time period during which the signal of the reset signal line connected with the control electrode of the second transistor is an effective level signal. The pixel driving circuit according to claim 13, wherein The starting time of the time period during which the signal of the scan signal line connected with the control electrode of the fourth transistor is an effective level signal is later than the ending time of the time period during which the signal of the reset signal line connected with the control electrode of the second transistor is an effective level signal. The pixel driving circuit according to claim 1, further comprising: A biasing sub-circuit; The biasing sub-circuit is electrically connected with at least one of the second node and the third node, the first reset signal line and the biasing signal line, and is configured to provide the signal of the biasing signal line to the at least one of the second node and the third node under the control of the signal of the first reset signal line; The biasing sub-circuit includes a tenth transistor; The control electrode of the tenth transistor is electrically connected with the first reset signal line, the first electrode of the tenth transistor is electrically connected with the biasing signal line, and the second electrode of the tenth transistor is electrically connected with the at least one of the second node and the third node. A display device comprising: The pixel driving circuit according to any one of claims 1 to 15. The display device according to claim 16, further comprising: A substrate, and a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of third reset signal lines, a plurality of fourth reset signal lines, a plurality of scan signal lines, a plurality of reference signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of light emitting signal lines, a plurality of first power supply lines, a plurality of data signal lines and a plurality of power connection lines are arranged on the substrate, and at least one power connection line is electrically connected with at least one first power supply line. At least one of the first reset signal line, the second reset signal line, the third reset signal line, the fourth reset signal line, the light-emitting signal line, the first initial signal line, the second initial signal line, the reference signal line and the power connection line extends at least partially along a first direction, and at least one of the first power line and the data signal line extends at least partially along a second direction, the first direction and the second direction intersecting each other; The normal projection of the first initial signal line on the substrate, the normal projection of the first reset signal line on the substrate, the normal projection of the third reset signal line on the substrate, the normal projection of the scanning signal line on the substrate, the normal projection of the light-emitting signal line on the substrate, the normal projection of the fourth reset signal line on the substrate, the normal projection of the second reset signal line on the substrate, the normal projection of the reference signal line on the substrate and the normal projection of the second initial signal line on the substrate are sequentially arranged along the second direction, and the normal projection of the power connection line on the substrate is located between the normal projection of the light-emitting signal line on the substrate and the normal projection of the fourth reset signal line on the substrate. The display device according to claim 17, further comprising: The driving circuit layer comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, the pixel driving circuit comprises at least one transistor and at least one capacitor, the transistor comprises an active pattern, a control electrode, a first electrode and a second electrode, and the capacitor comprises a first electrode plate and a second electrode plate; The semiconductor layer comprises the first initial signal line, the second initial signal line and the active pattern of the at least one transistor of the at least one pixel driving circuit; The first conductive layer comprises the light-emitting signal line, the control electrode of the at least one transistor of the at least one pixel driving circuit and the second electrode plate of the at least one capacitor; The second conductive layer comprises the first electrode plate of the at least one capacitor of the at least one pixel driving circuit; The third conductive layer comprises the first reset signal line, the second reset signal line, the third reset signal line, the fourth reset signal line, the scanning signal line, the reference signal line, the power connection line and the first electrode and the second electrode of the at least one transistor of the at least one pixel driving circuit; The fourth conductive layer comprises the data signal line and the first power line. The display device according to claim 18, further comprising: A shielding electrode is located on the second conductive layer, and the shielding electrode is electrically connected with the first initial signal line; The normal projection of the shielding electrode on the substrate at least partially overlaps with the normal projections of the first initial signal line, the first reset signal line, the third reset signal line and the scanning signal line on the substrate. A driving method of a pixel driving circuit is configured to drive the pixel driving circuit as claimed in any one of claims 1 to 15, and the method comprises: The driving sub-circuit provides a driving signal to the third node under the control of the signals of the first node and the second node; The light-emitting control sub-circuit outputs a driving signal under the control of the signal of the at least one light-emitting signal line; The first control sub-circuit connects the first node and the third node under the control of the at least one reset signal line; The second control sub-circuit provides the signal of the first power line to the fifth node on the basis of the fourth reset signal line; The storage sub-circuit stores the voltage difference of the signals between the first node, the second node and the fifth node.

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