Die attach film, packaging assembly and semiconductor device

Abstract

Embodiments of the present application relate to the technical field of semiconductor packaging, and provide a die attach film, a packaging assembly, and a semiconductor device. The die attach film comprises a thermally conductive structure layer. The thermally conductive structure layer comprises a first surface and a second surface, wherein the first surface and the second surface are respectively located on two sides of the thermally conductive structure layer in the thickness direction, the first surface has a plurality of nanoscale first pores, and the second surface has a plurality of nanoscale second pores. The first surface is used for bonding with a first device, and the second surface is used for bonding with a second device. The first device is one of a die and a matching device, and the second device is the other of the die and the matching device. Thus, improvement of the thermal conductivity between a die and a matching device that are connected by means of the die attach film is facilitated.

Description

Chip adhesive film, packaging assembly and semiconductor device

[0001] The present application claims priority to the Chinese patent application No. 202410834347.X filed on June 25, 2024, and entitled "Chip adhesive film, packaging assembly and semiconductor device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the technical field of semiconductor packaging, and in particular, to a chip adhesive film, a packaging assembly and a semiconductor device. BACKGROUND

[0003] In a semiconductor device, it is often necessary to mount a chip on other cooperating devices such as chips or packaging substrates, and a chip adhesive film (DAF) is a film material used to connect the chip and the cooperating device, which has the advantages of simple connection process, uniform thickness, etc.

[0004] In the related art, the chip adhesive film includes a glue layer made of a resin material, and the chip is bonded to the cooperating device through the glue layer. However, in the related art, the heat conduction performance between the chip and the cooperating device bonded by the glue layer is poor.

[0005] Therefore, how to improve the heat conduction performance between the chip and the cooperating device connected by the chip adhesive film has become a problem to be solved in the technical field of semiconductor devices. SUMMARY

[0006] Embodiments of the present application provide a chip adhesive film, a packaging assembly, a semiconductor device, a chip mounting method, and a manufacturing method of a chip adhesive film, which are beneficial to improve the heat conduction performance between the chip and the cooperating device connected by the chip adhesive film.

[0007] The first aspect of the embodiments of the present application provides a chip adhesive film, which includes a heat-conducting structure layer. The heat-conducting structure layer includes a first surface and a second surface, and the first surface and the second surface are respectively located on both sides of the thickness direction of the heat-conducting structure layer. The first surface has a plurality of first nanoscale pores, and the second surface has a plurality of second nanoscale pores. The first surface is used to combine with a first device, and the second surface is used to combine with a second device. The first device is one of the chip and the cooperating device, and the second device is the other of the chip and the cooperating device.

[0008] The chip bonding film provided by the embodiments of the present application can make the first surface have a larger surface energy through the plurality of nanoscale first pores, so that the first surface can be combined with the first device more easily under a certain pressure. The second surface can have a larger surface energy through the plurality of nanoscale second pores, so that the second surface can be combined with the second device more easily under a certain pressure. The connection between the chip and the cooperating device can not need to use a glue layer made of resin material or the like for bonding. The heat-conducting structure layer is made of a material with good heat-conducting performance. The heat-conducting structure layer made of the material with good heat-conducting performance is beneficial to improving the heat-conducting performance between the chip and the cooperating device connected through the chip bonding film. In addition, the heat-conducting structure layer is combined with the chip and the cooperating device after being formed. The forming process of the heat-conducting structure layer will not affect the chip and the cooperating device, so that the application of the heat-conducting structure layer has less restrictions. For example, the heat-conducting structure layer can be applied in a tube shell scene or a semiconductor bonding scene in which a III-V compound material is used as a substrate.

[0009] In some possible implementation manners of the chip bonding film provided in the first aspect, the heat-conducting structure layer is a metal structure layer.

[0010] In some possible implementation manners of the chip bonding film provided in the first aspect, the heat-conducting structure layer is a structure layer formed of a nanoporous metal.

[0011] In some possible implementation manners of the chip bonding film provided in the first aspect, at least one of the first pores and the second pores is filled with adhesive.

[0012] In some possible implementation manners of the chip bonding film provided in the first aspect, the decomposition point of the adhesive is greater than or equal to 50 DEG C and less than or equal to 300 DEG C.

[0013] In some possible implementation manners of the chip bonding film provided in the first aspect, the chip bonding film further includes a first substrate layer, the first substrate layer is bonded to the first surface, and the first substrate layer is used to be peeled off from the first surface under a first preset condition.

[0014] In some possible implementation manners of the chip bonding film provided in the first aspect, the chip bonding film further includes a second substrate layer, the second substrate layer is bonded to the second surface, and the second substrate layer is used to be peeled off from the second surface under a second preset condition.

[0015] In some possible implementation manners of the chip bonding film provided in the first aspect, the adhesive strength of the second substrate layer to the second surface under the first preset condition is greater than the adhesive strength of the first substrate layer to the first surface under the first preset condition.

[0016] In a second aspect, the embodiments provide a packaging assembly, which includes a first device, a second device, and a die attach film. The die attach film includes a thermally conductive structure layer, which includes a first surface and a second surface located at two sides of a thickness direction of the thermally conductive structure layer, respectively. The first surface has a plurality of first nano-sized apertures, and the second surface has a plurality of second nano-sized apertures. The first surface of the die attach film is combined with the first device, and the second surface of the die attach film is combined with the second device. The first device is one of a chip and a mating device, and the second device is the other of the chip and the mating device.

[0017] In some possible implementation of the packaging assembly provided in the second aspect, the thermally conductive structure layer is a metal structure layer.

[0018] In some possible implementation of the packaging assembly provided in the second aspect, the thermally conductive structure layer is a nano-porous metal formed structure layer.

[0019] In some possible implementation of the packaging assembly provided in the second aspect, at least one of the first apertures and the second apertures is filled with an adhesive.

[0020] In a third aspect, the embodiments provide a semiconductor device, which includes a first device, a second device, and a die attach film. The die attach film includes a thermally conductive structure layer, which includes a first surface and a second surface located at two sides of a thickness direction of the thermally conductive structure layer, respectively. The first surface has a plurality of first nano-sized apertures, and the second surface has a plurality of second nano-sized apertures. The first surface of the die attach film is combined with the first device, and the second surface of the die attach film is combined with the second device. The first device is one of a chip and a mating device, and the second device is the other of the chip and the mating device.

[0021] In some possible implementation of the semiconductor device provided in the third aspect, the thermally conductive structure layer is a metal structure layer.

[0022] In some possible implementation of the semiconductor device provided in the third aspect, the thermally conductive structure layer is a nano-porous metal formed structure layer.

[0023] In some possible implementation of the semiconductor device provided in the third aspect, at least one of the first apertures and the second apertures is filled with an adhesive.

[0024] The fourth aspect of the embodiments of the present application provides a chip mounting method. The chip is mounted on a matching device by using a chip adhesive film. The chip adhesive film comprises a heat-conducting structure layer. The heat-conducting structure layer comprises a first surface and a second surface. The first surface and the second surface are respectively located on two sides in the thickness direction of the heat-conducting structure layer. The first surface comprises a plurality of first nano-sized pores. The second surface comprises a plurality of second nano-sized pores.

[0025] The chip mounting method comprises the following steps: pressing the chip adhesive film and a first device stacked on the first surface, so that the first surface is combined with the first device. Pressing the chip adhesive film and a second device stacked on the second surface, so that the second surface is combined with the second device. The first device is one of the chip and the matching device. The second device is the other one of the chip and the matching device.

[0026] In some possible implementation manners of the chip mounting method provided in the fourth aspect, the step of pressing the chip adhesive film and the first device stacked on the first surface, so that the first surface is combined with the first device, comprises the following steps: pressing the chip adhesive film and a wafer stacked on the first surface, so that the first surface is combined with the wafer. The wafer is cut and the heat-conducting structure layer are cut on the surface of the second substrate layer, so that the first device and the heat-conducting structure layer sub-region are formed on the surface of the second substrate layer. The wafer comprises the chip. The first device is the chip. The chip adhesive film further comprises a second substrate layer. The second substrate layer is bonded to the second surface. The second substrate layer is used to be peeled off from the second surface under a second preset condition. The heat-conducting structure layer comprises the heat-conducting structure layer sub-region. The first surface comprises a first surface sub-region located in the heat-conducting structure layer sub-region. The first surface sub-region comprises a plurality of first pores. The second surface comprises a second surface sub-region located in the heat-conducting structure layer sub-region. The second surface sub-region comprises a plurality of second pores.

[0027] After the wafer and the heat-conducting structure layer are cut on the surface of the second substrate layer, so that the first device and the heat-conducting structure layer sub-region are formed on the surface of the second substrate layer, the chip mounting method further comprises the following step: peeling off the second substrate layer from the second surface.

[0028] The step of pressing the chip adhesive film and the second device stacked on the second surface, so that the second surface is combined with the second device, comprises the following step: after the second substrate layer is peeled off from the second surface, pressing the heat-conducting structure layer sub-region and the second device stacked on the second surface sub-region, so that the second surface sub-region is combined with the second device. The second device is the matching device.

[0029] In some possible implementation manners of the chip mounting method provided in the fourth aspect, the chip mounting method further comprises the following step: stacking the second device on the second surface, so that the second device is bonded to the second surface by using an adhesive, and the second device is pre-fixed to the second surface. The second pores are filled with the adhesive.

[0030] The pressing of the die-bonding film and the second device stacked on the second surface to bond the second surface with the second device includes, after the second device is pre-fixed to the second surface, pressing the heat-conducting structure layer and the second device to bond the second surface with the second device.

[0031] In some possible implementation manners of the chip mounting method provided in the fourth aspect, the pressing of the die-bonding film and the first device stacked on the first surface to bond the first surface with the first device includes, after the second device is pre-fixed to the second surface, pressing the heat-conducting structure layer and the first device stacked on the first surface to bond the first surface with the first device.

[0032] The pressing of the heat-conducting structure layer and the second device to bond the second surface with the second device after the second device is pre-fixed to the second surface includes, when the heat-conducting structure layer and the first device stacked on the first surface are pressed, pressing the heat-conducting structure layer and the second device to bond the second surface with the second device by the pressure applied to the heat-conducting structure layer by the first device.

[0033] The fifth aspect of the embodiments of the present application provides a manufacturing method of a die-bonding film, which includes: bonding a first substrate layer to a first surface of an alloy foil. A nano-porous metal is formed in the alloy foil by a dealloying process, so that the first surface has a plurality of first nano-sized pores and the second surface has a plurality of second nano-sized pores, to form a heat-conducting structure layer through the nano-porous metal. The alloy foil includes the first surface and the second surface, which are located on two sides in the thickness direction of the alloy foil, respectively, and the first substrate layer is used to be peeled off from the first surface under a first preset condition.

[0034] In some possible implementation manners of the manufacturing method of the die-bonding film provided in the fifth aspect, the manufacturing method further includes: filling an adhesive in at least one of the first pores and the second pores through the pore structure of the nano-porous metal.

[0035] In some possible implementation manners of the manufacturing method of the die-bonding film provided in the fifth aspect, the decomposition point of the adhesive is greater than or equal to 50°C and less than or equal to 300°C.

[0036] In some possible implementation manners of the manufacturing method of the die-bonding film provided in the fifth aspect, a second substrate layer is bonded to the second surface, and the second substrate layer is used to be peeled off from the second surface under a second preset condition.

[0037] In some possible implementation manners of the manufacturing method of the die-bonding film provided in the fifth aspect, the bonding strength of the second substrate layer to the second surface under the first preset condition is greater than the bonding strength of the first substrate layer to the first surface under the first preset condition. BRIEF DESCRIPTION OF DRAWINGS

[0038] Fig. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present application;

[0039] Fig. 2 is a schematic diagram of a chip adhesive film according to an embodiment of the present application;

[0040] Fig. 3 is a schematic diagram of another chip adhesive film according to an embodiment of the present application;

[0041] Fig. 4 is a schematic diagram of still another chip adhesive film according to an embodiment of the present application;

[0042] Fig. 5 is a process flow diagram of a method of manufacturing a chip adhesive film according to an embodiment of the present application;

[0043] Fig. 6 is a forming process diagram of a chip adhesive film according to an embodiment of the present application;

[0044] Fig. 7 is a process flow diagram of another method of manufacturing a chip adhesive film according to an embodiment of the present application;

[0045] Fig. 8 is a forming process diagram of another chip adhesive film according to an embodiment of the present application;

[0046] Fig. 9 is a process flow diagram of still another method of manufacturing a chip adhesive film according to an embodiment of the present application;

[0047] Fig. 10 is a forming process diagram of still another chip adhesive film according to an embodiment of the present application;

[0048] Fig. 11 is a process flow diagram of yet another method of manufacturing a chip adhesive film according to an embodiment of the present application;

[0049] Fig. 12 is a forming process diagram of yet another chip adhesive film according to an embodiment of the present application;

[0050] Fig. 13 is a process flow diagram of a chip mounting method according to an embodiment of the present application;

[0051] Fig. 14 is a process flow diagram of another chip mounting method according to an embodiment of the present application;

[0052] Fig. 15 is a mounting process diagram of a chip mounting method according to an embodiment of the present application;

[0053] Fig. 16 is a mounting process diagram of another chip mounting method according to an embodiment of the present application;

[0054] Fig. 17 is a process flow diagram of still another chip mounting method according to an embodiment of the present application;

[0055] Fig. 18 is a process flow diagram of yet another chip mounting method according to an embodiment of the present application;

[0056] FIG. 19 is a diagram of a mounting process of another chip mounting method according to an embodiment of the present application.

[0057] Reference signs: 10, circuit board; 20, packaging assembly; 21, mating device; 22, chip; 23, chip adhesive film; 30, wafer; 40, alloy sheet; 50, alloy foil; 60, calender; 100, thermally conductive structure layer; 110, first surface; 111, first aperture; 120, second surface; 121, second aperture; 130, sub-region of thermally conductive structure layer; 131, sub-region of first surface; 132, sub-region of second surface; 200, first substrate layer; 300, second substrate layer; 400, adhesive. DETAILED DESCRIPTION

[0058] The terms used in the embodiments of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0059] The embodiments of the present application provide a semiconductor device, which can include but is not limited to a device having a semiconductor device, such as a server, a switch, a router, a base station device, a mobile phone, a tablet computer, a notebook computer, an ultra-mobile personal computer (UMPC), a handheld computer, a walkie-talkie, a netbook, a point of sales (POS) machine, a personal digital assistant (PDA), a wearable device, a virtual reality device, a vehicle, etc.

[0060] FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present application.

[0061] As shown in FIG. 1, in the embodiments of the present application, the semiconductor device includes a chip 22 and a mating device 21, and the chip 22 can be connected to the mating device 21 through a chip adhesive film 23.

[0062] For example, the mating device 21 can include but is not limited to another chip, a packaging substrate, etc.

[0063] For example, the semiconductor device further includes a circuit board 10, and the mating device 21 can be disposed on the circuit board 10, and the chip 22 can be connected to the circuit board 10 through the mating device 21.

[0064] For example, the circuit board 10 can include but is not limited to a mainboard, a service board, etc.

[0065] In some examples, the semiconductor device includes a package assembly 20 including a chip 22 and a mating device 21, the package assembly 20 is disposed on the circuit board 10, the chip 22 of the package assembly 20 can be connected with the circuit board 10 through the mating device 21 of the package assembly 20.

[0066] For example, the package assembly 20 can include, but is not limited to, a chip on carrier (COC) package assembly, a chip on board (COB) package assembly, a chip on substrate (COS) package assembly, and the like.

[0067] When the semiconductor device includes the package assembly 20, the chip 22 and the mating device 21 can be the chip 22 and the mating device 21 in the package assembly 20, or can not be the chip 22 and the mating device 21 in the package assembly 20.

[0068] In the related art, the chip bonding film includes a glue layer made of a resin material or the like, and the chip is bonded to the mating device through the glue layer. Since the glue layer made of the resin material or the like has poor thermal conductivity, the thermal conductivity between the chip and the mating device connected through the chip bonding film is poor in the related art.

[0069] FIG. 2 is a schematic diagram of a chip bonding film according to an embodiment of the present application.

[0070] As shown in FIG. 2, and referring to FIG. 1, based on this, the present application provides a chip bonding film 23, the chip bonding film 23 includes a thermal conductive structure layer 100, the thermal conductive structure layer 100 is a structure layer made of a material with good thermal conductivity. The thermal conductive structure layer 100 includes a first surface 110 and a second surface 120, the first surface 110 and the second surface 120 are respectively located on both sides in the thickness direction of the thermal conductive structure layer 100, the first surface 110 has a plurality of first nano-sized pores 111, and the second surface 120 has a plurality of second nano-sized pores 121. The first surface 110 is used to combine with a first device, and the second surface 120 is used to combine with a second device. Wherein, the first device is one of the chip 22 and the mating device 21, and the second device is the other one of the chip 22 and the mating device 21.

[0071] In this way, the plurality of nanoscale first apertures 111 can make the first surface 110 have a large surface energy, so that the first surface 110 can be more easily combined with the first device under a certain pressure, the plurality of nanoscale second apertures 121 can make the second surface 120 have a large surface energy, so that the second surface 120 can be more easily combined with the second device under a certain pressure, the connection between the chip 22 and the cooperating device 21 can not need to use a glue layer made of resin material or the like for bonding, the heat conduction structure layer 100 is made of a material with good heat conduction performance, and the heat conduction structure layer 100 made of a material with good heat conduction performance is conducive to improving the heat conduction performance between the chip 22 and the cooperating device 21 connected by the chip bonding film 23. In addition, the heat conduction structure layer 100 is combined with the chip 22 and the cooperating device 21 after forming, and the forming process of the heat conduction structure layer 100 will not affect the chip 22 and the cooperating device 21, so that the application of the heat conduction structure layer 100 is less limited, for example, it can be applied to a tube shell scene, a semiconductor bonding scene of a III-V compound material as a substrate.

[0072] For example, the heat conduction structure layer 110 can be made of a high-temperature resistant material, and the heat conduction structure layer 110 can withstand the high-temperature process after the chip 22 is connected with the cooperating device 21, so that the chip 22 and the cooperating device 21 can be subjected to high-temperature treatment after being connected, thereby reducing the limitation on the process after the chip 22 and the cooperating device 21 are connected.

[0073] For example, the chip bonding film 23 can be applied in a chip on carrier (COC) packaging assembly, a chip on board (COB) packaging assembly, a chip on substrate (COS) packaging assembly, and the like.

[0074] For example, the chip bonding film 23 can be applied in a laser, a laser display, a semiconductor optical amplifier (SOA), and the like.

[0075] For example, the chip bonding film 23 can be applied in a high-heat-conduction-demand connection scene such as a connection between a substrate and a shell, a semiconductor refrigerator patch, and the like.

[0076] When the chip bonding film 23 is applied in a semiconductor device, the first device is combined with the first surface 110, and the second device is combined with the second surface 120, so that the first device and the second device are connected through the heat conduction structure layer 100.

[0077] In the process of applying the chip adhesive film 23 to the packaging assembly 20, the first device of the packaging assembly 20 is combined with the first surface 110, and the second device of the packaging assembly 20 is combined with the second surface 120, so that the first device of the packaging assembly 20 and the second device of the packaging assembly 20 are connected through the heat-conducting structure layer 100.

[0078] For example, the first aperture 111 can be in communication with one or more second apertures 121, and the second aperture 121 can be in communication with one or more first apertures 111.

[0079] For example, the heat-conducting structure layer 100 further comprises a third surface (not shown) connecting the first surface 110 and the second surface 120, and the third surface can have a plurality of nanoscale third apertures (not shown) in communication with one or more first apertures 111 and one or more second apertures 121.

[0080] For example, the heat-conducting structure layer 100 is made of an electrically conductive material. In this way, the chip 22 and the cooperating device 21 can be electrically connected through the heat-conducting structure layer 100.

[0081] In order to make the heat-conducting structure layer 100 more easily combined with the chip 22 and the cooperating device 21, the heat-conducting structure layer 100 is a structure layer having a metal element.

[0082] In some possible embodiments, the heat-conducting structure layer 100 can be a metal structure layer.

[0083] In this way, the heat-conducting structure layer 100 can have high strength, so that the connection strength of the chip 22 and the cooperating device 21 connected through the heat-conducting structure layer 100 is high, and the connection is stable. In addition, the metal structure layer has good heat-conducting performance, so that the heat-conducting performance of the chip 22 and the cooperating device 21 connected through the heat-conducting structure layer 100 is good. In addition, the metal structure layer has good electrical conductivity, so that the chip 22 and the cooperating device 21 can be well electrically connected. Furthermore, the metal structure layer has good high-temperature resistance, so that the chip 22 and the cooperating device 21 can be subjected to high-temperature treatment after being connected, and the process after the chip 22 and the cooperating device 21 are connected is less limited. In addition, the heat-conducting structure layer 100 is less likely to overflow when combined with the chip 22 and the cooperating device 21, and is less likely to affect the chip 22 and the cooperating device 21.

[0084] When the heat-conducting structure layer 100 is a metal structure layer, the surface of the chip 22 has a first metal region, the surface of the cooperating device 21 has a second metal region, the first surface 110 is used to combine with the first metal region, and the second surface 120 is used to combine with the second metal region. In this way, the heat-conducting structure layer 100 can be combined with the chip 22 and the cooperating device 21 more easily. In addition, it is also convenient to realize high-heat-conducting and high-conducting connection between the chip 22 and the cooperating device 21.

[0085] For example, the heat-conducting structure layer 100 can be made of one or more metals such as gold, silver, copper, etc.

[0086] In some possible embodiments, the heat-conducting structure layer 100 can be a structure layer formed of a nano-porous metal. The nano-porous metal is a metal material with a nano-porous structure, and the nano-porous metal has a high specific surface area.

[0087] In this way, it is easier to form the first nano-porous 111 and the second nano-porous 121 on the first surface 110 and the second surface 120. In addition, it is easier to form a large number of and relatively dense first nano-porous 111 and second nano-porous 121, so that the first surface 110 and the second surface 120 have a high surface energy, which is conducive to the combination with the chip 22 and the cooperating device 21.

[0088] In other possible embodiments, the heat-conducting structure can be a metal compound structure layer.

[0089] In some possible embodiments, the chip bonding film 23 can further include a first substrate layer 200, and the first substrate layer 200 is bonded to the first surface 110. The first substrate layer 200 is used to be peeled off from the first surface 110 under a first preset condition.

[0090] In this way, the first substrate layer 200 can serve as a carrier of the heat-conducting structure layer 100, and can enhance the strength of the chip bonding film 23. The requirement for the strength of the heat-conducting structure layer 100 during storage and movement of the chip bonding film 23 can be reduced, thereby facilitating the reduction of the thickness of the heat-conducting structure layer 100. After the thickness of the heat-conducting structure layer 100 is reduced, the heat-conducting and conducting performance between the chip 22 and the cooperating device 21 connected through the heat-conducting structure layer 100 can be further improved.

[0091] For example, when the heat-conducting structure layer 100 is a structure layer formed of a nano-porous metal, the first substrate layer 200 bonded to the first surface 110 can prevent the heat-conducting structure layer 100 from being broken during the alloy removal process.

[0092] In the chip adhesive film 23 including the first substrate layer 200, before the first surface 110 is combined with the first device, the first substrate layer 200 needs to be peeled off from the first surface 110 to expose the first surface 110, so that the first surface 110 can be combined with the first device.

[0093] The chip adhesive film 23 combined with the chip 22 and the mating device 21 does not include the first substrate layer 200.

[0094] In some examples, the first substrate layer 200 can be a first light release film layer, and the first substrate layer 200 is configured to be peeled off from the first surface 110 under first preset light, that is, the first substrate layer 200 has a small adhesive strength under the first preset light, so that the first substrate layer 200 can be peeled off from the first surface 110. For example, the first substrate layer 200 can be configured to be peeled off from the first surface 110 under first ultraviolet rays (UV) treatment.

[0095] In other examples, the first substrate layer 200 can be a first heat release film layer, and the first substrate layer 200 is configured to be peeled off from the first surface 110 under a first preset temperature, that is, the first substrate layer 200 has a small adhesive strength under the first preset temperature, so that the first substrate layer 200 can be peeled off from the first surface 110.

[0096] For example, the first preset temperature can be room temperature.

[0097] For example, the first preset temperature can also be higher than room temperature, for example, the first preset temperature can be 50°C, 55°C, 60°C, 70°C, etc. After the chip adhesive film 23 is heated to the first preset temperature, the first substrate layer 200 can be peeled off from the first surface 110.

[0098] For example, the first substrate layer 200 can be made of one or more of polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), etc.

[0099] FIG. 3 is a schematic diagram of another chip adhesive film according to an embodiment of the present application.

[0100] As shown in FIG. 3, in some possible implementations, at least one of the first aperture 111 and the second aperture 121 is filled with adhesive 400.

[0101] In this way, the adhesive 400 in the first aperture 111 can pre-fix the first surface 110 and the first device before the first surface 110 is combined with the first device, so that the first device and the heat-conducting structure layer 100 are not easily displaced when force is applied to the first device and the heat-conducting structure layer 100, and the first device can be more easily combined with the first surface 110. The adhesive 400 in the second aperture 121 can pre-fix the second surface 120 and the second device before the second surface 120 is combined with the second device, so that the second device and the heat-conducting structure layer 100 are not easily displaced when force is applied to the second device and the heat-conducting structure layer 100, and the second device can be more easily combined with the second surface 120.

[0102] When the heat-conducting structure layer 100 is a structure layer formed of a nano-porous metal, the adhesive 400 can be filled into the aperture structure of the nano-porous metal to fill the adhesive 400 into at least one of the first aperture 111 and the second aperture 121.

[0103] In some possible embodiments, the decomposition point of the adhesive 400 is greater than or equal to 50°C and less than or equal to 300°C.

[0104] In this way, the adhesive 400 can achieve adhesive properties during pre-fixing, and the adhesive 400 can be decomposed and volatilized in a process after the chip 22 is connected to the cooperating device 21, so that the heat-conducting, electrically-conducting, and high-temperature-resistant properties of the heat-conducting structure layer 100 are not reduced due to the filled adhesive 400, and the chip 22 and the cooperating device 21 are not affected by the overflow of the adhesive 400 in the final product.

[0105] The decomposition point refers to a critical temperature at which a substance is chemically changed and decomposed into other substances. The substance can be decomposed when the temperature is greater than or equal to the decomposition point, and the substance cannot be decomposed when the temperature is less than the decomposition point. For example, the substance can be decomposed from a large molecule into a small molecule when the temperature is greater than or equal to the decomposition point. For another example, the substance can be decomposed from a long molecular chain into a short molecular chain when the temperature is greater than or equal to the decomposition point.

[0106] The adhesive 400 can be decomposed into other substances and volatilized when the temperature is greater than or equal to the decomposition point.

[0107] The adhesive 400 can be selected according to the heating temperature of a heating process after pre-fixing by the adhesive 400, so that the adhesive 400 can be decomposed and volatilized by the subsequent heating process.

[0108] For example, the decomposition point of the adhesive 400 can include, but is not limited to, 60°C, 70°C, 80°C, 90°C, 100°C, 110°C, 120°C, 130°C, 140°C, 150°C, and the like.

[0109] When the first substrate layer 200 is bonded to the first surface 110 and the first substrate layer 200 is used to be peeled off from the first surface 110 at a first preset temperature, the first preset temperature can be lower than the decomposition point of the adhesive 400, so that after the first substrate layer 200 is peeled off from the first surface 110, the first surface 110 is pre-fixed to the first device through the adhesive 400.

[0110] In some other examples, the first aperture 111 and the second aperture 121 can also not be filled with the adhesive 400.

[0111] FIG. 4 is a schematic diagram of another chip bonding film provided by an embodiment of the present application.

[0112] As shown in FIG. 4, in some possible implementations, the chip bonding film 23 further includes a second substrate layer 300, the second substrate layer 300 is bonded to the second surface 120, and the second substrate layer 300 is used to be peeled off from the second surface 120 under a second preset condition.

[0113] In this way, the second substrate layer 300 can play a role of protecting the second surface 120.

[0114] In the chip bonding film 23 including the second substrate layer 300, before the second surface 120 is combined with the second device, the second substrate layer 300 needs to be peeled off from the second surface 120 to expose the second surface 120, so that the second surface 120 can be combined with the second device.

[0115] The chip bonding film 23 combined with the chip 22 and the cooperating device 21 does not include the second substrate layer 300.

[0116] In some examples, the second substrate layer 300 can be a second photo-release film layer, and the second substrate layer 300 is used to be peeled off from the second surface 120 under a second preset light, that is, the bonding strength of the second substrate layer 300 under the second preset light is small, so that the second substrate layer 300 can be peeled off from the second surface 120. For example, the second substrate layer 300 can be used to be peeled off from the second surface 120 under a second ultraviolet light treatment.

[0117] In some other examples, the second substrate layer 300 can be a second thermal-release film layer, and the second substrate layer 300 is used to be peeled off from the second surface 120 under a second preset temperature, that is, the bonding strength of the second substrate layer 300 under the second preset temperature is small, so that the second substrate layer 300 can be peeled off from the second surface 120.

[0118] When the second substrate layer 300 is bonded to the second surface 120 and the second substrate layer 300 is used to be peeled off from the second surface 120 at a second preset temperature, the second preset temperature can be lower than the decomposition point of the adhesive 400, so that after the second substrate layer 300 is peeled off from the second surface 120, the second surface 120 is pre-fixed to the second device through the adhesive 400.

[0119] For example, the second substrate layer 300 can be made of one or more of polyvinyl chloride (PVC), polyolefins (PO), polyimide (PI), and the like.

[0120] In some possible embodiments, the bonding strength of the second substrate layer 300 to the second surface 120 under the first preset condition is greater than the bonding strength of the first substrate layer 200 to the first surface 110 under the first preset condition. In this way, the second substrate layer 300 can be kept bonded to the second surface 120 when the first substrate layer 200 is peeled off from the first surface 110.

[0121] For example, the first substrate layer 200 is used to be peeled off from the first surface 110 at a first preset temperature, the second substrate layer 300 is used to be peeled off from the second surface 120 at a second preset temperature, the second preset temperature is higher than the first preset temperature, and the bonding strength of the second substrate layer 300 to the second surface 120 under the first preset temperature is greater than the bonding strength of the first substrate layer 200 to the first surface 110 under the first preset temperature. At this time, under the first preset temperature, the first substrate layer 200 can be peeled off from the first surface 110, and the second substrate layer 300 cannot be peeled off from the second surface 120.

[0122] For example, the first substrate layer 200 is used to be peeled off from the first surface 110 under a first preset light, the second substrate layer 300 is used to be peeled off from the second surface 120 under a second preset light, and the bonding strength of the second substrate layer 300 to the second surface 120 under the first preset light is greater than the bonding strength of the first substrate layer 200 to the first surface 110 under the first preset light. At this time, under the first preset light, the first substrate layer 200 can be peeled off from the first surface 110, and the second substrate layer 300 cannot be peeled off from the second surface 120.

[0123] For example, the first device is a chip 22, and the second device is a matching device 21, that is, the first surface 110 is used to be combined with the chip 22, and the second surface 120 is used to be combined with the matching device 21.

[0124] In this way, after the first substrate layer 200 is peeled from the first surface 110, the first surface 110 can be combined with the wafer 30 used to cut to form the chip 22 (as shown in FIG. 15 below), and when the wafer 30 is cut to form the chip 22, the thermally conductive structure layer 100 combined on the surface of the wafer 30 can be cut, and the size of the thermally conductive structure layer 100 combined on the surface of the chip 22 can be matched with the size of the chip 22, and the thermally conductive structure layer 100 is easier to combine with the smaller chip 22, and the second substrate layer 300 can support the wafer 30 and the thermally conductive structure layer 100 when the wafer 30 and the thermally conductive structure layer 100 are cut, so as to facilitate the cutting of the wafer 30 and the thermally conductive structure layer 100, and after the wafer 30 and the thermally conductive structure layer 100 are cut, the second substrate layer 300 is peeled from the second surface 120.

[0125] After the thermally conductive structure layer 100 is formed, the first surface 110 is combined with the wafer 30, and compared with the scheme of forming the thermally conductive structure layer 100 in the wafer 30 processing process, the forming process of the thermally conductive structure layer 100 does not affect the processing process of the wafer 30.

[0126] The first surface 110 can be combined with the wafer 30 after the wafer 30 is polished.

[0127] In other examples, the chip bonding film 23 can also not include the second substrate layer 300.

[0128] In some possible embodiments, the chip bonding film 23 can be a roll structure, for example, the chip bonding film 23 can be a roll belt structure. In order to facilitate transportation, storage and use.

[0129] FIG. 5 is a process flow diagram of a manufacturing method of a chip bonding film according to an embodiment of the present application, and FIG. 6 is a forming process diagram of a chip bonding film according to an embodiment of the present application.

[0130] As shown in FIGS. 5 and 6, the present application also provides a manufacturing method of a chip bonding film 23, and the manufacturing method comprises:

[0131] S100: bonding a first substrate layer 200 on a first surface 110 of an alloy foil 50.

[0132] S200: forming a nano-porous metal on the alloy foil 50 by a dealloying process, so that the first surface 110 has a plurality of first nano-pores 111, and the second surface 120 has a plurality of second nano-pores 121, to form a thermally conductive structure layer 100 by the nano-porous metal.

[0133] The alloy foil 50 includes a first surface 110 and a second surface 120 located on two sides in a thickness direction of the alloy foil 50, and the first substrate layer 200 is used to be peeled from the first surface 110 under a first preset condition.

[0134] In this way, the formed heat conduction structure layer 100 can be combined with the chip 22 and the cooperating device 21 through the first surface 110 and the second surface 120. After the chip 22 and the cooperating device 21 are connected through the heat conduction structure layer 100, the chip 22 and the cooperating device 21 have good heat conduction, electrical conductivity and connection strength. In addition, the heat conduction structure layer 100 has good high-temperature resistance, so that the chip 22 and the cooperating device 21 can be subjected to high-temperature treatment after being connected, thereby reducing the process restrictions after the chip 22 and the cooperating device 21 are connected. In addition, the heat conduction structure layer 100 is not easy to overflow when combined with the chip 22 and the cooperating device 21, and is not easy to affect the chip 22 and the cooperating device 21. In addition, the chip bonding film 23 is manufactured separately, and the heat conduction structure layer 100 is combined with the chip 22 and the cooperating device 21 after being formed. The forming process of the heat conduction structure layer 100 does not affect the chip 22 and the cooperating device 21, so that the application of the heat conduction structure layer 100 is less restricted, for example, it can be applied to a tube shell scene and a semiconductor bonding scene with III-V compound materials as a substrate.

[0135] The chip bonding film 23 is manufactured by the above method, and it is relatively easy to form the first aperture 111 and the second aperture 121 on the first surface 110 and the second surface 120. In addition, the first aperture 111 and the second aperture 121 are relatively numerous and dense, so that the first surface 110 and the second surface 120 have relatively high surface energy, which is beneficial to the combination with the chip 22 and the cooperating device 21. In addition, the first substrate layer 200 acts as a substrate for the alloy foil 50 and the formed nano-porous metal structure in the dealloying process, and can be used to provide strength so that the formed nano-porous metal structure is not easy to break during transfer.

[0136] For example, the alloy foil 50 can include but is not limited to a gold-silver alloy foil, a gold-aluminum alloy foil, a gold-copper alloy foil, a copper-magnesium alloy foil, etc. One or more elements in the alloy foil 50 can be removed by the dealloying process to form a nano-porous metal, which is a metal skeleton with a nano-porous structure.

[0137] For example, the alloy foil 50 can be continuously moved in a roll form to make each part of the alloy foil 50 pass through the dissolving solution in sequence, so as to remove one or more elements in the alloy foil 50, thereby facilitating the manufacture of a chip bonding film 23 with a relatively long length.

[0138] Exemplarily, the alloy sheet 40 can be formed by one or more processes such as smelting, evaporation, etc., and then the alloy sheet 40 can be calendered into the alloy foil 50 by the calendering machine 60.

[0139] Exemplarily, the thickness of the alloy foil 50 is 10-50 um.

[0140] FIG. 7 is a process flow diagram of another method for manufacturing the chip bonding film according to an embodiment of the present application, and FIG. 8 is a forming process diagram of another method for manufacturing the chip bonding film according to an embodiment of the present application.

[0141] As shown in FIGS. 7 and 8, in one possible implementation, after step S200, the method further includes:

[0142] S300: filling the adhesive 400 into at least one of the first pore 111 and the second pore 121 through the pore structure of the nanoporous metal.

[0143] In this way, the adhesive 400 in the first pore 111 can pre-fix the first surface 110 and the first device before the first surface 110 is combined with the first device, so that the first device and the heat-conducting structure layer 100 are not easily displaced when force is applied to the first device and the heat-conducting structure layer 100, and the first device can be more easily combined with the first surface 110. The adhesive 400 in the second pore 121 can pre-fix the second surface 120 and the second device before the second surface 120 is combined with the second device, so that the second device and the heat-conducting structure layer 100 are not easily displaced when force is applied to the second device and the heat-conducting structure layer 100, and the second device can be more easily combined with the second surface 120.

[0144] The adhesive 400 can be filled into the pore structure of the nanoporous metal to fill the adhesive 400 into at least one of the first pore 111 and the second pore 121.

[0145] In one possible implementation, the decomposition point of the adhesive 400 is greater than or equal to 50℃ and less than or equal to 300℃.

[0146] In this way, the adhesive 400 can achieve bonding performance during pre-fixing, and the adhesive 400 can be decomposed and volatilized in a process after the chip 22 is connected to the cooperating device 21, so that the heat-conducting, electrically-conducting, and high-temperature-resistant properties of the heat-conducting structure layer 100 are not reduced due to the filled adhesive 400, and the chip 22 and the cooperating device 21 are not affected by the overflow of the adhesive 400 in the final product.

[0147] The adhesive 400 can be selected according to the heating temperature of the heating process after pre-fixing by the adhesive 400, so that the adhesive 400 can be decomposed and volatilized by the subsequent heating process.

[0148] For example, the decomposition point of the adhesive 400 can include, but is not limited to, 60°C, 70°C, 80°C, 90°C, 100°C, 110°C, 120°C, 130°C, 140°C, 150°C, etc.

[0149] FIG. 9 is a process flow diagram of another method for manufacturing a chip adhesive film according to an embodiment of the present application, and FIG. 10 is a forming process diagram of the chip adhesive film according to an embodiment of the present application.

[0150] In a possible implementation, after step S200, the method further includes:

[0151] S400: bonding the second substrate layer 300 to the second surface 120, wherein the second substrate layer 300 is configured to be peeled from the second surface 120 under a second preset condition.

[0152] In this way, the second substrate layer 300 can play a role in protecting the second surface 120.

[0153] In a possible implementation, the bonding strength of the second substrate layer 300 to the second surface 120 under the first preset condition is greater than the bonding strength of the first substrate layer 200 to the first surface 110 under the first preset condition.

[0154] In this way, the second substrate layer 300 can be kept bonded to the second surface 120 when the first substrate layer 200 is peeled from the first surface 110. In addition, after the first substrate layer 200 is peeled from the first surface 110, the first surface 110 can be combined with the wafer 30 used to cut to form the chip 22, and when the wafer 30 is cut to form the chip 22, the thermally conductive structure layer 100 combined on the surface of the wafer 30 can be cut, so that the size of the thermally conductive structure layer 100 combined on the surface of the chip 22 is highly matched with the size of the chip 22, and the thermally conductive structure layer 100 is easily combined with the chip 22 with a smaller size. The second substrate layer 300 can support the wafer 30 and the thermally conductive structure layer 100 as a substrate when the wafer 30 and the thermally conductive structure layer 100 are cut, so as to facilitate the cutting of the wafer 30 and the thermally conductive structure layer 100. After the wafer 30 and the thermally conductive structure layer 100 are cut, the second substrate layer 300 is peeled from the second surface 120.

[0155] FIG. 11 is a process flow diagram of another method for manufacturing a chip adhesive film according to an embodiment of the present application, and FIG. 12 is a forming process diagram of the chip adhesive film according to an embodiment of the present application.

[0156] As shown in FIGS. 11 and 12, the method can include steps S300 and S400, and step S400 is performed after step S300.

[0157] FIG. 13 is a process flow diagram of a chip mounting method according to an embodiment of the present application.

[0158] The chip 22 mounting method according to an embodiment of the present application includes a chip 22 mounting method using a chip adhesive film 23 to mount the chip 22 on a mating device 21. The chip adhesive film 23 includes a thermally conductive structure layer 100, and the thermally conductive structure layer 100 includes a first surface 110 and a second surface 120, which are respectively located on two sides in the thickness direction of the thermally conductive structure layer 100. The first surface 110 has a plurality of first nano-sized pores 111, and the second surface 120 has a plurality of second nano-sized pores 121.

[0159] The chip 22 mounting method includes:

[0160] S500: Pressing the chip adhesive film 23 and a first device stacked on the first surface 110 to combine the first surface 110 with the first device. The first device is one of the chip 22 and the mating device 21.

[0161] For example, the chip adhesive film 23 stacked on the surface of the first device can be pressed by rolling to combine the first surface 110 with the first device.

[0162] S600: Pressing the chip adhesive film 23 and a second device stacked on the second surface 120 to combine the second surface 120 with the second device. The second device is the other one of the chip 22 and the mating device 21.

[0163] For example, the chip adhesive film 23 stacked on the surface of the second device can be pressed by rolling to combine the first surface 110 with the first device.

[0164] In this way, the plurality of nanoscale first pores 111 can make the first surface 110 have a large surface energy, so that the first surface 110 can be combined with the first device more easily under a certain pressure, the plurality of nanoscale second pores 121 can make the second surface 120 have a large surface energy, so that the second surface 120 can be combined with the second device more easily under a certain pressure, the connection between the chip 22 and the cooperating device 21 can not need to use a glue layer made of resin material or the like for bonding, the heat-conducting structural layer 100 is made of a material with good heat-conducting performance, and the heat-conducting structural layer 100 made of a material with good heat-conducting performance is conducive to improving the heat-conducting performance between the chip 22 and the cooperating device 21 connected by the chip bonding film 23. In addition, the heat-conducting structural layer 100 is combined with the first device and the second device after being formed, and the forming process of the heat-conducting structural layer 100 will not affect the first device and the second device, so that the application of the chip bonding film 23 is less limited, for example, can be applied to a tube shell scene, a semiconductor bonding scene in which a III-V compound material is used as a substrate.

[0165] It should be noted that the order of execution of steps S500 and S600 is not limited, that is, S500 can be executed first, and S600 can be executed after S500 is completed, or S600 can be executed first, and S500 can be executed after S600 is completed, or S500 and S600 can be executed synchronously.

[0166] For example, when the chip bonding film 23 and the first device stacked on the first surface 110 are pressed, the temperature at the chip bonding film 23 can be increased by heating to make the first surface 110 more easily combined with the first device, and the requirement for the pressure of the chip bonding film 23 and the first device stacked on the first surface 110 can be reduced.

[0167] For example, when the chip bonding film 23 and the second device stacked on the second surface 120 are pressed, the temperature at the chip bonding film 23 can be increased by heating to make the second surface 120 more easily combined with the second device, and the requirement for the pressure of the chip bonding film 23 and the second device stacked on the second surface 120 can be reduced.

[0168] FIG. 14 is a process flow diagram of another chip mounting method provided by an embodiment of the present application, and FIG. 15 is a mounting process diagram of a chip mounting method provided by an embodiment of the present application.

[0169] As shown in FIGS. 14 and 15, when the first substrate layer 200 is bonded to the first surface 110 of the chip bonding film 23, before step S500 is performed, the method further includes the following step:

[0170] S700: peeling the first substrate layer 200 from the first surface 110.

[0171] When the second substrate layer 300 is bonded to the second surface 120 of the chip bonding film 23, before step S600 is performed, a step of:

[0172] S800: peeling the second substrate layer 300 from the second surface 120.

[0173] In one possible implementation, the chip bonding film 23 can be combined with a wafer 30 used for cutting to form the chip 22. The wafer 30 includes the chip 22, the first device is the chip 22, the chip bonding film 23 further includes the second substrate layer 300, the second substrate layer 300 is bonded to the second surface 120, the second substrate layer 300 is used to be peeled from the second surface 120 under the second preset condition, the heat conduction structure layer 100 includes the heat conduction structure layer sub-region 130, the first surface 110 includes the first surface sub-region 131 located in the heat conduction structure layer sub-region 130, the first surface sub-region 131 has a plurality of first apertures 111, and the second surface 120 includes the second surface sub-region 132 located in the heat conduction structure layer sub-region 130, and the second surface sub-region 132 has a plurality of second apertures 121.

[0174] Step S500 includes:

[0175] S510: pressing the chip bonding film 23 and the wafer 30 stacked on the first surface 110 to combine the first surface 110 with the wafer 30. For example, a pressure with a size of F1 can be applied to the chip bonding film 23 and the wafer 30 stacked on the first surface 110.

[0176] S520: cutting the wafer 30 and the heat conduction structure layer 100 on the surface of the second substrate layer 300 to form the first device and the heat conduction structure layer sub-region 130 on the surface of the second substrate layer 300.

[0177] After step S520, step S800 is performed.

[0178] Step S600 includes:

[0179] S610: after step S800, pressing the heat conduction structure layer sub-region 130 and the second device stacked on the second surface sub-region 132 to combine the second surface sub-region 132 with the second device, wherein the second device is the mating device 21. For example, a pressure with a size of F2 can be applied to the heat conduction structure layer sub-region 130 and the second device stacked on the second surface sub-region 132.

[0180] In this way, the size of the surface-bonded sub-region 130 of the heat-conducting structure layer of the chip 22 is highly matched with the size of the chip 22. In addition, the heat-conducting structure layer 100 is bonded to the chip 22 with a small size, so that the chip 22 with a small size is easily attached. Furthermore, the first surface 110 is bonded to the wafer 30 after the heat-conducting structure layer 100 is formed, and compared with the scheme in which the heat-conducting structure layer 100 is formed in the process of processing the wafer 30, the formation process of the heat-conducting structure layer 100 does not affect the processing process of the wafer 30.

[0181] The step S500 can be performed after the wafer 30 is polished.

[0182] FIG. 16 is an attachment process diagram of another chip attachment method provided by the embodiment of the present application.

[0183] In some examples in which the chip adhesive film 23 does not include the second substrate layer 300, the step S600 can be performed first, and a pressure with a size of F3 is applied to the chip adhesive film 23 and the mating device 21 stacked on the second surface 120, so that the second surface 120 is bonded to the mating device 21. Then, the step S700 is performed, and after the step S700, the step S500 is performed, and a pressure with a size of F4 is applied to the chip adhesive film 23 and the chip 22 stacked on the first surface 110, so that the first surface 110 is bonded to the chip 22.

[0184] FIG. 17 is a process flow diagram of still another chip attachment method provided by the embodiment of the present application.

[0185] As shown in FIG. 17, in a possible implementation, the second aperture 121 is filled with the adhesive 400, and the chip 22 attachment method further includes:

[0186] S910: stacking a second device on the second surface 120, and bonding the second device to the second surface 120 through the adhesive 400, so that the second device is pre-fixed to the second surface 120.

[0187] The step S600 includes:

[0188] S620: after the step S910, pressing the heat-conducting structure layer 100 and the second device, so that the second surface 120 is bonded to the second device.

[0189] The step S500 includes:

[0190] S530: after the step S910, pressing the heat-conducting structure layer 100 and the first device stacked on the first surface 110, so that the first surface 110 is bonded to the first device.

[0191] In some examples, the step S530 can be performed after the step 620.

[0192] When the first substrate layer 200 is bonded to the first surface 110, step S700 can be performed after step S620, and step S530 is performed after step S700.

[0193] FIG. 18 is a process flow diagram of another chip mounting method according to an embodiment of the present application, and FIG. 19 is a mounting process diagram of the chip mounting method according to an embodiment of the present application.

[0194] As shown in FIGS. 18 and 19, in one possible implementation, step S620 includes:

[0195] Step S621: When step S530 is performed, the heat-conducting structure layer 100 and the second device are pressed by the pressure applied to the heat-conducting structure layer 100 by the first device, so that the second surface 120 is combined with the second device. For example, when step S530 is performed, the chip 22, the cooperating device 21 and the heat-conducting structure layer 100 can be pressed with a pressure F5, so that the first surface 110 and the second surface 120 are combined with the chip 22 and the cooperating device 21, respectively. In this way, the process flow can be simpler. In addition, it is also convenient to press the heat-conducting structure layer 100 with a small thickness.

[0196] When the first substrate layer 200 is bonded to the first surface 110, step S700 can be performed after step S910, and step S530 and step S621 are performed after step S700.

[0197] For example, the chip 22 mounting method further includes:

[0198] S920: After step S620, the heat-conducting structure layer 100 is heated, so that the temperature of the heat-conducting structure layer 100 after heating is higher than the decomposition point of the adhesive 400, so that the adhesive 400 is decomposed and volatilized.

[0199] Step S920 can be performed after step S530 and step 620.

[0200] In the description of the embodiments of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms “mounting”, “connected”, “connection” should be understood in a broad sense, for example, can be fixedly connected, can be indirectly connected through an intermediate medium, or can be the communication inside two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0201] In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically specified.

[0202] The terms "first", "second", "third", "fourth" and the like in the description of the present application and in the claims of the present application and above-described drawings, if any, are used for distinguishing between similar objects talking about the priority and should not necessarily be construed as referring numerically to the priority.

[0203] The term "a plurality" herein refers to two or more. The term "and / or" herein merely describes an associated relationship between associated objects, which means that there can be three relationships, for example, A and / or B, which can represent three cases: A exists alone, A and B exist together, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects; in the formula, the character " / " represents a "division" relationship between the associated objects.

[0204] It can be understood that various numbers involved in the embodiments of the present application are only distinguished for convenience of description, and do not limit the scope of the embodiments of the present application.

[0205] It can be understood that the size of the serial number of each process in the embodiments of the present application does not mean the order of execution, and the execution order of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Claims

1. A die bonding film, characterized by, The heat-conducting structure layer includes a first surface and a second surface, the first surface and the second surface are respectively located on both sides of the thickness direction of the heat-conducting structure layer, the first surface has a plurality of nanoscale first pores, and the second surface has a plurality of nanoscale second pores. The first surface is used in combination with a first device, and the second surface is used in combination with a second device. The first device is one of a chip and a matching device, and the second device is the other of the chip and the matching device. The heat-conducting structure layer is a metal structure layer.

2. The die bonding film according to claim 1, wherein The heat-conducting structure layer is a structure layer formed by a nanoporous metal.

3. The die bonding film according to claim 2, wherein At least one of the first pores and the second pores is filled with adhesive.

4. The die bonding film according to any one of claims 1 to 3, wherein The decomposition point of the adhesive is greater than or equal to 50 DEG C and less than or equal to 300 DEG C.

5. The die bonding film according to claim 4, wherein The first substrate layer is bonded to the first surface.

6. The die bonding film according to any one of claims 1 to 5, wherein The first substrate layer is used to be peeled off from the first surface under a first preset condition. The second substrate layer is bonded to the second surface. The second substrate layer is used to be peeled off from the second surface under a second preset condition.

7. The die bonding film according to claim 6, wherein The bonding strength of the second substrate layer to the second surface under the first preset condition is greater than the bonding strength of the first substrate layer to the first surface under the first preset condition. The chip bonding film is combined with the first device at the first surface thereof and combined with the second device at the second surface thereof. The chip bonding film is combined with the first device at the first surface thereof and combined with the second device at the second surface thereof.

8. The die bonding film according to claim 7, wherein ​ 9. A package assembly, comprising: ​ ​ 10. A semiconductor device, characterized by comprising: ​ ​

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