Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises: a base substrate, a plurality of pixel driving circuits, a first gate line and a fourth gate line. The orthographic projections of the plurality of pixel driving circuits on the base substrate are distributed in an array in a first direction (X) and a second direction (Y), the first direction (X) and the second direction (Y) intersecting each other. Each pixel driving circuit comprises a driving transistor (T3), a second transistor (T2) and a ninth transistor (T9), a first electrode of the ninth transistor (T9) being connected to a gate of the driving transistor (T3), a second electrode of the ninth transistor (T9) being connected to a first electrode of the second transistor (T2), and a second electrode of the second transistor (T2) being connected to a second electrode of the driving transistor (T3). The orthographic projection of the first gate line on the base substrate extends in the first direction (X), the first gate line being used for providing a gate driving signal for the second transistors (T2) in the plurality of pixel driving circuits distributed in the first direction (X). The orthographic projection of the fourth gate line on the base substrate extends in the second direction (Y), the fourth gate line being used for providing a gate driving signal for the ninth transistors (T9) in the plurality of pixel driving circuits distributed in the second direction (Y). The refresh rates of local display areas of the display panel can be adjusted.

Description

Display panel and display device

[0001] Cross Reference to Related Applications

[0002] The present application claims priority to Chinese Patent Application No. 202410831706.6, filed on June 25, 2024, entitled “Display panel and display device”, the disclosure of which is incorporated herein in its entirety as part of the present application. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0004] In the related art, in order to improve the display effect of the display panel, the display panel has a high refresh frequency. However, the high refresh frequency of the display panel can cause high power consumption of the display panel.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] According to an aspect of the present disclosure, a display panel is provided, wherein the display panel comprises:

[0007] a substrate substrate;

[0008] a plurality of pixel driving circuits, a plurality of the pixel driving circuits are arrayed in a first direction and a second direction on a normal projection of the substrate substrate, and the first direction and the second direction intersect;

[0009] wherein the pixel driving circuit comprises a driving transistor, a second transistor, and a ninth transistor, a first electrode of the ninth transistor is connected to a gate electrode of the driving transistor, a second electrode of the ninth transistor is connected to a first electrode of the second transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor;

[0010] a first gate line, a normal projection of the first gate line on the substrate substrate extends in the first direction, and the first gate line is configured to provide a gate driving signal to the second transistor in the plurality of pixel driving circuits distributed in the first direction;

[0011] a fourth gate line, a normal projection of the fourth gate line on the substrate substrate extends in the second direction, and the fourth gate line is configured to provide a gate driving signal to the ninth transistor in the plurality of pixel driving circuits distributed in the second direction.

[0012] In an example embodiment of the present disclosure, the display panel further includes:

[0013] a ninth active portion configured to form a channel region of the ninth transistor;

[0014] a sixth conductive portion connected to a stable power supply terminal, the conductive layer where the sixth conductive portion is located being between the active layer where the ninth active portion is located and the substrate, and a projection of the sixth conductive portion on the substrate and a projection of the ninth active portion on the substrate at least partially overlap.

[0015] In an example embodiment of the present disclosure, the display panel further includes:

[0016] a shielding layer located on one side of the substrate, the shielding layer including a first shielding portion;

[0017] a first active layer located on a side of the shielding layer away from the substrate, the first active layer including a third active portion configured to form a channel region of the driving transistor, a projection of the first shielding portion on the substrate and a projection of the third active portion on the substrate at least partially overlap;

[0018] The sixth conductive portion is located in the shielding layer.

[0019] In an example embodiment of the present disclosure, the shielding layer further includes:

[0020] a second connecting portion connected between two first shielding portions adjacent in the second direction;

[0021] The sixth conductive portion is connected to the second connecting portion, and a projection of the sixth conductive portion on the substrate is located on one side of a projection of the second connecting portion on the substrate in the first direction.

[0022] In an example embodiment of the present disclosure, the display panel further includes:

[0023] a second active portion configured to form a channel region of the second transistor;

[0024] a ninth active portion configured to form a channel region of the ninth transistor;

[0025] The second active portion and the ninth active portion are located in the same active layer, and an area of a projection of the ninth active portion on the substrate is smaller than an area of a projection of the second active portion on the substrate.

[0026] In an example embodiment of the present disclosure, a length of a channel region of the ninth transistor is less than a length of a channel region of the second transistor.

[0027] And / or, a width of the channel region of the ninth transistor is less than a width of the channel region of the second transistor.

[0028] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a first transistor, a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a second electrode of the driving transistor, and the display panel further comprises:

[0029] a first active part for forming a channel region of the first transistor;

[0030] a ninth active part for forming a channel region of the ninth transistor;

[0031] The first active part and the ninth active part are located in the same active layer, and an area of a normal projection of the ninth active part on the substrate substrate is less than an area of a normal projection of the first active part on the substrate substrate.

[0032] In an example embodiment of the present disclosure, the driving transistor and the ninth transistor are P-type transistors, and the display panel further comprises:

[0033] a first active layer located on one side of the substrate substrate, the first active layer comprising a third active part and a ninth active part, the third active part being used for forming a channel region of the driving transistor, and the ninth active part being used for forming a channel region of the ninth transistor.

[0034] In an example embodiment of the present disclosure, the driving transistor is a P-type transistor, and the ninth transistor is an N-type transistor, and the display panel further comprises:

[0035] a first active layer located on one side of the substrate substrate, the first active layer comprising a third active part, the third active part being used for forming a channel region of the driving transistor;

[0036] a second active layer located on a side of the first active layer away from the substrate substrate, the second active layer comprising a ninth active part, the ninth active part being used for forming a channel region of the ninth transistor.

[0037] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a first transistor and a fourth transistor, a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a second electrode of the driving transistor, and a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor.

[0038] The display panel further comprises:

[0039] A first reset signal line is located on one side of the substrate substrate, a projection of the first reset signal line on the substrate substrate extends along a first direction, and part of the structure of the first reset signal line is used to form a gate electrode of the first transistor.

[0040] A second gate line is located on one side of the substrate substrate, a projection of the second gate line on the substrate substrate extends along a first direction, and part of the structure of the second gate line is used to form a gate electrode of the fourth transistor.

[0041] In the same pixel driving circuit, a projection of a channel region of the ninth transistor on the substrate substrate is located between a projection of the second gate line on the substrate substrate and a projection of the first reset signal line on the substrate substrate.

[0042] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a fourth transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor.

[0043] In the same pixel driving circuit, a projection of a channel region of the ninth transistor on the substrate substrate is located between a projection of the fourth transistor on the substrate substrate and a projection of the second transistor on the substrate substrate.

[0044] In an example embodiment of the present disclosure, a length direction of the channel region of the second transistor is a second direction, and a length direction of the channel region of the ninth transistor is a first direction.

[0045] In an example embodiment of the present disclosure, the display panel further comprises:

[0046] A first source-drain layer is located on one side of the substrate substrate, and the first source-drain layer comprises a ninth bridge portion, and the ninth bridge portion is connected to a first electrode of the ninth transistor and a gate electrode of the driving transistor through a via hole, respectively.

[0047] A second source-drain layer is located on a side of the first source-drain layer away from the substrate substrate, and the second source-drain layer includes a first power supply line, which is configured to provide a high-level power supply signal to the pixel driving circuit.

[0048] A third source-drain layer is located on a side of the second source-drain layer away from the substrate substrate, and the third source-drain layer includes the fourth gate line.

[0049] In an example embodiment of the present disclosure, the display panel further includes:

[0050] The first power supply line is configured to provide a high-level power supply signal to the pixel driving circuit, and a projection of the first power supply line on the substrate substrate extends along the second direction.

[0051] A projection of the fourth gate line on the substrate substrate and a projection of the first power supply line on the substrate substrate at least partially overlap.

[0052] In an example embodiment of the present disclosure, the first power supply line includes a first extension and a second extension, and a size of a projection of the first extension on the substrate substrate in the first direction is greater than a size of a projection of the second extension on the substrate substrate in the first direction.

[0053] A projection of the fourth gate line on the substrate substrate and a projection of the second extension on the substrate substrate at least partially overlap.

[0054] In an example embodiment of the present disclosure, the display panel further includes:

[0055] The first power supply line is located on a side of the substrate substrate, and the first power supply line is configured to provide a high-level power supply signal to the pixel driving circuit, and a projection of the first power supply line on the substrate substrate and a projection of a channel region of the ninth transistor on the substrate substrate at least partially overlap.

[0056] In an example embodiment of the present disclosure, the display panel further includes:

[0057] The first source-drain layer is located on a side of the substrate substrate, and the first source-drain layer includes a second bridge portion and a ninth bridge portion, the second bridge portion is connected to the second electrode of the driving transistor and the second electrode of the second transistor through vias respectively, and the ninth bridge portion is connected to the first electrode of the ninth transistor and the gate electrode of the driving transistor through vias respectively.

[0058] A second source-drain layer is located on a side of the first source-drain layer away from the substrate substrate, and the second source-drain layer includes a first power supply line, which is configured to provide a high-level power supply signal to the pixel driving circuit.

[0059] The first power line and the second bridge portion on the substrate substrate at least partially overlap in the orthogonal projection, and / or the first power line and the ninth bridge portion on the substrate substrate at least partially overlap in the orthogonal projection.

[0060] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a first transistor, a first electrode of the first transistor being connected to a first initial signal line, and a second electrode of the first transistor being connected to a second electrode of the driving transistor.

[0061] The display panel further comprises:

[0062] A second bridge portion is located on one side of the substrate substrate, and the second bridge portion is connected to the second electrode of the driving transistor, the second electrode of the second transistor, and the second electrode of the first transistor through vias, respectively.

[0063] The first gate line comprises a third extension portion and a fourth extension portion, the third extension portion is used to form a gate electrode of the second transistor, and a size of an orthogonal projection of the third extension portion on the substrate substrate in a second direction is greater than a size of an orthogonal projection of the fourth extension portion on the substrate substrate in the second direction.

[0064] The second bridge portion and the first gate line are located in different conductive layers, the second bridge portion comprises a first sub-bridge portion, the first sub-bridge portion extends along the second direction in the orthogonal projection on the substrate substrate, and the orthogonal projection of the first sub-bridge portion on the substrate substrate intersects with the orthogonal projection of the fourth extension portion on the substrate substrate.

[0065] In an example embodiment of the present disclosure, the second bridge portion further comprises:

[0066] A second sub-bridge portion is connected to the second electrode of the first transistor through a via.

[0067] A third sub-bridge portion is connected to the second electrode of the second transistor and the second electrode of the driving transistor through a via.

[0068] The first sub-bridge portion is connected between the second sub-bridge portion and the third sub-bridge portion, an included angle between the orthogonal projection of the first sub-bridge portion on the substrate substrate and the orthogonal projection of the second sub-bridge portion on the substrate substrate is less than 180°, and an included angle between the orthogonal projection of the first sub-bridge portion on the substrate substrate and the orthogonal projection of the third sub-bridge portion on the substrate substrate is less than 180°.

[0069] In an example embodiment of the present disclosure, the display panel further comprises a light emitting unit, the pixel driving circuit is configured to drive the light emitting unit to emit light, and the pixel driving circuit further comprises:

[0070] a first transistor, a first electrode of the first transistor being connected to a first initial signal line, and a second electrode of the first transistor being connected to a second electrode of the driving transistor;

[0071] a fourth transistor, a first electrode of the fourth transistor being connected to a data line, and a second electrode of the fourth transistor being connected to the first electrode of the driving transistor;

[0072] a fifth transistor, a first electrode of the fifth transistor being connected to a first power supply line, and a second electrode of the fifth transistor being connected to the first electrode of the driving transistor;

[0073] a sixth transistor, a first electrode of the sixth transistor being connected to the second electrode of the driving transistor, and a second electrode of the sixth transistor being connected to the light emitting unit;

[0074] a seventh transistor, a first electrode of the seventh transistor being connected to a second initial signal line, and a second electrode of the seventh transistor being connected to the light emitting unit;

[0075] an eighth transistor, a first electrode of the eighth transistor being connected to a third initial signal line, and a second electrode of the eighth transistor being connected to the first electrode of the driving transistor;

[0076] a capacitor, a first electrode of the capacitor being connected to a gate electrode of the driving transistor, and a second electrode of the capacitor being connected to the first power supply line;

[0077] In an example embodiment of the present disclosure, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-type transistors, the second transistor is an N-type transistor, and the ninth transistor is an N-type transistor or a P-type transistor.

[0078] In an example embodiment of the present disclosure, the pixel driving circuit comprises a P-type transistor and an N-type transistor, and the display panel further comprises:

[0079] a first active layer, located on one side of the substrate, and part of the structure of the first active layer being configured to form a channel region of a P-type transistor in the pixel driving circuit;

[0080] a first gate layer, located on a side of the first active layer away from the substrate, and part of the structure of the first gate layer being configured to form a gate electrode of the P-type transistor in the pixel driving circuit;

[0081] a second gate layer, located on a side of the first gate layer away from the substrate, and part of the structure of the second gate layer being configured to form a bottom gate of an N-type transistor in the pixel driving circuit;

[0082] a second active layer located on a side of the second gate layer away from the substrate, and a part of the structure of the second active layer is used to form a channel region of an N-type transistor in the pixel driving circuit;

[0083] a third gate layer located on a side of the second active layer away from the substrate, and a part of the structure of the third gate layer is used to form a top gate of an N-type transistor in the pixel driving circuit;

[0084] a first source-drain layer located on a side of the third gate layer away from the substrate, and a part of the structure of the first source-drain layer is used to form a bridge connecting different transistors.

[0085] According to an aspect of the present disclosure, there is provided a display device, wherein the display device comprises the display panel as described above.

[0086] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0087] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0088] FIG. 1 is a structural schematic diagram of an exemplary embodiment of a display panel in the related art;

[0089] FIG. 2 is a structural schematic diagram of an exemplary embodiment of a pixel driving circuit according to the present disclosure;

[0090] FIG. 3 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in FIG. 2;

[0091] FIG. 4 is a structural schematic diagram of an exemplary embodiment of a display panel according to the present disclosure;

[0092] FIG. 5 is a timing diagram of some signal lines in an exemplary embodiment of the display panel according to the present disclosure;

[0093] FIG. 6 is a structural layout of an exemplary embodiment of a display panel according to the present disclosure;

[0094] FIG. 7 is a structural layout of a shielding layer in FIG. 6;

[0095] FIG. 8 is a structural layout of a first active layer in FIG. 6;

[0096] FIG. 9 is a structural layout of a first gate layer in FIG. 6;

[0097] FIG. 10 is a structure layout of the second gate layer in FIG. 6;

[0098] FIG. 11 is a structure layout of the second active layer in FIG. 6;

[0099] FIG. 12 is a structure layout of the third gate layer in FIG. 6;

[0100] FIG. 13 is a structure layout of the first source-drain layer in FIG. 6;

[0101] FIG. 14 is a structure layout of the second source-drain layer in FIG. 6;

[0102] FIG. 15 is a structure layout of the third source-drain layer in FIG. 6;

[0103] FIG. 16 is a structure layout of the shielding layer, the first active layer in FIG. 6;

[0104] FIG. 17 is a structure layout of the shielding layer, the first active layer, the first gate layer in FIG. 6;

[0105] FIG. 18 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer in FIG. 6;

[0106] FIG. 19 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer in FIG. 6;

[0107] FIG. 20 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer in FIG. 6;

[0108] FIG. 21 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer in FIG. 6;

[0109] FIG. 22 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, the second source-drain layer in FIG. 6;

[0110] FIG. 23 is a partial cross-sectional view of the display panel shown in FIG. 6 along the dashed line BB;

[0111] FIG. 24 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the third gate layer in an exemplary embodiment of the display panel of the present disclosure;

[0112] FIG. 25 is a structure layout of the shielding layer in the display panel shown in FIG. 24;

[0113] FIG. 26 is a structure layout of the second gate layer in the display panel shown in FIG. 24;

[0114] FIG. 27 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in FIG. 24;

[0115] FIG. 28 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure;

[0116] FIG. 29 is a structural layout of an exemplary embodiment of the display panel of the present disclosure;

[0117] FIG. 30 is a structural layout of the shielding layer in FIG. 29;

[0118] FIG. 31 is a structural layout of the first active layer in FIG. 29;

[0119] FIG. 32 is a structural layout of the first gate layer in FIG. 29;

[0120] FIG. 33 is a structural layout of the second gate layer in FIG. 29;

[0121] FIG. 34 is a structural layout of the second active layer in FIG. 29;

[0122] FIG. 35 is a structural layout of the third gate layer in FIG. 29;

[0123] FIG. 36 is a structural layout of the first source-drain layer in FIG. 29;

[0124] FIG. 37 is a structural layout of the second source-drain layer in FIG. 29;

[0125] FIG. 38 is a structural layout of the third source-drain layer in FIG. 29;

[0126] FIG. 39 is a structural layout of the shielding layer and the first active layer in FIG. 29;

[0127] FIG. 40 is a structural layout of the shielding layer, the first active layer, and the first gate layer in FIG. 29;

[0128] FIG. 41 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG. 29;

[0129] FIG. 42 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG. 29;

[0130] FIG. 43 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG. 29;

[0131] FIG. 44 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer in FIG. 29;

[0132] FIG. 45 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in FIG. 29;

[0133] FIG. 46 is a partial cross-sectional view of the display panel shown in FIG. 29 taken along the dotted line CC;

[0134] FIG. 47 is a cross-sectional view in another exemplary embodiment of the display panel of the present disclosure;

[0135] FIG. 48 is a cross-sectional view in another exemplary embodiment of the display panel of the present disclosure;

[0136] FIG. 49 is a structure layout of the display panel in another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0137] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and descriptions of the same elements can be omitted from the detailed description.

[0138] The terms "one", "a", "said" are used to indicate that there is one or more of the elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusion of elements / components / etc. in the resulting system, apparatus, etc. and do not preclude additional elements / components / etc.

[0139] As shown in FIG. 1, it is a structural schematic diagram of an exemplary embodiment of a display panel in the related art. The display panel can include a timing controller, a source driving circuit, a gate driving circuit and a pixel array, the timing controller is connected with the source driving circuit and the gate driving circuit respectively, the source driving circuit is connected with a plurality of data lines (Da1 to Dan) respectively. The gate driving circuit includes a scan driving circuit and a light emitting driving circuit. The scan driving circuit is connected with a plurality of scan signal lines (S1 to Sm) respectively, the light emitting driving circuit is connected with a plurality of light emitting signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, the sub-pixel Pxij can include a pixel driving circuit and a light emitting device connected with the pixel driving circuit, the pixel driving circuit can be connected with the scan signal line, the light emitting signal line and the data line respectively. The data line can be used for providing the above-mentioned data signal end, the light emitting signal line can be used for providing the above-mentioned enable signal end, the present exemplary embodiment only exemplarily draws a scan signal line connected with the pixel driving circuit, each row of pixel driving circuits can be connected with a plurality of scan signal lines, and the plurality of scan signal lines can be used for respectively providing the above-mentioned first gate driving signal end, the second gate driving signal end, the first reset signal end and the second reset signal end. In the exemplary embodiment, the timing controller can provide the gray scale value and the control signal suitable for the specification of the source driving circuit to the source driving circuit, can provide the clock signal, the scan start signal and the like suitable for the specification of the scan driving circuit to the scan driving circuit, and can provide the clock signal, the emission stop signal and the like suitable for the specification of the light emitting driving circuit to the light emitting driving circuit. The source driving circuit can generate the data signal to be provided to the data lines Da1, Da2, Da3, … and Dan by using the gray scale value and the control signal received from the timing controller. For example, the source driving circuit can sample the gray scale value by using the clock signal, and apply the data signal corresponding to the gray scale value to the data lines Da1 to Dan in a pixel row unit, and n can be a natural number. The scan driving circuit can generate the scan signal to be provided to the scan signal lines S1, S2, S3, … and Sm by receiving the clock signal, the scan start signal and the like from the timing controller. For example, the scan driving circuit can sequentially provide the scan signal with the on level pulse to the scan signal lines S1 to Sm. For example, the scan driving circuit can be configured in the form of a shift register, and can generate the scan signal in the way that the scan start signal provided in the form of the on level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal, and m can be a natural number. The light emitting driving circuit can generate the emission signal to be provided to the light emitting signal lines E1, E2, E3, … and Eo by receiving the clock signal, the emission stop signal and the like from the timing controller. For example, the light emitting driving circuit can sequentially provide the emission signal with the off level pulse to the light emitting signal lines E1 to Eo.For example, the light emitting driving circuit can be configured in the form of a shift register, and can sequentially transmit an emission stop signal provided in the form of a cutoff level pulse to a next stage circuit under the control of a clock signal to generate an emission signal. o can be a natural number. Thus, the display panel can implement line-by-line scanning and driving.

[0140] The present exemplary embodiment provides a pixel driving circuit, as shown in FIG. 2 and FIG. 3, FIG. 2 is a structural schematic diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure, and FIG. 3 is a timing diagram of part of nodes in an exemplary embodiment of the pixel driving circuit shown in FIG. 2.

[0141] The pixel driving circuit can comprise a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a capacitor C. The first electrode of the fourth transistor T4 is connected to a data signal terminal Da, the second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and the gate electrode of the fourth transistor T4 is connected to a second gate driving signal terminal G2. The first electrode of the fifth transistor T5 is connected to a first power supply terminal VDD, the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and the gate electrode of the fifth transistor T5 is connected to an enable signal terminal EM. The gate electrode of the driving transistor T3 is connected to a node N. The second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and the gate electrode of the second transistor T2 is connected to a first gate driving signal terminal G1. The first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, the gate electrode of the sixth transistor T6 is connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to a second initial signal terminal Vinit2, and the gate electrode of the seventh transistor T7 is connected to a second reset signal terminal Re2. The first electrode of the first transistor T1 is connected to a first initial signal terminal Vinit1, the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3, and the gate electrode of the first transistor T1 is connected to a first reset signal terminal Re1. The first electrode of the eighth transistor T8 is connected to a third initial signal terminal Vinit3, the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3, and the gate electrode of the eighth transistor T8 is connected to the second reset signal terminal Re2. The first electrode of the ninth transistor T9 is connected to the gate electrode of the driving transistor T3, the second electrode of the ninth transistor T9 is connected to the first electrode of the second transistor T2, and the gate electrode of the ninth transistor T9 is connected to a fourth gate driving signal terminal G4. The first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. The pixel driving circuit can be used to drive a light emitting unit L. The second electrode of the light emitting unit L can be connected to the second electrode of the sixth transistor T6, the first electrode of the light emitting unit L can be connected to the second power supply terminal VSS, the first electrode of the light emitting unit L can be the anode of the light emitting unit L, and the second electrode of the light emitting unit L can be the cathode of the light emitting unit L. The second transistor T2 and the ninth transistor T9 can be N-type transistors, for example, the second transistor T2 and the ninth transistor T9 can be N-type metal oxide transistors. The N-type transistors have smaller leakage current, so that the leakage current of the node N through the ninth transistor T9 and the second transistor T2 in the light emitting stage can be reduced.Meanwhile, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can be P-type transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can be P-type low-temperature polysilicon transistors, the P-type transistors have high carrier mobility, thereby being beneficial to realize a high-resolution, high-response-speed, high-pixel-density and high-aperture-ratio display panel. The first initial signal terminal, the second initial signal terminal and the third initial signal terminal can output the same or different voltage signals according to actual conditions.

[0142] As shown in FIG. 3, G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM. One driving period of the pixel driving circuit can include a first reset stage t1, a data writing stage t2, a second reset stage t3 and an emitting stage t4.

[0143] When the fourth gate drive signal terminal G4 turns on the ninth transistor T9:

[0144] In the first reset stage t1: the first gate drive signal terminal G1 outputs a high level, the first reset signal terminal Re1 outputs a low level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the node N through the first transistor T1 and the second transistor T2. In the data writing stage t2: the second gate drive signal terminal G2 outputs a low level signal, the first gate drive signal terminal G1 outputs a high level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to the node N through the fourth transistor T4 and the second transistor T2, wherein Vdata is the voltage of the data signal on the data signal terminal, and Vth is the threshold voltage of the driving transistor T3. In the second reset stage t3: the second reset signal terminal Re2 outputs a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the emitting unit L, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor T3. In the emitting stage t4: the enable signal terminal EM outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C. The driving transistor output current formula is as follows:

[0145] I=(μWCox / 2L)(Vgs-Vth) 2

[0146] wherein I is the output current of the driving transistor; μ is the carrier mobility; Cox is the unit area gate capacitance, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current I of the driving transistor in the pixel driving circuit above is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the threshold voltage of the driving transistor on the output current thereof.

[0147] When the fourth gate driving signal terminal G4 turns off the ninth transistor T9: the pixel driving circuit does not write the initial signal and the new data signal to the driving transistor T3 in the scanning stage, and the gate of the driving transistor maintains the voltage of the last frame.

[0148] As shown in FIG. 4, a structural schematic diagram of an exemplary embodiment of a display panel of the present disclosure is shown. The display panel comprises a substrate, a plurality of pixel driving circuits P1-P9, a plurality of first gate lines G11-G13, a plurality of fourth gate lines G41-G43, the orthogonal projections of the plurality of pixel driving circuits on the substrate are arrayed along a first direction X and a second direction Y, the first direction X and the second direction Y intersect, for example, the first direction X can be the row direction, and the second direction Y can be the column direction; the orthogonal projection of the first gate line on the substrate extends along the first direction, and the first gate line is configured to provide a gate driving signal to the second transistor in the plurality of pixel driving circuits distributed along the first direction X; the orthogonal projection of the fourth gate line on the substrate extends along the second direction Y, and the fourth gate line is configured to provide a gate driving signal to the ninth transistor in the plurality of pixel driving circuits distributed along the second direction.

[0149] It should be noted that the display panel shown in FIG. 4 is taken as an example of nine pixel driving circuits for illustration, and it should be understood that the display panel can comprise other numbers of pixel driving circuits, and correspondingly, the display panel can comprise other numbers of first gate lines and fourth gate lines.

[0150] As shown in FIG. 4, the fourth gate line G41 controls the on-off of the ninth transistor T9 in the pixel driving circuit P1, P4, P7 distributed along the second direction Y, the fourth gate line G42 controls the on-off of the ninth transistor T9 in the pixel driving circuit P2, P5, P8 distributed along the second direction Y, and the fourth gate line G43 controls the on-off of the ninth transistor T9 in the pixel driving circuit P3, P6, P9 distributed along the second direction Y. If the fourth gate line G41, G43 controls the ninth transistor T9 in the pixel driving circuit P1, P4, P7, P3, P6, P9 to be off, the pixel driving circuit P1, P4, P7, P3, P6, P9 will not write the initial signal and the new data signal to the driving transistor T3, and the gate of the driving transistor will maintain the voltage of the last frame, and the corresponding pixel driving circuit P1, P4, P7, P3, P6, P9 can realize low-frequency display. If the fourth gate line G42 controls the ninth transistor T9 in the pixel driving circuit P2, P5, P8 to be on, the pixel driving circuit P2, P5, P8 can normally write the compensation voltage to the gate of the driving transistor. At this time, the refresh frequency of the pixel driving circuit P2, P5, P8 can be controlled by controlling the frequency of the gate driving signal output by the first gate line G11, G12, G13, for example, the first gate line G11 outputs the on signal every frame, and then the pixel driving circuit P2 will be refreshed every frame, and the first gate line G12 outputs the on signal every 3 frames, and then the pixel driving circuit P5 will be refreshed every 3 frames. This method can control the refresh frequency of different pixel driving circuits by controlling the frequency of the on signal output by the fourth gate line and the first gate line.

[0151] The display panel can also realize the control of the refresh frequency of the local area by other driving methods. For example, the frequency of the on signal output by each first gate line can be the same, and when scanning the pixel driving circuit of each row, different fourth gate lines can control the on-off of the ninth transistor T9 connected thereto to control whether the pixel driving circuit of different areas writes the data signal. For example, when the pixel driving circuit P1, P2, P3 is scanned, the fourth gate line G41 can control the ninth transistor in the pixel driving circuit P1 to be on, the fourth gate line G42 can control the ninth transistor in the pixel driving circuit P2 to be on, and the fourth gate line G43 can control the ninth transistor in the pixel driving circuit P3 to be off, so as to control the pixel driving circuit P1 to be refreshed, the pixel driving circuit P2 to be refreshed, and the pixel driving circuit P3 not to be refreshed; when the pixel driving circuit P4, P5, P6 is scanned, the fourth gate line G41 can control the ninth transistor in the pixel driving circuit P4 to be off, the fourth gate line G42 can control the ninth transistor in the pixel driving circuit P5 to be on, and the fourth gate line G43 can control the ninth transistor in the pixel driving circuit P6 to be off, so as to control the pixel driving circuit P5 to be refreshed, and the pixel driving circuit P4, P6 not to be refreshed.

[0152] It should be understood that in other example embodiments, the pixel driving circuit can also be other structures, as long as the pixel driving circuit includes the driving transistor T3, the second transistor T2, and the ninth transistor T9, the first electrode of the ninth transistor is connected to the gate of the driving transistor T3, the second electrode of the ninth transistor T9 is connected to the first electrode of the second transistor T2, and the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3. The present example embodiment can control the refresh frequency of the display panel in different regions through the on-off control of the ninth transistor T9. Among them, the second transistor T2 and the ninth transistor T9 can be P-type transistors or N-type transistors.

[0153] In addition, in other example embodiments, one or more of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can also be N-type transistors.

[0154] As shown in FIG. 5, a timing diagram of part of the signal lines in an example embodiment of the display panel of the present disclosure is shown. Among them, G4x is the timing diagram of the fourth gate line in the low brush area, and G4y is the timing diagram of the fourth gate line in the high brush area. In the low brush area, the fourth gate line outputs an off signal in part of the frames and outputs a conductive signal in part of the frames; in the high brush area, the fourth gate line continuously outputs a conductive signal. When the ninth transistor T9 changes from the on state to the off state, the signal on the fourth gate line will change from high to low, and under the gate-source coupling effect of the ninth transistor T9, the gate of the driving transistor will be pulled low, thereby causing the phenomenon of high brightness in the low brush area and low brightness in the high brush area.

[0155] Of course, when the ninth transistor T9 is a P-type transistor, when the ninth transistor T9 changes from the on state to the off state, the signal on the fourth gate line will change from low to high, and under the gate-source coupling effect of the ninth transistor T9, the gate of the driving transistor will be pulled high, thereby also causing the phenomenon of low brightness in the low brush area and high brightness in the high brush area.

[0156] It should be noted that the off signal is a signal for turning off the target circuit, for example, the off signal of a P-type transistor is a high-level signal, and the off signal of an N-type transistor is a low-level signal. The conductive signal is a signal for turning on the target circuit, for example, the conductive signal of a P-type transistor is a low-level signal, and the conductive signal of an N-type transistor is a high-level signal.

[0157] Based on this, the example embodiment also provides a display panel, which can include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, a second source-drain layer, and a third source-drain layer arranged in sequence. An insulating layer can be arranged between adjacent layers. As shown in FIGS. 6-22, FIG. 6 is a structure layout of an example embodiment of the display panel of the present disclosure, FIG. 7 is a structure layout of the shielding layer in FIG. 6, FIG. 8 is a structure layout of the first active layer in FIG. 6, FIG. 9 is a structure layout of the first gate layer in FIG. 6, FIG. 10 is a structure layout of the second gate layer in FIG. 6, FIG. 11 is a structure layout of the second active layer in FIG. 6, FIG. 12 is a structure layout of the third gate layer in FIG. 6, FIG. 13 is a structure layout of the first source-drain layer in FIG. 6, FIG. 14 is a structure layout of the second source-drain layer in FIG. 6, FIG. 15 is a structure layout of the third source-drain layer in FIG. 6, FIG. 16 is a structure layout of the shielding layer and the first active layer in FIG. 6, FIG. 17 is a structure layout of the shielding layer, the first active layer, and the first gate layer in FIG. 6, FIG. 18 is a structure layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG. 6, FIG. 19 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG. 6, FIG. 20 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG. 6, FIG. 21 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer in FIG. 6, and FIG. 22 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in FIG. 6. The display panel can include a plurality of pixel driving circuits as shown in FIG. 2, and the plurality of pixel driving circuits are arranged in an array in the first direction X and the second direction Y.

[0158] As shown in FIG. 6, the plurality of pixel driving circuits can include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the first direction X, and the first pixel driving circuit P1 and the second pixel driving circuit P2 can be at least partially symmetrically arranged with respect to a mirror symmetry plane AA. The mirror symmetry plane AA can be perpendicular to the substrate. The first pixel driving circuit P1 and the second pixel driving circuit P2 can be at least partially symmetrically arranged with respect to the intersection line of the mirror symmetry plane AA and the substrate as a symmetric axis. The first pixel driving circuit P1 and the second pixel driving circuit P2 can form a repeating unit, and the display panel can include a plurality of repeating units arranged in an array in the first direction X and the second direction Y. The second direction Y and the first direction X can intersect, for example, the first direction X can be a row direction, and the second direction Y can be a column direction. In addition, in the present exemplary embodiment, there can be design errors and process errors in the display panel, and the first pixel driving circuit P1 and the second pixel driving circuit P2 can be substantially symmetrically arranged with respect to the mirror symmetry plane AA.

[0159] As shown in FIGS. 6, 7, and 16, the shielding layer includes a plurality of first shielding portions 81 arranged in an array in the first direction X and the second direction Y, and the first shielding portions 81 are connected to each other by second connecting portions 82.

[0160] As shown in FIGS. 6, 8, 16, 17, the first active layer can include: a first active part 71, a third active part 73, a fourth active part 74, a fifth active part 75, a sixth active part 76, a seventh active part 77, an eighth active part 78, a twenty-first active part 721, a tenth active part 710, an eleventh active part 711, a twelfth active part 712, a thirteenth active part 713, a fourteenth active part 714, a fifteenth active part 715, a sixteenth active part 716, a seventeenth active part 717, an eighteenth active part 718. The first active part 71 is used to form a channel region of the first transistor T1; the third active part 73 can be used to form a channel region of the driving transistor T3; the fourth active part 74 can be used to form a channel region of the fourth transistor T4; the fifth active part 75 can be used to form a channel region of the fifth transistor T5; the sixth active part 76 can be used to form a channel region of the sixth transistor T6; the seventh active part 77 can be used to form a channel region of the seventh transistor T7; the eighth active part 78 can be used to form a channel region of the eighth transistor T8; the twenty-first active part 721 is connected between the third active part 73 and the sixth active part 76; the tenth active part 710 and the twelfth active part 712 are connected at both ends of the eighth active part 78; the eleventh active part 711 is connected between the fourth active part 74 and the third active part 73; the thirteenth active part 713 is connected to a side of the fourth active part 74 away from the third active part 73; the fourteenth active part 714 is connected to a side of the seventh active part 77 away from the sixth active part 76; the fifteenth active part 715 is connected to a side of the fifth active part 75 away from the third active part 73; the sixteenth active part 716 is connected between the seventh active part 77 and the sixth active part 76, the seventeenth active part 717 and the eighteenth active part 718 are connected at both ends of the first active part 71. The first active layer can be formed of a polysilicon material, and accordingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polysilicon thin film transistors.

[0161] The first shielding part 81 can at least partially overlap the third active part 73 in the orthographic projection on the substrate, and the first shielding part 81 can shield the third active part 73 to improve the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure, and the shielding layer can be connected to a stable voltage source, and the shielding layer can shield signals for the pixel driving circuit.

[0162] As shown in FIGS. 6, 9, 16, 17, the first gate layer can include: the first conductive part 11, the second gate line G2, the enable signal line EM, the first reset signal line Re1, the second reset signal line Re2. The second gate line G2 can be used to provide the second gate driving signal end in FIG. 2; the enable signal line EM can be used to provide the enable signal end in FIG. 2; the first reset signal line Re1 can be used to provide the first reset signal end in FIG. 2; the second reset signal line Re2 can be used to provide the second reset signal end in FIG. 2. The orthogonal projection of the second gate line G2 on the substrate substrate, the orthogonal projection of the enable signal line EM on the substrate substrate, the orthogonal projection of the first reset signal line Re1 on the substrate substrate, the orthogonal projection of the second reset signal line Re2 on the substrate substrate can extend along the first direction X. The orthogonal projection of the second gate line G2 on the substrate substrate covers the orthogonal projection of the fourth active part 74 on the substrate substrate, and part of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthogonal projection of the enable signal line EM on the substrate substrate covers the orthogonal projection of the fifth active part 75 on the substrate substrate and the orthogonal projection of the sixth active part 76 on the substrate substrate, and part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5 and the sixth transistor T6, respectively. The orthogonal projection of the first reset signal line Re1 on the substrate substrate can cover the orthogonal projection of the first active part 71 on the substrate substrate, and part of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthogonal projection of the second reset signal line Re2 on the substrate substrate can cover the orthogonal projection of the seventh active part 77 on the substrate substrate and the orthogonal projection of the eighth active part 78 on the substrate substrate, and part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7 and the eighth transistor T8, respectively. The orthogonal projection of the first conductive part 11 on the substrate substrate covers the orthogonal projection of the third active part 73 on the substrate substrate, and the first conductive part 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to perform conductorization processing on the first active layer, that is, the region of the first active layer covered by the first gate layer can form the channel region of the transistor, and the region of the first active layer not covered by the first gate layer forms a conductor structure.

[0163] As shown in FIGS. 6, 10, 18, the second gate layer can include a third gate line 2G1, a second conductive part 22, a first connecting part 23, a fourth conductive part 24, and a first initial signal line Vinit1. The third gate line 2G1 can be used to provide the first gate driving signal terminal in FIG. 2. The second conductive part 22 can be used to form the second electrode of the capacitor C. Adjacent second conductive parts 22 in the first direction X can be connected by the first connecting part 23. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in FIG. 2.

[0164] As shown in FIGS. 6, 11, 19, the second active layer can include an active part 9, which can include a second active part 92, a ninth active part 99, a nineteenth active part 919, and a twentieth active part 920. The nineteenth active part 919 is connected to one end of the second active part 92 away from the ninth active part 99, and the twentieth active part 920 is connected to one end of the ninth active part 99 away from the second active part 92. The second active part 92 can be used to form the channel region of the second transistor T2, and the ninth active part 99 can be used to form the channel region of the ninth transistor T9. The third gate line 2G1 can cover the second active part 92 on the substrate substrate, and part of the structure of the third gate line 2G1 can be used to form the bottom gate of the second transistor T2. The fourth conductive part 24 can cover the ninth active part 99 on the substrate substrate, and at least part of the structure of the fourth conductive part 24 can be used to form the bottom gate of the ninth transistor T9. The second active layer can be formed of indium gallium zinc oxide, and the second transistor T2 and the ninth transistor T9 can be N-type metal oxide thin film transistors.

[0165] As shown in FIGS. 6, 12, and 20, the third gate layer can include the first gate line 3G1, the second initial signal line Vinit2, the third initial signal line Vinit3, and the fifth conductive part 35. The orthogonal projection of the first gate line 3G1 on the substrate substrate, the orthogonal projection of the second initial signal line Vinit2 on the substrate substrate, and the orthogonal projection of the third initial signal line Vinit3 on the substrate substrate can extend along the first direction X. The first gate line 3G1 can be used to provide the first gate driving signal end in FIG. 2, the orthogonal projection of the first gate line 3G1 on the substrate substrate can cover the orthogonal projection of the second active part 92 on the substrate substrate, and part of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. Meanwhile, the first gate line 3G1 can be connected to the third gate line 2G1 through a via located in the display panel frame area. The second initial signal line Vinit2 can be used to provide the second initial signal end in FIG. 2, and the third initial signal line Vinit3 can be used to provide the third initial signal end in FIG. 2. The orthogonal projection of the fifth conductive part 35 on the substrate substrate covers the orthogonal projection of the ninth active part 99 on the substrate substrate, and at least part of the structure of the fifth conductive part 35 is used to form the top gate of the ninth transistor. The orthogonal projection of the second initial signal line Vinit2 on the substrate substrate can at least partially coincide with the orthogonal projection of the second reset signal line Re2 in the pixel driving circuit of the same row on the substrate substrate, and the orthogonal projection of the third initial signal line Vinit3 on the substrate substrate at least partially coincides with the orthogonal projection of the enable signal line EM in the pixel driving circuit of the same row on the substrate substrate. This arrangement can improve the light transmittance and integration of the display panel. In addition, the display panel can use the third gate layer as a mask to perform conductorization processing on the second active layer, that is, the region of the second active layer covered by the third gate layer can form the channel region of the transistor, and the region of the second active layer not covered by the third gate layer forms a conductor structure.

[0166] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in other conductive layers, for example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in the second gate layer, the first source-drain layer, etc.

[0167] As shown in FIGS. 6, 13, and 21, the first source-drain layer can include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a ninth bridge portion 49, and a tenth bridge portion 410. The first bridge portion 41 can be connected to the fourth conductive portion 24 and the fifth conductive portion 35 through vias, respectively, to connect the bottom gate and the top gate of the ninth transistor T9. The second bridge portion 42 can be connected to the twenty-first active portion 721, the nineteenth active portion 919, and the seventeenth active portion 717 through vias, respectively, to connect the second electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the driving transistor T3. The third bridge portion 43 can be connected to the eighteenth active portion 718 and the first initial signal line Vinit1 through vias, respectively, to connect the first electrode of the first transistor T1 and the first initial signal end. The fourth bridge portion 44 can be connected to the fourteenth active portion 714 and the second initial signal line Vinit2 through vias, respectively, to connect the first electrode of the seventh transistor T7 and the second initial signal line. The fifth bridge portion 45 can be connected to the thirteenth active portion 713 through a via to connect the first electrode of the fourth transistor T4. The sixth bridge portion 46 can be connected to the eleventh active portion 711 and the tenth active portion 710 through vias, respectively, to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridge portion 47 can be connected to the first connection portion 23 and the fifteenth active portion 715 through vias, respectively, to connect the second electrode of the capacitor C and the first electrode of the fifth transistor T5. Two fifth active portions 75 in the same repeating unit can be connected through the fifteenth active portion 715, and two pixel driving circuits in the same repeating unit can share the same seventh bridge portion 47. The eighth bridge portion 48 can be connected to the sixteenth active portion 716 through a via to connect the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridge portion 49 can be connected to the twentieth active portion 920 and the first conductive portion 11 through vias, respectively, to connect the gate of the driving transistor T3 and the first electrode of the second transistor T2. An opening 221 can be formed in the second conductive portion 22, and the via connected between the ninth bridge portion 49 and the first conductive portion 11 can be disposed in the opening 221. The tenth bridge portion 410 can be connected to the third initial signal line Vinit3 and the twelfth active portion 712 through vias, respectively, to connect the first electrode of the eighth transistor and the third initial signal line Vinit3. Two eighth active portions 78 in the same repeating unit can be connected through the twelfth active portion 712, and two pixel driving circuits in the same repeating unit can share the same tenth bridge portion 410.

[0168] As shown in FIGS. 6, 13, and 21, the first source-drain layer can further include column initial signal lines Vinitx, a projection of the column initial signal lines Vinitx on the substrate substrate along the second direction Y extends. The column initial signal lines Vinitx can be multiple, and the column initial signal lines Vinitx can be connected to the same row initial signal line intersecting the projection of the column initial signal line Vinitx on the substrate substrate through a via, so as to form a grid structure of the row initial signal line. This arrangement can reduce the voltage difference of the initial signal end at different positions of the display panel. The row initial signal line can include one or more of the first initial signal line, the second initial signal line, and the third initial signal line described above. For example, three adjacent columns of pixel driving circuits can be respectively provided with initial connection lines Vinitx, wherein one initial connection line Vinitx is connected to the first initial signal line, one initial connection line Vinitx is connected to the second initial signal line, and one initial connection line Vinitx is connected to the third initial signal line.

[0169] As shown in FIGS. 6, 14, and 22, the second source-drain layer can include an eleventh bridge portion 511, a twelfth bridge portion 512, a thirteenth bridge portion 513, and a first power supply line VDD. The eleventh bridge portion 511 can be connected to the first bridge portion 41 through a via. The twelfth bridge portion 512 can be connected to the fifth bridge portion 45 through a via. The thirteenth bridge portion 513 can be connected to the eighth bridge portion 48 through a via. The first power supply line VDD can be used to provide the first power supply end in FIG. 2, and a projection of the first power supply line VDD on the substrate substrate can extend along the second direction Y. The first power supply line VDD can be connected to the seventh bridge portion 47 through a via.

[0170] As shown in FIGS. 6 and 15, the third source-drain layer can include a data line Da, a fourth gate line G4, and a fourteenth bridge portion 614. A projection of the data line Da and the fourth gate line G4 on the substrate substrate can extend along the second direction Y. The data line Da is used to provide the data signal end in FIG. 2, and the fourth gate line G4 is used to provide the fourth gate driving signal end in FIG. 2. The data line Da can be connected to the first electrode of the fourth transistor through a via and the twelfth bridge portion 512. The fourth gate line G4 can be connected to the gate electrode of the ninth transistor T9 through a via and the eleventh bridge portion 511. The fourteenth bridge portion 614 can be connected to the thirteenth bridge portion 513 through a via, and the fourteenth bridge portion 614 can be used to connect the first electrode of the light emitting unit.

[0171] It should be noted that, as shown in FIGS. 6, 21, 22, the black square drawn on the side of the first source-drain layer away from the substrate substrate represents the via of the first source-drain layer connecting the other levels facing the substrate substrate side; the black square drawn on the side of the second source-drain layer away from the substrate substrate represents the via of the second source-drain layer connecting the other levels facing the substrate substrate side; the black square drawn on the side of the third source-drain layer away from the substrate substrate represents the via of the third source-drain layer connecting the other levels facing the substrate substrate side; the black square drawn on the side of the electrode layer away from the substrate substrate represents the via of the electrode layer connecting the other levels facing the substrate substrate side. Different vias represented by black squares at different positions can penetrate different insulating layers.

[0172] As shown in FIG. 23, it is a partial cross-sectional view of the display panel shown in FIG. 6 along the dashed line BB. The display panel can also include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planar layer 108, and a second planar layer 109. Among them, the substrate substrate 100, the shielding layer, the buffer layer 101, the first active layer, the second insulating layer 102, the first gate layer, the third insulating layer 103, the second gate layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third gate layer, the first dielectric layer 106, the first source-drain layer, the passivation layer 107, the first planar layer 108, the second source-drain layer, the second planar layer 109, and the third source-drain layer are sequentially stacked. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 can be a silicon nitride layer; the materials of the first planar layer 108 and the second planar layer 109 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The passivation layer 107 can be a silicon oxide layer. The substrate substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer which are sequentially stacked, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, and niobium or an alloy, or a molybdenum / titanium alloy or a laminated conductive layer. The materials of the first source-drain layer, the second source-drain layer, and the third source-drain layer can include metal materials, which can be one of molybdenum, aluminum, copper, titanium, and niobium or an alloy, or a molybdenum / titanium alloy or a laminated conductive layer, or a titanium / aluminum / titanium laminated conductive layer, etc. The sheet resistance of any one of the first source-drain layer, the second source-drain layer, and the third source-drain layer can be smaller than that of any one of the first gate layer, the second gate layer, and the third gate layer.

[0173] The present example embodiment also provides another display panel, which can also include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, a second source-drain layer, and a third source-drain layer arranged in sequence. An insulating layer can be arranged between adjacent layers. As shown in FIGS. 24-27, FIG. 24 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the third gate layer in an example embodiment of the display panel of the present disclosure, FIG. 25 is a structure layout of the shielding layer in the display panel shown in FIG. 24, FIG. 26 is a structure layout of the second gate layer in the display panel shown in FIG. 24, and FIG. 27 is a structure layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in FIG. 24.

[0174] Compared with the embodiment shown in FIG. 6, the shielding layer and the second gate layer in the display panel shown in FIG. 24 are different.

[0175] As shown in FIGS. 24-27, compared with the embodiment shown in FIG. 6, the shielding layer further includes a sixth conductive part 86, the conductive layer where the sixth conductive part 86 is located is between the substrate and the active layer where the ninth active part 99 is located, the orthogonal projection of the sixth conductive part 86 on the substrate and the orthogonal projection of the ninth active part 99 on the substrate at least partially overlap, and optionally, the orthogonal projection of the sixth conductive part 86 on the substrate can cover the orthogonal projection of the ninth active part 99 on the substrate. The sixth conductive part 86 can be connected to a stable power supply end, and the sixth conductive part 86 can stabilize the voltage of the sixth conductive part 86, thereby reducing the gate-source capacitance of the ninth transistor and improving the above-mentioned split-screen problem. As shown in FIGS. 24-27, the shielding layer itself includes a first shielding part 81 and a second connecting part 82 connected between two adjacent first shielding parts 81 in the second direction Y, and the sixth conductive part 86 can be connected to the first shielding part 81 and the second connecting part 82. For example, the sixth conductive part 86 can be a protruding part connected to the second connecting part 82, and the orthogonal projection of the sixth conductive part 86 on the substrate is located on one side of the orthogonal projection of the second connecting part 82 on the substrate in the first direction X. As shown in FIGS. 24-27, compared with the embodiment shown in FIG. 6, the second gate layer does not include a fourth conductive part.

[0176] It should be understood that in other exemplary embodiments, the sixth conductive part connecting the stable power supply end can also be located in other conductive layers, the sixth conductive part can be located in any conductive layer on the side of the second active layer facing the substrate, for example, the sixth conductive part can be located in the first gate layer, the second gate layer, etc., in addition, the sixth conductive part can also be located in other additional conductive layers. For example, as shown in FIG. 47, a cross-sectional view in another exemplary embodiment of the display panel of the present disclosure is shown, wherein the sixth conductive part 86 is located in the second gate layer, and the sixth conductive part 86 can be connected to the shielding layer through a via. In other exemplary embodiments, the sixth conductive part 86 can also be connected to the first power line VDD in the second source-drain layer through a via. The sixth conductive part located in the second gate layer and the ninth active part 99 located in the second active layer are relatively close, so that the sixth conductive part can have a better voltage stabilizing effect on the ninth active part 99. For another example, as shown in FIG. 48, a cross-sectional view in another exemplary embodiment of the display panel of the present disclosure is shown, wherein the sixth conductive part 86 can be located in the first gate layer, and the sixth conductive part 86 can be connected to the shielding layer through a via. In other exemplary embodiments, the sixth conductive part 86 can also be connected to the first power line VDD in the second source-drain layer through a via. The sixth conductive part located in other conductive layers can be connected to the shielding layer through a via to connect the stable power supply end, the sixth conductive part located in other conductive layers can also be connected to the first power line VDD located in the second source-drain layer through a via to connect the stable power supply end, in addition, the sixth conductive part located in other conductive layers can also be connected to other stable power supply ends in the display panel.

[0177] It should be noted that other structures of the display panel shown in FIG. 24 can be the same as the display panel shown in FIG. 6.

[0178] As shown in FIG. 28, a structure schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure is shown. Compared with the pixel driving circuit shown in FIG. 2, the ninth transistor T9 in the pixel driving circuit shown in FIG. 28 is a P-type transistor.

[0179] The present example embodiment also provides another display panel, which can also include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, a second source-drain layer, and a third source-drain layer arranged in sequence. An insulating layer can be arranged between adjacent layers. As shown in FIGS. 29-45, FIG. 29 is a structural layout of one example embodiment of the display panel of the present disclosure, FIG. 30 is a structural layout of the shielding layer in FIG. 29, FIG. 31 is a structural layout of the first active layer in FIG. 29, FIG. 32 is a structural layout of the first gate layer in FIG. 29, FIG. 33 is a structural layout of the second gate layer in FIG. 29, FIG. 34 is a structural layout of the second active layer in FIG. 29, FIG. 35 is a structural layout of the third gate layer in FIG. 29, FIG. 36 is a structural layout of the first source-drain layer in FIG. 29, FIG. 37 is a structural layout of the second source-drain layer in FIG. 29, FIG. 38 is a structural layout of the third source-drain layer in FIG. 29, FIG. 39 is a structural layout of the shielding layer and the first active layer in FIG. 29, FIG. 40 is a structural layout of the shielding layer, the first active layer, and the first gate layer in FIG. 29, FIG. 41 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG. 29, FIG. 42 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG. 29, FIG. 43 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG. 29, FIG. 44 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer in FIG. 29, and FIG. 45 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in FIG. 29.

[0180] The display panel can include a plurality of pixel driving circuits as shown in FIG. 28, which are arranged in an array in the first direction X and the second direction Y.

[0181] As shown in FIG. 29, the plurality of pixel driving circuits can include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the first direction X, and the first pixel driving circuit P1 and the second pixel driving circuit P2 can be at least partially symmetrically arranged with respect to a mirror symmetry plane AA. The mirror symmetry plane AA can be perpendicular to the substrate. The first pixel driving circuit P1 and the second pixel driving circuit P2 can be at least partially symmetrically arranged with respect to the intersection line of the mirror symmetry plane AA and the substrate as a symmetric axis. The first pixel driving circuit P1 and the second pixel driving circuit P2 can form a repeating unit, and the display panel can include a plurality of repeating units arranged in the first direction X and the second direction Y. The second direction Y and the first direction X can intersect, for example, the first direction X can be a row direction, and the second direction Y can be a column direction. In addition, in the present exemplary embodiment, there can be design errors and process errors in the display panel, and the first pixel driving circuit P1 and the second pixel driving circuit P2 can be substantially symmetrically arranged with respect to the mirror symmetry plane AA.

[0182] As shown in FIGS. 29, 30, and 39, the shielding layer includes a plurality of first shielding portions 81 and a plurality of second connecting portions 82 arranged in the first direction X and the second direction Y, and the first shielding portions 81 are connected to each other by the second connecting portions 82.

[0183] As shown in FIG. 29, 31, 39, 40, the first active layer can include: a first active part 71, a third active part 73, a fourth active part 74, a fifth active part 75, a sixth active part 76, a seventh active part 77, an eighth active part 78, a ninth active part 79, a twentieth active part 720, a twenty-first active part 721, a tenth active part 710, an eleventh active part 711, a twelfth active part 712, a thirteenth active part 713, a fourteenth active part 714, a fifteenth active part 715, a sixteenth active part 716, a seventeenth active part 717, an eighteenth active part 718. The first active part 71 is used to form a channel region of the first transistor T1; the third active part 73 can be used to form a channel region of the driving transistor T3; the fourth active part 74 can be used to form a channel region of the fourth transistor T4; the fifth active part 75 can be used to form a channel region of the fifth transistor T5; the sixth active part 76 can be used to form a channel region of the sixth transistor T6; the seventh active part 77 can be used to form a channel region of the seventh transistor T7; the eighth active part 78 can be used to form a channel region of the eighth transistor T8; the ninth active part 79 can be used to form a channel region of the ninth transistor T9; the twenty-first active part 721 is connected between the third active part 73 and the sixth active part 76; the tenth active part 710 and the twelfth active part 712 are connected at both ends of the eighth active part 78; the eleventh active part 711 is connected between the fourth active part 74 and the third active part 73; the thirteenth active part 713 is connected to a side of the fourth active part 74 away from the third active part 73; the fourteenth active part 714 is connected to a side of the seventh active part 77 away from the sixth active part 76; the fifteenth active part 715 is connected to a side of the fifth active part 75 away from the third active part 73; the sixteenth active part 716 is connected between the seventh active part 77 and the sixth active part 76; the seventeenth active part 717 and the eighteenth active part 718 are connected at both ends of the first active part 71; the twentieth active part 720 and the twenty-second active part 722 are connected at both ends of the ninth active part 79. The first active layer can be formed of a polysilicon material, and accordingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be P-type low-temperature polysilicon thin film transistors.

[0184] The first shielding part 81 can at least partially overlap the third active part 73 in the orthographic projection on the substrate, and the first shielding part 81 can shield the third active part 73 to improve the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure, and the shielding layer can be connected to a stable voltage source, and the shielding layer can shield signals for the pixel driving circuit.

[0185] As shown in FIGS. 29, 30, and 39, the shielding layer further includes a sixth conductive portion 86, the conductive layer where the sixth conductive portion 86 is located is between the active layer where the ninth active portion 79 is located and the substrate, the orthogonal projection of the sixth conductive portion 86 on the substrate and the orthogonal projection of the ninth active portion 79 on the substrate at least partially overlap, and optionally, the orthogonal projection of the sixth conductive portion on the substrate can cover the orthogonal projection of the ninth active portion 79 on the substrate. The sixth conductive portion 86 can be connected to a stable power supply end, and the sixth conductive portion 86 can play a voltage stabilizing role for the sixth conductive portion 86, thereby reducing the gate-source capacitance of the ninth transistor, and further improving the above-mentioned split screen problem. The shielding layer itself includes the first shielding portion 81 and the second connecting portion 82 connected between two adjacent first shielding portions 81 in the second direction Y, and the sixth conductive portion 86 can be connected to the first shielding portion 81 and the second connecting portion 82. For example, the sixth conductive portion 86 can be a protruding portion connected to the second connecting portion 82, and the orthogonal projection of the sixth conductive portion 86 on the substrate can be located on one side of the orthogonal projection of the second connecting portion 82 on the substrate in the first direction X.

[0186] As shown in FIGS. 29, 32, and 40, the first gate layer can include the first conductive part 11, the fifth conductive part 15, the second gate line G2, the enable signal line EM, the first reset signal line Re1, and the second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in FIG. 2; the enable signal line EM can be used to provide the enable signal terminal in FIG. 2; the first reset signal line Re1 can be used to provide the first reset signal terminal in FIG. 2; and the second reset signal line Re2 can be used to provide the second reset signal terminal in FIG. 2. The orthogonal projection of the second gate line G2 on the substrate substrate, the orthogonal projection of the enable signal line EM on the substrate substrate, the orthogonal projection of the first reset signal line Re1 on the substrate substrate, and the orthogonal projection of the second reset signal line Re2 on the substrate substrate can extend along the first direction X. The orthogonal projection of the second gate line G2 on the substrate substrate covers the orthogonal projection of the fourth active part 74 on the substrate substrate, and part of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthogonal projection of the enable signal line EM on the substrate substrate covers the orthogonal projection of the fifth active part 75 on the substrate substrate and the orthogonal projection of the sixth active part 76 on the substrate substrate, and part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5 and the sixth transistor T6, respectively. The orthogonal projection of the first reset signal line Re1 on the substrate substrate can cover the orthogonal projection of the first active part 71 on the substrate substrate, and part of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthogonal projection of the second reset signal line Re2 on the substrate substrate can cover the orthogonal projection of the seventh active part 77 on the substrate substrate and the orthogonal projection of the eighth active part 78 on the substrate substrate, and part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7 and the eighth transistor T8, respectively. The orthogonal projection of the first conductive part 11 on the substrate substrate covers the orthogonal projection of the third active part 73 on the substrate substrate, and the first conductive part 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The orthogonal projection of the fifth conductive part 15 on the substrate substrate covers the orthogonal projection of the ninth active part 79 on the substrate substrate, and at least part of the structure of the fifth conductive part 15 is used to form the gate of the ninth transistor T9.

[0187] The display panel can perform a conductorization process on the first active layer using the first gate layer as a mask, that is, the region of the first active layer covered by the first gate layer can form the channel region of the transistor, and the region of the first active layer not covered by the first gate layer forms the conductor structure.

[0188] As shown in FIGS. 29, 33, 41, the second gate layer can include: a third gate line 2G1, a second conductive part 22, a first connecting part 23, a first initial signal line Vinit1. The third gate line 2G1 has an orthogonal projection on the substrate substrate extending along the first direction X, and the third gate line 2G1 can be used to provide the first gate drive signal end in FIG. 28. The orthogonal projection of the second conductive part 22 on the substrate substrate can at least partially overlap the orthogonal projection of the first conductive part 11 on the substrate substrate, and the second conductive part 22 is used to form the second electrode of the capacitor C. Adjacent second conductive parts 22 in the first direction X can be connected by the first connecting part 23. The first initial signal line Vinit1 is used to provide the first initial signal end in FIG. 2.

[0189] As shown in FIGS. 29, 34, 42, the second active layer can include an active part 9, and the active part 9 can include: a second active part 92, a nineteenth active part 919, and a twenty-third active part 923, and the nineteenth active part 919 and the twenty-third active part 923 are connected to both ends of the second active part 92. The second active part 92 is used to form the channel region of the second transistor T2. The orthogonal projection of the third gate line 2G1 on the substrate substrate can cover the orthogonal projection of the second active part 92 on the substrate substrate, and part of the structure of the third gate line 2G1 can be used to form the bottom gate of the second transistor T2. Among them, the second active layer can be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 can be an N-type metal oxide thin film transistor.

[0190] As shown in FIGS. 29, 35 and 43, the third gate layer can include a first gate line 3G1, a second initial signal line Vinit2, and a third initial signal line Vinit3. The orthogonal projection of the first gate line 3G1 on the substrate substrate, the orthogonal projection of the second initial signal line Vinit2 on the substrate substrate, and the orthogonal projection of the third initial signal line Vinit3 on the substrate substrate can extend along the first direction X. The first gate line 3G1 can be configured to provide the first gate driving signal terminal in FIG. 28, the orthogonal projection of the first gate line 3G1 on the substrate substrate can cover the orthogonal projection of the second active part 92 on the substrate substrate, and part of the structure of the first gate line 3G1 can be configured to form the top gate of the second transistor T2. Meanwhile, the first gate line 3G1 can be connected to the third gate line 2G1 through a via in the display panel frame area. The second initial signal line Vinit2 can be configured to provide the second initial signal terminal in FIG. 28, and the third initial signal line Vinit3 can be configured to provide the third initial signal terminal in FIG. 28. The orthogonal projection of the second initial signal line Vinit2 on the substrate substrate can at least partially coincide with the orthogonal projection of the second reset signal line Re2 in the pixel driving circuit in the same row on the substrate substrate, and the orthogonal projection of the third initial signal line Vinit3 on the substrate substrate at least partially coincides with the orthogonal projection of the enable signal line EM in the pixel driving circuit in the same row on the substrate substrate. This arrangement can improve the light transmittance and integration of the display panel. In addition, the display panel can use the third gate layer as a mask to perform conductorization processing on the second active layer, that is, the region of the second active layer covered by the third gate layer can form the channel region of the transistor, and the region of the second active layer not covered by the third gate layer can form a conductor structure.

[0191] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in other conductive layers, for example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in the second gate layer, the first source-drain layer, etc.

[0192] As shown in FIGS. 29, 36, 44, the first source-drain layer can include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a ninth bridge portion 49, a tenth bridge portion 410, and a fifteenth bridge portion 415. The first bridge portion 41 can be connected to the fifth conductive portion 15 through a via hole to connect the gate of the ninth transistor T9. The second bridge portion 42 can be connected to the twenty-first active portion 721, the nineteenth active portion 919, and the seventeenth active portion 717 through via holes, respectively, to connect the second electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the driving transistor T3. The third bridge portion 43 can be connected to the eighteenth active portion 718 and the first initial signal line Vinit1 through via holes, respectively, to connect the first electrode of the first transistor T1 and the first initial signal terminal. The fourth bridge portion 44 can be connected to the fourteenth active portion 714 and the second initial signal line Vinit2 through via holes, respectively, to connect the first electrode of the seventh transistor T7 and the second initial signal line. The fifth bridge portion 45 can be connected to the thirteenth active portion 713 through a via hole to connect the first electrode of the fourth transistor T4. The sixth bridge portion 46 can be connected to the eleventh active portion 711 and the tenth active portion 710 through via holes, respectively, to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridge portion 47 can be connected to the first connection portion 23 and the fifteenth active portion 715 through via holes, respectively, to connect the second electrode of the capacitor C and the first electrode of the fifth transistor T5. Two fifth active portions 75 in the same repeating unit can be connected through the fifteenth active portion 715, and two pixel driving circuits in the same repeating unit can share the same seventh bridge portion 47. The eighth bridge portion 48 can be connected to the sixteenth active portion 716 through a via hole to connect the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridge portion 49 can be connected to the twentieth active portion 920 and the first conductive portion 11 through via holes, respectively, to connect the gate of the driving transistor T3 and the first electrode of the second transistor T2. An opening 221 can be formed in the second conductive portion 22, and the via hole connected between the ninth bridge portion 49 and the first conductive portion 11 can be disposed in the opening 221. The tenth bridge portion 410 can be connected to the third initial signal line Vinit3 and the twelfth active portion 712 through via holes, respectively, to connect the first electrode of the eighth transistor and the third initial signal line Vinit3. Two eighth active portions 78 in the same repeating unit can be connected through the twelfth active portion 712, and two pixel driving circuits in the same repeating unit can share the same tenth bridge portion 410. The fifteenth bridge portion 415 can be connected to the twenty-third active portion 923 and the twenty-second active portion 722 through via holes, respectively, to connect the second electrode of the ninth transistor T9 and the first electrode of the second transistor T2.

[0193] As shown in FIGS. 29, 36, and 44, the first source-drain layer can further include column initial signal lines Vinitx, a projection of the column initial signal lines Vinitx on the substrate substrate along the second direction Y extends. The column initial signal lines Vinitx can be multiple, and the column initial signal lines Vinitx can be connected to the same row initial signal line intersecting the projection of the column initial signal lines Vinitx on the substrate substrate through a via, so as to form a grid structure of the row initial signal line, which can reduce the voltage difference of the initial signal end at different positions of the display panel. The row initial signal line can include one or more of the first initial signal line, the second initial signal line, and the third initial signal line. For example, three adjacent columns of pixel driving circuits can be respectively provided with initial connection lines Vinitx, wherein one initial connection line Vinitx is connected to the first initial signal line, one initial connection line Vinitx is connected to the second initial signal line, and one initial connection line Vinitx is connected to the third initial signal line.

[0194] As shown in FIGS. 29, 37, and 45, the second source-drain layer can include an eleventh bridge portion 511, a twelfth bridge portion 512, a thirteenth bridge portion 513, and a first power supply line VDD. The eleventh bridge portion 511 can be connected to the first bridge portion 41 through a via. The twelfth bridge portion 512 can be connected to the fifth bridge portion 45 through a via. The thirteenth bridge portion 513 can be connected to the eighth bridge portion 48 through a via. The first power supply line VDD can be used to provide the first power supply end in FIG. 2, and a projection of the first power supply line VDD on the substrate substrate can extend along the second direction Y. The first power supply line VDD can be connected to the seventh bridge portion 47 through a via.

[0195] As shown in FIGS. 29 and 38, the third source-drain layer can include a data line Da, a fourth gate line G4, and a fourteenth bridge portion 614. The data line Da and the fourth gate line G4 can extend along the second direction Y. The data line Da can be used to provide the data signal end in FIG. 2, and the fourth gate line G4 can be used to provide the fourth gate driving signal end in FIG. 2. The data line Da can be connected to the first electrode of the fourth transistor through a via and the connection of the data signal end. The fourth gate line G4 can be connected to the gate electrode of the ninth transistor T9 through a via and the connection of the eleventh bridge portion 511. The fourteenth bridge portion 614 can be connected to the thirteenth bridge portion 513 through a via, and the fourteenth bridge portion 614 can be used to connect the first electrode of the light emitting unit.

[0196] It should be noted that, as shown in FIGS. 29, 44, 45, the black square drawn on the side of the first source-drain layer away from the substrate substrate represents the via of the first source-drain layer connecting the other levels facing the substrate substrate side; the black square drawn on the side of the second source-drain layer away from the substrate substrate represents the via of the second source-drain layer connecting the other levels facing the substrate substrate side; the black square drawn on the side of the third source-drain layer away from the substrate substrate represents the via of the third source-drain layer connecting the other levels facing the substrate substrate side; the black square drawn on the side of the electrode layer away from the substrate substrate represents the via of the electrode layer connecting the other levels facing the substrate substrate side. Different vias represented by black squares at different positions can penetrate different insulating layers.

[0197] As shown in FIG. 46, it is a partial cross-sectional view of the display panel shown in FIG. 29 along the dashed line CC. The display panel can also include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planar layer 108, and a second planar layer 109. Among them, the substrate substrate 100, the shielding layer, the buffer layer 101, the first active layer, the second insulating layer 102, the first gate layer, the third insulating layer 103, the second gate layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third gate layer, the first dielectric layer 106, the first source-drain layer, the passivation layer 107, the first planar layer 108, the second source-drain layer, the second planar layer 109, and the third source-drain layer are sequentially stacked. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 can be a silicon nitride layer; the materials of the first planar layer 108 and the second planar layer 109 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The passivation layer 107 can be a silicon oxide layer. The substrate substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer which are sequentially stacked, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, and niobium or an alloy, or a molybdenum / titanium alloy or a laminated conductive layer. The materials of the first source-drain layer, the second source-drain layer, and the third source-drain layer can include metal materials, which can be one of molybdenum, aluminum, copper, titanium, and niobium or an alloy, or a molybdenum / titanium alloy or a laminated conductive layer, or a titanium / aluminum / titanium laminated conductive layer, etc. The sheet resistance of any one of the first source-drain layer, the second source-drain layer, and the third source-drain layer can be smaller than that of any one of the first gate layer, the second gate layer, and the third gate layer.

[0198] As shown in FIG. 6, the area of the orthographic projection of the ninth active region 99 on the substrate is less than the area of the orthographic projection of the second active region 92 on the substrate. The present exemplary embodiment can reduce the gate-source parasitic capacitance of the ninth transistor T9 by reducing the area of the orthographic projection of the ninth active region 99 on the substrate, thereby improving the split-screen problem.

[0199] Optionally, the length of the channel region of the ninth transistor T9 is less than the length of the channel region of the second transistor T2; and / or, the width of the channel region of the ninth transistor T9 is less than the width of the channel region of the second transistor T2.

[0200] It should be understood that the scheme of reducing the area of the channel region of the ninth transistor can also be applied to the display panel shown in FIG. 24. That is, the scheme of reducing the area of the orthographic projection of the ninth active region 99 on the substrate to improve the split-screen problem and the scheme of stabilizing the voltage of the ninth active region 99 by the sixth conductive region to improve the split-screen problem can be applied to the same display panel. Similarly, the scheme of reducing the area of the channel region of the ninth transistor can also be applied to the display panel shown in FIG. 29, and accordingly, in FIG. 29, the area of the orthographic projection of the ninth active region on the substrate can be less than the area of the orthographic projection of the first active region on the substrate.

[0201] In the present exemplary embodiment, as shown in FIGS. 6, 24, and 29, the orthographic projection of the channel region of the ninth transistor T9 on the substrate is located between the orthographic projection of the second gate line G2 on the substrate and the orthographic projection of the first reset signal line Re1 on the substrate in the same pixel driving circuit.

[0202] In the present exemplary embodiment, as shown in FIGS. 6, 24, and 29, the orthographic projection of the channel region of the ninth transistor T9 on the substrate is located between the orthographic projection of the channel region of the fourth transistor T4 on the substrate and the orthographic projection of the channel region of the second transistor T2 on the substrate in the first direction X of the same pixel driving circuit.

[0203] In the present exemplary embodiment, as shown in FIGS. 6, 24, and 29, the length direction of the channel region of the second transistor is the second direction, and the length direction of the channel region of the ninth transistor is the first direction.

[0204] In the present exemplary embodiment, as shown in FIGS. 6, 24, and 29, the fourth gate line G4 is located in the third source-drain layer. It should be understood that in other exemplary embodiments, the fourth gate line G4 can also be located in the second source-drain layer, the first source-drain layer, or other conductive layers.

[0205] In this example embodiment, as shown in FIGS. 6, 24, and 29, the fourth gate line G4 has an orthogonal projection on the substrate that at least partially overlaps an orthogonal projection of the first power supply line VDD on the substrate. The first power supply line VDD can shield the fourth gate line G4 and other signal terminals from interference.

[0206] In this example embodiment, as shown in FIGS. 6, 24, and 29, the first power supply line VDD includes a first extension VDD1 and a second extension VDD2, the orthogonal projection of the first extension VDD1 on the substrate has a dimension in the first direction X that is greater than a dimension of the orthogonal projection of the second extension VDD2 on the substrate in the first direction, and the orthogonal projection of the fourth gate line G4 on the substrate at least partially overlaps the orthogonal projection of the second extension VDD2 on the substrate.

[0207] In this example embodiment, as shown in FIGS. 6, 24, and 29, the orthogonal projection of the first power supply line VDD on the substrate at least partially overlaps the orthogonal projection of the channel region of the ninth transistor T9 on the substrate. The first power supply line VDD can shield the ninth transistor T9 from light and interference.

[0208] In this example embodiment, as shown in FIGS. 6, 24, and 29, the orthogonal projection of the first power supply line VDD on the substrate at least partially overlaps the orthogonal projection of the second bridge portion 42 on the substrate and / or the orthogonal projection of the ninth bridge portion 49 on the substrate. The first power supply line VDD can shield and stabilize the second bridge portion 42 and the ninth bridge portion 49.

[0209] In this example embodiment, as shown in FIGS. 6, 24, and 29, the first gate line 3G1 includes a third extension 3G13 and a fourth extension 3G14, the third extension 3G13 is used to form a gate of the second transistor T2, the orthogonal projection of the third extension 3G13 on the substrate has a dimension in the second direction Y that is greater than a dimension of the orthogonal projection of the fourth extension 3G14 on the substrate in the second direction Y, the second bridge portion 42 and the first gate line 3G1 are located in different conductive layers, the second bridge portion 42 includes a first sub-bridge portion 421, the orthogonal projection of the first sub-bridge portion 421 on the substrate extends along the second direction Y, and the orthogonal projection of the first sub-bridge portion 421 on the substrate intersects the orthogonal projection of the fourth extension 3G14 on the substrate. This arrangement can reduce the parasitic capacitance between the second bridge portion 42 and the first gate line 3G1.

[0210] In the example embodiment, as shown in FIGS. 6, 24 and 29, the second bridge portion 42 further includes a second sub-bridge portion 422 and a third sub-bridge portion 423. The second sub-bridge portion 422 is connected to the second electrode of the first transistor through a via. The third sub-bridge portion 423 is connected to the second electrode of the second transistor and the second electrode of the driving transistor through a via. The first sub-bridge portion 421 is connected between the second sub-bridge portion 422 and the third sub-bridge portion 423. The angle b between the orthogonal projection of the first sub-bridge portion 421 on the substrate and the orthogonal projection of the second sub-bridge portion 422 on the substrate is less than 180°. The angle a between the orthogonal projection of the first sub-bridge portion 421 on the substrate and the orthogonal projection of the third sub-bridge portion 423 on the substrate is less than 180°.

[0211] As shown in FIGS. 24 and 29, the shielding layer can further include a seventh conductive portion 87. The orthogonal projection of the seventh conductive portion 87 on the substrate covers the orthogonal projection of the via between the ninth bridge portion 49 and the twentieth active portion 720 on the substrate. The via between the ninth bridge portion 49 and the twentieth active portion 720 has a position error when formed, which can cause the light shielding degree of the via to be different in different pixel driving circuits, and further cause the exposure size of the via to be inconsistent. The seventh conductive portion 87 can make the exposure degree of the via consistent and the size of the via consistent in the exposure process.

[0212] In the example embodiment, as shown in FIG. 49, a structure layout of another example embodiment of the display panel of the present disclosure is shown. The orthogonal projection of the fourth gate line G4 on the substrate can be arranged in a bent manner along the second direction Y. This arrangement can increase the overlapping area of the orthogonal projection of the fourth gate line G4 on the substrate and the orthogonal projection of the first power line VDD on the substrate, thereby further improving the shielding effect of the first power line VDD on the fourth gate line G4.

[0213] The example embodiment further provides a display device including the display panel described above. The display device can be a mobile phone, a tablet computer, a television, or the like.

[0214] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0215] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the concepts disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

[0216] It should be understood that the present disclosure is not limited to the precise structures as herein described and illustrated in the drawings, and that various modifications and changes can be made without departing from its scope. The scope of the present disclosure is limited only by the claims that follow.

Claims

1. A display panel, wherein, The display panel includes: Substrate; Multiple pixel driving circuits, wherein the orthographic projections of the multiple pixel driving circuits on the substrate are distributed in an array along a first direction and a second direction, the first direction and the second direction intersecting; The pixel driving circuit includes a driving transistor, a second transistor, and a ninth transistor. The first terminal of the ninth transistor is connected to the gate of the driving transistor, the second terminal of the ninth transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor. A first gate line, whose orthogonal projection on the substrate extends along the first direction, is used to provide a gate drive signal to a second transistor in a plurality of pixel driving circuits distributed in the first direction. A fourth gate line, whose orthogonal projection on the substrate extends along the second direction, is used to provide a gate drive signal to a ninth transistor in a plurality of pixel drive circuits distributed in the second direction.

2. The display panel according to claim 1, wherein, The display panel also includes: A ninth active portion, wherein the ninth active portion is used to form the channel region of the ninth transistor; The sixth conductive part is connected to a stable power supply terminal. The conductive layer where the sixth conductive part is located is located between the active layer where the ninth active part is located and the substrate. The orthographic projection of the sixth conductive part on the substrate and the orthographic projection of the ninth active part on the substrate at least partially overlap.

3. The display panel according to claim 2, wherein, The display panel also includes: A shielding layer is located on one side of the substrate, and the shielding layer includes a first shielding portion; A first active layer is located on the side of the shielding layer away from the substrate. The first active layer includes a third active portion, which is used to form the channel region of the driving transistor. The orthographic projection of the first shielding portion on the substrate and the orthographic projection of the third active portion on the substrate at least partially overlap. The sixth conductive part is located in the shielding layer.

4. The display panel according to claim 3, wherein, The shielding layer also includes: The second connecting portion is connected between two adjacent first blocking portions in the second direction; The sixth conductive part is connected to the second connecting part, and the orthographic projection of the sixth conductive part on the substrate is located on the side of the orthographic projection of the second connecting part on the substrate in the first direction.

5. The display panel according to claim 1, wherein, The display panel also includes: The second active portion is used to form the channel region of the second transistor; A ninth active portion, wherein the ninth active portion is used to form the channel region of the ninth transistor; The second active portion and the ninth active portion are located in the same active layer, and the area of ​​the orthographic projection of the ninth active portion on the substrate is smaller than the area of ​​the orthographic projection of the second active portion on the substrate.

6. The display panel according to claim 5, wherein, The length of the channel region of the ninth transistor is less than the length of the channel region of the second transistor. And / or, the width of the channel region of the ninth transistor is smaller than the width of the channel region of the second transistor.

7. The display panel according to claim 1, wherein, The pixel driving circuit further includes a first transistor, the first terminal of which is connected to a first initial signal line, and the second terminal of which is connected to the second terminal of the driving transistor. The display panel further includes: The first active portion is used to form the channel region of the first transistor; A ninth active portion, wherein the ninth active portion is used to form the channel region of the ninth transistor; The first active portion and the ninth active portion are located in the same active layer, and the area of ​​the orthographic projection of the ninth active portion on the substrate is smaller than the area of ​​the orthographic projection of the first active portion on the substrate.

8. The display panel according to any one of claims 1-7, wherein, The driving transistor and the ninth transistor are P-type transistors, and the display panel further includes: A first active layer is located on one side of the substrate. The first active layer includes a third active portion and a ninth active portion. The third active portion is used to form the channel region of the driving transistor, and the ninth active portion is used to form the channel region of the ninth transistor.

9. The display panel according to any one of claims 1-7, wherein, The driving transistor is a P-type transistor, the ninth transistor is an N-type transistor, and the display panel further includes: A first active layer is located on one side of the substrate. The first active layer includes a third active portion, which is used to form the channel region of the driving transistor. The second active layer is located on the side of the first active layer away from the substrate. The second active layer includes a ninth active portion, which is used to form the channel region of the ninth transistor.

10. The display panel according to any one of claims 1-7, wherein, The pixel driving circuit further includes a first transistor and a fourth transistor. The first terminal of the first transistor is connected to a first initial signal line, the second terminal of the first transistor is connected to the second terminal of the driving transistor, and the first terminal of the fourth transistor is connected to a data line. The second terminal of the fourth transistor is connected to the first terminal of the driving transistor. The display panel also includes: A first reset signal line is located on one side of the substrate. The orthographic projection of the first reset signal line on the substrate extends along a first direction, and a portion of the structure of the first reset signal line is used to form the gate of the first transistor. The second gate line is located on one side of the substrate, and the orthographic projection of the second gate line on the substrate extends along the first direction, and a portion of the structure of the second gate line is used to form the gate of the fourth transistor. In the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first reset signal line on the substrate.

11. The display panel according to any one of claims 1-7, wherein, The pixel driving circuit also includes a fourth transistor, the first terminal of which is connected to the data line and the second terminal of which is connected to the first terminal of the driving transistor. In the first direction of the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor on the substrate is located between the orthographic projection of the channel region of the fourth transistor on the substrate and the orthographic projection of the channel region of the second transistor on the substrate.

12. The display panel according to any one of claims 1-7, wherein, The length direction of the channel region of the second transistor is the second direction, and the length direction of the channel region of the ninth transistor is the first direction.

13. The display panel according to any one of claims 1-7, wherein, The display panel also includes: The first source / drain layer is located on one side of the substrate. The first source / drain layer includes a ninth bridging portion, which is connected to the first electrode of the ninth transistor and the gate of the driving transistor through vias. The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes a first power line, which is used to provide a high-level power signal to the pixel driving circuit. The third source / drain layer is located on the side of the second source / drain layer away from the substrate, and the third source / drain layer includes the fourth gate line.

14. The display panel according to any one of claims 1-7, wherein, The display panel also includes: A first power line is used to provide a high-level power signal to the pixel driving circuit, and the orthographic projection of the first power line on the substrate extends along the second direction. The orthographic projection of the fourth gate line on the substrate and the orthographic projection of the first power line on the substrate at least partially overlap.

15. The display panel according to claim 14, wherein, The first power line includes: a first extension and a second extension, wherein the size of the orthographic projection of the first extension on the substrate in the first direction is greater than the size of the orthographic projection of the second extension on the substrate in the first direction; The orthographic projection of the fourth gate line on the substrate and the orthographic projection of the second extension on the substrate at least partially overlap.

16. The display panel according to any one of claims 1-7, wherein, The display panel also includes: A first power line is located on one side of the substrate. The first power line is used to provide a high-level power signal to the pixel driving circuit. The orthographic projection of the first power line on the substrate and the orthographic projection of the channel region of the ninth transistor on the substrate at least partially overlap.

17. The display panel according to any one of claims 1-7, wherein, The display panel also includes: A first source / drain layer is located on one side of the substrate. The first source / drain layer includes a second bridging portion and a ninth bridging portion. The second bridging portion is connected to the second terminal of the driving transistor and the second terminal of the second transistor through vias, respectively. The ninth bridging portion is connected to the first terminal of the ninth transistor and the gate of the driving transistor through vias, respectively. The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes a first power line, which is used to provide a high-level power signal to the pixel driving circuit. Wherein, the orthographic projection of the first power line on the substrate and the orthographic projection of the second bridging portion on the substrate at least partially overlap, and / or, the orthographic projection of the first power line on the substrate and the orthographic projection of the ninth bridging portion on the substrate at least partially overlap.

18. The display panel according to any one of claims 1-7, wherein, The pixel driving circuit further includes a first transistor, the first terminal of the first transistor being connected to a first initial signal line, and the second terminal of the first transistor being connected to the second terminal of the driving transistor. The display panel also includes: The second bridging portion is located on one side of the substrate. The second bridging portion is connected to the second terminal of the driving transistor, the second terminal of the second transistor, and the second terminal of the first transistor through vias. The first gate line includes a third extension and a fourth extension. The third extension is used to form the gate of the second transistor. The size of the orthogonal projection of the third extension on the substrate in the second direction is larger than the size of the orthogonal projection of the fourth extension on the substrate in the second direction. The second bridging portion and the first gate line are located in different conductive layers. The second bridging portion includes a first sub-bridging portion. The orthographic projection of the first sub-bridging portion on the substrate extends along the second direction. The orthographic projection of the first sub-bridging portion on the substrate and the orthographic projection of the fourth extension portion on the substrate intersect.

19. The display panel according to claim 18, wherein, The second bridging part also includes: The second sub-bridge portion is connected to the second terminal of the first transistor via a via; The third sub-bridge portion is connected to the second terminal of the second transistor and the second terminal of the driving transistor through a via; Wherein, the first sub-bridging portion is connected between the second sub-bridging portion and the third sub-bridging portion, the angle between the orthographic projection of the first sub-bridging portion on the substrate and the orthographic projection of the second sub-bridging portion on the substrate is less than 180°, and the angle between the orthographic projection of the first sub-bridging portion on the substrate and the orthographic projection of the third sub-bridging portion on the substrate is less than 180°.

20. The display panel according to any one of claims 1-7, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit further includes: A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the second terminal of the driving transistor; The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor. The fifth transistor has its first terminal connected to the first power supply line and its second terminal connected to the first terminal of the driving transistor. The sixth transistor has its first terminal connected to the second terminal of the driving transistor, and the second terminal connected to the light-emitting unit; The seventh transistor has its first terminal connected to the second initial signal line and its second terminal connected to the light-emitting unit. The eighth transistor has its first terminal connected to the third initial signal line and its second terminal connected to the first terminal of the driving transistor. The capacitor has a first electrode connected to the gate of the driving transistor and a second electrode connected to the first power supply line. Wherein, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, the second transistor is an N-type transistor, and the ninth transistor is either an N-type transistor or a P-type transistor.

21. The display panel according to claim 1, wherein, The pixel driving circuit includes P-type transistors and N-type transistors, and the display panel further includes: A first active layer is located on one side of the substrate, and a portion of the structure of the first active layer is used to form the channel region of the P-type transistor in the pixel driving circuit. A first gate layer is located on the side of the first active layer away from the substrate, and a portion of the structure of the first gate layer is used to form the gate of the P-type transistor in the pixel driving circuit. The second gate layer is located on the side of the first gate layer away from the substrate, and a portion of the structure of the second gate layer is used to form the bottom gate of the N-type transistor in the pixel driving circuit. The second active layer is located on the side of the second gate layer away from the substrate, and a portion of the structure of the second active layer is used to form the channel region of the N-type transistor in the pixel driving circuit. The third gate layer is located on the side of the second active layer away from the substrate, and a portion of the structure of the third gate layer is used to form the top gate of the N-type transistor in the pixel driving circuit. The first source / drain layer is located on the side of the third gate layer opposite to the substrate, and a portion of the structure of the first source / drain layer is used to form a bridging portion connecting different transistors.

22. A display device, wherein, The display device includes the display panel as described in any one of claims 1-21.

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