Anti-shoot-through driving circuit

Abstract

Embodiments of the present invention provide an anti-shoot-through driving circuit, comprising: a node detection circuit and a first logic control circuit. The node detection circuit is configured to detect the voltage of a switch node, and generate a level indication signal on the basis of the voltage of the switch node, the level indication signal comprises a high-level indication signal and a low-level indication signal, and the switch node is a node between a high-side power transistor and a low-side power transistor. The first logic control circuit is configured to generate a high-side transistor driving signal and a low-side transistor driving signal on the basis of a high-side transistor turn-on signal and the level indication signal output by the node detection circuit, and the high-side transistor turn-on signal is an indication signal, generated internally by a switching power supply and received by the driving circuit, for turning on the high-side power transistor. The present invention solves the problem of shoot-through between the high-side power transistor and the low-side power transistor caused by reducing the driving speed of the power transistors in a use of a driving chip DRIVIER.

Description

Anti-tie-in driving circuit

[0001] Cross Reference to Related Applications

[0002] The present disclosure claims priority to the Chinese Patent Application No. 202410834500.9, filed on June 26, 2024, and entitled “Anti-tie-in driving circuit”, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to an anti-tie-in driving circuit. BACKGROUND

[0004] At present, in a Buck circuit of a step-down converter, when the upper power transistor is turned on, the lower power transistor needs to be detected to be turned off before the upper power transistor is turned on; when the lower power transistor is turned on, the upper power transistor needs to be detected to be turned off before the lower power transistor is turned on; in this way, a dead zone is formed to avoid the upper and lower power transistors being turned on at the same time.

[0005] As shown in FIG. 1, in the application of a driving chip DRIVIER, some applications will add a resistor R0 between the gate (control electrode) GATE of the power transistor and the DRIVIER in order to reduce the driving speed of the power transistor. At this time, the voltage feedback signal of the upper / lower power transistor detected inside the DRIVIER chip has a certain delay from the voltage at the GATE of the power transistor, and cannot correctly reflect whether the power transistor is turned on, which may cause the upper and lower power transistors to be tied in. The following will be specifically described in combination with a waveform diagram.

[0006] FIG. 2 is a working waveform when the two ends of R0 in FIG. 1 are short-circuited, and FIG. 3 is a working waveform when the two ends of R0 in FIG. 1 are not short-circuited. hson is an internal control signal of the DRIVIER chip, when hson = H, the upper power transistor is required to be turned on and the lower power transistor is required to be turned off; when hson = L, the lower power transistor is required to be turned on and the upper power transistor is required to be turned off; when the gate-source voltage of the power transistor (HS, LS) is greater than the threshold voltage, i.e., VGS < VTH, the power transistor is turned off, and vice versa.

[0007] In FIG. 2, the voltage of DRVLA and DRVLB is the same, and the voltage of DRVHA and DRVHB is the same. At this time, the working principle corresponding to FIG. 1 is as follows: when the upper tube HS is turned on, the internal control signal hson changes from L to H, the lower tube driving signal DRVLA quickly changes to low, after the voltage of DRVLA is less than VTH, the lower tube LS is turned off, and after time t0, the upper tube driving signal DRVHA quickly changes to high, and the upper tube HS is turned on; similarly, when the lower tube LS is turned on, the internal control signal hson changes from H to L, the upper tube driving signal DRVHA quickly changes to low, after the voltage difference between DRVHA and SW is less than VTH, the upper tube HS is turned off, and after time t1, the lower tube driving signal DRVLA quickly changes to high, and the lower tube LS is turned on; thus, in time t0 and t1, a dead zone is generated, and the simultaneous turning on of the upper and lower tubes is avoided.

[0008] In FIG. 3, due to the resistance R0, DRVLB has a certain delay compared with DRVLA, and similarly, DRVHB has a certain delay compared with DRVHA. At this time, the working principle corresponding to FIG. 1 is as follows: when the upper tube HS is turned on, the internal control signal hson changes from L to H, the lower tube driving signal DRVLA quickly changes to low, and due to the resistance R0, DRVLB slowly changes to low, after the voltage of DRVLA is less than VTH, the lower tube LS is turned off, after time t0, the upper tube driving signal DRVHA quickly changes to high, and at this time, due to the resistance R0, DRVHB slowly rises, which will cause the voltage of DRVHB and the voltage of DRVLB to be both greater than VTH in time tove rlap1, and the simultaneous turning on of the upper and lower tubes occurs. Similarly, when the lower tube LS is turned on, it will cause the voltage of DRVHB and the voltage of DRVLB to be both greater than VTH in time tove rlap2, and the simultaneous turning on of the upper and lower tubes also occurs.

[0009] For the simultaneous turning on of the upper and lower tubes in FIG. 3, the existing technical solution is to increase a fixed dead zone time t0 / t1 long enough to avoid the simultaneous turning on of the upper and lower tubes. The specific circuit diagram is shown in FIG. 4, wherein the working principle of the rising delay circuit is that when the input signal changes from L to H, it will be delayed for a period of time to change to H, and when the input signal changes from H to L, it will immediately change to low; the delay of the two rising delay circuits in FIG. 4 is t0 and t1 respectively. FIG. 5 is a working waveform diagram corresponding to FIG. 4, wherein when hson changes from L to H, DRVLA immediately changes from H to L, and DRVHA needs to change to high after DRVLA changes to low with a delay of t0; similarly, when hson changes from H to L, DRVLA needs to change to high after DRVHA changes to low with a delay of t1.

[0010] For the solution of FIG. 4, the inventor finds that, due to the uncertainty of the size of the resistance R0, simply increasing the dead time t0 / t1, in combination with FIG. 3, it can be seen that, when the resistance R0 is small, the dead time during normal operation will be increased as a whole, affecting the system efficiency; when the resistance R0 is large, t0>trc1 and t1>trc2 need to be ensured to ensure the existence of the dead zone and avoid the upper and lower tubes from being in series; when the resistance R0 is particularly large, due to the insufficiency of t0 and t1, the upper and lower tubes will be in series.

[0011] In summary, how to better solve the problem of causing the upper and lower tubes to be in series in order to reduce the driving speed of the power tube in the application of the driving chip DRIVIER is urgently needed to be solved. SUMMARY

[0012] The embodiments described herein provide an anti-tie driving circuit to better solve the problem of causing the upper and lower tubes to be in series in order to reduce the driving speed of the power tube in the application of the driving chip DRIVIER.

[0013] According to a first aspect of the present disclosure, an anti-tie driving circuit is provided, the driving circuit is used to drive the upper power tube and the lower power tube of a switching power supply, a resistance is coupled between the driving circuit and the control electrode of the upper power tube and the lower power tube respectively, the driving circuit is used to generate an upper power tube driving signal and a lower power driving signal, and the driving circuit comprises a node detection circuit and a first logic control circuit, wherein the node detection circuit is configured to detect the voltage of a switching node and generate a level indication signal according to the voltage of the switching node, the level indication signal comprises a high level indication signal and a low level indication signal, and the switching node is the node between the upper power tube and the lower power tube; the first logic control circuit is configured to generate an upper tube driving signal and a lower tube driving signal according to an upper tube opening signal and the level indication signal output by the node detection circuit, and the upper tube opening signal is an indication signal generated inside the switching power supply and received by the driving circuit, which needs to open the upper power tube.

[0014] Optionally, the first logic control circuit comprises a first logic control module and a second logic control module, wherein the first logic control module is configured to generate the upper tube driving signal so that the upper tube driving signal is high when the upper tube opening signal changes from low to high and the level indication signal is a high level indication signal; and the second logic control module is configured to generate the lower tube driving signal so that the lower tube driving signal is high when the upper tube opening signal changes from high to low and the level indication signal is a high level indication signal.

[0015] Optionally, the first logic control module comprises: a first to third NAND gate, a first NAND gate, a first to third NOR gate, wherein the input end of the first NAND gate is coupled with the turn-on signal and the first input end of the first NAND gate, the output end of the first NAND gate is coupled with the first input end of the first NOR gate; the second input end of the first NAND gate is coupled with the level indication signal, the output end of the first NAND gate is coupled with the input end of the second NAND gate, the output end of the second NAND gate is coupled with the first input end of the second NOR gate; the second input end of the first NOR gate is coupled with the output end of the second NOR gate, the output end of the first NOR gate is coupled with the second input end of the second NOR gate and the input end of the third NAND gate, the output end of the third NAND gate is coupled with the first input end of the third NOR gate; the second input end of the third NOR gate is coupled with the down tube driving signal output by the second logic control module, and the output end of the third NOR gate outputs the up tube driving signal.

[0016] Optionally, the second logic control module comprises: a fourth to fifth NAND gate, a fourth to seventh NOR gate, wherein the input end of the fourth NAND gate is coupled with the level indication signal, the output end of the fourth NAND gate is coupled with the first input end of the fourth NOR gate; the second input end of the fourth NOR gate is coupled with the turn-on signal and the first input end of the fifth NOR gate, the output end of the fourth NOR gate is coupled with the first input end of the sixth NOR gate; the second input end of the fifth NOR gate is coupled with the output end of the sixth NOR gate, the output end of the fifth NOR gate is coupled with the second input end of the sixth NOR gate and the input end of the fifth NAND gate, the output end of the fifth NAND gate is coupled with the first input end of the seventh NOR gate; the second input end of the seventh NOR gate is coupled with the up tube driving signal output by the first logic control module, and the output end of the seventh NOR gate outputs the down tube driving signal.

[0017] Optionally, the node detection circuit comprises: a first negative detection circuit, wherein the first negative detection circuit is configured to detect the voltage of the switching node, and output the level indication signal according to the positive and negative of the voltage of the switching node, and when the voltage of the switching node is negative, the level indication signal is a high level indication signal.

[0018] Optionally, the node detection circuit comprises: a first forward detection circuit, a second forward detection circuit, a third forward detection circuit, a second negative detection circuit, a third negative detection circuit, and a second logic control circuit. The first forward detection circuit is configured to detect the voltage of the switching node and output a first state indication signal according to the positive or negative of the voltage of the switching node. The first state indication signal comprises a high level indication signal and a low level indication signal. When the voltage of the switching node is positive, the first state indication signal is the high level indication signal. The second forward detection circuit is configured to detect the voltage of the switching node and output a second state indication signal according to the magnitude of the voltage of the switching node. The second state indication signal comprises a high level indication signal and a low level indication signal. When the voltage of the switching node is positive and smaller than the input voltage of the switching power supply, the second state indication signal is the high level indication signal. The third forward detection circuit is configured to detect the voltage of the switching node and output a third state indication signal according to the magnitude of the voltage of the switching node. The third state indication signal comprises a high level indication signal and a low level indication signal. When the voltage of the switching node is greater than the input voltage of the switching power supply, the third state indication signal is the high level indication signal. The second negative detection circuit is configured to detect the voltage of the switching node and output a fourth state indication signal according to the positive or negative of the voltage of the switching node. The fourth state indication signal comprises a high level indication signal and a low level indication signal. When the voltage of the switching node is negative, the fourth state indication signal is the high level indication signal. The third negative detection circuit is configured to detect the voltage of the switching node and output a fifth state indication signal according to the positive or negative of the voltage of the switching node. The fifth state indication signal comprises a high level indication signal and a low level indication signal. When the voltage of the switching node is negative, the fifth state indication signal is the high level indication signal. The second logic control circuit is configured to output the level indication signal according to the first to fifth state indication signals and the gate-on signal. When the gate-on signal changes from low level to high level and the second negative detection circuit or the first forward detection circuit outputs the high level indication signal, the level indication signal is the high level indication signal. When the gate-on signal changes from high level to low level and the third negative detection circuit or the second forward detection circuit or the third forward detection circuit outputs the high level indication signal, the level indication signal is the high level indication signal.

[0019] Optionally, the second logic control circuit comprises: a third logic control module, a fourth logic control module, and a first OR gate, wherein the third logic control module is configured to control the state of the level indication signal by the first state indication signal or the fourth state indication signal when the turn-on signal changes from low level to high level; the fourth logic control module is configured to control the state of the level indication signal by the second state indication signal or the third state indication signal or the fifth state indication signal when the turn-on signal changes from high level to low level; and the first OR gate is configured to couple the output signal of the third logic control module and the output signal of the fourth logic control module respectively, and output the level indication signal.

[0020] Optionally, the third logic control module comprises a second NAND gate, a third NAND gate, a sixth NOT gate, a seventh NOT gate, a second OR gate, a first monostable circuit, and a second monostable circuit, wherein the first input end of the second NAND gate is coupled to the turn-on signal, the second input end of the second NAND gate is coupled to the fourth state indication signal, the output end of the second NAND gate is coupled to the input end of the sixth NOT gate, the output end of the sixth NOT gate is coupled to the input end of the first monostable circuit, the output end of the first monostable circuit is coupled to the first input end of the second OR gate; the first input end of the third NAND gate is coupled to the turn-on signal, the second input end of the third NAND gate is coupled to the first state indication signal, the output end of the third NAND gate is coupled to the input end of the seventh NOT gate, the output end of the seventh NOT gate is coupled to the input end of the second monostable circuit, the output end of the second monostable circuit is coupled to the second input end of the second OR gate, and the output end of the second OR gate is coupled to the first input end of the first OR gate; the fourth logic control module comprises a fourth to sixth NAND gate, an eighth to eleventh NOT gate, a third to fifth monostable circuit, and a third OR gate, wherein the input end of the eighth NOT gate is coupled to the turn-on signal, the output end of the eighth NOT gate is coupled to the first input end of the fourth NAND gate, the first input end of the fifth NAND gate, and the first input end of the sixth NAND gate respectively; the second input end of the fourth NAND gate is coupled to the fifth state indication signal, the output end of the fourth NAND gate is coupled to the input end of the ninth NOT gate, the output end of the ninth NOT gate is coupled to the input end of the third monostable circuit, the output end of the third monostable circuit is coupled to the first input end of the third OR gate; the second input end of the fifth NAND gate is coupled to the second state indication signal, the output end of the fifth NAND gate is coupled to the input end of the tenth NOT gate, the output end of the tenth NOT gate is coupled to the input end of the fourth monostable circuit, the output end of the fourth monostable circuit is coupled to the second input end of the third OR gate; the second input end of the sixth NAND gate is coupled to the third state indication signal, the output end of the sixth NAND gate is coupled to the input end of the eleventh NOT gate, the output end of the eleventh NOT gate is coupled to the input end of the fifth monostable circuit, the output end of the fifth monostable circuit is coupled to the third input end of the third OR gate, and the output end of the third OR gate is coupled to the second input end of the first OR gate.

[0021] Optionally, the drive circuit further comprises a dead time limiting circuit and a fourth OR gate, wherein the dead time limiting circuit is configured to generate a first pulse signal after delaying for a first time length after the turn-on signal changes from low to high, and generate a second pulse signal after delaying for a second time length after the turn-on signal changes from high to low; the fourth OR gate is configured to provide a high-level indication signal to the first logic control circuit from the first pulse signal or the second pulse signal when the level indication signal is low.

[0022] Optionally, the dead time limiting circuit comprises a twelfth NOT gate, a thirteenth NOT gate, a first delay circuit, a second delay circuit, a sixth monostable circuit and a seventh monostable circuit, wherein an input end of the twelfth NOT gate is coupled to the upper tube driving signal, an output end of the twelfth NOT gate is coupled to an input end of the first delay circuit, an output end of the first delay circuit is coupled to an input end of the sixth monostable circuit, and an output end of the sixth monostable circuit outputs the first pulse signal; an input end of the thirteenth NOT gate is coupled to the lower tube driving signal, an output end of the thirteenth NOT gate is coupled to an input end of the second delay circuit, an output end of the second delay circuit is coupled to an input end of the seventh monostable circuit, and an output end of the seventh monostable circuit outputs the second pulse signal.

[0023] Compared with the prior art, the anti-crossing driving circuit of the embodiments of the present disclosure no longer only controls the lower tube driving signal according to the upper tube driving signal, or controls the upper tube driving signal according to the lower tube driving signal, but needs to jointly control the opening of the upper tube and the lower tube in combination with the information of the switching node, avoids the crossing of the upper tube and the lower tube, at the same time, generates the smallest dead zone as possible, and improves the efficiency of the system. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but not limit the present disclosure, wherein:

[0025] FIG. 1 shows a schematic block diagram of a driving chip DRIVIER applied in the prior art;

[0026] FIGS. 2 and 3 show working waveform schematic diagrams in different cases corresponding to FIG. 1;

[0027] FIG. 4 shows an exemplary circuit diagram for solving the crossing phenomenon of the upper tube and the lower tube in the prior art;

[0028] FIG. 5 shows a working waveform schematic diagram corresponding to FIG. 4;

[0029] FIG. 6 shows a schematic block diagram of an anti-crossing driving circuit according to an embodiment of the present disclosure;

[0030] FIG. 7 shows an exemplary circuit diagram of a first logic control circuit according to an embodiment of the present disclosure;

[0031] FIG. 8 shows a schematic block diagram of a node detection circuit according to an embodiment of the present disclosure;

[0032] FIG. 9 shows a working waveform schematic diagram of an anti-crossing driving circuit according to an embodiment of the present disclosure;

[0033] Fig. 10 shows a waveform diagram of the voltage of a switching node varying with the inductor current according to an embodiment of the present disclosure;

[0034] Fig. 11 shows an exemplary circuit diagram of another node detection circuit according to an embodiment of the present disclosure;

[0035] Fig. 12 shows a schematic block diagram of another anti-cross-conduction drive circuit according to an embodiment of the present disclosure;

[0036] Fig. 13 shows a schematic block diagram of a dead-time limiting circuit according to an embodiment of the present disclosure;

[0037] Figs. 14 and 15 show waveform diagrams of the anti-cross-conduction drive circuit according to an embodiment of the present disclosure under different working conditions;

[0038] The elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of, but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present disclosure.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together refer to an indirect or direct connection or coupling.

[0041] In all embodiments of the present disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as a control terminal, and the remaining two terminals of the MOS transistor are referred to as a first terminal and a second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or part of a component) from another component (or another part of a component).

[0042] In order to better solve the problem of the upper and lower power tubes being turned on at the same time caused by the low driving speed of the power tube in the application of the driving chip DRIVIER, a new anti-serial driving circuit structure is proposed. The anti-serial driving circuit of the embodiment of the disclosure is through sampling the information of the switch node SW to make the upper tube or the lower tube conductive at the moment, and adaptively generates the smallest dead zone to avoid the upper and lower tubes being turned on at the same time. The anti-serial driving circuit 100 of the disclosure will be described in detail below.

[0043] First of all, it needs to be pointed out that, as shown in FIG. 6, the driving circuit in the embodiment of the disclosure is used to drive the upper power tube HS and the lower power tube LS of the switching power supply, and the driving circuit is coupled with the control poles of the upper power tube HS and the lower power tube LS through resistors R, respectively. The driving circuit is used to generate the upper power tube driving signal DRVHA and the lower power driving signal DRVLA. In addition, FIG. 6 also shows other devices in the switching power supply, such as inductors L, capacitors C, and loads load.

[0044] FIG. 6 shows a schematic block diagram of the anti-serial driving circuit 100 of the embodiment of the disclosure. As shown in FIG. 6, the anti-serial driving circuit 100 includes a node detection circuit 110 and a first logic control circuit 120.

[0045] Among them, the node detection circuit 110 is configured to detect the voltage of the switch node SW, and generate a level indication signal SWout according to the voltage of the switch node SW. The level indication signal SWout includes a high level indication signal (H) and a low level indication signal (L). The switch node SW is the node between the upper power tube HS and the lower power tube LS. The input end of the node detection circuit 110 is coupled with the switch node SW, and the output end of the node detection circuit 110 is coupled with the first logic control circuit 120.

[0046] The first logic control circuit 120 is configured to generate the upper tube driving signal DRVHA and the lower tube driving signal DRVLA according to the upper-tube-on signal hson and the level indication signal SWout output by the node detection circuit 110. The upper-tube-on signal hson is an indication signal for turning on the upper power tube HS generated by the switching power supply and received by the driving circuit. The first logic control circuit 120 includes a first logic control module and a second logic control module. The first logic control module is configured to generate the upper tube driving signal DRVHA according to the upper-tube-on signal hson and the level indication signal SWout, so that the upper tube driving signal DRVHA is high when the upper-tube-on signal hson changes from low to high and the level indication signal SWout is high. The second logic control module is configured to generate the lower tube driving signal DRVLA according to the upper-tube-on signal hson and the level indication signal SWout, so that the lower tube driving signal DRVLA is high when the upper-tube-on signal hson changes from high to low and the level indication signal SWout is high.

[0047] Further, as shown in FIG. 7, the first logic control module 121 includes a first to third NOT gate (NOT1-NOT3), a first NAND gate NAND1, and a first to third NOR gate (NOR1-NOR3). The input end of the first NOT gate NOT1 is coupled to the upper-tube-on signal hson and the first input end of the first NAND gate NAND1, and the output end of the first NOT gate NOT1 is coupled to the first input end of the first NOR gate NOR1. The second input end of the first NAND gate NAND1 is coupled to the level indication signal SWout, the output end of the first NAND gate NAND1 is coupled to the input end of the second NOT gate NOT2, and the output end of the second NOT gate NOT2 is coupled to the first input end of the second NOR gate NOR2. The second input end of the first NOR gate NOR1 is coupled to the output end of the second NOR gate NOR2, the output end of the first NOR gate NOR1 is coupled to the second input end of the second NOR gate NOR2 and the input end of the third NOT gate NOT3, and the output end of the third NOT gate NOT3 is coupled to the first input end of the third NOR gate NOR3. The second input end of the third NOR gate NOR3 is coupled to the lower tube driving signal DRVLA output by the second logic control module 122, and the output end of the third NOR gate NOR3 outputs the upper tube driving signal DRVHA.

[0048] As shown in FIG. 7, the second logic control module 122 comprises: fourth to fifth NOT gates (NOT4, NOT5), fourth to seventh NOR gates (NOR4-NOR7), wherein the input end of the fourth NOT gate NOT4 is coupled with the level indication signal SWout, the output end of the fourth NOT gate NOT4 is coupled with the first input end of the fourth NOR gate NOR4; the second input end of the fourth NOR gate NOR4 is coupled with the on-off tube signal hson and the first input end of the fifth NOR gate NOR5 respectively, the output end of the fourth NOR gate NOR4 is coupled with the first input end of the sixth NOR gate NOR6; the second input end of the fifth NOR gate NOR5 is coupled with the output end of the sixth NOR gate NOR6, the output end of the fifth NOR gate NOR5 is coupled with the second input end of the sixth NOR gate NOR6 and the input end of the fifth NOT gate NOT5 respectively, the output end of the fifth NOT gate NOT5 is coupled with the first input end of the seventh NOR gate NOR7; the second input end of the seventh NOR gate NOR7 is coupled with the on-off tube driving signal DRVHA output by the first logic control module 121, and the output end of the seventh NOR gate NOR7 outputs the off-tube driving signal DRVLA.

[0049] Further, as shown in FIG. 8, the node detection circuit 110 comprises: a first negative detection circuit 111, wherein the first negative detection circuit 111 is configured to detect the voltage of the switching node SW, and output the level indication signal SWout according to the positive and negative of the voltage of the switching node SW, and when the voltage of the switching node SW is negative, the level indication signal SWout is a high level indication signal, otherwise the level indication signal SWout is a low level indication signal. The design theory of the first negative detection circuit 111 in the embodiment of the present disclosure is explained in combination with FIG. 6: when the upper power tube HS is turned on, the current flows from HS, passes through Lout to Vout, when the upper power tube HS is turned off, HS is not conductive, LS is not conductive, when the two power tubes are not conductive at the same time, because the inductance current will not change suddenly, the voltage of the SW point can only be negative, therefore, when VSW (the voltage of the switching node SW) is detected to be negative, it can be determined that the upper and lower tubes are not conductive, at this time, the upper tube or the lower tube can be turned on, to prevent the upper and lower tubes from being turned on, therefore, detecting that the voltage of the switching node SW is negative can be used as a judgment condition for turning on the upper tube or the lower tube. In addition, it should be noted that in theory, the first negative detection circuit 111 compares VSW with zero voltage when judging the positive and negative of the voltage of the switching node SW, but in actual application, because VSW is negative, the corresponding voltage is -VD, wherein D is the voltage drop of the body diode of the lower power tube LS, in order to detect conveniently and accurately, the first negative detection circuit 111 can be set to compare VSW with a voltage value between 0 and -VD, such as -VD / 2, -VD / 3, etc.

[0050] The principle of the anti-crossing drive circuit in the embodiment of the present disclosure is described below in combination with FIGS. 6-8: 1) when hson changes from L to H, DRVLA is set to L, at this time, due to the resistor R, DRVLB slowly decreases, when DRVLB is less than VTH (the threshold voltage of LS), LS is off, at this time, HS is also in the off state, due to the need for the body diode of LS to continue to flow, VSW≈-VD<0, according to the detection principle of the first negative detection circuit 111, when VSW<0, SWout is a high-level indication signal, that is, SWout=H, then DRVLA=H, and then DRVLB slowly rises, and LS is turned on; 2) when hson changes from H to L, DRVHA is set to L, at this time, due to the resistor R, DRVHB slowly decreases, when DRVHB is less than VTH, HS is off, at this time, LS is also in the off state, due to the need for the body diode of LS to continue to flow, VSW≈-VD<0, according to the detection principle of the first negative detection circuit 111, when VSW<0, SWout is a high-level indication signal, that is, SWout=H, then DRVLA=H, and then DRVLB slowly rises, and LS is turned on.

[0051] In summary, it can be obtained that: when hson changes from L to H, the following conditions need to be met: ① DRVLA is detected to be low; ② the body diode of the lower tube continues to flow; and the upper tube can be turned on; when hson changes from H to L, the following conditions need to be met: ① DRVHA is detected to be low; ② the body diode of the lower tube continues to flow; and the lower tube can be turned on.

[0052] Further, the working waveform diagram corresponding to the anti-crossing drive circuit 100 in the above embodiment is shown in FIG. 9, from top to bottom, it is the waveform diagram of hson, DRVHA, DRVHB, DRVLA, DRVLB, VSW, and the inductance current IL, respectively, t2 and t3 are dead time, from FIG. 9, it can be seen that the anti-crossing drive circuit 100 in the embodiment of the present disclosure reduces the dead time under the premise of avoiding the crossing of the upper and lower tubes.

[0053] For the above embodiment, when the load is small or the inductance current is negative, there is a possibility that HS and LS are closed at the same time, that is, IL can be less than or equal to 0, which will not trigger VSW≈-VD<0, that is, the above embodiment is suitable for heavy load and works in the continuous conduction mode (CCM mode), but is not suitable for small load or negative inductance current.

[0054] In order to solve the problem that the above embodiment is not suitable for small load or negative inductance current, first, all situations of VSW changing with the inductance current (as shown in FIG. 10) are analyzed, and another structure of the node detection circuit 110 is proposed based on the analysis.

[0055] As shown in Fig. 10, there are six cases:

[0056] Among them, when LS is off to HS is on, there are three cases:

[0057] I. IL > 0. Because of the early trigger of zero-crossing detection, DRVLB is low to turn off LS, at this time IL > 0A, the body diode of LS needs to continue to flow, SW can detect a negative pulse, SW ≈ -VD < 0; therefore, after detecting the body diode of LS continues to flow (VSW < 0), as long as hson changes from L to H, HS can be turned on immediately;

[0058] II. IL = 0. Because of the trigger of zero-crossing detection, DRVLB is low to turn off LS, at this time IL = 0A, the body diode of LS does not need to continue to flow, and VSW will be lifted to Vout by Vout through inductor L; therefore, after detecting VSW > 0, as long as hson changes from L to H, HS can be turned on immediately.

[0059] III. IL < 0. Because of the late trigger of zero-crossing detection, DRVLB is low to turn off LS, at this time IL < 0A, IL will lift VSW to Vin+VD until the energy in the inductor is exhausted, so that SW slowly decreases to Vout; therefore, after detecting VSW > 0, as long as hson changes from L to H, HS can be turned on immediately.

[0060] When HS is off to LS is on, there are three other cases:

[0061] IV. IL > 0. When HS is off, because IL > 0A at this time, if LS is not turned on at this time, SW can detect a negative pulse, VSW ≈ -VD < 0, and the body diode of LS continues to flow; therefore, after detecting the body diode of LS continues to flow (VSW < 0), as long as hson changes from H to L, LS can be turned on immediately.

[0062] V. IL = 0. When HS is off, because IL = 0A at this time, if LS is not turned on at this time, VSW is still equal to Vin, and then VSW will be slowly pulled down by Vout; therefore, after detecting SW < Vin, as long as hson changes from H to L, LS can be turned on immediately.

[0063] VI. IL < 0. When HS is off, because IL < 0A at this time, if LS is not turned on at this time, SW ≈ Vin+VD > Vin, and the body diode of HS continues to flow; therefore, after detecting the body diode of HS continues to flow (SW > Vin), as long as hson changes from H to L, LS can be turned on immediately.

[0064] Based on the analysis of the above six cases, another node detection circuit 110 is provided in the embodiments of the present disclosure, and specifically shown in FIG. 11. The node detection circuit 110 includes: a first forward detection circuit 112, a second forward detection circuit 113, a third forward detection circuit 114, a second negative detection circuit 115, a third negative detection circuit 116, a second logic control circuit 117,

[0065] The first forward detection circuit 112 is configured to detect the voltage of the switch node SW, and output a first state indication signal SW1 according to the positive and negative of the voltage of the switch node SW. The first state indication signal SW1 includes a high level indication signal (H) and a low level indication signal (L), and the first state indication signal SW1 is the high level indication signal when the voltage of the switch node SW is positive. The first forward detection circuit 112 corresponds to the second and third cases in the foregoing. In addition, it should be noted that, like the first negative detection circuit 111, the first forward detection circuit 112 is configured to compare VSW with a voltage value greater than 0, instead of zero voltage, for the convenience and accuracy of detection. For example, the voltage value can be set to Vout / 2, and of course can be set to other voltage values between 0 and Vout, or between 0 and Vin+VD.

[0066] The second forward detection circuit 113 is configured to detect the voltage of the switch node SW, and output a second state indication signal SW2 according to the size of the voltage of the switch node SW. The second state indication signal SW2 includes a high level indication signal (H) and a low level indication signal (L), and the second state indication signal SW2 is the high level indication signal when the voltage of the switch node SW is positive and less than the input voltage Vin of the switch power supply. The second forward detection circuit 113 corresponds to the fifth case in the foregoing. In addition, it should be noted that, like the first negative detection circuit 111, the second forward detection circuit 113 is configured to compare VSW with a voltage value less than Vin, instead of Vin, for the convenience and accuracy of detection. For example, the voltage value can be set to (Vin+Vout) / 2, and of course can be set to other voltage values between Vout and Vin.

[0067] The third forward detection circuit 114 is configured to detect the voltage of the switch node SW, and output a third state indication signal SW3 according to the magnitude of the voltage of the switch node SW, the third state indication signal SW3 comprising a high level indication signal (H) and a low level indication signal (L), and the third state indication signal SW3 being the high level indication signal when the voltage of the switch node SW is greater than the input voltage Vin of the switching power supply. The third forward detection circuit 114 corresponds to the VIth case in the foregoing. In addition, it should be noted that, like the first negative detection circuit 111, in order to facilitate and ensure the accuracy of detection, the third forward detection circuit 114 is configured to compare VSW with a voltage value greater than Vin, instead of comparing VSW with Vin, and the voltage value can be set to (Vin+VD) / 2, and of course can be set to other voltage values between 0 and Vin+VD.

[0068] The second negative detection circuit 115 is configured to detect the voltage of the switch node SW, and output a fourth state indication signal SW4 according to the positive or negative of the voltage of the switch node SW, the fourth state indication signal SW4 comprising a high level indication signal (H) and a low level indication signal (L), and the fourth state indication signal SW4 being the high level indication signal when the voltage of the switch node SW is negative. The second negative detection circuit 115 is the same as the first negative detection circuit 111, and will not be described here. It corresponds to the first case in the foregoing.

[0069] The third negative detection circuit 116 is configured to detect the voltage of the switch node SW, and output a fifth state indication signal SW5 according to the positive or negative of the voltage of the switch node SW, the fifth state indication signal SW5 comprising a high level indication signal (H) and a low level indication signal (L), and the fifth state indication signal SW5 being the high level indication signal when the voltage of the switch node SW is negative. The third negative detection circuit 116 is also the same as the first negative detection circuit 111, and will not be described here. It corresponds to the IVth case in the foregoing.

[0070] The second logic control circuit 117 is configured to output a level indication signal SWout according to the first to fifth state indication signals (SW1-SW5) and the on-off signal hson, so that the level indication signal SWout is the high level indication signal when the on-off signal hson changes from low level to high level, and the second negative detection circuit 115 or the first forward detection circuit 112 outputs the high level indication signal, and the level indication signal SWout is the high level indication signal when the on-off signal hson changes from high level to low level, and the third negative detection circuit 116 or the second forward detection circuit 113 or the third forward detection circuit 114 outputs the high level indication signal.

[0071] Further, as shown in FIG. 11, the second logic control circuit 117 comprises a third logic control module 1171, a fourth logic control module 1172, and a first OR gate OR1, wherein the third logic control module 1171 is configured to control the state of the level indication signal SWout by the first state indication signal SW1 or the fourth state indication signal SW4 after the high-on signal hson changes from low to high; the third logic control module 1171 comprises a second NAND gate NAND2, a third NAND gate NAND3, a sixth NOT gate NOT6, a seventh NOT gate NOT7, a second OR gate OR2, a first one-shot circuit oneshot1, and a second one-shot circuit oneshot2, wherein a first input terminal of the second NAND gate NAND2 is coupled to the high-on signal hson, a second input terminal of the second NAND gate NAND2 is coupled to the fourth state indication signal SW4, an output terminal of the second NAND gate NAND2 is coupled to an input terminal of the sixth NOT gate NOT6, an output terminal of the sixth NOT gate NOT6 is coupled to an input terminal of the first one-shot circuit oneshot1, and an output terminal of the first one-shot circuit oneshot1 is coupled to a first input terminal of the second OR gate OR2; a first input terminal of the third NAND gate NAND3 is coupled to the high-on signal hson, a second input terminal of the third NAND gate NAND3 is coupled to the first state indication signal SW1, an output terminal of the third NAND gate NAND3 is coupled to an input terminal of the seventh NOT gate NOT7, an output terminal of the seventh NOT gate NOT7 is coupled to an input terminal of the second one-shot circuit oneshot2, an output terminal of the second one-shot circuit oneshot2 is coupled to a second input terminal of the second OR gate OR2, and an output terminal of the second OR gate OR2 is coupled to a first input terminal of the first OR gate OR1;

[0072] The fourth logic control module 1172 is configured to control the state of the level indication signal SWout by the second state indication signal SW2 or the third state indication signal SW3 or the fifth state indication signal SW5 after the high level of the high-on signal hson changes to low level; the fourth logic control module 1172 comprises a fourth to sixth NAND gate, an eighth to eleventh NOT gate, a third to fifth one-shot circuit, and a third OR gate OR3, wherein the input end of the eighth NOT gate NOT8 is coupled with the high-on signal hson, the output end of the eighth NOT gate NOT8 is respectively coupled with the first input end of the fourth NAND gate NAND4, the first input end of the fifth NAND gate NAND5, and the first input end of the sixth NAND gate NAND6; the second input end of the fourth NAND gate NAND4 is coupled with the fifth state indication signal SW5, the output end of the fourth NAND gate NAND4 is coupled with the input end of the ninth NOT gate NOT9, the output end of the ninth NOT gate NOT9 is coupled with the input end of the third one-shot circuit oneshot3, and the output end of the third one-shot circuit oneshot3 is coupled with the first input end of the third OR gate OR3; the second input end of the fifth NAND gate NAND5 is coupled with the second state indication signal SW2, the output end of the fifth NAND gate NAND5 is coupled with the input end of the tenth NOT gate NOT10, the output end of the tenth NOT gate NOT10 is coupled with the input end of the fourth one-shot circuit oneshot4, and the output end of the fourth one-shot circuit oneshot4 is coupled with the second input end of the third OR gate OR3; the second input end of the sixth NAND gate NAND6 is coupled with the third state indication signal SW3, the output end of the sixth NAND gate NAND6 is coupled with the input end of the eleventh NOT gate NOT11, the output end of the eleventh NOT gate NOT11 is coupled with the input end of the fifth one-shot circuit oneshot5, the output end of the fifth one-shot circuit oneshot5 is coupled with the third input end of the third OR gate OR3, and the output end of the third OR gate OR3 is coupled with the second input end of the first OR gate OR1. It should be noted that the first to fifth one-shot circuits in FIG. 11 all output pulse signals when the rising edges of the input signals are detected.

[0073] The first OR gate OR1 is configured to be coupled with the output signal of the third logic control module 1171 and the output signal of the fourth logic control module 1172 respectively, and output the level indication signal SWout.

[0074] The anti-connection driving circuit corresponding to FIGS. 6, 7 and 11 is different from the anti-connection driving circuit corresponding to FIGS. 6-8 in that the node detection circuit 110, that is, the condition for making the SWout a high level indication signal is different, but the other logics are the same.

[0075] In summary, the working principle of the anti-connection driving circuit corresponding to FIGS. 6, 7 and 11 can be obtained as follows: after the hson changes from L to H, the following conditions need to be met to turn on the lower power tube:

[0076] ① detect DRVLA goes low;

[0077] ② a. detect SW < 0, identify that the LS is in body diode freewheeling;

[0078] b. detect SW > 0, identify that Vout charges SW;

[0079] One of a / b is met, condition ② is true;

[0080] When hson changes from H to L, the following conditions need to be met to turn on the upper power tube:

[0081] ① detect DRVHA goes low;

[0082] ② a. detect SW < 0, the lower power tube is in body diode freewheeling;

[0083] b. detect SW < Vin, Vout discharges SW;

[0084] c. detect SW > Vin, Vout charges SW;

[0085] One of a / b / c is met, condition ② is true.

[0086] In summary, the anti-parallel circuit corresponding to FIGS. 6, 7, and 11 can also reduce the dead time under the premise of avoiding the parallel of the upper and lower tubes, and is suitable for not only heavy load conditions but also light load conditions, and is suitable for both CCM and DCM modes.

[0087] In addition, in the foregoing embodiments, the voltage of the switch node SW needs to be detected, but in actual application, the parasitic capacitance of the SW node may be too large, causing VSW to change slowly and the VSW change information to be undetectable. To address this situation, the embodiment of the present disclosure adds a dead time limiting circuit 130 and a fourth OR gate OR4 on the basis of the foregoing embodiments, as shown in FIG. 12. Specifically, the dead time limiting circuit 130 is coupled to the first logic control circuit 120 and is configured to generate a first pulse signal dly1 after a first time delay after the upper tube opening signal hson changes from low to high, and generate a second pulse signal dly2 after a second time delay after the upper tube opening signal hson changes from high to low. The dead time limiting circuit 130 in the embodiment of the present disclosure is used to limit the maximum dead time.

[0088] The fourth OR gate OR4 is coupled to the first logic control circuit 120 and is configured to provide a high-level indication signal to the first logic control circuit 120 from the first pulse signal dly1 or the second pulse signal dly2 when the level indication signal SWout is low.

[0089] Further, as shown in FIG. 13, the dead time limiting circuit 130 includes a twelfth NOT gate NOT12, a thirteenth NOT gate NOT13, a first delay circuit 131, a second delay circuit 132, a sixth one-shot circuit oneshot6, and a seventh one-shot circuit oneshot7. The input terminal of the twelfth NOT gate NOT12 is coupled to the upper tube driving signal DRVHA, the output terminal of the twelfth NOT gate NOT12 is coupled to the input terminal of the first delay circuit 131, the output terminal of the first delay circuit 131 is coupled to the input terminal of the sixth one-shot circuit oneshot6, and the output terminal of the sixth one-shot circuit oneshot6 outputs a first pulse signal dly1. The input terminal of the thirteenth NOT gate NOT13 is coupled to the lower tube driving signal DRVLA, the output terminal of the thirteenth NOT gate NOT13 is coupled to the input terminal of the second delay circuit 132, the output terminal of the second delay circuit 132 is coupled to the input terminal of the seventh one-shot circuit oneshot7, and the output terminal of the seventh one-shot circuit oneshot7 outputs a second pulse signal dly2. The sixth one-shot circuit oneshot6 and the seventh one-shot circuit oneshot7 are configured to generate a pulse signal, for example, a 5 ns pulse signal, when detecting a rising edge of an input signal.

[0090] The working principle of the anti-crossing driving circuit 100 in the embodiment of the present disclosure is described in combination with the circuit diagrams in FIGS. 12 and 13. It is assumed that the delay of the first delay circuit 131 is T1 and the delay of the second delay circuit 132 is T2. After hson changes from L to H, DRVLA becomes low, and after passing through the second delay circuit 132, it is delayed by T2 to generate the second pulse signal dly2. If SWout = H (the parasitic capacitance of the SW node is not large, and the change speed of VSW is fast, so that the VSW change information can be detected, and the condition for making SWout high in the foregoing embodiment is met), it is indicated that DRVHA has become high. If SWout = L (the parasitic capacitance of the SW node is too large, so that the change of VSW is very slow, and the SW change information cannot be detected, and SWout is always L), DRVHA is set to H by the pulse signal of dly2. Similarly, after hson changes from H to L, DRVHA becomes low, and after passing through the first delay circuit 131, it is delayed by T1 to generate the first pulse signal dly1. If SWout = H (the parasitic capacitance of the SW node is not large, and the change speed of VSW is fast, so that the VSW change information can be detected, and the condition for making SWout high in the foregoing embodiment is met), it is indicated that DRVLA has become high. If SWout = L (the parasitic capacitance of the SW node is too large, so that the change of VSW is very slow, and the SW change information cannot be detected, and SWout is always L), DRVLA is set to high by the pulse signal of dly1.

[0091] Further, FIG. 14 and 15 respectively show the corresponding waveform diagrams in the case of too large SW node parasitic capacitance and the case of not too large SW node parasitic capacitance. Wherein, T1 and T2 are the corresponding delays of the first delay circuit 131 and the second delay circuit 132 respectively, in FIG. 14, it can be seen that SWout is always low, after hson changes from L to H, T2 time is passed, making DRVHA flip high; after hson changes from H to L, T1 time is passed, making DRVLA flip high. The actual dead time in FIG. 14 is t4, t5. It should be noted that in actual application, in order to minimize the dead time t4, t5, the capacitance of the SW node needs to be known, and T1, T2 needs to be reasonably configured.

[0092] In FIG. 15, after hson changes from L to H, SWout will change high when the condition of making SWout high in the foregoing embodiment is met, and when SWout is high, DRVHA is flipped high; after hson changes from H to L, SWout will change high when the condition of making SWout high in the foregoing embodiment is met, and when SWout is high, DRVLA is flipped high. The actual dead time in FIG. 15 is t6, t7.

[0093] In summary, the anti-creep driving circuit 100 in the embodiment of the present disclosure reduces the dead time under the premise of avoiding the creep of the upper and lower tubes.

[0094] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular form of a word includes the plural and vice versa. Thus, the use of the singular will include the plural unless specifically stated otherwise. Similarly, the use of the word "comprise" or "comprises" or "include" or "includes" will be understood to encompass the saying "consisting of" or "consisting" or "comprising" or "comprises" unless otherwise indicated. As used herein, the term "example" is used to mean "an example of" and not "an example that excludes others". Thus, the use of the term "example" in the context of this document is not a disclaimer of others.

[0095] Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended to be illustrative only and are not intended to limit the scope of the present disclosure.

[0096] The above has described in detail several embodiments of the present disclosure, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A drive circuit for preventing crosstalk, wherein the drive circuit is used to drive an upper power transistor and a lower power transistor of a switching power supply, wherein the drive circuit is coupled to the control terminals of the upper power transistor and the lower power transistor respectively by resistors, and the drive circuit is used to generate an upper power transistor drive signal and a lower power transistor drive signal, characterized in that, The driving circuit comprises a node detection circuit, a first logic control circuit, The node detection circuit is configured to detect the voltage of a switching node and generate a level indication signal according to the voltage of the switching node, the level indication signal comprising a high level indication signal and a low level indication signal, the switching node being a node between the upper power tube and the lower power tube. The first logic control circuit is configured to generate an upper tube driving signal and a lower tube driving signal according to an upper tube opening signal and the level indication signal output by the node detection circuit, the upper tube opening signal being an indication signal generated by the switching power supply and received by the driving circuit, the indication signal indicating that the upper power tube needs to be turned on.

2. The anti-tie-in driving circuit according to claim 1, characterized by The first logic control circuit comprises a first logic control module and a second logic control module, The first logic control module is configured to generate the upper tube driving signal according to the upper tube opening signal and the level indication signal, the upper tube driving signal being high when the upper tube opening signal changes from low to high and the level indication signal is a high level indication signal. The second logic control module is configured to generate the lower tube driving signal according to the upper tube opening signal and the level indication signal, the lower tube driving signal being high when the upper tube opening signal changes from high to low and the level indication signal is a high level indication signal.

3. The anti-tie-in driving circuit according to claim 2, characterized by The first logic control module comprises a first to third NAND gate, a first NAND gate, a first to third NOR gate, The input end of the first NAND gate is coupled to the upper tube opening signal and the first input end of the first NAND gate, the output end of the first NAND gate is coupled to the first input end of the first NOR gate; the second input end of the first NAND gate is coupled to the level indication signal, the output end of the first NAND gate is coupled to the input end of the second NAND gate, the output end of the second NAND gate is coupled to the first input end of the second NOR gate; the second input end of the first NOR gate is coupled to the output end of the second NOR gate, the output end of the first NOR gate is coupled to the second input end of the second NOR gate and the input end of the third NAND gate, the output end of the third NAND gate is coupled to the first input end of the third NOR gate; the second input end of the third NOR gate is coupled to the lower tube driving signal output by the second logic control module, and the output end of the third NOR gate outputs the upper tube driving signal.

4. The anti-tie-in driving circuit according to claim 3, characterized by The second logic control module comprises a fourth to fifth NAND gate and a fourth to seventh NOR gate, The input end of the fourth NOT gate is coupled with the level indication signal, and the output end of the fourth NOT gate is coupled with the first input end of the fourth OR gate; the second input end of the fourth OR gate is coupled with the on-pipe signal and the first input end of the fifth OR gate, and the output end of the fourth OR gate is coupled with the first input end of the sixth OR gate; the second input end of the fifth OR gate is coupled with the output end of the sixth OR gate, the output end of the fifth OR gate is coupled with the second input end of the sixth OR gate and the input end of the fifth NOT gate, and the output end of the fifth NOT gate is coupled with the first input end of the seventh OR gate; the second input end of the seventh OR gate is coupled with the up-pipe driving signal output by the first logic control module, and the output end of the seventh OR gate outputs the down-pipe driving signal.

5. The anti-tie-in driving circuit according to claim 2, wherein The node detection circuit comprises a first negative detection circuit, The first negative detection circuit is configured to detect the voltage of the switching node and output the level indication signal according to the positive and negative of the voltage of the switching node, and the level indication signal is a high-level indication signal when the voltage of the switching node is negative.

6. The anti-tie-in drive circuit according to claim 2, characterized by The node detection circuit comprises a first positive detection circuit, a second positive detection circuit, a third positive detection circuit, a second negative detection circuit, a third negative detection circuit, and a second logic control circuit, The first positive detection circuit is configured to detect the voltage of the switching node and output the first state indication signal according to the positive and negative of the voltage of the switching node, and the first state indication signal comprises a high-level indication signal and a low-level indication signal, and the first state indication signal is a high-level indication signal when the voltage of the switching node is positive. The second positive detection circuit is configured to detect the voltage of the switching node and output the second state indication signal according to the size of the voltage of the switching node, and the second state indication signal comprises a high-level indication signal and a low-level indication signal, and the second state indication signal is a high-level indication signal when the voltage of the switching node is positive and smaller than the input voltage of the switching power supply. The third positive detection circuit is configured to detect the voltage of the switching node and output the third state indication signal according to the size of the voltage of the switching node, and the third state indication signal comprises a high-level indication signal and a low-level indication signal, and the third state indication signal is a high-level indication signal when the voltage of the switching node is greater than the input voltage of the switching power supply. The second negative detection circuit is configured to detect the voltage of the switching node and output the fourth state indication signal according to the positive and negative of the voltage of the switching node, and the fourth state indication signal comprises a high-level indication signal and a low-level indication signal, and the fourth state indication signal is a high-level indication signal when the voltage of the switching node is negative. The third negative detection circuit is configured to detect the voltage of the switching node, and output a fifth state indication signal according to the positive and negative of the voltage of the switching node, the fifth state indication signal comprising a high level indication signal and a low level indication signal, and the fifth state indication signal being the high level indication signal when the voltage of the switching node is negative; The second logic control circuit is configured to output the level indication signal according to the first to fifth state indication signals and the on-off tube signal, the level indication signal being the high level indication signal when the on-off tube signal changes from the low level to the high level and the second negative detection circuit or the first positive detection circuit outputs the high level indication signal, and the level indication signal being the high level indication signal when the on-off tube signal changes from the high level to the low level and the third negative detection circuit or the second positive detection circuit or the third positive detection circuit outputs the high level indication signal.

7. The anti-tie-in drive circuit according to claim 6, characterized by The second logic control circuit comprises a third logic control module, a fourth logic control module and a first OR gate, The third logic control module is configured to control the state of the level indication signal by the first state indication signal or the fourth state indication signal when the on-off tube signal changes from the low level to the high level. The fourth logic control module is configured to control the state of the level indication signal by the second state indication signal or the third state indication signal or the fifth state indication signal when the on-off tube signal changes from the high level to the low level. The first OR gate is configured to output the level indication signal by coupling the output signal of the third logic control module and the output signal of the fourth logic control module.

8. The anti-tie-in drive circuit according to claim 7, characterized by The third logic control module comprises a second NAND gate, a third NAND gate, a sixth NOT gate, a seventh NOT gate, a second OR gate, a first single trigger circuit and a second single trigger circuit, the first input end of the second NAND gate being coupled to the on-off tube signal, the second input end of the second NAND gate being coupled to the fourth state indication signal, the output end of the second NAND gate being coupled to the input end of the sixth NOT gate, the output end of the sixth NOT gate being coupled to the input end of the first single trigger circuit, the output end of the first single trigger circuit being coupled to the first input end of the second OR gate; the first input end of the third NAND gate being coupled to the on-off tube signal, the second input end of the third NAND gate being coupled to the first state indication signal, the output end of the third NAND gate being coupled to the input end of the seventh NOT gate, the output end of the seventh NOT gate being coupled to the input end of the second single trigger circuit, the output end of the second single trigger circuit being coupled to the second input end of the second OR gate, and the output end of the second OR gate being coupled to the first input end of the first OR gate. The fourth logic control module comprises a fourth to sixth NAND gate, an eighth to eleventh NAND gate, a third to fifth monostable circuit, and a third OR gate, wherein an input end of the eighth NAND gate is coupled to the turn-on signal, output ends of the eighth NAND gate are respectively coupled to a first input end of the fourth NAND gate, a first input end of the fifth NAND gate, and a first input end of the sixth NAND gate, a second input end of the fourth NAND gate is coupled to the fifth state indication signal, an output end of the fourth NAND gate is coupled to an input end of the ninth NAND gate, an output end of the ninth NAND gate is coupled to an input end of the third monostable circuit, an output end of the third monostable circuit is coupled to a first input end of the third OR gate, a second input end of the fifth NAND gate is coupled to the second state indication signal, an output end of the fifth NAND gate is coupled to an input end of the tenth NAND gate, an output end of the tenth NAND gate is coupled to an input end of the fourth monostable circuit, an output end of the fourth monostable circuit is coupled to a second input end of the third OR gate, and a second input end of the sixth NAND gate is coupled to the third state indication signal, an output end of the sixth NAND gate is coupled to an input end of the eleventh NAND gate, an output end of the eleventh NAND gate is coupled to an input end of the fifth monostable circuit, an output end of the fifth monostable circuit is coupled to a third input end of the third OR gate, and an output end of the third OR gate is coupled to a second input end of the first OR gate.

9. The anti-tamper driving circuit according to claim 5 or 6, wherein The drive circuit further comprises a dead time limiting circuit and a fourth OR gate. The dead time limiting circuit is configured to generate a first pulse signal after a first time length after the turn-on signal changes from low to high, and generate a second pulse signal after a second time length after the turn-on signal changes from high to low. The fourth OR gate is configured to provide a high-level indication signal for the first logic control circuit from the first pulse signal or the second pulse signal when the level indication signal is low.

10. The anti-tie-in drive circuit according to claim 9, characterized by The dead time limiting circuit comprises a twelfth NAND gate, a thirteenth NAND gate, a first delay circuit, a second delay circuit, a sixth monostable circuit, and a seventh monostable circuit. An input end of the twelfth NAND gate is coupled to the upper tube driving signal, an output end of the twelfth NAND gate is coupled to an input end of the first delay circuit, an output end of the first delay circuit is coupled to an input end of the sixth monostable circuit, and an output end of the sixth monostable circuit outputs the first pulse signal. An input end of the thirteenth NAND gate is coupled to the lower tube driving signal, an output end of the thirteenth NAND gate is coupled to an input end of the second delay circuit, an output end of the second delay circuit is coupled to an input end of the seventh monostable circuit, and an output end of the seventh monostable circuit outputs the second pulse signal.

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