Communication method and communication apparatus

Abstract

An LDPC-code-based communication method and communication apparatus. In the method, a device can perform encoding or decoding on the basis of an LDPC matrix, wherein the LDPC matrix is determined on the basis of an LDPC base matrix, the base matrix comprises an extended check matrix, the extended check matrix is a lower triangular matrix with diagonal elements all being 1, the extended check matrix comprises a plurality of lower triangular matrices, diagonal elements of each of the plurality of lower triangular matrices are located on the diagonal of the extended check matrix, the positions of the diagonal elements of the plurality of lower triangular matrices do not overlap, and the elements in the extended check matrix other than the diagonal elements of the extended check matrix and the diagonal elements of the plurality of lower triangular square matrices are all zero elements. The method can increase the column weight of a check region, reduce the occurrence probability of an error plane, and also support retransmissions at some specific columns, and thus the method is compatible with an IR-HARQ scheme of 5G LDPC codes.

Description

Communication method and communication apparatus

[0001] This application claims priority to the Chinese Patent Application No. 202410825776.0, filed on June 24, 2024, entitled “Communication method and communication apparatus”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of coding, and more particularly, to a communication method and a communication apparatus. BACKGROUND

[0003] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low density parity check (QC-LDPC) codes are a class of structured LDPC codes. Due to the unique structure of the parity check matrix, a simple feedback shift register can be used for encoding, which reduces the encoding complexity of LDPC codes. In the design of the LDPC base graph for the 5th generation (5G) system, the extended parity check region adopts a raptor-like structure, i.e., the extended parity check region is a unit matrix, and in the extended parity check region, the row weight of each row is equal to 1 and the column weight of each column is equal to 1. The disadvantage of the raptor-like structure is that the column weight is only 1 in this region, so density evolution cannot occur, and in addition, the raptor-like node is prone to error floor in the high reliability region.

[0004] In one possible implementation, the extended parity check region can be designed as a lower triangular structure to overcome the above-mentioned disadvantages. However, the lower triangular structure is not compatible with the incremental redundancy hybrid automatic repeat request (IR-HARQ) scheme of the current 5G LDPC code, i.e., it cannot be used for IR-HARQ at a specified position. It can be understood that the specified position is the starting column of the redundancy version (RV) set in the 5G LDPC base graph. SUMMARY

[0005] Embodiments of the present application provide a communication method and a communication apparatus, which can be compatible with the IR-HARQ scheme of the 5G LDPC code.

[0006] In a first aspect, a communication method is provided, which can be performed by a transmitting device. In the absence of a special description, the "transmitting device" in the present application can refer to the transmitting device itself (for example, a network device or a terminal device), a component (for example, a processor, a chip, or a chip system) in the transmitting device, or a logic module or software capable of realizing all or part of the functions of the transmitting device.

[0007] The method comprises: obtaining an information bit sequence; determining an LDPC check matrix, the LDPC check matrix being determined based on an LDPC base matrix, the base matrix comprising an extended check matrix, the extended check matrix being a lower triangular matrix with diagonal elements being 1, wherein the extended check matrix comprises a plurality of lower triangular matrices, the diagonal elements of each lower triangular matrix in the plurality of lower triangular matrices being located on the diagonal line of the extended check matrix, the positions of the diagonal elements of the plurality of lower triangular matrices not overlapping, and the remaining elements in the extended check matrix except the diagonal elements of the extended matrix and the plurality of lower triangular matrices being 0 elements; encoding the information bit sequence according to the LDPC check matrix to obtain a codeword sequence; and outputting the codeword sequence.

[0008] In the above technical solution, the Raptor Like structure of the extended check region of the 5G LDPC base graph can be changed into the structure of a plurality of lower triangular matrices in cascade, which can not only improve the column weight of the check region and reduce the probability of error floor, but also support retransmission of some specific columns, thereby being compatible with the IR-HARQ scheme of the 5G LDPC code.

[0009] In a second aspect, a communication method is provided, which can be performed by a receiving device. In the absence of a special description, the "receiving device" in the present application can refer to the receiving device itself (for example, a network device or a terminal device), a component (for example, a processor, a chip, or a chip system) in the receiving device, or a logic module or software capable of realizing all or part of the functions of the receiving device.

[0010] The method comprises: obtaining a symbol sequence; determining an LDPC check matrix, the LDPC check matrix being determined based on an LDPC base matrix, the base matrix comprising an extended check matrix, the extended check matrix being a lower triangular matrix with diagonal elements being 1, wherein the extended check matrix comprises a plurality of lower triangular matrices, the diagonal elements of each lower triangular matrix in the plurality of lower triangular matrices being located on the diagonal line of the extended check matrix, the positions of the diagonal elements of the plurality of lower triangular matrices not overlapping, and the remaining elements in the extended check matrix except the diagonal elements of the extended matrix and the plurality of lower triangular matrices being 0 elements; and decoding the symbol sequence based on the LDPC check matrix to obtain an information bit sequence.

[0011] The beneficial effects of the second aspect are described in relation to the first aspect and will not be repeated here.

[0012] In some implementations of the first aspect or the second aspect, a first diagonal element of the first lower triangular matrix has a first characteristic, where the first lower triangular matrix is any of the plurality of lower triangular matrices, the first diagonal element is a diagonal element of the first lower triangular matrix other than the first diagonal element, and the first characteristic is that elements in a region formed by a column preceding a column in which the first diagonal element is located and a first column and a last row of the first lower triangular matrix are not all zeros.

[0013] In some implementations of the first aspect or the second aspect, a starting column of one redundancy version (RV) of the base matrix corresponds to a starting column of one lower triangular matrix of the plurality of lower triangular matrices.

[0014] The above technical solution only indicates that there is one starting column of one RV corresponding to one starting column of one lower triangular matrix. In practice, there can be XI starting columns of XI RVs corresponding to XI starting columns of XI lower triangular matrices of the plurality of lower triangular matrices, where XI is an integer greater than 1. For example, the starting columns of the RVs of the base matrix correspond to all columns in a first column set, and the first column set includes the starting columns of the plurality of lower triangular matrices, or the first column set includes columns other than the first column of the extended parity check matrix among the starting columns of the plurality of lower triangular matrices.

[0015] In some implementations of the first aspect or the second aspect, a starting column of one RV of the base matrix corresponds to one column in a second column set, where the second column set includes columns in which diagonal elements other than all diagonal elements of the plurality of lower triangular matrices are located.

[0016] The above technical solution only indicates that there is one starting column of one RV corresponding to one column in the second column set. In practice, there can be X2 starting columns of X2 RVs corresponding to X2 columns in the second column set, where X2 is an integer greater than 1.

[0017] In some implementations of the first aspect or the second aspect, a union of positions of the diagonal elements of the plurality of lower triangular matrices is equal to a set corresponding to positions of all diagonal elements of the extended parity check matrix.

[0018] The above technical solution can be regarded as that the positions of all diagonal elements of the extended parity check matrix are occupied by the diagonal elements of the plurality of lower triangular matrices. In the cascading manner of the plurality of lower triangular matrices, the column weights of the extended parity check matrix are not all 1, so the matrix has better evolution characteristics and lower error floor, while it can also support retransmission in some specific columns.

[0019] In some implementations of the first aspect or the second aspect, at least one of the plurality of lower triangular matrices corresponds to a second feature, the second feature is that column weights of N columns after a last column of the second lower triangular matrix are all 1, and N rows after a last row of the second lower triangular matrix correspond to rows in the expanded check matrix whose row weights are all 1, the second lower triangular matrix is any one of the at least one lower triangular matrix, N is greater than or equal to 1, and a next column of the N columns after the last column of the second lower triangular matrix is a first column of another lower triangular matrix in the plurality of lower triangular matrices.

[0020] The above technical solution can realize the alternative concatenation of the lower triangular structure and the raptor like structure. The scheme can construct a mixed structure of the lower triangular structure and the raptor like structure in a plurality of regions corresponding to a plurality of RVs. Since the plurality of regions all have nodes with a degree of 1, the degree distribution of the whole can be made more reasonable, and the threshold performance is thus improved.

[0021] In some implementations of the first aspect or the second aspect, positions of diagonal elements of the plurality of lower triangular matrices are consecutive positions on a diagonal line of the expanded check matrix, and only a third lower triangular matrix in the plurality of lower triangular matrices corresponds to the second feature, and a first column of the third lower triangular matrix is located after a last column of any matrix in a first matrix set, and the first matrix set includes remaining matrices in the plurality of lower triangular matrices except the third lower triangular matrix.

[0022] In the above technical solution, the raptor like structure is concatenated after the last lower triangular matrix in the plurality of lower triangular matrices. The density of the lower triangular matrix is too high, and the decoding threshold is lost. The advantage of the scheme is that when the code rate is low, the point with a degree of 1 is introduced, and the decoding threshold performance is improved.

[0023] In some implementations of the first aspect or the second aspect, a starting column of a redundancy version (RV) of the base matrix corresponds to a starting column of a lower triangular matrix in the plurality of lower triangular matrices, and a starting column of an RV of the base matrix corresponds to a next column of a last column of the third lower triangular matrix.

[0024] In some implementations of the first aspect or the second aspect, N is greater than or equal to 2, and the starting column of the RV of the base matrix further corresponds to a column in a third column set, and the third column set is a set of remaining columns except a first column in N columns after the last column of the third lower triangular matrix.

[0025] In a third aspect, a communication apparatus is provided. The apparatus is configured to execute the method in any of the preceding aspects or implementation manners. Specifically, the apparatus can include units and / or modules for performing the method in any of the preceding aspects or implementation manners, such as a processing unit and / or a transceiving unit.

[0026] In an implementation manner, the apparatus is a sending device or a receiving device. When the apparatus is the sending device or the receiving device, the transceiving unit can be a transceiver, or an input / output interface, or a communication interface; and the processing unit can be at least one processor. Optionally, the transceiver is a transceiving circuit. Optionally, the input / output interface is an input / output circuit.

[0027] In another implementation manner, the apparatus is a chip, a chip system, or a circuit for the sending device or the receiving device. When the apparatus is the chip, the chip system, or the circuit for the sending device or the receiving device, the transceiving unit can be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin, or related circuitry, etc. on the chip, the chip system, or the circuit; and the processing unit can be at least one processor, a processing circuit, or a logic circuit, etc.

[0028] In a fourth aspect, a communication apparatus is provided. The apparatus includes a memory configured to store a program; and at least one processor configured to execute the computer program or instructions stored in the memory to perform the method in any of the preceding aspects or implementation manners.

[0029] In an implementation manner, the apparatus is a sending device or a receiving device.

[0030] In another implementation manner, the apparatus is a chip, a chip system, or a circuit for the sending device or the receiving device.

[0031] In a fifth aspect, a communication apparatus is provided. The apparatus includes at least one processor and a communication interface. The at least one processor is configured to acquire, through the communication interface, a computer program or instructions stored in a memory to perform the method in any of the preceding aspects or implementation manners. The communication interface can be implemented by hardware or software.

[0032] In an implementation manner, the apparatus further includes the memory.

[0033] In a sixth aspect, a processor is provided. The processor is configured to perform the method in any of the preceding aspects.

[0034] For the sending and obtaining / receiving operations involved by the processor, if no special description is made, or if it does not conflict with the actual role or internal logic in the related description, it can be understood as the processor output and receive, input, etc. Operation, but also can be understood as the sending and receiving operations performed by the radio frequency circuit and the antenna, and the present application does not limit this.

[0035] In a seventh aspect, a computer readable storage medium is provided, which stores program codes for execution by an apparatus, and the program codes comprise codes for performing the method provided in any of the aspects or the implementation manners thereof.

[0036] In an eighth aspect, a computer program product containing instructions, which, when run on a computer, causes the computer to perform the method provided in any of the aspects or the implementation manners thereof.

[0037] In a ninth aspect, a chip is provided, which comprises a processor and a communication interface, and the processor reads instructions stored on a memory through the communication interface and executes the method provided in any of the aspects or the implementation manners thereof. The communication interface can be realized by hardware or software.

[0038] Optionally, as an implementation manner, the chip further comprises a memory, and the memory stores a computer program or instructions, and the processor is configured to execute the computer program or instructions stored in the memory, and when the computer program or instructions are executed, the processor is configured to execute the method provided in any of the aspects or the implementation manners thereof.

[0039] When the method provided in the present application is executed by a chip, the present application does not limit the number of chips for specifically implementing the method of the present application, for example, it can be executed by one chip, or two or more chips. Moreover, when the number of chips for implementing the method of the present application is two or more, the chip manufacturers are not limited, which can be the same manufacturer or different manufacturers.

[0040] In a tenth aspect, a computer program is provided, which, when run on a computer, causes the method provided in any of the aspects or the implementation manners thereof to be executed.

[0041] In an eleventh aspect, a communication system is provided, which comprises at least one of the sending device or the receiving device described above. BRIEF DESCRIPTION OF DRAWINGS

[0042] Fig. 1 is a schematic diagram of a network architecture to which the embodiments of the present application can be applied.

[0043] Fig. 2 is a schematic diagram of a check matrix H of an LDPC.

[0044] FIG. 3 is a Tanner graph of a parity check matrix H of an LDPC code.

[0045] FIG. 4 is a schematic diagram of a structure of a parity check matrix.

[0046] FIG. 5 is a schematic diagram of a process of information transmission.

[0047] FIG. 6 is a schematic diagram of a base matrix of an LDPC code in a WIFI (802.11AY) standard.

[0048] FIG. 7 is a schematic flowchart of a communication method 700 based on an LDPC code provided by the present application.

[0049] FIG. 8 is a schematic diagram of a first lower triangular matrix provided by the present application.

[0050] FIGS. 9 to 11 are schematic diagrams of base matrices based on a first mode, a second mode and a third mode respectively provided by the present application.

[0051] FIG. 12 is a schematic block diagram of a communication apparatus 1000 provided by an embodiment of the present application.

[0052] FIG. 13 is a schematic block diagram of a communication apparatus 1100 provided by an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to facilitate understanding of the embodiments of the present application, the following points are explained before the embodiments of the present application are introduced.

[0054] "Indicative of" or "indicate" can include both direct and indirect indication, or "indicative of" or "indicate" can explicitly and / or implicitly indicate. The first, second, etc. various numerical designations are only for the convenience of description and do not limit the scope of the embodiments of the present application, for example, to distinguish different messages, different information, etc. "Predefined" can be achieved by pre-storing corresponding codes, tables or other means for indicating relevant information in the device, and the specific implementation manner is not limited in the present application. The "protocol" referred to can refer to a standard protocol in the communication field, which can include a long term evolution (LTE) protocol, a new radio (NR) protocol and a related protocol applied in a future communication system, and the present application is not limited thereto. The words "example", "for example", "exemplary", "as an example", etc. are used to indicate an example, illustration or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. The terms "include", "contain", "have" and their variants mean "including but not limited to", unless otherwise specifically emphasized. "At least one" refers to one or more, and "multiple" refers to two or more. "At most one" refers to one or 0. "And / or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can represent: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple. The description related to the network element A sending a message, information or data to the network element B, and the network element B receiving the message, information or data from the network element A, is intended to indicate which network element the message, information or data is intended to send to, and does not limit whether they are directly sent or indirectly sent via other network elements. "When", "in the case of", "if" and "if" and other descriptions all refer to the objective situation in which the device will make corresponding processing, and are not limited by time, and do not require the device to have a judgment action when implemented, nor does it mean that there are other limitations.

[0055] In addition, the network architecture and service scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of network architecture and the emergence of new service scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0056] The communication system to which the embodiments of the present application can be applied will be described below.

[0057] The embodiments of the present application can be applied to various communication systems, including but not limited to: a 5th generation (5G) system, an LTE system, a long term evolution-advanced (LTE-A) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as a 6th generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), an internet of things (IoT) communication system, a narrow band-internet of things (NB-IoT) system, or other communication systems. In addition, it can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and 3rd generation partnership project (3GPP) related communication systems, etc., without limitation.

[0058] The communication system to which the embodiments of the present application can be applied can include one or more transmitting end devices and one or more receiving end devices. Alternatively, one of the transmitting end device and the receiving end device can be a terminal device, and the other can be a network device. Alternatively, the transmitting end device and the receiving end device can both be terminal devices. Alternatively, the transmitting end device and the receiving end device can both be network devices.

[0059] FIG. 1 is a schematic diagram of a network architecture to which embodiments of the present application are applicable. As shown in FIG. 1, embodiments of the present application are applicable to both uplink data transmission and downlink data transmission. In FIG. 1, only uplink data transmission or downlink data transmission between one network device and two terminal devices (e.g., terminal device 1 and terminal device 2) is taken as an example. In uplink data transmission, the transmitting terminal device is the terminal device and the receiving terminal device is the network device; conversely, in downlink data transmission, the transmitting terminal device is the network device and the receiving terminal device is the terminal device. In addition, embodiments of the present application are not limited to be applicable to other communication scenarios, for example, they can also be applied to sidelink communication.

[0060] The terminal device in the embodiments of the present application can also be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station, a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a drone, a wireless communication device, a user agent or a user apparatus, etc. The terminal device in the embodiments of the present application can refer to a device that provides voice and / or data connectivity to a user, and can be used to connect people, things and machines, such as handheld devices with wireless connection functions, vehicle-mounted devices, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc.

[0061] The network device of the present application can be a device with wireless transceiving function, which can be a device providing wireless communication function service, usually located at the network side, including but not limited to next generation base station (gNodeB, gNB) in 5G system, base station in sixth generation mobile communication system, base station in future mobile communication system, or access node in wireless fidelity (WiFi) system, evolved node B (eNB) in long term evolution (LTE) system, radio network controller (RNC), node B (NB), base station controller (BSC), home base station (such as home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellite, unmanned aerial vehicle, etc. In one network structure, the network device can include a centralized unit (CU) node, or include a distributed unit (DU) node, or be a RAN device including CU node and DU node, or be a RAN device including control plane CU node and user plane CU node, and DU node, or the network device can also be a wireless controller in cloud radio access network (CRAN) scenario, relay station, vehicle-mounted device, wearable device, etc. In addition, the base station can be a macro base station, micro base station, relay node, donor node or combination thereof. The base station can also refer to a communication module, modem or chip for setting in the aforementioned device or apparatus. The base station can also be a mobile switching center, and a device assuming base station function in D2D, V2X, M2M communication, network side device in future communication network, device assuming base station function in future communication system, etc. The base station can support networks of the same or different access technologies, without limitation.

[0062] Unless otherwise defined, the apparatuses used in the embodiments of the present application to realize the functions of the terminal device or the network device can refer to the terminal device or the network device itself, or can refer to an apparatus capable of supporting the terminal device or the network device to realize the functions, such as a chip system or a chip, specifically, a system on a chip (SoC) or a Modem. The apparatus can be installed in the terminal device or the network device. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0063] It should also be noted that some embodiments in the present document take the 5G system as an example to introduce specific scheme details. It can be understood that when the scheme is used in other communication systems, for example, the LTE system, or future communication systems, the messages, channels or information in the scheme can be replaced by messages, channels or information capable of realizing corresponding functions in other communication systems, and the present application does not limit this.

[0064] In addition, the embodiments of the present application can be applied to various application scenarios, such as a high throughput scenario, a high reliability scenario, a low latency scenario, a high reliability low latency scenario or a low power consumption scenario. Among them, the high throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, and the high reliability low latency scenario can be, for example, an ultra reliable low latency communication (URLLC) scenario.

[0065] In order to facilitate understanding of the embodiments of the present application, several concepts or terms related to the embodiments of the present application are briefly described. The concepts or terms described below are based on the concepts or terms defined in the protocol, but do not mean that the embodiments of the present application can only be applied to the existing system, and the concepts or terms related to the embodiments of the present application can be applied to future systems. And the specific name of the concept or term (for example, the concept or term related to the functional description) can be adjusted with the development of future systems.

[0066] 1、LDPC code

[0067] LDPC code is a kind of linear block code. Linear block code is to divide the information sequence to be coded into groups in units of q bits, and then linearly operate the q information bits by the encoder to obtain m check bits, and then combine the q information bits and the m check bits to obtain a code word with length n=q+m. The mapping relationship from the q-bit information bits to the n-bit code word is usually represented by a corresponding check matrix H. According to the check matrix H, the code word sequence can be generated to complete the encoding process. After the code word sequence is transmitted through the channel, the receiving end device decodes the received signal to determine the original information bits.

[0068] The check matrix H of LDPC is a sparse matrix. The number of zero elements in the check matrix H is much larger than the number of non-zero elements, or in other words, the row weight (or column weight) of the check matrix is much smaller than the number of elements in each row (or each column) of the LDPC matrix. The LDPC code with the information bit sequence length equal to q and the code length equal to n can be uniquely determined by its check matrix H.

[0069] Tanner represented the check matrix H in the form of a graph in 1981. This graph is now called a Tanner graph, and the Tanner graph and the check matrix correspond one-to-one. The Tanner graph is composed of two types of vertices. One type of vertex represents a code word bit, which is called a variable node. The other type of vertex is a check node, which represents a check constraint relationship. Each check node represents a check constraint relationship. The following will be explained in conjunction with FIG. 2 and FIG. 3.

[0070] FIG. 2 is a schematic diagram of a check matrix H of an LDPC.

[0071] In FIG. 2, {V i} represents a set of variable nodes (VN), and {C i} represents a set of check nodes (CN). Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, each column represents a code word bit, and each code word bit corresponds to a variable node. In FIG. 2, there are 8 variable nodes and 4 check nodes. If a code word bit is included in the corresponding check equation, a line is used to connect the variable node and the check node involved to obtain a Tanner graph.

[0072] FIG. 3 is a Tanner graph of a check matrix H of an LDPC.

[0073] As shown in FIG. 3, the Tanner graph represents the check matrix of the LDPC. For example, for a check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes, namely n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the check matrix H, and the m check nodes correspond to the m rows of the check matrix H. A cycle in the Tanner graph is formed by a group of vertices connected to each other, and a loop is formed by a vertex in the group of vertices serving as both a starting point and an ending point, and passing through each node only once. The length of the loop is defined as the number of edges it contains, and the girth of the graph can also be referred to as the perimeter of the graph, which is defined as the minimum cycle length in the graph. As shown in FIG. 3, the girth is 4, as indicated by the black connecting line. Each variable node in the Tanner graph corresponds to each column of the check matrix H, that is, each code bit of the LDPC. Each check node in the Tanner graph corresponds to each row of the check matrix H, that is, each check bit of the LDPC. The connection between the two types of nodes corresponds to the value of the element in the H matrix. If there is a connection between the i th check node and the j th variable node, it means that the value of the element (i, j) in the H matrix is 1, and if there is no connection, the corresponding element is 0. The connection between the variable node and the check node can also be referred to as an edge. The connection between the check node and the variable node can also be described as: the check node and the variable node have a connection or an edge. The edge relationship between the check node and the variable node can include the existence of an edge or the non-existence of an edge. In addition, in the Tanner graph, a cycle refers to a closed loop formed by variable nodes, check nodes, and edges connected end to end.

[0074] 2. QC-LDPC code

[0075] The QC-LDPC code is a structured LDPC code. Due to the unique structure of the check matrix, a simple feedback shift register can be used for encoding, reducing the encoding complexity of the LDPC code. The QC-LDPC code actually used is represented by a base graph (BG). The elements in the BG are 0 or 1. The 1 and 0 in the BG are expanded, and after the expansion is completed, the check matrix H obtained can be used for encoding or decoding. In the embodiments of the present application, the BG can be written in the form of a matrix, which can be referred to as a base matrix H BG in the present application. The element 0 in the base matrix H BG indicates that there is no edge in the base graph, and the value 1 indicates that there is an edge (or indicates that the corresponding check is associated with the corresponding variable) in the base graph.

[0076] The NR LDPC code involves multiple base graph selection, and currently two base graphs BG1 and BG2 are stored in the standard. The expansion process of the base matrix is described below.

[0077] Based on the base matrix and the lifting value Zc (lifting size), the base matrix can be expanded to a complete check matrix for encoding or decoding. In this application, Z c It can also be referred to as expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The process of expansion is to lift all elements in the base matrix to a Z c ×Z c matrix, wherein 0 is lifted to a Z c ×Z c matrix, 1 is lifted to a unit matrix and cyclically shifted based on the shifting value (SV) corresponding to 1, and the cyclic shift can be left or right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 unit matrix as an example, if the shifting values are 0, 1 and 3, respectively, the cyclic shift matrix after right cyclic shift is as shown in the following table:

[0078] (1) When the shifting value is 0 (i.e. unchanged), the corresponding matrix after cyclic shift is

[0079] (2) When the shifting value is 1, the corresponding matrix after cyclic shift is

[0080] (3) When the shifting value is 3, the corresponding matrix after cyclic shift is

[0081] 3、Column weight and row weight

[0082] For a column of the matrix, the column weight can refer to the number of non-zero elements contained in the column.

[0083] For a row of the matrix, the row weight can refer to the number of non-zero elements contained in the row.

[0084] 4、Structure of LDPC code check matrix and base matrix

[0085] FIG. 4 is a schematic diagram of the structure of the LDPC code check matrix of 5G.

[0086] As shown in (a) of FIG. 4, the check matrix can include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region can include the A and B parts shown in (b) of FIG. 4, where the A part corresponds to information bits (or information bits, system bits, etc.), and the B part is a square matrix and corresponds to core check bits (or core check bits), where the core check can be a check corresponding to the highest code rate, or can be a check having a degree greater than or equal to 2, or can be a check node corresponding to a row set having a maximum row weight (a row weight significantly / higher than other rows). The matrix corresponding to the A part can be referred to as a core matrix. The matrix corresponding to the B part can be referred to as a core check matrix. The all-zero region can correspond to the C part of (b) of FIG. 4, which is an all-zero matrix. The incremental redundancy region can correspond to the D part of (b) of FIG. 4. The raptor-like region can correspond to the E part of (b) of FIG. 4, which can be a unit matrix and corresponds to check bits for low rate extension. In this disclosure, the E part can also be referred to as an extension check region, and the matrix corresponding to the E region can also be referred to as an extension check matrix.

[0087] The check matrix of the LDPC code shown in FIG. 4 adopts a "raptor-like" structure and can be gradually extended to a low code rate from a high code rate core matrix. In actual use, as shown in (a) of FIG. 4, the first X rows and the first Y columns of the check matrix can be intercepted, and as the code rate gradually decreases from high to low, X and Y gradually increase, and the region of the matrix used also gradually expands.

[0088] It can be understood that the check matrix H can be obtained by extending the LDPC base matrix, and thus the structure of the LDPC base matrix is similar to that of the check matrix, and can also be divided into A, B, C, D, and E parts. The characteristics of each part are described above and will not be described in detail here.

[0089] 5. Information columns, check columns, and core check columns

[0090] The columns of the LDPC base matrix are composed of information columns and check columns.

[0091] Information columns: correspond to information bits (or information bits, system bits, etc.), and are the columns corresponding to the A part.

[0092] Parity column: corresponds to a parity bit (or a parity position, etc.), and can include a core parity column and an extension parity column, wherein the core parity column is a column corresponding to the B part, and the extension parity column is a column corresponding to the C part or the E part. The extension parity column can also be referred to as a raptor-like column.

[0093] Core parity column: N columns in the base matrix of the LDPC after the information columns, N is equal to the number of rows corresponding to the core rows. For example, if the information columns are 1 to K b columns, then the core parity columns are K b +1 to K b columns.

[0094] 6、Core row, core column and core matrix

[0095] Core row: a row of the core parity bit corresponding to the core row in the base matrix of the LDPC. In other words, the core row is a row corresponding to the high code rate region, or a row corresponding to the A part, the B part or the C part.

[0096] Core column: can include all information columns and all core parity columns. In other words, the core column is a column corresponding to the high code rate region, or a column corresponding to the A part and the B part.

[0097] Core matrix: a matrix region composed of all core rows and all core columns of the base matrix of the LDPC. In other words, the core matrix is a high code rate region of the base matrix of the LDPC, or a part composed of the A part and the B part.

[0098] 7、Information length, code length and code rate

[0099] The information length is the length (i.e., the number of bits contained) of the information bit sequence to be sent, which can be the length of the payload information bit, or the length of the payload information bit after adding the cyclic redundancy check (CRC) bit, and the present application does not make specific limitations.

[0100] The code length refers to the length of the bit sequence to be sent, which can be a transmission bit sequence corresponding to a modulated symbol.

[0101] The code rate refers to the ratio of the length of the information bit sequence to be sent to the code length.

[0102] 8. Redundancy transmission: LDPC can retransmit part of the encoded data when decoding error occurs. In 5G LDPC, four retransmission starting positions are set. When error occurs, the sending side selects a position from the four redundancy positions corresponding to the four redundancy versions (RVs) (RV0-RV3) to start retransmitting the encoded data.

[0103] 9. Information transmission process

[0104] FIG. 5 is a schematic diagram of an information transmission process suitable for the present application. As shown in FIG. 5, information is sent by a source, processed by source encoding, channel encoding, modulation, air interface transmission, demodulation, channel decoding, source recovery, and the like, and reaches a sink, completing the transmission of information from the source to the sink. Among them, the processing shown in the upper layer of FIG. 5 (including source encoding, channel encoding, modulation, etc.) is executed at the sending end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is executed at the receiving end device. Embodiments of the present application mainly relate to source encoding, channel encoding, channel decoding, and source recovery shown in FIG. 5.

[0105] As can be seen from the above, in the LDPC base graph design of 5G, the E area adopts a raptor-like structure, and the E area is a unit matrix, that is, in the E area, the row weight of each row is equal to 1, and the column weight of each column is equal to 1. The advantage of such design is that the check positions of any row in the E area can be quickly encoded.

[0106] FIG. 6 is a schematic diagram of an LDPC code base matrix in the WIFI (802.11AY) standard. The LDPC base graph in the WIFI (802.11AY) standard is one base graph for each code rate, and also has a common matrix structure. Among them, the A part corresponds to the information column area of high code rate, and the B part corresponds to the check area. Unlike the extended check matrix of the base graph of 5G (i.e., the matrix corresponding to the E part), the check matrix of the base graph of 802.11AY (i.e., the matrix corresponding to the B part) is a low triangle matrix. The advantage of the low triangle structure is that the column weight of most columns is greater than 1, so density evolution can occur in these areas, the decoding threshold performance of LDPC will be improved, and the code weight of LDPC can also be improved, and error floor is not easy to occur in the interval of high reliability area (for example, block error rate (BLER) <1e-6).

[0107] It can be understood that, compared with the structure of the lower triangular check matrix, since the column weight of each column in the E area in the design of the 5G LDPC base graph is equal to 1, the lower triangular check matrix does not have the advantage. Therefore, the lower triangular structure can be applied in the E area, but if the matrix corresponding to the E area is designed as a lower triangular structure, it will not be compatible with the incremental redundancy-hybrid automatic repeat request (IR-HARQ) scheme of the 5G LDPC code, that is, the retransmission can only start from the end position of the last transmission, and the IR-HARQ of the specified position cannot be performed. It can be understood that the specified position is the starting column of the RV set in the 5G LDPC base graph.

[0108] Therefore, the present application provides a communication method based on LDPC code, which can effectively solve the above technical problems.

[0109] FIG. 7 is a schematic flow chart of a communication method 700 based on LDPC code provided by the present application. The method comprises the following steps.

[0110] It can be understood that the method 700 can be executed by a sending end device and a receiving end device, and the "sending end device" or "receiving end device" can refer to the sending end device or receiving end device itself, or can refer to a device capable of supporting the sending end device or receiving end device to implement the function. For the convenience of description, the sending end device and the receiving end device are used to describe the following. The sending end device can be a terminal device or a network device, and the receiving end device can be a terminal device or a network device.

[0111] S710, the sending end device acquires an information bit sequence.

[0112] It can be understood that if the sending end device needs to communicate with the receiving end device, that is, the sending end device needs to send a signal to the receiving end device, the sending end device needs to acquire the information bit sequence corresponding to the signal to be sent to the receiving end device.

[0113] The sending end device acquires the information bit sequence can refer to that the sending end device source encodes the source symbol to generate the information bit sequence, or the sending end device acquires the information bit sequence can also refer to that the sending end device receives the information bit sequence from other communication devices, and the present application does not limit the way of acquiring the information bit sequence.

[0114] S720, the sending end device determines an LDPC check matrix.

[0115] The LDPC check matrix is determined based on an LDPC base matrix (hereinafter referred to as a base matrix), wherein the base matrix includes an extended check matrix, and the extended check matrix is a lower triangular matrix with diagonal elements being 1. The extended check matrix includes a plurality of lower triangular matrices, the diagonal elements of each lower triangular matrix in the plurality of lower triangular matrices are located on the diagonal line of the extended check matrix, the positions of the diagonal elements of the plurality of lower triangular matrices do not overlap, and the remaining elements in the extended check matrix except the diagonal elements of the extended matrix and the plurality of lower triangular matrices are 0 elements.

[0116] It can be understood that the extended check matrix described in the present application can be regarded as a matrix obtained by redefining the matrix corresponding to the E area in (a) of FIG. 4.

[0117] It can also be understood that the lower triangular matrix described in the present application refers to a matrix that is both a lower triangular matrix and a square matrix (i.e., a matrix with the number of rows equal to the number of columns).

[0118] In the present application, the extended check matrix can also be referred to as a first matrix or a first area, and the name of the extended check matrix is not specifically limited in the present application. The extended check matrix is a matrix composed of the remaining rows except the core rows in all rows of the base matrix and the remaining columns except the core columns in all columns of the base matrix.

[0119] In a possible implementation, the first diagonal element of a first lower triangular matrix in the plurality of lower triangular matrices included in the extended check matrix has a first feature, wherein the first lower triangular matrix is any lower triangular matrix in the plurality of lower triangular matrices, the first diagonal element is a diagonal element in the first lower triangular matrix except the first diagonal element, and the first feature is that the elements in the area composed of the previous column of the column where the first diagonal element is located, the first column (i.e., the first column) of the first lower triangular matrix, and the last row do not all have a value of 0.

[0120] It can be understood that the first diagonal element can also be referred to as the first diagonal element in the first lower triangular matrix, or the diagonal element with the smallest column number among all the diagonal elements in the first lower triangular matrix.

[0121] The first feature is illustrated in combination with FIG. 8. FIG. 8 is a first lower triangular matrix. As can be seen, any first diagonal element in the first lower triangular matrix has the first feature. Taking the diagonal element #3 in the third row and the third column in FIG. 8 as an example, it can be seen that the dashed box in the figure is the area composed of the previous column (i.e., the second column in the figure) of the column where the diagonal element #3 is located (i.e., the third row in the figure), the first column (i.e., the first column in the figure) of the first lower triangular matrix, and the last row (i.e., the sixth row in the figure), and the elements in the area do not all have a value of 0.

[0122] It can be understood that in the above implementation manner, the row weight and the column weight of the row and the column where the first diagonal element is located in the first lower triangular matrix can both be 1. For example, the diagonal element #4 in the 4th row and the 4th column in FIG. 8 has a row weight and a column weight of 1 in the corresponding first lower triangular matrix, but the diagonal element #4 still has the first characteristic.

[0123] It can also be understood that the first lower triangular matrix with the first characteristic described above is only an example of the first lower triangular matrix, and the characteristics of the first lower triangular matrix are not limited in the present application.

[0124] It can be understood that the matrix corresponding to the E region of the BG1 or the BG2 of the 5G is a unit matrix. Since the elements in the region composed of the previous column of the row where each diagonal element is located and the column where the diagonal element is located in the E region, and the first column of the E region and the last row of the E region are all 0 elements (hereinafter referred to as the third characteristic), the column where each diagonal element in the E region is located can be used as the starting point of the encoding, that is, the starting column of an RV can be any column where a diagonal element in the E region is located. For example, the current standard sets four RVs for the BG2 of the 5G, and the base matrix H BG2 corresponding to the BG2 has column numbers 0 to 51, wherein the starting column of the RV0 is the 2nd column in the BG2, the starting column of the RV1 is the 15th column, the starting column of the RV2 is the 27th column, and the starting column of the RV3 is the 45th column.

[0125] Therefore, at least two RVs can be configured for the base matrix proposed in the present application, and the starting column of at least one RV in the at least two RVs can correspond to the column where a diagonal element with the third characteristic among all the diagonal elements of the extended check matrix proposed in the present application is located. The following is an example.

[0126] Example one, the starting column of an RV corresponds to the starting column of one of the plurality of lower triangular matrices.

[0127] It can be understood that example one is only to illustrate that the starting column of one RV corresponds to the starting column of one lower triangular matrix, and in practice, the starting column of X1 RVs can correspond to the starting column of X1 lower triangular matrices in the plurality of lower triangular matrices, X1 being an integer greater than 1. For example, the starting column of the RV of the base matrix corresponds to all columns in the first column set, the first column set including the starting columns of the plurality of lower triangular matrices, or the first column set including the columns other than the first column of the extended check matrix among the starting columns of the plurality of lower triangular matrices.

[0128] Example two, the starting column of an RV corresponds to one column in the second column set, wherein the second column set includes the columns where the diagonal elements other than all the diagonal elements of the plurality of lower triangular matrices among all the diagonal elements of the extended check matrix are located.

[0129] It can be understood that, together with example one, in practice, example two can have X2 starting columns of RVs corresponding to X2 columns in the second column set, X2 being an integer greater than 1.

[0130] It can also be understood that the above-mentioned example one and example two can also be combined, that is, part of the RVs correspond to example one and part of the RVs correspond to example two.

[0131] In the above technical solution, the E area of the LDPC base graph of 5G is changed to a mode of cascading multiple lower triangular matrices, which not only improves the column weight of the check area and reduces the error floor, but also can support retransmission in some specific columns and be compatible with the existing LDPC IR-HARQ scheme.

[0132] The following gives several possible cascading modes of multiple lower triangular matrices.

[0133] Mode one: the union of the positions of the diagonal elements of the multiple lower triangular matrices is equal to the set corresponding to the positions of all the diagonal elements of the extended check matrix.

[0134] FIG. 9 is a schematic diagram of a base matrix based on mode one provided by the present application. The base matrix is obtained by modifying the extended check area (i.e., the E area) of BG2 based on the method proposed in the present application. In the example, the column number of the base matrix is 0 to 51, a total of 52 columns, and the extended check matrix includes a total of 4 lower triangular matrices, wherein the area composed of the 0th column to the 9th column and the first 4 rows is the A area of the base matrix, the area composed of the 10th column to the 13th column and the first 4 rows is the B area of the base matrix, the area composed of the 14th column to the 51st column and the first 4 rows is the C area of the base matrix, the area composed of the 0th column to the 13th column and all the rows except the first 4 columns is the D area of the base matrix, and the area composed of the 14th column to the 51st column and all the rows except the first 4 columns is the E area (i.e., the extended check matrix) of the base matrix. The positions of the 4 lower triangular matrices included in the extended check matrix are as follows:

[0135] Lower triangular matrix #1 is located in area 1 composed of the 14th column to the 16th column of the base matrix, the first 4 rows of this area 1 are all 0 matrices (belonging to the C area), the middle 3 rows are lower triangular matrix #1, and the last 35 rows are also all 0 matrices.

[0136] Lower triangular matrix #2 is located in area 2 composed of the 17th column to the 26th column of the base matrix, the first 7 rows of this area 2 are all 0 matrices (belonging to the C area), the middle 10 rows are lower triangular matrix #2, and the last 25 rows are also all 0 matrices.

[0137] The lower triangular matrix #3 is located in the area 3 composed of the 27th column to the 39th column of the base matrix, the first 17 rows of the area 3 are all 0 matrix (belonging to the C area), the middle 13 rows are the lower triangular matrix #3, and the last 12 rows are also all 0 matrix.

[0138] The lower triangular matrix #4 is located in the area 4 composed of the 40th column to the 51st column of the base matrix, the first 30 rows of the area 4 are all 0 matrix (belonging to the C area), and the remaining 12 rows are the lower triangular matrix #4.

[0139] Optionally, in the mode, the starting column of one RV of the base matrix corresponds to the starting column of one lower triangular matrix of the plurality of lower triangular matrices. Further, the starting columns of the plurality of RVs of the base matrix correspond to all columns in the first column set one by one, wherein the first column set includes the starting columns of the plurality of lower triangular matrices, or the first column set includes the columns other than the first column of the extended check matrix among the starting columns of the plurality of lower triangular matrices. For example, as shown in FIG. 9, the base matrix corresponds to 4 RVs (RV0-RV3), the starting column of the RV0 is the 2nd column in the BG2, the starting column of the RV1 is the 17th column, the starting column of the RV2 is the 27th column, and the starting column of the RV3 is the 40th column, wherein the starting columns of the RV1-RV3 correspond to the starting columns of the lower triangular matrix #2, the lower triangular matrix #3 and the lower triangular matrix #4 one by one.

[0140] In a possible implementation, the plurality of RVs can be set for the base matrix first, and then the lower triangular matrix shown in the mode 1 is constructed based on the starting columns of the set RVs. For example, as shown in FIG. 9, 4 RVs are set first, wherein the RV0 corresponds to 3 columns in the E area, the RV1 corresponds to 10 columns in the E area, the RV2 corresponds to 13 columns in the E area, and the RV3 corresponds to 12 columns in the E area, so that a 3*3 lower triangular matrix is constructed in the E area corresponding to the RV0, a 10*10 lower triangular matrix is constructed in the E area corresponding to the RV1, a 13*13 lower triangular matrix is constructed in the E area corresponding to the RV2, and a 12*12 lower triangular matrix is constructed in the E area corresponding to the RV3, and the positions of the diagonal elements of each lower triangular matrix are located on the diagonal line of the extended check matrix.

[0141] In the mode, the column weight of the extended check matrix is not all 1, so the matrix has better evolution characteristics and lower error floor. Under high-order modulation, the encoding bits do not need to be interleaved. At the same time, the characteristics of retransmission starting from somewhere in the middle of the E area are also possessed.

[0142] The second feature is that the column weights corresponding to the N columns after the last column of the second lower triangular matrix in the extended parity check matrix are all 1, and the row weights corresponding to the N rows after the last row of the second lower triangular matrix in the extended parity check matrix are all 1, the second lower triangular matrix is any one of the at least one lower triangular matrix, N is greater than or equal to 1, and the next column of the N columns after the last column of the second lower triangular matrix is the first column of another lower triangular matrix in the plurality of lower triangular matrices.

[0143] Optionally, the first diagonal element of a lower triangular matrix in the plurality of lower triangular matrices is located at the position of the first element in the diagonal elements of the extended parity check matrix.

[0144] FIG. 10 is a schematic diagram of a base matrix based on mode two provided in the present application. The base matrix is obtained by modifying the extended parity check region (i.e., the E region) of BG2 based on the method proposed in the present application. FIG. 10 can be regarded as a base matrix obtained by changing the lower triangular matrix #2 to the lower triangular matrix #4 in FIG. 9 to the hybrid structure of the lower triangular matrix + raptor like based on FIG. 9. Among them, the positions and characteristics of the four lower triangular matrices in FIG. 10 are as follows:

[0145] The description of the lower triangular matrix #1 is consistent with that of the lower triangular matrix #1 in FIG. 9, which will not be repeated here.

[0146] The lower triangular matrix #2 is located in the region 2 composed of the 17th to 24th columns of the base matrix, the first 7 rows of the region 2 are all 0 matrices, the middle 8 rows are the lower triangular matrix #2, and the last 27 rows are also all 0 matrices. In addition, the column weights corresponding to the 2 columns after the last column of the second lower triangular matrix in the extended parity check matrix are all 1, and the row weights corresponding to the 2 rows after the last row of the lower triangular matrix #2 in the extended parity check matrix are all 1. It can be seen that the second lower triangular matrix corresponds to the second feature, and N = 2.

[0147] The lower triangular matrix #3 is located in the region 3 composed of the 27th to 36th columns of the base matrix, the first 17 rows of the region 3 are all 0 matrices, the middle 10 rows are the lower triangular matrix #3, and the last 15 rows are also all 0 matrices. In addition, the column weights corresponding to the 3 columns after the last column of the third lower triangular matrix in the extended parity check matrix are all 1, and the row weights corresponding to the 3 rows after the last row of the lower triangular matrix #3 in the extended parity check matrix are all 1. It can be seen that the third lower triangular matrix corresponds to the second feature, and N = 3.

[0148] The lower triangular matrix #4 is located in the 40th column to the 47th column of the base matrix, the first 29 rows of the area 4 are all 0 matrix, the remaining 8 rows are the lower triangular matrix #4, and the last 4 rows are also all 0 matrix. In addition, the 4 columns after the last column of the lower triangular matrix #4 have a column weight of 1 in the extended check matrix, and the 4 rows after the last row of the lower triangular matrix #4 have a row weight of 1 in the extended check matrix. It can be seen that the lower triangular matrix #4 corresponds to the second feature, and N = 4.

[0149] Optionally, in this mode, the starting column of one RV of the base matrix corresponds to the starting column of one lower triangular matrix of the plurality of lower triangular matrices. Further, the starting columns of the plurality of RVs of the base matrix correspond to all columns in the first column set one by one, wherein the first column set includes the starting columns of the plurality of lower triangular matrices, or the first column set includes the columns in the starting columns of the plurality of lower triangular matrices except the first column of the extended check matrix. For example, as shown in FIG. 10, the base matrix corresponds to 4 RVs (RV0-RV3), the starting column of RV0 is the 2nd column in BG2, the starting column of RV1 is the 17th column, the starting column of RV2 is the 27th column, and the starting column of RV3 is the 40th column, that is, the starting positions of RV1-RV3 correspond to the starting columns of the lower triangular matrix #2, the lower triangular matrix #3 and the lower triangular matrix #4 one by one.

[0150] Based on this mode, the lower triangular matrix corresponding to one RV in mode one can be changed to a hybrid structure of lower triangular + raptor like, so that there are nodes with a degree of 1 in the area corresponding to one RV to participate in retransmission, so that the overall degree distribution is more reasonable, thereby improving the threshold performance.

[0151] In a possible implementation, a plurality of RVs can be set for the base matrix first, and then the lower triangular matrix shown in mode two is constructed based on the starting columns of the set RVs. For example, as shown in FIG. 10, 4 RVs are set first, wherein RV0 corresponds to 3 columns in the E area, RV1 corresponds to 10 columns in the E area, RV2 corresponds to 13 columns in the E area, and RV3 corresponds to 12 columns in the E area. Then, a 3*3 lower triangular matrix can be constructed in the E area corresponding to RV0, an 8*8 lower triangular matrix can be constructed in the E area corresponding to RV1, a 10*10 lower triangular matrix can be constructed in the E area corresponding to RV2, and an 8*8 lower triangular matrix can be constructed in the E area corresponding to RV3. The positions of the diagonal elements of each lower triangular matrix are located on the diagonal of the extended check matrix, and the column where the first diagonal element of each lower triangular matrix is located is the starting column of the corresponding RV. It can be seen that FIG. 10 constructs three lower triangular matrices satisfying the second feature in the E areas corresponding to RV1 to RV3.

[0152] In the third mode, the positions of the diagonal elements of the plurality of lower triangular matrices are continuous positions on the diagonal of the extended parity check matrix, and only the third lower triangular matrix corresponds to the second feature, and the first column of the third lower triangular matrix is located after the last column of any lower triangular matrix in a first matrix set, the first matrix set being the remaining lower triangular matrices except the third lower triangular matrix in the plurality of lower triangular matrices. That is, the third lower triangular matrix is the last lower triangular matrix in the plurality of lower triangular matrices.

[0153] Optionally, the first diagonal element of one of the plurality of lower triangular matrices is located at the position of the first element of the diagonal elements of the extended parity check matrix.

[0154] FIG. 11 is a schematic diagram of a base matrix based on the third mode provided in the present application. The base matrix is obtained by modifying the extension check area (i.e., the E area) of BG2 based on the method provided in the present application. FIG. 11 can be regarded as a base matrix obtained by changing the lower triangular matrix #4 in FIG. 9 to a raptor like structure based on FIG. 9, and the positions of the three lower triangular matrices in FIG. 11 are the same as the descriptions of the lower triangular matrix #1, the lower triangular matrix #2, and the lower triangular matrix #3 in FIG. 9, which will not be described here.

[0155] Optionally, in the third mode, the starting column of one RV of the base matrix corresponds to the starting column of one of the plurality of lower triangular matrices. Further, the starting columns of the plurality of RVs of the base matrix correspond to all columns in a first column set one by one, wherein the first column set includes the starting columns of the plurality of lower triangular matrices, or the first column set includes the remaining columns except the first column of the extended parity check matrix in the starting columns of the plurality of lower triangular matrices.

[0156] Optionally, based on the above-mentioned optional one, the starting column of one RV of the base matrix also corresponds to the column next to the last column of the third lower triangular matrix. For example, as shown in FIG. 11, the base matrix corresponds to four RVs (RV0-RV3), the starting column of RV0 is the second column, the starting column of RV1 is the 17th column, the starting column of RV2 is the 27th column, and the starting column of RV3 is the 40th column, that is, the starting columns of RV1 and RV2 correspond to the starting columns of the lower triangular matrix #2 and the lower triangular matrix #3 one by one, and the starting column of RV3 corresponds to the column next to the last column of the lower triangular matrix #3.

[0157] Optionally, in the above option 2, the starting column of one RV of the base matrix further corresponds to a column in a third column set, wherein the third column set is a set of columns after the last column of the third lower triangular matrix and excluding the first column in the N columns, and N is greater than or equal to 2. For example, FIG. 11 is only an example of option 3. For example, based on FIG. 11, the lower triangular matrix #3 in FIG. 11 can also be changed to a raptor like structure. In this case, the base matrix corresponds to 4 RVs (RV0-RV3), the starting column of RV0 is the 2nd column, the starting column of RV1 is the 17th column, the starting column of RV2 is the 27th column, and the starting column of RV3 is the 40th column. That is, the starting column of RV1 corresponds to the starting column of the lower triangular matrix #2, the starting column of RV2 corresponds to the next column after the last column of the lower triangular matrix #2, and the starting column of RV3 corresponds to the 14th column after the last column of the lower triangular matrix #2 (the 40th column of the base matrix).

[0158] Based on this method, the lower triangular matrix #4 in FIG. 9 can be changed to a raptor like structure. The reason is that the density of the lower triangular matrix is too high, and the decoding threshold will be lost. Therefore, part of the RV area can be changed to an area with a column degree of 1. The advantage of this change is that when the code rate is very low, the introduction of the point with a degree of 1 can improve the decoding threshold performance.

[0159] In a possible implementation, a plurality of RVs can be set for the base matrix, and then a lower triangular matrix shown in option 3 is constructed based on the starting column of the set RV. For example, as shown in FIG. 11, 4 RVs are set, wherein RV0 corresponds to 3 columns in the E area, RV1 corresponds to 10 columns in the E area, RV2 corresponds to 13 columns in the E area, and RV3 corresponds to 12 columns in the E area. A 3*3 lower triangular matrix is constructed in the E area corresponding to RV0, a 10*10 lower triangular matrix is constructed in the E area corresponding to RV1, a 13*13 lower triangular matrix is constructed in the E area corresponding to RV2, and a raptor like structure is constructed in the E area corresponding to RV3. The positions of the diagonal elements of each lower triangular matrix are located on the diagonal line of the extended check matrix.

[0160] In S730, the sending device encodes the information bit sequence according to the LDPC check matrix, and outputs a codeword sequence.

[0161] In S740, the sending device determines a symbol sequence based on the codeword sequence.

[0162] It can be understood that the symbol sequence can be a sequence after rate matching and modulation. For example, the sending device performs rate matching on the codeword sequence, then modulates the sequence after rate matching to obtain a symbol sequence, and then maps the modulated symbol sequence to a physical resource for transmission.

[0163] S750, the sending device sends the symbol sequence to the receiving device. Correspondingly, the receiving device receives the symbol sequence from the sending device.

[0164] It can be understood that the symbol sequence #1 sent by the sending device and the symbol sequence #2 received by the receiving device can be different due to the channel noise signal introduced in the transmission process of the symbol sequence.

[0165] S760, the receiving device decodes the symbol sequence according to the LDPC check matrix to obtain the information bit sequence.

[0166] The LDPC check matrix used by the receiving device for decoding is the same as the LDPC check matrix used by the sending device for encoding. The specific manner in which the receiving device determines the LDPC check matrix can refer to the description on the sending device side, which will not be described in detail here.

[0167] It can be understood that the steps in the above figures are only exemplary and are not strictly limited. In addition, the size of the serial number of the above processes does not mean the order of execution, and the execution order of the processes should be determined according to their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0168] It can also be understood that some optional features in the embodiments of the present application can not depend on other features in some scenarios, or can be combined with other features in some scenarios, without limitation.

[0169] It can also be understood that the methods and operations implemented by the device (sending device or receiving device) in the above method embodiments can also be implemented by the components (such as chips or circuits) of the device, without limitation.

[0170] The above describes the method embodiments provided by the present application in combination with FIG. 1 to FIG. 11. The device embodiments of the present application will be described below in combination with FIG. 12 and FIG. 13. It can be understood that in order to realize the functions in the above embodiments, the device in FIG. 12 and FIG. 13 includes the corresponding hardware structure and / or software module for executing each function. Those skilled in the art should easily realize that the units and method steps of each example described in combination with the embodiments disclosed in the present application can be realized in the form of hardware or hardware and computer software. It can be understood that the technical features described in the above method embodiments are also applicable to the following device embodiments.

[0171] FIG. 12 and FIG. 13 are structural schematic diagrams of possible devices provided by the embodiments of the present application. These devices can be used to realize the functions of the sending device or the receiving device in the above method embodiments, and thus can also realize the beneficial effects possessed by the above method embodiments.

[0172] FIG. 12 is a schematic block diagram of the communication apparatus 1000 according to an embodiment of the present application. As shown in FIG. 12, the apparatus 1000 can include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can be configured to communicate with an external device, and the processing unit 1020 can be configured to process data.

[0173] In a possible design, the apparatus 1000 can implement steps or procedures corresponding to those performed by the sending-end device in the above method embodiments. The processing unit 1020 can be configured to perform processing-related operations of the sending-end device in the above method embodiments, and the communication unit 1010 can be configured to perform sending-related operations of the sending-end device in the above method embodiments.

[0174] In another possible design, the apparatus 1000 can implement steps or procedures corresponding to those performed by the receiving-end device in the above method embodiments. The communication unit 1010 can be configured to perform receiving-related operations of the receiving-end device in the above method embodiments, and the processing unit 1020 can be configured to perform processing-related operations of the receiving-end device in the above method embodiments.

[0175] It can be understood that the apparatus 1000 is in the form of functional units in the above embodiments. The term “unit” can refer to an application specific integrated circuit (ASIC) or an electronic circuit, a processor (shared, dedicated or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and / or other suitable components that provide the described functionality. In one possible design, the apparatus 1000 can be specifically the sending-end device in the above embodiments, and can be configured to perform the procedures and / or steps corresponding to the sending-end device in the above method embodiments. Alternatively, the apparatus 1000 can be specifically the receiving-end device in the above embodiments, and can be configured to perform the procedures and / or steps corresponding to the receiving-end device in the above method embodiments. To avoid repetition, details are not described herein.

[0176] The apparatus 1000 of each of the above-mentioned solutions has a function of implementing the corresponding steps performed by the sending-end device in the above-mentioned methods, or the apparatus 1000 of each of the above-mentioned solutions has a function of implementing the corresponding steps performed by the receiving-end device in the above-mentioned methods. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions; for example, the communication unit can be replaced by a transceiver (for example, the sending unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units such as the processing unit can be replaced by a processor, which respectively performs the transceiving operation and the related processing operation in each method embodiment.

[0177] In addition, the communication unit can also be a transceiving circuit (for example, can include a receiving circuit and a sending circuit), and the processing unit can be a processing circuit. In embodiments of the present application, the apparatus in FIG. 12 can be a receiving-end device or a sending-end device in the foregoing embodiments, or can be a chip or a chip system, for example, a system on chip (SoC). The communication unit can be an input / output circuit or a communication interface, and the processing unit can be a processor or a microprocessor integrated on the chip or an integrated circuit. In this regard, no limitation is made.

[0178] FIG. 13 is a schematic block diagram of a communication apparatus 1100 provided by embodiments of the present application. The apparatus 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is configured to execute instructions to control the transceiver 1120 to send and / or receive signals.

[0179] Optionally, the apparatus 1100 can further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 through an internal connection path. The memory 1130 is configured to store instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In a possible implementation, the apparatus 1100 is configured to implement the corresponding procedures and steps of the sending-end device in the above-mentioned method embodiments. In another possible implementation, the apparatus 1100 is configured to implement the corresponding procedures and steps of the receiving-end device in the above-mentioned method embodiments.

[0180] Optionally, the memory 1130 can be integrated in the processor 1110.

[0181] In a possible scenario, the apparatus 1100 includes at least one processor integrated with a memory and other memory in addition to the memory integrated on the processor.

[0182] It can be understood that the apparatus 1100 can be specifically a sending device or a receiving device in the above-described embodiments, or can be a chip or a chip system. Correspondingly, the transceiver 1120 can be a transceiver circuit of the chip, which is not limited here. Specifically, the apparatus 1100 can be configured to perform various steps and / or processes in the above-described method embodiments corresponding to the sending device or the receiving device.

[0183] Optionally, the memory 1130 can include read-only memory and random access memory, and provide instructions and data for the processor. The memory can include non-volatile random access memory. For example, the memory can also store device type information. The processor 1110 can be configured to execute instructions stored in the memory, and when the processor 1110 executes the instructions stored in the memory, the processor 1110 is configured to perform various steps and / or processes of the above-described method embodiments corresponding to the sending device or the receiving device.

[0184] In the implementation process, the steps of the above method can be completed by the integrated logic circuit of hardware in the processor or the instructions in the form of software. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as hardware processor execution completion, or executed by a combination of hardware and software modules in the processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, and other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0185] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with a signal processing capability. In the implementation process, the steps of the method embodiments described above can be completed by the integrated logic circuit or the software form of instructions in the processor. The processor described above can be a general purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The processor in the embodiments of the present application can realize or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general purpose processor can be a microprocessor or the processor can also be any conventional processor or the like. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or be executed by a combination of hardware and software modules in the code processor. The software module can be located in a random access memory, a flash memory, a read only memory, a programmable read only memory or an electrically erasable programmable memory, a register or the like mature storage medium in the art. The storage medium is located in the storage, and the processor reads the information in the storage, and combines the hardware to complete the steps of the above method.

[0186] It is to be understood that the memory in the embodiments of the present application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the nonvolatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the system and method described herein is intended to include, but not be limited to, these and any other suitable types of memory.

[0187] Optionally, the memory (e.g. 1130) in the embodiments of the present application can be integrated in the processor (e.g. 1110).

[0188] In addition, the present application also provides a computer readable storage medium, the computer readable storage medium stores computer instructions, when the computer instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the present application are executed.

[0189] The present application also provides a computer program product, the computer program product includes computer program codes or instructions, when the computer program codes or instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the present application are executed.

[0190] Further, the application provides a chip including a processor. A memory for storing a computer program is arranged independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processes performed by the sending device or the receiving device in any one of the method embodiments are performed.

[0191] Further, the chip can further include a communication interface. The communication interface can be an input / output interface, an interface circuit, or the like. Further, the chip can further include a memory.

[0192] Further, the application provides a communication system including the sending device and the receiving device in the embodiments of the application.

[0193] It should be further noted that the memory described herein is intended to include, but not limited to, these and any other suitable type of memory.

[0194] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the application. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here. In several embodiments provided in the application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other form. The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., they can be located in one place, or distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment. In addition, each functional unit in each embodiment of the application can be integrated into a processing unit, or each unit can be physically present separately, or two or more units can be integrated into one unit.

[0195] The functions described can be implemented in hardware, software, firmware or any combination thereof. If implemented in software, the functions can be stored or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or other

[0196] It is to be understood that the terminology “including,” “includes,” “included,” “including,” “has,” “have,” “had,” or variants thereof is intended to be open-ended and means that there can be additional items or steps other than those specifically recited. Thus, these terms, when they appear in a claim, are intended to show only what is described as the essential implementation form of the claim and does not foreclose use of more than what is claimed.

[0197] It is to be understood that the terminology “including,” “includes,” “included,” “including,” “has,” “have,” “had,” or variants thereof is intended to be open-ended and means that there can be additional items or steps other than those specifically recited. Thus, these terms, when they appear in a claim, are intended to show only what is described as the essential implementation form of the claim and does not foreclose use of more than what is claimed.

[0198] It is to be understood that the terminology “including,” “includes,” “included,” “including,” “has,” “have,” “had,” or variants thereof is intended to be open-ended and means that there can be additional items or steps other than those specifically recited. Thus, these terms, when they appear in a claim, are intended to show only what is described as the essential implementation form of the claim and does not foreclose use of more than what is claimed.

Claims

1. A communication method based on low-density parity-check (LDPC) codes, characterized in that, include: Obtain the information bit sequence; The LDPC parity-check matrix is ​​determined based on the LDPC base matrix, which includes an extended parity-check matrix. The extended parity-check matrix is ​​a lower triangular square matrix with all diagonal elements being 1. The extended verification matrix includes multiple lower triangular matrices, and the diagonal elements of each lower triangular matrix are located on the diagonal of the extended verification matrix. The positions of the diagonal elements of the multiple lower triangular matrices do not overlap. Furthermore, all elements in the extended verification matrix except for the diagonal elements and the plurality of lower triangular matrices are 0 elements; The information bit sequence is encoded according to the LDPC parity check matrix to obtain a codeword sequence; Output the codeword sequence.

2. A communication method based on low-density parity-check (LDPC) codes, characterized in that, include: Obtain the symbol sequence; The LDPC parity-check matrix is ​​determined based on the LDPC base matrix, which includes an extended parity-check matrix. The extended parity-check matrix is ​​a lower triangular square matrix with all diagonal elements being 1. The extended verification matrix includes multiple lower triangular matrices, and the diagonal elements of each lower triangular matrix are located on the diagonal of the extended verification matrix. The positions of the diagonal elements of the multiple lower triangular matrices do not overlap. Furthermore, all elements in the extended verification matrix except for the diagonal elements and the plurality of lower triangular matrices are 0 elements; The symbol sequence is decoded based on the LDPC parity-check matrix to obtain the information bit sequence.

3. The method according to claim 1 or 2, characterized in that, The first diagonal element of the first lower triangular matrix has a first characteristic, wherein... The first lower triangular matrix is ​​any one of the plurality of lower triangular matrices. The first diagonal element is the remaining diagonal element in the first lower triangular matrix excluding the first diagonal element. The first feature is that the elements in the region formed by the row and column of the first diagonal element, the column preceding the first diagonal element, and the first column and the last row of the first lower triangular matrix are not all 0.

4. The method according to claim 3, characterized in that, The union of the positions of the diagonal elements of the plurality of lower triangular matrices is equal to the set of all positions of the diagonal elements of the extended check matrix.

5. The method according to claim 3, characterized in that, At least one of the plurality of lower triangular matrices corresponds to the second feature. The second feature is that the column weights of the N columns following the last column of the second lower triangular matrix in the extended parity-check matrix are all 1, and the row weights of the N rows following the last row of the second lower triangular matrix in the extended parity-check matrix are all 1. The second lower triangular matrix is ​​any one of the at least one lower triangular matrix, and N is greater than or equal to 1. and, The next column after the last column of the second lower triangular matrix is ​​the column containing the first column of another lower triangular matrix among the plurality of lower triangular matrices.

6. The method according to claim 5, characterized in that, The diagonal elements of the plurality of lower triangular matrices are located in consecutive positions on the diagonal of the extended parity-check matrix. Furthermore, among the plurality of lower triangular matrices, only the third lower triangular matrice corresponds to the second feature. The first column of the third lower triangular matrix is ​​located after the last column of any matrix in the first matrix set, which includes the remaining matrices in the plurality of lower triangular matrices excluding the third lower triangular matrix.

7. The method according to any one of claims 1 to 6, characterized in that, The starting column of a redundant version RV of the basis matrix corresponds to the starting column of one of the plurality of lower triangular matrices.

8. The method according to claim 7, characterized in that, The starting column of the RV of the base matrix corresponds one-to-one with all columns in the first column set, which includes the starting columns of the plurality of lower triangular matrices, or the first column set includes the remaining columns of the starting columns of the plurality of lower triangular matrices excluding the first column of the extended parity matrix.

9. The method according to claim 7 or 8, characterized in that, The starting column of one RV of the base matrix corresponds to a column of the second column set, wherein the second column set includes the column containing the remaining diagonal elements of all diagonal elements of the extended parity matrix excluding all diagonal elements of the plurality of lower triangular matrices.

10. The method according to claim 6, characterized in that, The starting column of a redundant version RV of the basis matrix corresponds to the starting column of one of the plurality of lower triangular matrices, and the starting column of one RV of the basis matrix corresponds to the column after the last column of the third lower triangular matrix.

11. The method according to claim 10, characterized in that, The N is greater than or equal to 2. The starting column of one RV of the basis matrix also corresponds to a column in the third column set, wherein the third column set is the set of columns remaining in the N columns after the last column of the third lower triangular matrix, excluding the first column of the N columns.

12. A communication device, characterized in that, The device includes at least one processor and an interface circuit, the interface circuit being configured to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, the processor causing the method as described in any one of claims 1 to 11 to be implemented via logic circuits or executing code instructions.

13. The communication device according to claim 12, characterized in that, The communication device is a chip or chip system.

14. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed, cause the method as described in any one of claims 1 to 11 to be implemented.

15. A computer program product, characterized in that, Includes a computer program that, when run, causes the method as described in any one of claims 1 to 11 to be implemented.

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