Register configuration apparatus and method, data processing circuit and electronic device

Abstract

The present application belongs to the technical field of data storage. Disclosed are a register configuration apparatus and method, a data processing circuit and an electronic device. The data processing circuit is connected to a memory and at least one register. A first command queue group is stored in the memory, each command queue in the first command queue group having a corresponding storage space of same size in the memory. The data processing circuit is used for determining, on the basis of the starting physical address of a starting command queue and a preset data bit width, a physical address in the memory corresponding to each first command queue in a first sub-command queue group, and caching, on the basis of the physical address corresponding to each first command queue, register configuration information stored in each first command queue. The data processing circuit is further used for allocating to a corresponding register the cached register configuration information of each first command queue.

Description

Register configuration apparatus, method, data processing circuit and electronic device

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202410859508.0, filed on June 28, 2024, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application belongs to the technical field of data storage, and particularly relates to a register configuration apparatus, method, data processing circuit and electronic device. BACKGROUND

[0004] At present, an electronic device can configure register information, such as register addresses and register data, in the electronic device through a linked list data structure.

[0005] In related technologies, an electronic device can find a linked list through a physical address stored in a head of the linked list, and then obtain corresponding register configuration information stored in the linked list. Then, the electronic device can obtain corresponding register configuration information stored in a next linked list through a physical address of the next linked list stored in a tail of the linked list. In this way, the electronic device can configure different register configuration information.

[0006] However, in the above method, when the electronic device obtains the physical address of the next linked list, the electronic device needs to perform a triggering operation again, that is, to determine the position of the next linked list in the memory according to the physical address of the next linked list, and then to obtain the corresponding register configuration information stored in the next linked list. Further, when the electronic device configures multiple registers, the electronic device needs to perform multiple triggering operations, which leads to a relatively cumbersome and time-consuming process of configuring multiple registers by the electronic device. Therefore, the efficiency of configuring multiple registers by the electronic device is relatively poor. SUMMARY

[0007] An object of embodiments of the present application is to provide a register configuration apparatus, method, data processing circuit and electronic device, which can improve the efficiency of configuring multiple registers by an electronic device.

[0008] In a first aspect, an embodiment of the present application provides a data processing circuit, which is connected with a memory and at least one register respectively; the memory stores a first command queue group, and a size of a corresponding storage space of each command queue in the first command queue group in the memory is the same; wherein the data processing circuit is configured to determine a physical address corresponding to each first command queue in a first sub-command queue group in the memory based on a starting physical address of a starting command queue and a preset data bit width, and cache register configuration information stored in each first command queue based on the physical address corresponding to each first command queue; the starting command queue is one of the command queues in the first command queue group, and the first sub-command queue group includes the starting command queue and each command queue after the starting command queue; and the data processing circuit is further configured to allocate the cached register configuration information of each first command queue to a corresponding register.

[0009] In a second aspect, an embodiment of the present application provides a register configuration method, which includes: determining, by a data processing circuit, a physical address corresponding to each first command queue in a first sub-command queue group in a memory based on a starting physical address of a starting command queue and a preset data bit width, and caching register configuration information stored in each first command queue based on the physical address corresponding to each first command queue; the starting command queue is one of the command queues in the first command queue group, the first sub-command queue group includes the starting command queue and each command queue after the starting command queue, and the first command queue group is stored in the memory, and a size of a corresponding storage space of each command queue in the first command queue group in the memory is the same; and allocating, by the data processing circuit, the cached register configuration information of each first command queue to a corresponding register.

[0010] In a third aspect, an embodiment of the present application provides a register configuration device, which includes a data processing circuit, a memory and at least one register; wherein the data processing circuit is connected with the memory and the at least one register respectively.

[0011] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, the memory stores programs or instructions executable on the processor, and the programs or instructions are executed by the processor to implement the steps of the method according to the second aspect.

[0012] In a fifth aspect, an embodiment of the present application provides a readable storage medium, which stores programs or instructions, and the programs or instructions are executed by a processor to implement the steps of the method according to the second aspect.

[0013] In a sixth aspect, an embodiment of the present application provides a chip, which comprises a processor and a communication interface, the communication interface is coupled with the processor, and the processor is configured to run programs or instructions to implement the method in the second aspect.

[0014] In a seventh aspect, an embodiment of the present application provides a computer program product stored in a storage medium, which is executed by at least one processor to implement the method in the second aspect.

[0015] In the embodiment of the present application, the data processing circuit is connected with the memory and the at least one register respectively, and the memory stores a first command queue group, and the size of the corresponding storage space of each command queue in the first command queue group in the memory is the same; wherein, the data processing circuit is configured to determine the physical address corresponding to each first command queue in the first sub-command queue group in the memory based on the starting physical address of the starting command queue and the preset data bit width, and cache the register configuration information stored in each first command queue based on the physical address corresponding to each first command queue, the starting command queue being one of the command queues in the first command queue group, and the first sub-command queue group including the starting command queue and each command queue after the starting command queue; and the data processing circuit is further configured to allocate the cached register configuration information of each first command queue to the corresponding register. In the scheme, since the storage size of each command queue is the same, after obtaining the physical address corresponding to the starting queue in the first sub-command queue group, the electronic device can directly determine the physical address of the next command queue after the preset storage space. In this way, the electronic device only needs to be triggered once to obtain the register configuration information stored in each command queue in the first sub-command queue group, thereby improving the efficiency of the electronic device in configuring multiple registers. BRIEF DESCRIPTION OF DRAWINGS

[0016] FIG. 1 is a structural schematic diagram of a linked list in the related art;

[0017] FIG. 2 is a structural schematic diagram of a data processing circuit according to an embodiment of the present application;

[0018] FIG. 3 is a structural schematic diagram of a first command queue group according to an embodiment of the present application;

[0019] FIG. 4 is a structural schematic diagram of a command queue group according to an embodiment of the present application;

[0020] FIG. 5 is a structural schematic diagram of a data processing circuit according to another embodiment of the present application;

[0021] FIG. 6 is a structural schematic diagram of a data processing circuit according to still another embodiment of the present application;

[0022] Figure 7 is a structural schematic diagram of one of the memory arrangement modes provided by the embodiments of the present application;

[0023] Figure 8 is a structural schematic diagram of another of the memory arrangement modes provided by the embodiments of the present application;

[0024] Figure 9 is a structural schematic diagram of a third of the memory arrangement modes provided by the embodiments of the present application;

[0025] Figure 10 is a structural schematic diagram of a fourth of the data processing circuit provided by the embodiments of the present application;

[0026] Figure 11 is a structural schematic diagram of a fifth of the data processing circuit provided by the embodiments of the present application;

[0027] Figure 12 is a structural schematic diagram of a sixth of the data processing circuit provided by the embodiments of the present application;

[0028] Figure 13 is a structural schematic diagram of a seventh of the data processing circuit provided by the embodiments of the present application;

[0029] Figure 14 is a structural schematic diagram of an eighth of the data processing circuit provided by the embodiments of the present application;

[0030] Figure 15 is a structural schematic diagram of a ninth of the data processing circuit provided by the embodiments of the present application;

[0031] Figure 16 is a flowchart of one of the register configuration methods provided by the embodiments of the present application;

[0032] Figure 17 is a flowchart of another of the register configuration methods provided by the embodiments of the present application;

[0033] Figure 18 is a hardware structural schematic diagram of one of the electronic devices provided by the embodiments of the present application;

[0034] Figure 19 is a hardware structural schematic diagram of another of the electronic devices provided by the embodiments of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0036] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0037] The terms "at least one," "at least one of," etc., used in the specification and claims of this application refer to any one, any two, or a combination of two or more of the included items. For example, at least one of a, b, and c can mean: "a," "b," "c," "a and b," "a and c," "b and c," and "a, b, and c," where a, b, and c can be single or multiple. Similarly, "at least two" refers to two or more items, and its meaning is similar to that of "at least one."

[0038] The technical terms used in the embodiments of this application will be explained in detail below.

[0039] Advanced Peripheral Bus (APB) protocol: As an advanced peripheral bus, APB is one of the protocols in the Advanced Microcontroller Bus Architecture (AMBA) and is also the most basic bus protocol. According to the official definition, APB is a low-cost interface protocol that enables low power consumption and simplified interface design, reducing the complexity of interface design.

[0040] The APB protocol does not support pipelined design and is primarily used in interfaces with low bandwidth requirements. High-performance, high-bandwidth requirements can be met using the Advanced eXtensible Interface (AXI) bus. The APB protocol implementation is clock-edge aligned to simplify peripheral interface design. Each transmission requires at least two clock cycles.

[0041] System on a chip In a chip (SOC) design, the APB is generally configured as an interface of a functional module (Intellectual Property, IP) in a register system, including low-speed peripherals such as I2C, UART, I2S, and high-speed IPs such as DDR, PCIe, Ethernet, and the like, and can facilitate the register configuration of a CPU on the peripheral IP. An AXI2APB or AHB2APB conversion bridge is generally implemented in the system to mount the APB port on the system.

[0042] The AHB-Lite protocol is part of AMBA 3 (Advanced Microcontroller Bus Architecture), which is a high-performance bus interface with higher performance than the APB and can support communication between a single master and multiple slaves.

[0043] A queue allows only a deletion operation at the front end of the table and an insertion operation at the rear end of the table. The end for the insertion operation is called a queue tail, and the end for the deletion operation is called a queue head. When there is no element in the queue, it is called an empty queue.

[0044] The register configuration device, method, data processing circuit, electronic device and medium provided in the embodiments of the present application will be described in detail in combination with the accompanying drawings, specific embodiments and application scenarios.

[0045] The register configuration device, method, data processing circuit and electronic device provided in the embodiments of the present application can be applied in a scenario of configuring multiple registers.

[0046] At present, with the improvement of the integration of SOC chips, the complexity of multimedia subsystems such as image processing is increasing, and the number of registers brought by this is increasing exponentially.

[0047] Generally, an electronic device can rely on multiple configuration registers of an AHB_Lite protocol or an APB protocol issued by a central processing unit (CPU). If the number is too large, it will cause problems in the register configuration mechanism of the entire subsystem based on shadow, that is, the time for configuring the registers of the next frame under the current frame will cover the current frame and the next frame, resulting in that the next frame cannot be shadowed and needs to be shadowed until the next frame. This situation is particularly prominent in register reconfiguration during image switching or scene switching.

[0048] In order to solve such problems, a scheme of directly accessing memory in a command queue by using DMA is usually introduced in the industry to reduce the register configuration pressure of the subsystem. A common implementation is as shown in FIG. 1. The register address and the register configuration value are stored in the memory in close arrangement, form a command queue in a certain size, and the tail of each command queue, denoted as Footer in FIG. 1, is linked to the head of the next command queue, denoted as Header in FIG. 1, until the end of the chain.

[0049] However, in the above scheme, the electronic device needs to perform a triggering operation again when the physical address of the next chain table is obtained, that is, the position of the next chain table in the memory is determined according to the physical address of the next chain table, and then the corresponding register configuration information stored in the next chain table can be obtained. Further, the electronic device needs to perform multiple triggering operations when configuring multiple registers, which leads to a relatively cumbersome and time-consuming process of configuring multiple registers by the electronic device, and thus the efficiency of configuring multiple registers by the electronic device is poor. Moreover, the design and control logic of the chain table are relatively complex.

[0050] In the register configuration apparatus, method, data processing circuit and electronic device provided in the embodiments of the present application, since the storage size of each command queue is the same, after the electronic device obtains the physical address corresponding to the starting queue in the first sub-command queue group, the electronic device can directly determine the physical address of the next command queue after the preset storage space. In this way, the electronic device only needs to trigger once to obtain the register configuration information stored in each command queue in the first sub-command queue group, and thus the efficiency of configuring multiple registers by the electronic device is improved.

[0051] In the data processing circuit provided in the embodiments of the present application, as shown in FIG. 2, the data processing circuit 20 is connected with the memory 21 and at least one register 22.

[0052] In the embodiments of the present application, the data processing circuit is configured to determine the physical address corresponding to each first command queue in the first sub-command queue group in the memory based on the starting physical address of the starting command queue and the preset data bit width, and cache the register configuration information stored in each first command queue based on the physical address corresponding to each first command queue. The starting command queue is one of the command queues in the first command queue group, and the first sub-command queue group includes the starting command queue and each command queue after the starting command queue.

[0053] For example, as shown in FIG. 3, the memory includes N first command queues 10, the N first command queues form a first command queue group 101, and the N-1 first command queues form a first sub-command queue group 102.

[0054] In the embodiments of the present application, the functional module in one of the subsystems of the electronic device comprises at least one register.

[0055] In the embodiments of the present application, the data processing circuit is further configured to assign the register configuration information of each first command queue in the first sub-command queue group to the corresponding register.

[0056] In the embodiments of the present application, the memory stores a first command queue group, and each command queue in the first command queue group has the same size of the corresponding storage space in the memory.

[0057] Optionally, in the embodiments of the present application, each command queue in the first command queue group comprises a first entry and a second entry. That is, each command queue in the first command queue group does not contain a queue tail.

[0058] In the embodiments of the present application, the first entry is configured to store a starting physical address, and the second entry is configured to store register configuration information, and the data bit width corresponding to the first entry and the second entry is a preset data bit width.

[0059] For example, the preset data bit width can be 4 bytes or 8 bytes. The actual use can be determined, and the embodiments of the present application are not limited.

[0060] Optionally, in the embodiments of the present application, the second entry can be one or more.

[0061] For example, as shown in FIG. 4, a command queue comprises a first entry, denoted as Header in FIG. 4, and a second entry, denoted as Payload in FIG. 4.

[0062] In the embodiments of the present application, each two command queues in the first command queue group are arranged adjacently.

[0063] Optionally, in the embodiments of the present application, each command queue in the first command queue group corresponds to one register.

[0064] Optionally, in the embodiments of the present application, the subsystem can be an image processing subsystem, an image display subsystem, a data operation subsystem, etc. The actual use can be determined, and the embodiments of the present application are not limited.

[0065] Optionally, in the embodiments of the present application, the register configuration information can comprise at least one of the following: a register address and register data.

[0066] Optionally, in the embodiments of the present application, the command queue can be any one of a linked list queue or a set queue.

[0067] Optionally, in the embodiments of the present application, the storage size corresponding to each command queue in the first command queue group can be preset. For example, the storage size corresponding to each command queue in the first command queue group can be 128 bytes or 256 bytes. The actual use can be determined, and the embodiments of the present application are not limited.

[0068] Optionally, in the embodiments of the present application, the physical address corresponding to the start command queue is transmitted from the CPU in the electronic device to the data processing circuit.

[0069] In the data processing circuit provided in the embodiments of the present application, the data processing circuit is connected with the memory and at least one register respectively; the memory stores a first command queue group, and the storage space corresponding to each command queue in the first command queue group in the memory has the same size; wherein the data processing circuit is configured to determine the physical address corresponding to each first command queue in the first sub-command queue group in the memory based on the start physical address of the start command queue and a preset data bit width, and cache the register configuration information stored in each first command queue based on the physical address corresponding to each first command queue, the start command queue being one of the command queues in the first command queue group, and the first sub-command queue group including the start command queue and each command queue after the start command queue; the data processing circuit is further configured to allocate the cached register configuration information of each first command queue to the corresponding register. In the present scheme, since the storage size of each command queue is the same, after the electronic device obtains the physical address corresponding to the start queue in the first sub-command queue group, the electronic device can directly determine the physical address of the next command queue after the preset storage space. In this way, the electronic device only needs to trigger once to obtain the register configuration information stored in each command queue in the first sub-command queue group, thereby improving the efficiency of the electronic device in configuring multiple registers.

[0070] Optionally, in the embodiments of the present application, as shown in FIG. 5, the data processing circuit 20 includes a triggering module 201 and a caching module 202 in combination with FIG. 2.

[0071] In the embodiments of the present application, the triggering module 201 is connected with the memory 21, and the caching module 201 is connected with the memory 21 and at least one register 22 respectively.

[0072] In the embodiments of the present application, the triggering module is configured to receive a register configuration trigger message sent by the processor, and the register configuration trigger message includes the start physical address of the start command queue.

[0073] The trigger module is further configured to determine the physical address corresponding to each first command queue in the first sub-command queue group in the memory based on the starting physical address of the starting command queue and a preset data bit width.

[0074] The cache module is configured to obtain the register configuration information stored in each first command queue from the physical address corresponding to each first command queue, and cache the register configuration information.

[0075] The cache module is further configured to allocate the cached register configuration information of each first command queue to the corresponding register.

[0076] Optionally, in an embodiment of the present application, the data processing circuit can obtain the physical address corresponding to the starting command queue, and then sequentially increase from the starting command queue according to the preset data bit width to obtain the physical address corresponding to each first command queue in the first sub-command queue group.

[0077] Illustratively, the preset data bit width can be preset.

[0078] Illustratively, assuming that the physical address corresponding to the starting command queue is 8, the data processing circuit can start from 8 and automatically increase by 4 each time to obtain the physical address corresponding to each first command queue in the first sub-command queue group.

[0079] It can be understood that, since each first command queue in the first sub-command queue group is arranged adjacently, the data processing circuit only needs the physical address corresponding to the starting command queue to directly obtain the register configuration information stored in all command queues from the starting command queue to the ending command queue.

[0080] Optionally, in an embodiment of the present application, after the data processing circuit caches the register configuration information stored in each first command queue in the first sub-command queue group, the data processing circuit can perform parsing processing on the register configuration information stored in each first command queue in the first sub-command queue group to determine the register corresponding to each first command queue in the first sub-command queue group.

[0081] Illustratively, the data processing circuit can determine the register corresponding to each first command queue in the first sub-command queue group according to the register address stored in each first command queue in the first sub-command queue group.

[0082] Optionally, in an embodiment of the present application, after determining the register corresponding to each first command queue, the data processing circuit can sequentially configure the register configuration information stored in each first command queue to the corresponding register, or the data processing circuit can concurrently configure the register configuration information stored in each first command queue to the corresponding register.

[0083] In an example, after the data processing circuit stores the register configuration information stored in the five first command queues and determines the registers corresponding to the five first command queues respectively, the data processing circuit can first configure the register configuration information stored in the first first command queue to the register corresponding to the first first command queue; then, configure the register configuration information stored in the second first command queue to the register corresponding to the second first command queue; and so on, until the register configuration information stored in the fifth first command queue is configured to the register corresponding to the fifth first command queue. In this way, the register configuration information stored in each first command queue is sequentially configured to the corresponding register.

[0084] In another example, after the data processing circuit stores the register configuration information stored in the five first command queues and determines the registers corresponding to the five first command queues respectively, the data processing circuit can simultaneously configure the register configuration information stored in the five first command queues to the registers corresponding to the five first command queues. In this way, the register configuration information stored in each first command queue is concurrently configured to the corresponding register.

[0085] In this way, the data processing circuit can concurrently configure the register configuration information stored in each first command queue in the first sub-command queue group to the corresponding register, without sequentially configuring each first command queue in the first sub-command queue group to the corresponding register through the CPU, thereby improving the efficiency of configuring multiple registers.

[0086] Optionally, in an embodiment of the present application, as shown in FIG. 6, the trigger module 201 includes a configuration register 2011 and a control unit 2012.

[0087] In the embodiment of the present application, the first end of the configuration register 2011 is connected with the processor 30.

[0088] The second end of the configuration register is connected with the first end of the control unit.

[0089] In the embodiment of the present application, the configuration register is configured to receive the register configuration trigger message sent by the processor and store the start physical address of the start command queue.

[0090] The control unit is configured to generate the physical address corresponding to each first command queue in the first sub-command queue group based on the preset data bit width and the start physical address, and send a data read command to the physical address corresponding to each first command queue in the first sub-command queue group.

[0091] Optionally, in embodiments of the present application, the control unit is specifically configured to, in a case where the register configuration information stored in each first command queue in the first sub-command queue group is in a first arrangement mode, generate a physical address corresponding to each first command queue in the first sub-command queue group based on a target data bit width and a starting physical address, and send a data read command to the physical address corresponding to each first command queue in the first sub-command queue group.

[0092] In embodiments of the present application, the first arrangement mode is any one of an incremental arrangement mode or a singleton arrangement mode, and the target data bit width is obtained by multiplying a preset data bit width and an address generation number.

[0093] In embodiments of the present application, the control unit can determine that the register configuration information stored in each first command queue is in the first arrangement mode based on the arrangement mode identifier stored in the head of each first command queue in the first sub-command queue group.

[0094] Exemplarily, as shown in FIG. 7, the incremental arrangement mode is as shown in FIG. 7, where 0 and 31 in FIG. 7 are 4 bytes, i.e. 32 bits, which is the storage size of each entry in a first queue. CMD MODE in FIG. 5 is a data arrangement mode identifier, Reserved is a reserved field, and Register Number is the number of register configuration information that can be stored in a first queue. Start address of one group of register in FIG. 7 is the physical address of the register corresponding to a first queue, and Register Data 0 to Register Data N are the number of register configuration information that can be stored.

[0095] Exemplarily, as shown in FIG. 8, the above-mentioned single arrangement mode is shown in FIG. 8, where 0 and 31 in FIG. 8 are 4 bytes, i.e. 32 bits, which is the storage size of each entry in a first queue. CMD MODE in FIG. 5 is the data arrangement mode identifier, Reserved is a reserved field, and Register Number is the number of register configuration information that can be stored in a first queue. Register Address 0 in FIG. 8 is the physical address of the first register, and Register Data 0 is the register configuration information of the first register; Register Address 1 is the physical address of the second register, and Register Data 0 is the register configuration information of the second register; Register Address 2 is the physical address of the third register, and Register Data 2 is the register configuration information of the third register; and Register Address N is the physical address of the N+1th register, and Register Data N is the register configuration information of the N+1th register.

[0096] Optionally, in the embodiment of the present application, the control unit is further configured to, in the case that the register configuration information stored in each first command queue is in a second arrangement mode, send a starting physical address to the subsystem, and control the subsystem to generate a physical address corresponding to each first command queue based on the starting physical address and a target data bit width; receive the physical address corresponding to each first command queue generated by the subsystem, and send a data read command to the physical address corresponding to each first command queue.

[0097] In the embodiment of the present application, the above-mentioned second arrangement mode is a repeated read arrangement mode.

[0098] In the embodiment of the present application, the control unit can determine that the register configuration information stored in each first command queue is in a second arrangement mode based on the data arrangement mode identifier stored in the head of each first command queue.

[0099] Exemplarily, as shown in FIG. 9, the above-mentioned repeated read arrangement mode is shown in FIG. 9, where 0 and 31 in FIG. 9 are 4 bytes, i.e. 32 bits, which is the storage size of each entry in a first queue. CMD MODE in FIG. 7 is the data arrangement mode, Reserved is a reserved field, and Register Number is the number of register configuration information that can be stored in a first queue. One Specified Address in FIG. 7 is the physical address of the register corresponding to a first queue, and Register Data 0 to Register Data N are the number of register configuration information that can be stored.

[0100] Optionally, in the embodiments of the present application, as shown in FIG. 10, the control unit 2012 further comprises a control subunit 40 and a read address generator 41 connected in sequence.

[0101] The control subunit is configured to generate a first physical address based on a start physical address of the start command queue and a target data bit width, the target data bit width being obtained by multiplying a preset data bit width and an address generation number.

[0102] The read address generator is configured to generate a data read command corresponding to the first command queue based on the first physical address.

[0103] Optionally, in the actual examples of the present application, as shown in FIG. 11, the control subunit 40 comprises a controller 401 and a read arbiter 402.

[0104] In the embodiments of the present application, the read arbiter and the read address generator are intercepted.

[0105] In the embodiments of the present application, the read arbiter is configured to guide the generation of a command queue in the memory according to the N-way buffer.

[0106] Optionally, in the embodiments of the present application, as shown in FIG. 12, the cache module 202 comprises a data cache unit 2021 and a data configuration unit 2022 connected in sequence.

[0107] In the embodiments of the present application, the data cache unit 2021 is connected with the memory 21, and the data configuration unit is connected with at least one register 22.

[0108] In the embodiments of the present application, the data cache unit is configured to receive register configuration information stored in each first command queue in the first sub-command queue group sent by the memory, and cache the register configuration information stored in each first command queue in the first sub-command queue group.

[0109] The data configuration unit is configured to allocate the cached register configuration information of each first command queue in the first sub-command queue group to a corresponding register.

[0110] Optionally, in the embodiments of the present application, as shown in FIG. 13, the data cache unit 2021 comprises a pre-cache subunit 50 and an N-way cache subunit 51 connected in sequence.

[0111] In the embodiments of the present application, the pre-cache subunit is configured to receive register configuration information stored in each first command queue sent by the memory, and cache the register configuration information stored in each first command queue.

[0112] In the embodiment of the present application, one cache subunit is used to store the register configuration information stored in one first command queue.

[0113] Optionally, in the embodiment of the present application, as shown in FIG. 14, the data cache unit 2021 further comprises an empty bus 52.

[0114] In the embodiment of the present application, the empty bus is used to empty the register configuration information cached in the data cache unit after the cached register configuration information of all first command queues is allocated to the corresponding registers.

[0115] Exemplarily, after the read arbiter receives the physical address corresponding to the start command queue sent by the control unit, the read arbiter can transmit the physical address corresponding to the start command queue to the read address generator; the read address generator can convert the physical address corresponding to the start command queue into the physical address corresponding to the start command queue in the memory, and determine the start command queue from the memory through the AXI bus and read the register configuration information stored in the start command queue; then, the read register configuration information is transmitted to the empty bus through the AXI bus, and then transmitted to the pre-cache subunit through the empty bus, and then transmitted to the N-way cache subunit through the pre-cache subunit; finally, after the N-way cache subunit caches all the register configuration information stored in the first command queue, the above-mentioned register configuration information stored in all the first command queue is sent to the processor; so that the processor analyzes all the register configuration information stored in the first command queue and transmits it to the configuration unit, and the configuration unit can configure at least one register concurrently.

[0116] Optionally, in the embodiment of the present application, as shown in FIG. 15, the above-mentioned data processing circuit further comprises a clock reset module 53 and an interrupt module 54, the clock reset module is used to reset the data processing circuit; the interrupt module is used to interrupt the acquisition of the physical address of the command queue in the memory after all the register configurations are completed.

[0117] In the register configuration device provided in the embodiment of the present application, the register configuration device comprises a data processing circuit, a memory and at least one register.

[0118] In the embodiment of the present application, the above-mentioned data processing circuit is connected with the memory and at least one register respectively, and the functional module in one subsystem comprises at least one register.

[0119] In the embodiment of the present application, all the command queues are pre-stored in the memory, and the processor only needs to configure the trigger to start the work of the data processing circuit, and the queues in the memory will be continuously read to the data processing circuit through the read channel of the AXI, and then the analysis work of various CMD MODE (incremental arrangement mode, single arrangement mode and repeated reading arrangement mode) is completed according to the indication of the head of the command queue, and finally the register values arranged in the memory are written into each IP in the subsystem to complete the efficient concurrent register configuration work.

[0120] Optionally, in the embodiment of the present application, the memory is configured to allocate a first entry and a second entry for the first storage space, store a starting physical address of the first storage space in the first entry, and store the first register configuration information in the second entry, so as to generate a command queue in the first storage space, and the data bit widths corresponding to the first entry and the second entry are both preset data bit widths.

[0121] In an example, in the case that the register data is a group of RGB pixel values, if a single component is 8 bits, three components are 24 bits in total, and in the case that the storage size of one entry is 4 bytes, i.e. 32 bits, the group of RGB pixel values can be stored in one entry.

[0122] In another example, if a single component is 12 bits, three components are 36 bits in total, and in the case that the storage size of one entry is 4 bytes, i.e. 32 bits, the group of RGB pixel values can be stored in two entries.

[0123] Optionally, in the embodiment of the present application, the first register configuration information includes a register address and at least one register data.

[0124] In the embodiment of the present application, the memory is specifically configured to store the register address and the at least one register data in the second entry in sequence according to a memory alignment strategy.

[0125] Optionally, in the embodiment of the present application, the electronic device can store the register address and the at least one register data in the second entry in sequence according to a memory alignment strategy through a first writing mode.

[0126] Exemplarily, the first writing mode can be high-bit writing or low-bit writing.

[0127] In the embodiment of the present application, the register address and the register data stored in the memory are no longer closely arranged, so that the efficiency of reading the stored information in the memory can be improved.

[0128] The execution subject of the register configuration method provided in the embodiments of the present application can be a register configuration apparatus, which can be an electronic device or a functional module in the electronic device. The technical solutions provided in the embodiments of the present application are described below by taking an electronic device as an example.

[0129] The embodiments of the present application provide a register configuration method, and FIG. 16 shows a flowchart of a register configuration method provided in the embodiments of the present application. As shown in FIG. 16, the register configuration method provided in the embodiments of the present application can include the following steps 201 and 202.

[0130] In step 201, the electronic device determines, by using a data processing circuit, a physical address corresponding to each first command queue in a first sub-command queue group in the memory based on a starting physical address of a starting command queue and a preset data bit width, and caches register configuration information stored in each first command queue based on the physical address corresponding to each first command queue.

[0131] In the embodiments of the present application, the starting command queue is one of the first command queue group, and the first sub-command queue group includes the starting command queue and each command queue after the starting command queue.

[0132] In the embodiments of the present application, the functional module in one subsystem in the electronic device includes at least one register.

[0133] Optionally, in the embodiments of the present application, the electronic device can obtain the physical address corresponding to the starting command queue, and sequentially increase from the starting command queue to obtain the physical address corresponding to each first command queue in the first sub-command queue group.

[0134] For example, assuming that the physical address corresponding to the starting command queue is 8, the data processing circuit can start from 8 and automatically increase by 4 each time to obtain the physical address corresponding to each first command queue.

[0135] It can be understood that, since each first command queue in the first sub-command queue group is arranged adjacently, the data processing circuit can directly obtain the register configuration information stored in all the command queues from the starting command queue to the ending command queue by using only the physical address corresponding to the starting command queue.

[0136] Optionally, in the embodiments of the present application, after the electronic device obtains the physical address corresponding to each first command queue in the first sub-command queue group, the register configuration information stored in the starting command queue can be cached by the electronic device, and the register configuration information in the next first command queue after the starting command queue can be pre-cached by using a pre-caching unit.

[0137] In this way, the electronic device can improve the efficiency of caching the register configuration information and the efficiency of processing the register configuration information by pre-caching the register configuration information in the next first command queue.

[0138] In step 202, the electronic device assigns the cached register configuration information of each first command queue to the corresponding register through the data processing circuit in the register configuration device.

[0139] In the embodiments of the present application, the electronic device can determine the register corresponding to the register configuration information according to the register configuration information contained in each command queue.

[0140] For example, after the electronic device caches the register configuration information stored in each first command queue in the first sub-command queue group, the electronic device parses the register address stored in each first command queue in the first sub-command queue group through the processor to determine the register corresponding to each first command queue in the first sub-command queue group.

[0141] Optionally, in the embodiments of the present application, the electronic device can sequentially configure the register configuration information stored in each first command queue in the first sub-command queue group to the corresponding register; or the electronic device can concurrently configure the register configuration information stored in each first command queue in the first sub-command queue group to the corresponding register.

[0142] In one example, after the electronic device caches the register configuration information stored in the five first command queues and determines the registers corresponding to the five first command queues respectively, the electronic device can first configure the register configuration information stored in the first first command queue to the register corresponding to the first first command queue; then, configure the register configuration information stored in the second first command queue to the register corresponding to the second first command queue; and so on, until the register configuration information stored in the fifth first command queue is configured to the register corresponding to the fifth first command queue. In this way, the register configuration information stored in each first command queue is sequentially configured to the corresponding register.

[0143] In another example, after the electronic device caches the register configuration information stored in the five first command queues and determines the registers corresponding to the five first command queues respectively, the electronic device can concurrently configure the register configuration information stored in the five first command queues to the registers corresponding to the five first command queues. In this way, the register configuration information stored in each first command queue is concurrently configured to the corresponding register.

[0144] In this way, the electronic device can concurrently configure the register configuration information stored in each first command queue in the first sub-command queue group to the corresponding register, without sequentially configuring each first command queue in the at least one first command queue to the corresponding register through the CPU, thereby improving the efficiency of configuring multiple registers.

[0145] Optionally, in an embodiment of the present application, after the electronic device caches the register configuration information stored in each first command queue in the first sub-command queue group, the electronic device can perform parsing processing on the register configuration information stored in each first command queue in the first sub-command queue group to determine the register corresponding to each first command queue.

[0146] For example, the electronic device can determine the register corresponding to each first command queue in the first sub-command queue group according to the register address stored in each first command queue in the first sub-command queue group.

[0147] For example, the electronic device compares the register address stored in one first command queue with the register address corresponding to the register, so as to determine the register corresponding to one first command queue in the case that the register address stored in one first command queue is the same as the register address corresponding to the register.

[0148] It should be noted that, for each first command queue in the first sub-command queue group, the electronic device can determine the register corresponding to each first command queue in the first sub-command queue group through the above embodiments. To avoid repetition, details are not described here.

[0149] In the register configuration method provided in the embodiment of the present application, the data processing circuit determines the physical address corresponding to each first command queue in the first sub-command queue group in the memory based on the starting physical address of the starting command queue and the preset data bit width, and caches the register configuration information stored in each first command queue based on the physical address corresponding to each first command queue. The data processing circuit in the register configuration device allocates the cached register configuration information of each first command queue to the corresponding register. In this scheme, since the storage size of each command queue is the same, after obtaining the physical address corresponding to the starting queue in the first sub-command queue group, the electronic device can directly determine the physical address of the next command queue after the preset storage space. In this way, the electronic device only needs to be triggered once to obtain the register configuration information stored in each command queue in the first sub-command queue group, thereby improving the efficiency of the electronic device in configuring multiple registers.

[0150] Optionally, in the embodiment of the present application, as shown in FIG. 17, the step 201 of "determining the physical address corresponding to each first command queue in the first sub-command queue group in the memory based on the starting physical address of the starting command queue and the preset data bit width" can be implemented by the following step 201a.

[0151] The step 201a, in the case that the register configuration information stored in each first command queue is in the third arrangement mode, the electronic device generates the physical address corresponding to each first command queue based on the target data bit width and the starting physical address.

[0152] In the embodiment of the present application, the third arrangement mode is any one of the incremental arrangement mode, the single instance arrangement mode or the repeated reading arrangement mode.

[0153] In the embodiment of the present application, the target data bit width is obtained by multiplying the preset data bit width and the address generation times.

[0154] It should be noted that the specific implementation process can be found in the above embodiments, and will not be repeated here.

[0155] Optionally, in the embodiment of the present application, the register configuration method provided by the embodiment of the present application further includes the following step 301.

[0156] The step 301, the electronic device allocates a first entry and a second entry for the first storage space through the memory, stores the starting physical address of the first storage space in the first entry, and stores the first register configuration information in the second entry, so as to generate a command queue in the first storage space.

[0157] Optionally, in the embodiment of the present application, the second entry can be at least one.

[0158] Optionally, in the embodiment of the present application, the register configuration information includes: a register address and a register data; and the register address and the register data are stored in different entries respectively.

[0159] Optionally, in the embodiment of the present application, the first register configuration information includes a register address and at least one register data; and the step 301 of "storing the first register configuration information in the second entry" can be implemented by the following step 301a.

[0160] The step 301a, the electronic device stores the register address and the at least one register data in the second entry in turn according to the memory alignment strategy through the memory.

[0161] Optionally, in the embodiments of the present application, when the register configuration information is a register address, the register configuration device can write the register address into a next entry in a command queue according to the high-bit mode.

[0162] Optionally, in the embodiments of the present application, when the register configuration information is a register data, the register configuration device can write the register address into a next entry in a command queue according to the high-bit mode.

[0163] In the embodiments of the present application, the electronic device can store the register configuration information through the memory alignment strategy, thereby improving the efficiency of reading the register configuration information by the electronic device.

[0164] The various method embodiments or various possible implementation manners in each method embodiment can be executed individually or in combination without contradiction, and the specific implementation can be determined according to actual use requirements, which is not limited in the embodiments of the present application.

[0165] The register configuration device in the embodiments of the present application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices except the terminal. For example, the mobile electronic device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc., and can also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, etc., which is not limited in the embodiments of the present application.

[0166] The register configuration device in the embodiments of the present application can be a device with an operating system. The operating system can be an Android operating system, an iOS operating system, or other possible operating systems, which is not limited in the embodiments of the present application.

[0167] The register configuration device provided in the embodiments of the present application can implement the processes of the above embodiments, and details are not repeated here to avoid repetition.

[0168] Optionally, as shown in FIG. 18, the embodiment of the application further provides an electronic device 90, comprising a processor 91 and a memory 92, wherein the memory 92 stores programs or instructions executable on the processor 91, and the programs or instructions are executed by the processor 91 to implement each step of the register configuration method embodiment and achieve the same technical effects. To avoid repetition, details are not described herein.

[0169] It should be noted that the electronic device in the embodiment of the application includes the mobile electronic device and the non-mobile electronic device.

[0170] FIG. 19 is a schematic diagram of a hardware structure of an electronic device for implementing the embodiment of the application.

[0171] The electronic device 100 includes but is not limited to the radio frequency unit 101, the network module 102, the audio output unit 103, the input unit 104, the sensor 105, the display unit 106, the user input unit 107, the interface unit 108, the memory 109, and the processor 110, etc.

[0172] Those skilled in the art can understand that the electronic device 100 can further include a power supply (such as a battery) for supplying power to each component, and the power supply can be logically connected to the processor 110 through a power management system, so as to realize the functions of power management, such as charging, discharging, and power consumption management, through the power management system. The electronic device structure shown in FIG. 19 does not constitute a limitation on the electronic device, and the electronic device can include more or fewer components than the illustrated components, or combine certain components, or different component arrangements, which are not described herein.

[0173] The processor 110 is configured to determine, by the data processing circuit in the register configuration apparatus, a physical address corresponding to each first command queue in a first sub-command queue group in the memory based on a starting physical address of a starting command queue and a preset data bit width, and cache register configuration information stored in each first command queue based on the physical address corresponding to each first command queue, the starting command queue being one of the first command queue group, and the first sub-command queue group including the starting command queue and each command queue after the starting command queue; and distribute, by the data processing circuit in the register configuration apparatus, the cached register configuration information of each first command queue to a corresponding register.

[0174] The electronic device provided in the embodiments of the present application can directly determine the physical address of the next command queue after the starting queue in the first sub-command queue group corresponds to the physical address, because the storage size of each command queue is the same. In this way, the electronic device only needs to be triggered once to obtain the register configuration information stored in each command queue in the first sub-command queue group, thereby improving the efficiency of the electronic device in configuring multiple registers.

[0175] Optionally, in the embodiments of the present application, the processor 110 is specifically configured to, in the case that the register configuration information stored in each first command queue is in a third arrangement mode, generate the physical address corresponding to each first command queue based on the target data bit width and the starting physical address, the first arrangement mode being any one of an incremental arrangement mode or a singleton arrangement mode; wherein the target data bit width is obtained by multiplying the preset data bit width and the address generation number, and the third arrangement mode is any one of an incremental arrangement mode, a singleton arrangement mode or a repeated reading arrangement mode.

[0176] Optionally, in the embodiments of the present application, the processor 110 is further configured to allocate a first entry and a second entry for the first storage space through the memory, store the starting physical address of the first storage space in the first entry, and store the first register configuration information in the second entry, so as to generate a command queue in the first storage space.

[0177] Optionally, in the embodiments of the present application, the first register configuration information includes a register address and at least one register data; and the processor 110 is specifically configured to store the register address and the at least one register data in the second entry in sequence according to a memory alignment strategy through the memory.

[0178] The electronic device provided in the embodiments of the present application can implement each process achieved by the method embodiments, and achieve the same technical effects. To avoid repetition, details are not described here.

[0179] The beneficial effects of various implementation manners in the embodiments can refer to the beneficial effects of the corresponding implementation manners in the method embodiments, and details are not described here to avoid repetition.

[0180] It should be understood that in the embodiments of the present application, the input unit 104 can include a graphics processor (GPU) 1041 and a microphone 1042. The graphics processor 1041 processes image data of a still picture or a video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 106 can include a display panel 1061, which can be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also referred to as a touch screen. The touch panel 1071 can include two parts of a touch detection device and a touch controller. The other input devices 1072 can include, but are not limited to, a physical keyboard, function keys (such as volume control keys, on-off keys, and the like), a trackball, a mouse, a joystick, and the like, which will not be described here.

[0181] The memory 109 can be used to store software programs and various data. The memory 109 can mainly include a first storage area storing programs or instructions and a second storage area storing data, wherein the first storage area can store an operating system, application programs or instructions required by at least one function (such as a sound playing function, an image playing function, and the like), and the like. In addition, the memory 109 can include a volatile memory or a non-volatile memory, or the memory 109 can include both volatile and non-volatile memories. The non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synch link dynamic random access memory (SLDRAM), and a direct memory bus random access memory (Direct Rambus RAM, DRRAM). The memory 109 in the embodiments of the present application includes but is not limited to these and any other suitable types of memory.

[0182] The processor 110 can include one or more processing units; optionally, the processor 110 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and an application program, and the modem processor mainly processes a wireless communication signal, such as a baseband processor. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 110.

[0183] The embodiment of the present application further provides a readable storage medium, and the readable storage medium stores a program or instructions, the program or instructions are executed by a processor to realize various processes of the above-mentioned method embodiments, and the same technical effects can be achieved, and details are not repeated here.

[0184] The processor is the processor in the electronic device in the above-mentioned embodiments. The readable storage medium includes a computer readable storage medium, such as a computer readable only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like.

[0185] The embodiment of the present application further provides a chip, and the chip includes a processor and a communication interface, the communication interface is coupled with the processor, and the processor is used to run a program or instructions to realize various processes of the above-mentioned method embodiments, and the same technical effects can be achieved, and details are not repeated here.

[0186] It should be understood that the chip mentioned in the embodiment of the present application can also be referred to as a system level chip, a system chip, a chip system, or a system on chip, and the like.

[0187] The embodiment of the present application provides a computer program product, and the program product is stored in a storage medium, and the program product is executed by at least one processor to realize various processes of the above-mentioned register configuration method embodiments, and the same technical effects can be achieved, and details are not repeated here.

[0188] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. Furthermore, it is to be understood that the method and apparatus of the present application can be carried out by more than one process, method, article, or apparatus either simultaneously, concurrently, or with intervening action that are carried out at the same time, either in a simultaneous fashion or in a fashion that is interleaved in time. For example, the described methods can be performed in a different order from that described, and / or various steps can be combined or omitted, and / or additional steps can be added, without departing from the scope of the present application. Also, features described with respect to certain examples can be combined in other examples.

[0189] From the above description of the embodiments, it is apparent that the above-described method of the embodiments can be realized by means of software and general-purpose hardware platforms, and of course, can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such an understanding, the technical solutions of the present application can be embodied in the form of a computer software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk), and includes a plurality of instructions for causing a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the method described in each embodiment of the present application.

[0190] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-described specific embodiments, and the above-described specific embodiments are merely illustrative, rather than limiting, and those of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims, which all belong to the protection of the present application.

Claims

1. A data processing circuit, the data processing circuit being connected to a memory and at least one register respectively; The memory stores a first command queue group, and each command queue in the first command queue group has the same storage space size in the memory. in, The data processing circuit is used to determine the physical address corresponding to each first command queue in the first sub-command queue group in the memory based on the starting physical address of the starting command queue and the preset data bit width, and to cache the register configuration information stored in each first command queue based on the physical address corresponding to each first command queue. The starting command queue is one of the command queues in the first command queue group, and the first sub-command queue group includes the starting command queue and each command queue after the starting command queue. The data processing circuit is also used to allocate the cached register configuration information of each of the first command queues to the corresponding registers.

2. The data processing circuit according to claim 1, wherein, Each command queue in the first command queue group includes a first entry and a second entry; The first entry is used to store the starting physical address, and the second entry is used to store register configuration information. The data bit widths corresponding to the first entry and the second entry are both preset data bit widths.

3. The data processing circuit according to claim 1, wherein, The data processing circuit includes: a trigger module and a cache module; The triggering module is connected to the memory; The cache module is connected to the memory and at least one register, respectively. The triggering module is used to receive a register configuration trigger message sent by the processor, wherein the register configuration trigger message contains the starting physical address of the starting command queue; The triggering module is also used to determine the physical address corresponding to each first command queue in the first sub-command queue group in the memory based on the starting physical address of the starting command queue and the preset data bit width; The caching module is used to obtain the register configuration information stored in each first command queue from the physical address corresponding to each first command queue, and cache the register configuration information; The cache module is further configured to allocate the cached register configuration information of each of the first command queues to the corresponding registers.

4. The data processing circuit according to claim 3, wherein, The triggering module includes: a configuration register and a control unit; The first end of the configuration register is connected to the processor; The second end of the configuration register is connected to the first end of the control unit; The configuration register is used to receive the register configuration trigger message sent by the processor and to store the starting physical address of the starting command queue. The control unit is configured to generate a physical address corresponding to each first command queue based on the preset data bit width and the starting physical address, and send a data read command to the physical address corresponding to each first command queue.

5. The data processing circuit according to claim 3, wherein, The control unit is specifically configured to, when the register configuration information stored in each first command queue is in a first arrangement mode, generate a physical address corresponding to each first command queue based on the target data bit width and the starting physical address, and send a data read command to the physical address corresponding to each first command queue. The first arrangement mode is either an incremental arrangement mode or a singleton arrangement mode, and the target data bit width is obtained by multiplying the preset data bit width by the number of address generation.

6. The data processing circuit according to claim 3, wherein, The control unit is further configured to send the starting physical address to the subsystem when the register configuration information stored in each first command queue is in the second arrangement mode, and control the subsystem to generate the physical address corresponding to each first command queue based on the starting physical address and the target data bit width. Receive the physical address corresponding to each first command queue generated by the subsystem, and send a data read command to the physical address corresponding to each first command queue; The second arrangement mode is a repeat read arrangement mode, and the target data bit width is obtained by multiplying the preset data bit width and the number of address generation.

7. The data processing circuit according to claim 4, wherein, The control unit further includes: a control subunit and a read address generator connected in sequence; The control subunit is used to generate a first physical address based on the starting physical address and the target data bit width of the starting command queue, wherein the target data bit width is obtained by multiplying the preset data bit width by the number of address generation. The read address generator is used to generate a data read command corresponding to a first command queue based on the first physical address.

8. The data processing circuit according to claim 3, wherein, The caching module includes: a data caching unit and a data configuration unit connected in sequence; The data cache unit is connected to the memory; The data configuration unit is connected to the at least one register; The data caching unit is used to receive the register configuration information stored in each of the first command queues sent by the memory, and to cache the register configuration information stored in each of the first command queues; The data configuration unit is used to allocate the cached register configuration information of each first command queue to the corresponding register.

9. The data processing circuit according to claim 8, wherein, The data caching unit includes a pre-caching sub-unit and an N-way caching sub-unit connected in sequence; The pre-caching subunit is used to receive the register configuration information stored in each of the first command queues sent by the memory, and to cache the register configuration information stored in each of the first command queues. One of the cache subunits is used to store register configuration information stored in the first command queue.

10. The data processing circuit according to claim 8, wherein, The data caching unit also includes a bus clearing function; The clear bus is used to clear the register configuration information cached in the data cache unit after allocating the register configuration information of all the first command queues in the cache to the corresponding registers.

11. A register configuration apparatus, the register configuration apparatus comprising a data processing circuit according to any one of claims 1 to 10, a memory, and at least one register; in, The data processing circuit is connected to the memory and at least one register, respectively.

12. The apparatus according to claim 11, wherein, The memory is used to allocate a first entry and a second entry for the first storage space. The first entry stores the starting physical address of the first storage space, and the second entry stores the first register configuration information to generate a command queue in the first storage space. The data bit widths corresponding to the first entry and the second entry are both preset data bit widths.

13. The apparatus according to claim 12, wherein, The first register configuration information includes a register address and at least one register data; Specifically, the memory is used to store the register address and the at least one register data sequentially in the second entry according to a memory alignment strategy.

14. A register configuration method, the method comprising: Through the data processing circuit, based on the starting physical address of the starting command queue and the preset data bit width, the physical address corresponding to each first command queue in the first sub-command queue group in memory is determined, and based on the physical address corresponding to each first command queue, the register configuration information stored in each first command queue is cached. The starting command queue is one of the command queues in the first command queue group, and the first sub-command queue group includes the starting command queue and each command queue after the starting command queue. The first command queue group is stored in memory, and the storage space corresponding to each command queue in the first command queue group is the same size in the memory. The data processing circuit allocates the cached register configuration information of each first command queue to the corresponding register.

15. The method according to claim 14, wherein, The step of determining the physical address corresponding to each of the at least one first command queues in the memory based on the starting physical address of the starting command queue and the preset data bit width includes: When the register configuration information stored in each first command queue is in the third arrangement mode, the physical address corresponding to each first command queue is generated based on the target data bit width and the starting physical address; The target data bit width is obtained by multiplying the preset data bit width by the number of address generation, and the third arrangement mode is any one of incremental arrangement mode, singleton arrangement mode or repeated read arrangement mode.

16. The method of claim 14, wherein, The method further includes: The memory is used to allocate a first entry and a second entry to the first storage space. The first entry stores the starting physical address of the first storage space, and the second entry stores the configuration information of the first register, so as to generate a command queue in the first storage space.

17. The method according to claim 16, wherein, The first register configuration information includes a register address and at least one register data; The step of storing the first register configuration information in the second entry includes: The register address and at least one register data are stored sequentially in the second entry using the memory according to a memory alignment strategy.

18. An electronic device comprising a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the register configuration method as claimed in any one of claims 14 to 17.

19. A readable storage medium storing a program or instructions that, when executed by a processor, implement the steps of the register configuration method as described in any one of claims 14 to 17.

20. A computer program product stored in a storage medium, the program product being executed by at least one processor to implement the register configuration method as described in any one of claims 14 to 17.

21. A chip comprising a processor and a communication interface coupled to the processor, the processor being configured to run a program or instructions to implement the register configuration method as described in any one of claims 14 to 17.

Images