Micro light emitting element and manufacturing method therefor

Abstract

A micro light emitting element and a manufacturing method therefor. The micro light emitting element comprises: a driving substrate (101); a first bonding layer (102) arranged on the driving substrate (101), the first bonding layer (102) comprising patterned metal layers (1021) and insulating layers (1022) each arranged between two metal layers (1021); a plurality of LED units (120), each LED unit (120) comprising: a second bonding layer (103) arranged on the first bonding layer (102), the second bonding layers (103) between adjacent LED units (120) being disconnected; an epitaxial layer (104), the epitaxial layer (104) comprising: a second semiconductor layer (107) arranged on the second bonding layer (103); an active layer (106) arranged on the second semiconductor layer (107); a first semiconductor layer (105) arranged on the active layer (106); a passivation layer (108) arranged on the outer wall of the epitaxial layer (104) and provided with an opening on the top surface of the epitaxial layer (104); and an N electrode layer (109) deposited above the passivation layer (108). Thus, the proposed etching process for the micro light-emitting element reduces process complexity and effectively avoids the problems such as over-etching, incomplete etching, metal residue on sidewalls, thereby improving the product yield of micro light emitting elements.

Description

Micro light emitting element and preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor display, in particular to a micro light emitting element and a preparation method thereof. BACKGROUND

[0002] In recent years, light emitting diodes (LEDs) have been widely used in the field of lighting and other fields due to their unique advantages, and have replaced the original traditional lighting sources. With the development of the display industry, there is a higher demand for small-sized LEDs.

[0003] Micro LED (micro light emitting element) display technology refers to a display technology in which micron-sized LEDs that self-emit light are used as light emitting pixel units, and the LEDs are assembled on a CMOS driving panel to form a high-density LED array. Due to the small size, high integration and self-emission of Micro-LEDs, the Micro-LED display technology has great advantages in brightness, resolution, contrast, energy consumption, service life, response speed and thermal stability compared with LCD and OLED, and can be applied in the fields of AR / VR, wearable devices, automotive head-up HUD, micro projection, 3D printing and other display fields.

[0004] To realize display, a plurality of Micro LED chips and a driving substrate are assembled together. The wafer-to-wafer bonding method is widely used because it does not require alignment. The conventional method is to respectively plate metal on the driving substrate side and the Micro LED chip epitaxial side, then bond them together by using the thermal expansion characteristics of the metal, and then completely disconnect each LED unit from the epitaxial layer to the bonding layer by etching process to realize independent control of the Micro LED, as shown in FIG. 1. In this process, due to the extremely small size of the Micro LED and the small spacing between adjacent LED units 120, the etching difficulty is extremely high, the aspect ratio of the etching opening 150 is large, the process window is small, and problems such as over-etching, incomplete etching, and metal residue on the sidewall may occur, which affects the product yield of the Micro LED. SUMMARY

[0005] To solve the above problems, the present application provides a micro light emitting element, comprising:

[0006] a driving substrate;

[0007] A first bonding layer is arranged on the driving substrate, and the first bonding layer comprises a plurality of metal layers arranged at intervals and insulating layers arranged between the metal layers; a plurality of LED units are arranged on the first bonding layer at intervals, and each LED unit comprises: a second bonding layer arranged on the first bonding layer, and the second bonding layers between adjacent LED units are disconnected; an epitaxial layer comprising: a second semiconductor layer arranged on the second bonding layer; an active layer arranged on the second semiconductor layer; a first semiconductor layer arranged on the active layer; a passivation layer arranged on the outer wall of the LED unit and the surface of the first bonding layer, and having an opening on the top surface of the epitaxial layer; and an N electrode layer arranged on the passivation layer.

[0008] The application further provides a manufacturing method of the micro light emitting element.

[0009] S1, providing a driving substrate, depositing an insulating material on the driving substrate to form an insulating layer, and using a photolithography process to obtain a patterned insulating layer and expose the driving substrate;

[0010] S2, depositing a metal material on the driving substrate, and then removing the excess metal material on the surface of the insulating layer until the surface of the insulating layer is exposed, so that the metal material forms a metal layer, and the metal layer and the insulating layer form a first bonding layer;

[0011] S3, providing an LED substrate, growing an epitaxial layer on the LED substrate, and sequentially arranging a first semiconductor layer, an active layer and a second semiconductor layer; depositing a transparent conductive layer on the second semiconductor layer, and evaporating a second bonding layer on the surface of the transparent conductive layer;

[0012] S4, using a bonding process to bond the first bonding layer and the second bonding layer, and combining the LED wafer and the driving substrate;

[0013] S5, peeling off the LED substrate;

[0014] S6, etching the LED epitaxial layer until the transparent conductive layer is exposed, and obtaining a plurality of completely disconnected epitaxial layers;

[0015] S7, etching the transparent conductive layer and the second bonding layer until the first bonding layer is exposed;

[0016] S8, depositing an insulating material to form a passivation layer

[0017] S9, depositing a metal conductive material to form an N electrode layer, the N electrode layer is electrically connected to the first semiconductor layer of each LED unit, each adjacent LED unit is connected through the N electrode layer, and the N electrode layer surrounds the driving substrate.

[0018] The application has the following beneficial effects:

[0019] The micro light emitting element is provided with a first bonding layer on the driving substrate side, which is a patterned metal layer, and the metal layer is disconnected by an insulating layer, so that two adjacent LED units are electrically isolated. Therefore, compared with the prior art, the etching depth is only to the second bonding layer, so that the etching process difficulty is reduced, and problems such as over-etching, incomplete etching, and side wall metal residue are effectively avoided, and the product yield of the Micro LED is improved

[0020] The micro light emitting element is provided with a first bonding layer on the driving substrate side, which is a patterned metal layer, and the metal layer is disconnected by an insulating layer, so that two adjacent LED units are electrically isolated. Therefore, compared with the prior art, the etching depth is only to the second bonding layer, so that the etching process difficulty is reduced, and problems such as over-etching, incomplete etching, and side wall metal residue are effectively avoided, and the product yield of the Micro LED is improved BRIEF DESCRIPTION OF DRAWINGS

[0021] FIG. 1 is a cross-sectional view of a micro light emitting element in the prior art;

[0022] FIG. 2 is a cross-sectional view of a micro light emitting element according to an embodiment of the present application;

[0023] FIG. 3 is an enlarged view of a part of FIG. 2;

[0024] FIG. 4 is an enlarged view of a part of an LED unit of the micro light emitting element according to the embodiment of the present application;

[0025] FIG. 5 is a top view of the micro light emitting element according to the embodiment of the present application;

[0026] FIGS. 6 to 12 are a method of manufacturing a micro light emitting element according to another embodiment of the present application;

[0027] BRIEF DESCRIPTION OF DRAWINGS

[0028] 100: micro light emitting element 120: LED unit 101: driving substrate 102: first bonding layer 1021: metal layer 1022: insulating layer 103: second bonding layer 104: epitaxial layer 105: first semiconductor layer 106: active layer 107: second semiconductor layer 108: passivation layer 109: N electrode layer 110: transparent conductive layer 111: P-type electrical contact point 112: N-type electrical contact point 130: driving substrate periphery 140: epitaxial sidewall 150: etching opening 200: LED growth substrate DETAILED DESCRIPTION

[0029] The application will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the application.

[0030] In order for those skilled in the art to better understand the technical solutions of the application, the problems existing in the prior art are specifically described.

[0031] In the embodiment, the concept of "micro light emitting element" generally means that the structural size is within 100 μm. Embodiment 1

[0032] Fig. 2 is a schematic cross-sectional view of a micro light emitting element according to an embodiment of the application. For the convenience of understanding, Fig. 2 takes two LED units 120 as an example, and the actual number of LED units 120 can be adjusted according to requirements.

[0033] Referring to Fig. 2, in order to achieve at least one of the advantages of the application or other advantages, an embodiment of the application provides a micro light emitting element 100, which includes a driving substrate 101, a first bonding layer 102 disposed on the driving substrate 101, and a plurality of LED units 120.

[0034] In the application, the driving substrate 101 can be a CMOS substrate or a TFT glass substrate and other substrates with driving circuits to provide current to the LED units 120 to make them emit light. In the embodiment, CMOS is used as the driving substrate, and a plurality of P-type electrical contact points 111 and N-type electrical contact points 112 are disposed in the driving substrate 101 to serve as circuit connections.

[0035] In the application, the first bonding layer 102 is disposed on the driving substrate 101 and is composed of spaced metal layers 1021 and insulating layers 1022 between the metal layers 1021. The first bonding layer 102 is electrically isolated in sections, and the independent metal layers 1021 can conduct electricity, but the adjacent metal layers 1021 are insulated by the insulating layers 1022.

[0036] In some embodiments, the thickness of the metal layer 1021 in the first bonding layer 102 is 97% to 103% of the thickness of the insulating layer 1022, and the optimal value is that the thickness of the metal layer 1021 is equal to the thickness of the insulating layer 1022, that is, the first bonding layer 102 has a flat horizontal surface, but due to the process difficulty of micro-LED and the difficulty of measurement, there may be some errors, so the thickness of the metal layer 1021 is set to be 97% to 103% of the thickness of the insulating layer 1022, and in this embodiment, the thicknesses of the two are equal. In order to ensure smooth understanding, the thickness of the metal layer 1021 is defined as the thickness of the first bonding layer 102, and the two are the same concept.

[0037] In some embodiments, the thickness of the first bonding layer 102 is 0.3-3um, if it is lower than 0.3um, the first bonding layer 102 is too thin, and the bonding effect is weak, if it is higher than 3um, the first bonding layer 102 is too thick, which is not conducive to heat dissipation and controlling the size of the micro light emitting element 100, and the cost is too high. In this embodiment, the thickness of the first bonding layer 102 is 0.5um.

[0038] The material of the metal layer 1021 is a metal conductive material, and in some embodiments, the metal layer 1021 can be one or a combination of several of Cr, Al, Ti, Pt, Au, Sn, Cu, such as a single layer, a stack layer or a mixed layer with different contents. The material of the insulating layer 1022 is an insulating medium material, and in some embodiments, it can be one or a combination of several of SiO2, Si3N4, Al2O3, MgF2, SiF4. In this embodiment, the metal layer 1021 selects Cr, Pt and Au stack, and the insulating layer 1022 selects SiO2.

[0039] Referring to FIGS. 2-3, the first bonding layer 102 is provided with a plurality of LED units 120, and each LED unit 120 includes a second bonding layer 103, an epitaxial layer 104, a passivation layer 108, and an N electrode layer 109.

[0040] In the micro light emitting element 100, the second bonding layer 103 needs to be etched off in the process, and each LED unit 120 contains a partially disconnected second bonding layer 103, so as to realize the electrical isolation of each LED unit 120 and realize independent control by being electrically connected to the lower driving substrate 101 through the respective second bonding layer 103. In some embodiments, the material of the second bonding layer 103 is a metal conductive material, such as one or a combination of several of Cr, Al, Ti, Pt, Au, Sn, Cu, and gold-tin alloy, and in this embodiment, Cr, Pt, Au and Sn are used in a stack.

[0041] In some embodiments, the thickness of the second bonding layer 103 ranges from 0.3 to 3 um. If the thickness is less than 0.3 um, the second bonding layer 103 is too thin, and the bonding effect is weak. If the thickness is greater than 3 um, the second bonding layer 103 is too thick, which is not conducive to heat dissipation and controlling the size of the micro light emitting element 100, and the cost is too high. In the present embodiment, the thickness of the second bonding layer 103 ranges from 0.5 um.

[0042] In some embodiments, the orthographic projection of the metal layer 1021 in the first bonding layer 102 falls within the orthographic projection range of the second bonding layer 103. Referring to FIG. 4, the leftmost point of the metal layer 1021 is a, the rightmost point is b, the leftmost point of the second bonding layer 103 is c, and the rightmost point is d. Both endpoints a and b of the metal layer 1021 are between the two endpoints c and d of the second bonding layer. As shown in FIG. 5, the dashed line of the inner circle is the edge of the metal layer 1021, and the solid line of the outer circle is the edge of the second bonding layer 103. The orthographic projection of the metal layer 1021 falls completely within the second bonding layer 103. Such a design shrinks the metal layer 1021 within the projection of the LED unit 120, which is conducive to good insulation of the metal layer 1021 between the LED units 120.

[0043] Referring to FIG. 4, in some embodiments, the width L1 of the metal layer 1021 ranges from 0.5 to 50 um, and the width L2 of the insulating layer 1022 ranges from 0.5 to 50 um, which can further optimize the electrical isolation between the LED units 120. In the present embodiment, L1 is 2.0 um, and L2 is 4.0 um.

[0044] In some embodiments, the maximum width L3 of the second bonding layer 103 ranges from 1.0 to 60 um, which can further achieve the electrical isolation of the LED units 120 and ensure good bonding contact. In the present embodiment, L3 is 3 um.

[0045] There is a spacing D1 between the second bonding layers 103 in adjacent LED units 120. The spacing D1 is the shortest distance between adjacent second bonding layers 103, such as the distance between the rightmost point d of one second bonding layer and the leftmost point c' of the adjacent second bonding layer. In some embodiments, D1 ranges from 0.5 to 20 um, and in the present embodiment, D1 is 2 um. This range is conducive to the development of the preparation process and is also conducive to arranging a sufficient number of LED units 120 to meet the needs of the micro light emitting element.

[0046] In some embodiments, the distance between the endpoints a, b, c, and d is further limited, and the shortest distance between the leftmost endpoint a of the metal layer 1021 and the leftmost endpoint c of the second bonding layer 103 is in the range of 0.2-10 um, and the shortest distance between the rightmost endpoint b of the metal layer 1021 and the rightmost endpoint d of the second bonding layer 103 is in the range of 0.2-10 um. Further, the electrical isolation of the LED unit 120 is achieved. In this embodiment, the shortest distance between ac is 0.5 um, and the shortest distance between bd is 0.5 um.

[0047] The epitaxial layer 104 includes a first semiconductor layer 105, an active layer 106, and a second semiconductor layer 107.

[0048] The second semiconductor layer 107 is disposed above the second bonding layer 103, which can be a P-type semiconductor layer, such as the P-type GaN used in this embodiment, and can also be AlGaN, InGaN, GaAs, AlGaAS, AlGaInP, InGaAs, etc. according to different requirements.

[0049] The active layer 106 is disposed above the second semiconductor layer 107, which can be a multi-quantum well (MQW) structure.

[0050] The first semiconductor layer 105 is disposed above the active layer 106, which can be an N-type semiconductor layer, such as the N-type GaN used in this embodiment, and can also be AlGaN, InGaN, GaAs, AlGaAS, AlGaInP, InGaAs, etc. according to different requirements.

[0051] As shown in FIG. 3, in some embodiments, the epitaxial side wall 140 has a horizontal angle a with the driving substrate 101, and the angle a is in the range of 45°-85°, which is suitable for LED light emission and subsequent passivation layer 108 and N electrode layer 109 coverage, reducing the risk of fault. It should be noted here that the definition of the epitaxial side wall 140 is any side wall of the first semiconductor layer 105, the active layer 106, and the second semiconductor layer 107.

[0052] In some embodiments, the width of the LED unit 120 gradually increases from top to bottom, with the smallest width on the upper surface of the first semiconductor layer 105 and the largest width on the lower surface of the second bonding layer 103.

[0053] In some embodiments, a transparent conductive layer 110 is further disposed between the second semiconductor layer 107 and the second bonding layer 103, which can be ITO, TCO, IZO, etc. In this embodiment, ITO is used as the transparent conductive layer 110 to optimize the conductive condition of the epitaxial layer 104 and the second bonding layer 103.

[0054] A passivation layer 108 is disposed outside the LED unit 120, which is made of insulating material, such as SiO2, Si3N4, Al2O3, MgF2, SiF4, or a combination of one or more of them. In this embodiment, the material of the passivation layer 108 is Al2O3 and SiO2. The passivation layer 108 is partially opened on the surface of the epitaxial layer 104 and the second bonding layer 103 around the driving substrate 101. The size of the opening is adjusted according to the subsequent electrode, which is not limited here.

[0055] The passivation layer 108 is also disposed on the surface of the first bonding layer 102, further isolating the several LED units 120 and protecting the epitaxial layer 104.

[0056] The LED unit 120 further includes an N electrode layer 109, which is made of metal conductive material, such as Cr, Al, Ti, Pt, Au, or Sn, or a combination of one or more of them.

[0057] Referring to FIG. 2 and FIG. 5, the N electrode layer 109 is disposed on the passivation layer 108 and surrounds the outside of the driving substrate 101, connecting the several LED units 120 as their common N electrode. The connection principle is that the N-type electrical contact point 112 is disposed around the driving substrate 101, and the N electrode layer 109 is electrically connected to the second bonding layer 103 and the metal layer 1021 of the first bonding layer 102 through the partial opening of the passivation layer 108, and then ohmically contacts the N-type electrical contact point 112 of the driving substrate 101, realizing the common N-pole conduction. On the other hand, the second semiconductor layers 107 of the several LED units 120 are disconnected, and the second bonding layer 103 is disconnected, and the first bonding layer 102 is electrically isolated by the insulating layer 1021, and the second semiconductor layers 107 of each LED unit 120 are connected to the P-type electrical contact point 111 on the driving substrate 101, completing the P-pole conduction of each LED unit 120, and realizing the independent control of light emission. The P-type electrical contact point 111 is located below the several LED units, and the N-type electrical contact point 112 surrounds the outside of the driving substrate.

[0058] FIG. 5 is a top view of embodiment 1, which is illustrated by taking four LED units 120 as an example for clarity, and the number of LED units can be changed according to requirements in actual situations.

[0059] In FIG. 5, the circular solid line is the edge of the second bonding layer 103, and the dashed line is the edge of the metal layer 1021. As mentioned before, the metal layer 1021 is projected inside the second bonding layer. FIG. 5 contains two squares, and the inner square is the insulating layer 1022 except for the four LED units. The part between the inner square and the outer square is the N electrode layer 109, which surrounds the outside of the driving substrate 101 as the common N electrode of the four LED units 120.

[0060] In some embodiments, a step is arranged on the surface of the first semiconductor layer 105, which is slightly lower than the plane of the first semiconductor layer 105 without the step, and the partial N electrode layer 109 is arranged on the step. This design is adopted in the present embodiment to make the N electrode layer more easily adhere to the first semiconductor layer 105.

[0061] In some embodiments, an exposed mesa is arranged between the second semiconductor layer 107 and the second bonding layer 103, which is covered by the passivation layer 108. This design is adopted in the present embodiment to make the N electrode layer 109 more easily adhere to the epitaxial layer sidewall 150.

[0062] Beneficial effects: The present application provides a micro light emitting element 100, in which the first bonding layer 102 is arranged as a patterned metal layer 1021, and an insulating layer 1022 is arranged between the metal layers 1021, and the metal layers 1021 between the plurality of LED units 120 are electrically isolated. Therefore, one step of etching the first bonding layer 102 can be reduced during subsequent etching. Referring to FIG. 1 and FIG. 2, FIG. 1 is a prior art, in which the etching opening 105 has a large depth, and the etching process is very difficult. FIG. 2 is an embodiment adopting the present application, and it can be clearly seen that, since the first bonding layer 102 does not need to be etched, the depth of the etching opening is reduced, specifically, the thickness of the first bonding layer 102 is reduced, which greatly improves the process window, reduces the problems that may be caused by the difficulty of etching, such as over-etching, incomplete etching, sidewall metal residue, etc., and greatly improves the yield of the micro light emitting element. Embodiment 2

[0063] In order to prepare the micro light emitting element of the above-mentioned embodiment 1, the present application further proposes an embodiment of a preparation method of a micro light emitting element, which is specifically described with reference to FIG. 6 to FIG. 12.

[0064] Referring to FIG. 6, a driving substrate 101 is provided, which is a CMOS substrate in the present embodiment, and TFT glass substrate and other substrates with driving circuit can be selected according to requirements. The CMOS substrate 101 has a plurality of electrical contact points, including a plurality of P-type electrical contact points 111 and a plurality of N-type electrical contact points 112. An insulating material, which is SiO2 in the present embodiment, is deposited on the CMOS substrate 101 to form an insulating layer 1022. A photolithography process is used to obtain a patterned insulating layer, which exposes the driving substrate 101, as shown in FIG. 6.

[0065] The thickness of the deposited insulating material is preferably 0.3-3 um, and is 0.5 um in the present embodiment.

[0066] Referring to FIG. 7, a metal layer 1021 is deposited on the CMOS substrate 101 obtained in the above steps, and the metal material can be Cr, Al, Ti, Pt, Au, Sn, or a gold-tin alloy. In this embodiment, a Cr / Pt / Au metal stack is used, and the excess metal material on the surface is removed until the insulating layer 1022 is exposed. The insulating layer 1022 is almost level with the surface of the metal layer 1021, and the difference is controlled to be within ±3%. In this embodiment, the two are level.

[0067] Referring to FIG. 8, an LED growth substrate 200 is provided, which can be a sapphire, silicon, gallium nitride, silicon carbide, aluminum nitride, or the like. In this embodiment, a sapphire substrate is used. A first semiconductor layer 105, an active layer 106, and a second semiconductor layer 107 are grown on the growth substrate 200. A transparent conductive layer 110 is then deposited, and ITO is used in this embodiment. A metal layer is then deposited on the transparent conductive layer 110 as a second bonding layer 103. The metal material can be Cr, Al, Ti, Pt, Au, Sn, or a gold-tin alloy. In this embodiment, a Cr / Pt / Au / Sn metal stack is used.

[0068] Referring to FIG. 9, the first bonding layer 102 and the second bonding layer 103 are bonded by a wafer bonding process such as hot pressing, and the LED growth substrate 200 is peeled off. The peeling method can be laser peeling, chemical peeling, or mechanical grinding.

[0069] Referring to FIG. 10, the epitaxial layer 104 of the LED unit 120 is etched until the transparent conductive layer 110 is exposed, and a plurality of completely disconnected epitaxial layers 104 are obtained. The etching method can be dry etching, ion beam etching, or plasma etching. In this embodiment, ion beam etching is used.

[0070] In some embodiments, a step is etched on the surface of the first semiconductor layer 105 after the above steps, and the height of the step is lower than the height of the unetched surface of the first semiconductor layer 105.

[0071] In some embodiments, the etching rate and angle are controlled when etching the LED epitaxial layer 104, and the horizontal angle between the sidewall of the epitaxial layer 104 and the transparent conductive layer 110 is in the range of 45°-85° after etching.

[0072] Referring to FIG. 11, the transparent conductive layer 110 and the second bonding layer 103 are etched downward until the first bonding layer 102 is exposed. In some embodiments, a portion of the second semiconductor layer 107 and the second transparent conductive layer 110 is reserved when etching the transparent conductive layer 110 and the second bonding layer 103 to form a mesa.

[0073] In some embodiments, the etching rate and angle are controlled when etching the transparent conductive layer 110 and the second bonding layer 103, and the horizontal angle between the sidewall of the second bonding layer 103 and the driving substrate ranges from 45° to 85° after etching.

[0074] In some embodiments, the amount of etching medium is controlled when etching the epitaxial layer of the LED unit 120 and etching the transparent conductive layer 110 and the second bonding layer 103, and the etched part becomes less and less from the upper surface of the first semiconductor layer 105 to the lower surface of the second bonding layer 103, and the remaining part becomes more and more.

[0075] Referring to FIG. 12, on the basis of the structure of FIG. 11, an insulating material is deposited to form a passivation layer 108, which can be SiO2, Si3N4, Al2O3, and in this embodiment, SiO2 and Al2O3 are used. Finally, a conductive metal material, such as Cr, Al, Ti, Pt, Au, or Sn, is deposited to form an N electrode layer 109, and in this embodiment, the metal material is a Cr, Pt, and Au metal stack. The N electrode layer is electrically connected to the first semiconductor layer 105 of each LED unit 120, and each adjacent LED unit 120 is connected through the N electrode layer 109, and the N electrode layer 109 surrounds the driving substrate 101.

[0076] Beneficial effects: Before wafer bonding, the first bonding layer 102 on the driving substrate 101 is patterned, and the metal layer 1021 is blocked by the insulating material, which reduces the subsequent step of etching a metal layer for isolating the LED unit 120, expands the process window, and reduces the damage to the micro light emitting element during etching.

[0077] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for part or all of the technical features; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

[0078] Enter sequence listing free form content description paragraph here.

Claims

1. A micro-light-emitting element, characterized in that, include: Drive substrate; A first bonding layer is disposed on a driving substrate. The first bonding layer includes a plurality of metal layers arranged at intervals and an insulating layer disposed between the metal layers. A plurality of LED units are disposed at certain intervals on the first bonding layer. Each LED unit includes: a second bonding layer disposed on the first bonding layer, wherein the second bonding layers between adjacent LED units are disconnected; an epitaxial layer comprising: a second semiconductor layer disposed on the second bonding layer; an active layer disposed on the second semiconductor layer; and a first semiconductor layer disposed on the active layer. A passivation layer is disposed on the outer wall of the LED unit and the surface of the first bonding layer, and an opening is provided on the top surface of the epitaxial layer; An N-electrode layer is disposed on the passivation layer.

2. A micro-light-emitting element according to claim 1, characterized in that, The orthographic projection of the endpoint of the metal layer falls within the orthographic projection range of the endpoint of the second bonding layer.

3. A micro-light-emitting element according to claim 1, characterized in that, The width of the metal layer ranges from 0.5 to 50 μm, and the width of the insulating layer ranges from 0.5 to 50 μm.

4. A micro-light-emitting element according to claim 1, characterized in that, The width of the second bonding layer ranges from 1 to 60 μm.

5. A micro-light-emitting element according to claim 1, characterized in that, The spacing between adjacent second bonding layers of adjacent LED units is 0.5-20 μm.

6. A micro-light-emitting element according to claim 1, characterized in that, The thickness of the first bonding layer ranges from 0.3 to 3 μm.

7. A micro-light-emitting element according to claim 1, characterized in that, The thickness of the second bonding layer ranges from 0.3 to 3 μm.

8. A micro-light-emitting element according to claim 1, characterized in that, The epitaxial sidewall has an inclination angle of 45°-85° relative to the horizontal surface of the driving substrate.

9. A micro-light-emitting element according to claim 1, characterized in that, The width of the LED unit gradually increases from the first semiconductor layer to the second bonding layer, with the width being smallest on the upper surface of the first semiconductor layer and largest on the lower surface of the second bonding layer.

10. A micro-light-emitting element according to claim 1, characterized in that, The metal layer in the first bonding layer is made of one or more of Cr, Al, Ti, Pt, Au, Sn, and Cu, and the insulating layer is made of one or more of SiO2, Si3N4, Al2O3, MgF2, and SiF4.

11. A micro-light-emitting element according to claim 1, characterized in that, The material of the second bonding layer is one or a combination of several of Cr, Al, Ti, Pt, Au, Sn, and Cu.

12. A micro-light-emitting element according to claim 1, characterized in that, It includes a transparent conductive layer disposed between the second semiconductor layer and the second bonding layer.

13. A micro-light-emitting element according to claim 1, characterized in that, The N-electrode layer surrounds the entire periphery of the LED driving substrate, enclosing the plurality of LED units on the driving substrate, forming a common N-electrode for the plurality of LED units.

14. A method for fabricating a micro-light-emitting element, characterized in that, include: S1 provides a driving substrate, on which an insulating material is deposited to form an insulating layer. A patterned insulating layer is obtained using a photolithography process, exposing the driving substrate. S2 deposits metal material on the driving substrate, and then removes excess metal material from the surface of the insulating layer until the surface of the insulating layer is exposed. The metal material forms a metal layer, and the metal layer and the insulating layer constitute the first bonding layer. S3 provides an LED substrate, on which an epitaxial layer is grown, consisting of a first semiconductor layer, an active layer, and a second semiconductor layer in sequence; a transparent conductive layer is deposited on the second semiconductor layer, and a second bonding layer is evaporated on the surface of the transparent conductive layer; S4 uses a bonding process to bond the first bonding layer and the second bonding layer together, thus completing the bonding of the LED wafer and the driver substrate; S5 Removes the LED substrate; S6 Etches the LED epitaxial layer until the transparent conductive layer is exposed, resulting in several completely disconnected epitaxial layers; S7 Etch the transparent conductive layer and the second bonding layer until the first bonding layer is exposed; S8 deposits insulating material to form a passivation layer. S9 deposits a conductive metal material to form an N-electrode layer. The N-electrode layer is electrically connected to the first semiconductor layer of each LED unit, and each adjacent LED unit is connected through the N-electrode layer. The N-electrode layer surrounds the driving substrate.

15. The method for fabricating a micro-light-emitting element according to claim 14, characterized in that, In S1, the thickness of the deposited insulating material is 0.3-3 μm.

16. The method for fabricating a micro-light-emitting element according to claim 14, characterized in that, In S6, the etching rate and angle are controlled when etching the LED epitaxial layer. After etching, the sidewall of the epitaxial layer and the horizontal angle between the transparent conductive layer are 45°-85°.

17. The method for fabricating a micro-light-emitting element according to claim 14, characterized in that, In S6-S7, the amount of etching medium is controlled so that the etched portion decreases from the upper surface of the first semiconductor layer to the lower surface of the second bonding layer.

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