Clamping systems and methods for semiconductor processing

Abstract

A new clamping system is described. The system comprises an electrode configured to generate an electric field to provide a clamping force, and a capping layer coupled to the electrode. The capping layer is configured to reduce a local maximum in the electric field strength, located at or near the edge of the electrode. The capping layer causes a redistribution of electric field lines around the edge of the electrode, as material of the capping layer is configured to store more electric energy, which locally reduces the electric field strength. This local reduction in electric field strength reduces or prevents "hot spots" in a clamp, which facilitates increased clamping pressure, reduces the risk of clamp failure, reduces or prevents residual clamp holding forces, and has other advantages.

Description

CLAMPING SYSTEMS AND METHODS FOR SEMICONDUCTOR PROCESSINGCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of US application 63 / 665,137 which was filed on 27 June 2024, and which is incorporated herein in its entirety by reference.TECHNICAL FIELD

[0002] This description generally relates to clamping systems and methods for semiconductor processing.BACKGROUND

[0003] A lithography (e.g., projection) apparatus can be used, for example, in the manufacture of integrated circuits (ICs). A patterning device (e.g., a reticle or mask) may contain or provide a pattern corresponding to an individual layer of the IC (“design layout”), and this pattern can be transferred onto a target portion (e.g. comprising one or more dies) on a substrate (e.g., silicon wafer) that has been coated with a layer of radiation-sensitive material (“resist”), by methods such as irradiating the target portion through the pattern on the patterning device. In general, a single substrate contains a plurality of adjacent target portions to which the pattern is transferred successively by the lithographic projection apparatus, one target portion at a time. In one type of lithographic projection apparatus, the pattern on the entire patterning device is transferred onto one target portion in one operation. Such an apparatus is commonly referred to as a stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, a projection beam scans over the patterning device in a given reference direction (the “scanning” direction) while synchronously moving the substrate parallel or anti-parallel to this reference direction. Different portions of the pattern on the patterning device are transferred to one target portion progressively. During pattern transfer, a reticle or a wafer may be clamped.SUMMARY

[0004] New clamping systems and methods are described. In these systems and methods, an electrode is configured to generate an electric field to provide a clamping force. A capping layer is coupled to the electrode. The capping layer is configured to reduce a local maximum in the electric field strength, located at or near the edge of the electrode. The capping layer causes a redistribution of electric field lines around the edge of the electrode, as material of the capping layer is configured to store more electric energy, which locally reduces the electric field strength. This local reduction in electric field strength reduces or prevents “hot spots” (local electric field strength concentrations), which facilitates increased clamping pressure, reduces the risk of clamp failure, reduces or prevents residual clamp holding forces, and / or has other advantages.

[0005] According to an embodiment, a clamping system is provided. The system includes a baseconfigured to removably hold an object (e.g., a reticle, a wafer, etc.), a dielectric coupled to the base, an electrode coupled to the dielectric, a capping layer coupled to the electrode, and / or other components. The electrode is configured to generate an electric field to provide a clamping force to hold the object against the base. The dielectric has a first permittivity. The capping layer has a second permittivity higher than the first permittivity, such that the capping layer is configured to locally reduce the strength of the electric field.

[0006] In some embodiments, the base comprises a burl configured to removably contact the object. The dielectric may comprise a channel configured to receive the burl such that the burl protrudes through the dielectric, with the channel comprising an interior electrical ground surface. The dielectric may comprise an insulator positioned between the electrode and the interior electrical ground surface. The channel may be oriented generally perpendicular to the first dielectric layer and the second dielectric layer. The electrode, the capping layer, and the insulator may be oriented generally parallel to the first dielectric layer and the second dielectric layer, with the insulator between the electrode and the capping layer on one side, and the channel on an opposite side.

[0007] In some embodiments, the dielectric comprises a first dielectric layer and a second dielectric layer. The electrode and capping layer and / or the insulator are coupled to the dielectric between the first dielectric layer and the second dielectric layer. For example, the electrode, the capping layer, and the insulator may be sandwiched between the first dielectric layer and the second dielectric layer.

[0008] The insulator has a third permittivity. The second permittivity (of the capping layer) is higher than (e.g., at least two, three, four, or five times higher than) the first permittivity (of the dielectric) and the third permittivity (of the insulator). For example, in some embodiments, the capping layer comprises a relatively high dielectric constant (k) material, having a dielectric constant greater than that of a first and / or second dielectric layer and the insulator. In some embodiments, the capping layer has a dielectric constant greater than about 5.75.

[0009] In some embodiments, the first dielectric layer comprises a first glass layer; and the second dielectric layer comprises a second glass layer. The electrode may be coupled to the first glass layer. The capping layer may comprise a dielectric coating disposed on the electrode between the electrode and the second glass layer. For example, the capping layer may comprise titanium oxide, barium titanium oxide, aluminum oxide, lanthanum oxide, zirconium oxide, hafnium oxide, strontium titanium oxide, and / or other materials. The capping layer may be coupled to the dielectric using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other processes.

[0010] In some embodiments, the insulator comprises an adhesive layer disposed between (1) the first glass layer and the second glass layer, and (2) between the electrode and the capping layer and the electrical ground surface.

[0011] In some embodiments, the capping layer covers at least an edge of the electrode, proximateto the insulator and / or the interior electrical ground surface of the channel. As described above, the capping layer is configured to reduce a local maximum in the electric field strength, located at or near the edge of the electrode. The capping layer causes a redistribution of electric field lines around the edge of the electrode, as material of the capping layer is configured to store more electric energy, which locally reduces the electric field strength.

[0012] In some embodiments, there may be a plurality of burls, and a plurality of corresponding channels, with each burl and corresponding channel combination comprising corresponding electrodes, capping layers, and insulators.

[0013] In some embodiments, the clamping force comprises a clamping pressure, and reducing the local maximum electric field strength facilitates enhanced overall clamping pressure. The clamping force may be an electrostatic force that creates electrostatic pressure on the object, for example.

[0014] In some embodiments, the base, the dielectric, the electrode, and the capping layer form a portion of an electrostatic clamp, and the electrostatic clamp is configured to releasably clamp the object for a semiconductor processing operation.

[0015] In some embodiments, the system comprises a second dielectric and a chuck, with the second dielectric comprising a second electrode, optionally with a second capping layer, configured to couple the base to the chuck. The chuck is configured to hold the clamp, and the object, and facilitate movement of the clamp, and the object.

[0016] In some embodiments, the object comprises a wafer, and the clamping system is part of a lithography apparatus used in semiconductor manufacturing. In some embodiments, the object comprises a reticle, and the clamping system is part of a lithography apparatus used in semiconductor manufacturing.

[0017] According to another embodiment, there is provided a clamping method. The method comprises one or more operations performed by the clamping system described above.BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate one or more embodiments and, together with the description, explain these embodiments. Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts.

[0019] Fig. 1 schematically depicts a lithography apparatus, according to an embodiment.

[0020] Fig. 2 schematically depicts an embodiment of a lithographic cell or cluster, according to an embodiment.

[0021] Fig. 3 illustrates example portions of a clamping system, according to an embodiment.

[0022] Fig. 4 illustrates an enlarged portion of the clamping system in Fig. 3, showing a dielectric comprising a first dielectric layer and a second dielectric layer, with an electrode and an insulatorcoupled to the dielectric between the first dielectric layer and the second dielectric layer, according to an embodiment.

[0023] Fig. 5 illustrates a simulation of a local increase in electric field strength at or near the edge of the electrode shown in Fig. 4, according to an embodiment.

[0024] Fig. 6 illustrates another embodiment of the clamping system, with a capping layer coupled to the electrode, according to an embodiment.

[0025] Fig. 7 illustrates a graph of electric field strength verses location relative to the edge of the electrode, with and without a capping layer, according to an embodiment.

[0026] Fig. 8 illustrates a clamping method, according to an embodiment.

[0027] Fig. 9 is a block diagram of an example computer system, according to an embodiment.DETAILED DESCRIPTION

[0028] A clamp (e.g., an electrostatic clamp) is used in a lithographic apparatus to secure an object such as a wafer or a reticle (e.g., a mask, or more generally a patterning device) during processing. Similar clamps may be used to clamp other objects. Typical clamps include an electrode configured to generate an electric field to provide a clamping force to hold the object. Dielectric layers surround the electrode, with insulators positioned between the electrode and channels or holes in the dielectric layers. The channels or holes are configured to accommodate burls which contact the object. There may be tens of thousands of these channels or holes in the clamp. Because of this arrangement, local increases in electric field strength at electrode edges (near the channels or holes) are generated, and charge may build up in the insulators or the dielectric layers or along the interface between them, charge may unexpectedly dissipate, the insulator and / or other components of the clamp may break down, and / or the local increases in electric field strength can have other undesired effects. These undesired effects cause an object to stick or slip unexpectedly during processing, introduce particles into the lithographic apparatus (e.g., after breakdown of the insulator, which is most likely to occur at or near the electrode edge), prevent use of an otherwise higher clamping force, and / or have other disadvantages.

[0029] New clamping systems and methods are described herein. As described above, in these new systems and methods, a capping layer is coupled to the electrode. The capping layer is configured to reduce a local maximum in the electric field strength, located at or near the edge of the electrode. The capping layer causes a redistribution of electric field lines around the edge(s) of the electrode, as material of the capping layer is configured to store more electric energy, which locally reduces the electric field strength. This local reduction in electric field strength reduces or prevents “hot spots” (local electric field strength concentrations), which facilitates increased clamping pressure, reduces the risk of clamp failure because of particle generation (e.g., at full breakdown), reduces or prevents undesired residual clamp holding forces and / or unexpected loss of clamp holding forces, and / or has other advantages. For example, a local electric field strength may be so high thatcharge may be injected from the electrode edge into interfacial layers. Another effect may be that a discharge occurs in a void, damaging clamp material, reducing the insulating properties, from which a new discharge event may happen in the neighboring void, forming a chain. This is known as treeing. A full breakdown (e.g., of the insulator) can occur as a result of treeing. At positive voltages, electrons can be extracted from the dielectric or interfacial layers, leaving holes behind. The capping layer described herein reduces and / or prevents these and other potential issues in an electrostatic clamp.

[0030] Although specific reference may be made in this text to the manufacture of integrated circuits, it should be understood that the description herein has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms “reticle”, “wafer” or “die” in this text should be considered as interchangeable with the more general terms “mask”, “substrate” and “target portion”, respectively. In addition, any use of the terms “reticle” or “mask” herein may be considered synonymous with the more general term “patterning device.”

[0031] As an introduction, prior to transferring a pattern from a patterning device such as a mask to a substrate, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures (“post-exposure procedures”), such as a post-exposure bake (PEB), development, a hard bake and measurement and / or other inspection of the transferred pattern. This array of procedures is used as a basis to make an individual layer of a device, e.g., an IC. The substrate may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemical mechanical polishing, etc., all intended to finish an individual layer of the device. If several layers are required in the device, then the whole procedure, or a variant thereof, is repeated for each layer. Eventually, a device will be present in each target portion on the substrate. These devices are then separated from one another by a technique such as dicing or sawing, after which the individual devices can be mounted on a carrier, connected to pins, etc.

[0032] Manufacturing devices, such as semiconductor devices, typically involves processing a substrate (e.g., a semiconductor wafer) using a number of fabrication processes to form various features and multiple layers of the devices. Such layers and features are typically manufactured and processed using, e.g., deposition, lithography, etch, chemical mechanical polishing, ion implantation, and / or other processes. Multiple devices may be fabricated on a plurality of dies on a substrate and then separated into individual devices. This device manufacturing process may be considered a patterning process. A patterning process involves a patterning step, such as optical and / or nanoimprint lithography using a patterning device in a lithographic apparatus, to transfer a pattern on the patterning device to a substrate and typically, but optionally, involves one or more related patternprocessing steps, such as resist development by a development apparatus, baking of the substrate using a bake tool, etching using the pattern using an etch apparatus, etc. One or more metrology processes are typically involved in the patterning process.

[0033] Lithography is a step in the manufacturing of devices such as ICs, where patterns formed on substrates define functional elements of the devices, such as microprocessors, memory chips, etc. Similar lithographic techniques are also used in the formation of flat panel displays, micro-electro mechanical systems (MEMS) and other devices.

[0034] Fig. 1 schematically depicts an embodiment of a lithographic apparatus LA that may include and / or associated with the present systems and / or methods. The apparatus comprises: an illumination system (illuminator) IL configured to condition a radiation beam B (e.g. UV radiation, DUV radiation, or EUV radiation); a support structure (e.g. a mask table) MT constructed to support a patterning device (e.g. a mask) MA and connected to a first positioner PM configured to accurately position the patterning device in accordance with certain parameters; a substrate table (e.g. a wafer table) WT (e.g., WTa, WTb or both) configured to hold a substrate (e.g. a resist-coated wafer) W and coupled to a second positioner PW configured to accurately position the substrate in accordance with certain parameters; and a projection system (e.g. a refractive projection lens system) PS configured to project a pattern imparted to the radiation beam B by patterning device MA onto a target portion C (e.g. comprising one or more dies and often referred to as fields) of the substrate W. The projection system is supported on a reference frame (RF). As depicted, the apparatus is of a transmissive type (e.g. employing a transmissive mask). Alternatively, the apparatus may be of a reflective type (e.g. employing a programmable mirror array of a type as referred to above, or employing a reflective mask).

[0035] The illuminator IL receives a beam of radiation from a radiation source SO. The source and the lithographic apparatus may be separate entities, for example when the source is an excimer laser. In such cases, the source is not considered to form part of the lithographic apparatus and the radiation beam is passed from the source SO to the illuminator IL with the aid of a beam delivery system BD comprising for example suitable directing mirrors and / or a beam expander. In other cases, the source may be an integral part of the apparatus, for example when the source is a mercury lamp. The source SO and the illuminator IL, together with the beam delivery system BD if required, may be referred to as a radiation system.

[0036] The illuminator IL may alter the intensity distribution of the beam. The illuminator may be arranged to limit the radial extent of the radiation beam such that the intensity distribution is non-zero within an annular region in a pupil plane of the illuminator IL. Additionally or alternatively, the illuminator IL may be operable to limit the distribution of the beam in the pupil plane such that the intensity distribution is non-zero in a plurality of equally spaced sectors in the pupil plane. The intensity distribution of the radiation beam in a pupil plane of the illuminator IL may be referred to as an illumination mode.

[0037] The illuminator IL may comprise adjuster AD configured to adjust the (angular / spatial) intensity distribution of the beam. Generally, at least the outer and / or inner radial extent (commonly referred to as o-outer and o-inner, respectively) of the intensity distribution in a pupil plane of the illuminator can be adjusted. The illuminator IL may be operable to vary the angular distribution of the beam. For example, the illuminator may be operable to alter the number, and angular extent, of sectors in the pupil plane wherein the intensity distribution is non-zero. By adjusting the intensity distribution of the beam in the pupil plane of the illuminator, different illumination modes may be achieved. For example, by limiting the radial and angular extent of the intensity distribution in the pupil plane of the illuminator IL, the intensity distribution may have a multi-pole distribution such as, for example, a dipole, quadrupole or hexapole distribution. A desired illumination mode may be obtained, e.g., by inserting an optic which provides that illumination mode into the illuminator IL or using a spatial light modulator.

[0038] The illuminator IL may be operable to alter the polarization of the beam and may be operable to adjust the polarization using adjuster AD. In addition, the illuminator IL generally comprises various other components, such as an integrator IN and a condenser CO. The illumination system may include various types of optical components, such as refractive, reflective, magnetic, electromagnetic, electrostatic, or other types of optical components, or any combination thereof, for directing, shaping, or controlling radiation. Thus, the illuminator provides a conditioned beam of radiation B, having a desired uniformity and intensity distribution in its cross section.

[0039] The support structure MT supports the patterning device in a manner that depends on the orientation of the patterning device, the design of the lithographic apparatus, and other conditions, such as for example whether or not the patterning device is held in a vacuum environment. The support structure may use mechanical, vacuum, electrostatic or other clamping techniques to hold the patterning device. The support structure may be a frame or a table, for example, which may be fixed or movable as required. The support structure may ensure that the patterning device is at a desired position, for example with respect to the projection system.

[0040] The term “patterning device” used herein should be broadly interpreted as referring to any device that can be used to impart a pattern in a target portion of the substrate. In an embodiment, a patterning device is any device that can be used to impart a radiation beam with a pattern in its crosssection to create a pattern in a target portion of the substrate. It should be noted that the pattern imparted to the radiation beam may not exactly correspond to the desired pattern in the target portion of the substrate, for example if the pattern includes phase-shifting features or so called assist features. Generally, the pattern imparted to the radiation beam will correspond to a particular functional layer in a device being created in a target portion of the device, such as an integrated circuit.

[0041] A patterning device may be transmissive or reflective. Examples of patterning devices include reticles or masks, programmable mirror arrays, and programmable LCD panels. Reticles or masks are well known in lithography, and include mask types such as binary, alternating phase-shift,and attenuated phase-shift, as well as various hybrid mask types. An example of a programmable mirror array employs a matrix arrangement of small mirrors, each of which can be individually tilted to reflect an incoming radiation beam in different directions. The tilted mirrors impart a pattern in a radiation beam, which is reflected by the mirror matrix.

[0042] The projection system PS may comprise a plurality of optical (e.g., lens) elements and may further comprise an adjustment mechanism configured to adjust one or more of the optical elements to correct for aberrations (phase variations across the pupil plane throughout the field). To achieve this, the adjustment mechanism may be operable to manipulate one or more optical (e.g., lens) elements within the projection system PS in one or more different ways. The projection system may have a coordinate system wherein its optical axis extends in the z direction. The adjustment mechanism may be operable to do any combination of the following: displace one or more optical elements; tilt one or more optical elements; and / or deform one or more optical elements. Displacement of an optical element may be in any direction (x, y, z, or a combination thereof). Tilting of an optical element is typically out of a plane perpendicular to the optical axis, by rotating about an axis in the x and / or y directions although a rotation about the z axis may be used for a non-rotationally symmetric aspherical optical element. Deformation of an optical element may include a low frequency shape (e.g. astigmatic) and / or a high frequency shape (e.g. free form aspheres). Deformation of an optical element may be performed for example by using one or more actuators to exert force on one or more sides of the optical element and / or by using one or more heating elements to heat one or more selected regions of the optical element. In general, it may not be possible to adjust the projection system PS to correct for apodization (transmission variation across the pupil plane). The transmission map of a projection system PS may be used when designing a patterning device (e.g., mask) MA for the lithography apparatus LA. Using a computational lithography technique, the patterning device MA may be designed to at least partially correct for apodization.

[0043] The lithographic apparatus may be of a type having two (dual stage) or more tables (e.g., two or more substrate tables WTa, WTb, two or more patterning device tables, a substrate table WTa and a table WTb below the projection system without a substrate that is dedicated to, for example, facilitating measurement, and / or cleaning, etc.). In such “multiple stage” machines, the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposure. For example, alignment measurements using an alignment sensor AS and / or level (height, tilt, etc.) measurements using a level sensor LS may be made.

[0044] In operation of the lithographic apparatus, a radiation beam is conditioned and provided by the illumination system IL. The radiation beam B is incident on the patterning device (e.g., mask) MA, which is held on the support structure (e.g., mask table) MT. Having traversed the patterning device MA, the radiation beam B passes through the projection system PS, which focuses the beam onto a target portion C of the substrate W. With the aid of the second positioner PW and positionsensor IF (e.g., an interferometric device, linear encoder, 2-D encoder, or capacitive sensor), the substrate table WT can be moved accurately, e.g. to position different target portions C in the path of the radiation beam B. Similarly, the first positioner PM and another position sensor (which is not explicitly depicted in Fig. 1) can be used to accurately position the patterning device MA with respect to the path of the radiation beam B, e.g. after mechanical retrieval from a mask library, or during a scan. In general, movement of the support structure MT may be realized with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning), which form part of the first positioner PM. Similarly, movement of the substrate table WT may be realized using a long-stroke module and a short-stroke module, which form part of the second positioner PW. In the case of a stepper (as opposed to a scanner), the support structure MT may be connected to a short-stroke actuator only, or may be fixed. Patterning device MA and substrate W may be aligned using patterning device alignment marks Ml, M2 and substrate alignment marks Pl, P2. Although the substrate alignment marks as illustrated occupy dedicated target portions, they may be located in spaces between target portions (these are known as scribe-lane alignment marks). Similarly, in situations in which more than one die is provided on the patterning device MA, the patterning device alignment marks may be located between the dies.

[0045] The depicted apparatus may be used in a step mode and / or a scan mode. In step mode, the support structure MT and the substrate table WT are kept essentially stationary, while a pattern imparted to the radiation beam is projected onto a target portion C at one time (i.e. a single static exposure). The substrate table WT is then shifted in the X and / or Y direction so that a different target portion C can be exposed. In step mode, the maximum size of the exposure field limits the size of the target portion C imaged in a single static exposure. In scan mode, the support structure MT and the substrate table WT are scanned synchronously while a pattern imparted to the radiation beam is projected onto a target portion C (i.e. a single dynamic exposure). The velocity and direction of the substrate table WT relative to the support structure MT may be determined by the (de-) magnification and image reversal characteristics of the projection system PS. In scan mode, the maximum size of the exposure field limits the width (in the non-scanning direction) of the target portion in a single dynamic exposure, whereas the length of the scanning motion determines the height (in the scanning direction) of the target portion. In another mode, the support structure MT is kept essentially stationary holding a programmable patterning device, and the substrate table WT is moved or scanned while a pattern imparted to the radiation beam is projected onto a target portion C. In this mode, generally a pulsed radiation source is employed, and the programmable patterning device is updated as required after each movement of the substrate table WT or in between successive radiation pulses during a scan. This mode of operation can be readily applied to maskless lithography that utilizes programmable patterning device, such as a programmable mirror array of a type as referred to above. Combinations and / or variations on the above-described modes of use or entirely different modes of use may also be employed.

[0046] A substrate may be processed, before or after exposure, in for example a track (a tool that typically applies a layer of resist to a substrate and develops the exposed resist) or a metrology or inspection tool. Where applicable, the disclosure herein may be applied to such and other substrate processing tools. Further, the substrate may be processed more than once, for example in order to create a multi-layer IC, so that the term substrate used herein may also refer to a substrate that already includes multiple processed layers.

[0047] The terms “radiation” and “beam” used herein encompass all types of electromagnetic radiation, including ultraviolet (UV) or deep ultraviolet (DUV) radiation (e.g. having a wavelength of 365, 248, 193, 157 or 126 nm) and extreme ultra-violet (EUV) radiation (e.g. having a wavelength in the range of 5-20 nm), as well as particle beams, such as ion beams or electron beams.

[0048] Various patterns on or provided by a patterning device may have different process windows, i.e., a space of processing variables under which a pattern will be produced within specification. Examples of pattern specifications that relate to potential systematic defects include checks for necking, line pull back, line thinning, critical dimension (CD), edge placement, overlapping, resist top loss, resist undercut and / or bridging. The process window of the patterns on a patterning device or an area thereof may be obtained by merging (e.g., overlapping) process windows of each individual pattern. The boundary of the process window of a group of patterns comprises boundaries of process windows of some of the individual patterns. In other words, these individual patterns limit the process window of the group of patterns. These patterns can be referred to as “process window limiting patterns (PWLPs),” for example.

[0049] As shown in Fig. 2, the lithographic apparatus LA may form part of a lithographic cell LC, also sometimes referred to as a lithocell or cluster, which also includes apparatuses to perform pre- and post-exposure processes on a substrate. Conventionally these include one or more spin coaters SC to deposit one or more resist layers, one or more developers to develop exposed resist, one or more chill plates CH and / or one or more bake plates BK. A substrate handler, or robot, RO picks up one or more substrates from input / output port I / Ol, I / O2, moves them between the different process apparatuses and delivers them to the loading bay LB of the lithographic apparatus. These apparatuses, which are often collectively referred to as the track, are under the control of a track control unit TCU which is itself controlled by the supervisory control system SCS, which also controls the lithographic apparatus via lithography control unit LACU. Thus, the different apparatuses can be operated to maximize throughput and processing efficiency.

[0050] In order to ensure that a substrate that is exposed by the lithographic apparatus is exposed correctly and consistently and / or in order to monitor a part of the patterning process (e.g., a device manufacturing process) that includes at least one pattern transfer step (e.g., an optical lithography step), it is desirable to inspect a substrate or other object to measure or determine one or more properties such as alignment, overlay (which can be, for example, between structures in overlying layers or between structures in a same layer that have been provided separately to the layer by, forexample, a double patterning process), line thickness, critical dimension (CD), focus offset, a material property, etc. For example, contamination on reticle clamp membranes (e.g., as described herein) may adversely affect overlay because clamping a reticle over such contamination will distort the reticle. Accordingly, a manufacturing facility in which lithocell LC is located also typically includes a metrology system that measures some or all of the substrates W (Fig. 1) that have been processed in the lithocell or other objects in the lithocell. The metrology system may be part of the lithocell LC; for example it may be part of the lithographic apparatus LA (such as alignment sensor AS (Fig. 1)).

[0051] The one or more measured parameters may include, for example, alignment, overlay between successive layers formed in or on the patterned substrate, critical dimension (CD) (e.g., critical linewidth) of, for example, features formed in or on the patterned substrate, focus or focus error of an optical lithography step, dose or dose error of an optical lithography step, optical aberrations of an optical lithography step, etc. This measurement may be performed on a target of the product substrate itself and / or on a dedicated metrology target provided on the substrate. The measurement can be performed after-development of a resist but before etching, after-etching, after deposition, and / or at other times.

[0052] Thus, in a device fabrication process (e.g., a patterning process, a lithography process, etc.), a substrate or other objects may be subjected to various types of measurement during or after the process. The measurement may determine whether a particular substrate is defective, may establish adjustments to the process and apparatuses used in the process (e.g., aligning two layers on the substrate or aligning the patterning device to the substrate), may measure the performance of the process and the apparatuses, or may be for other purposes. Examples of measurement include optical imaging (e.g., optical microscope), non-imaging optical measurement (e.g., measurement based on diffraction such as the ASML YieldStar metrology tool, the ASML SMASH metrology system), mechanical measurement (e.g., profiling using a stylus, atomic force microscopy (AFM)), and / or non- optical imaging (e.g., scanning electron microscopy (SEM)).

[0053] Metrology results may be provided directly or indirectly to the supervisory control system SCS. If an error is detected, an adjustment may be made to exposure of a subsequent substrate (especially if the inspection can be done soon and fast enough that one or more other substrates of the batch are still to be exposed) and / or to subsequent exposure of the exposed substrate. Also, an already exposed substrate may be stripped and reworked to improve yield, or discarded, thereby avoiding performing further processing on a substrate known to be faulty. In a case where only some target portions of a substrate are faulty, further exposures may be performed only on those target portions which meet specifications.

[0054] Within a metrology system, a metrology apparatus is used to determine one or more properties of the substrate, and in particular, how one or more properties of different substrates vary, or different layers of the same substrate vary from layer to layer. As noted above, the metrology apparatus may be integrated into the lithographic apparatus LA or the lithocell LC or may be a stand-alone device.

[0055] To enable the metrology, one or more targets can be provided on the substrate. In an embodiment, the target is specially designed and may comprise a periodic structure. In an embodiment, the target is a part of a device pattern, e.g., a periodic structure of the device pattern. In an embodiment, the device pattern is a periodic structure of a memory device (e.g., a Bipolar Transistor (BPT), a Bit Line Contact (BLC), etc. structure).

[0056] The present systems, and / or methods may be used as stand-alone tools and / or techniques, and / or or used in conjunction with semiconductor manufacturing processes, to enhance the accurate transfer of complex designs to physical wafers.

[0057] As described above, a clamping system may be used in a lithographic and / or metrology apparatus to clamp an object such as a patterning device (e.g., a reticle), a substrate such as a wafer, and / or other objects. Before clamping, the lithographic apparatus (for example) may move the object through typical movements and / or positions to a clamping position.

[0058] Fig. 3 illustrates example portions of a clamping system 300. In some embodiments, clamping system 300 is part of a lithography apparatus (e.g., lithography apparatus LA shown in Fig. 1) used in semiconductor manufacturing. Clamping system 300 may be used to clamp reticles, wafers, and / or other objects. Clamping system 300 may be and / or include an electrostatic clamp for an extreme ultra violet (EUV) lithographic apparatus in this example, though the principles described herein may potentially be applied in a clamp for a deep ultra violet (DUV) lithographic apparatus clamp (e.g., a DUV reticle stage clamp) and / or other clamps. Object 302 (e.g., a wafer in this example) may be brought into the lithographic apparatus with a tool handler and clamped by clamping system 300. Clamping system 300 includes a base 304 (two different possible versions: version 301 - with shorter burls 312, and version 303 - with longer more flexible burls 312, are shown in Fig. 3), a dielectric 306, an electrode 308, an insulator 310, and / or other components. Fig. 3 also illustrates burls 312, adhesive 314, channels or holes 316 with interior electrical ground surfaces 318, and / or other components. Fig. 3 illustrates an enlarged portion 350 of areas 360 which repeat across clamping system 300.

[0059] Electrode 308 is configured to generate an electric field to provide a clamping force to hold object 302 against base 304. Electrode 308 may be formed by a layer of metal, for example. Power may be provided to electrode 308 by, for example, wires that connect a contact pad on the edge of base 304 to a high power electronics amplifier. This contact pad makes electrical contact to the embedded electrode 308 in dielectric 306 (a dielectric sheet). This is bipolar: one half positive, one half negative. So there are two wires, as well as a ground connection to ground the core / base. In this example, the clamping force is an electrostatic force that creates electrostatic pressure on object 302.

[0060] Base 304 is configured to removably contact object 302 (e.g., a wafer) via burls 312. Burls 312 extend from base 304. Channels or holes 316 in dielectric 306 are configured to receive each burl 312 such that each burl 312 protrudes through dielectric 306. Contacting may include touching,nearly touching, and / or other contacting. In some embodiments, the contacting is controlled by one or more processors (see Fig. 9), via the tool handler, and / or using other components of a lithography apparatus (e.g., as described herein). For example, a charge may be propagated through electrode 308 such that an opposite polarity is induced in a side of a clamped object configured to contact burls 312. Base 304 and / or burls 312 may be formed from a silicon - silicon carbide material and / or other materials.

[0061] Dielectric 306 comprises an insulating material that does not conduct electricity, but can support an electrostatic field. Such materials can generally include glass, plastic, ceramics, and polymers. Dielectric 306 may comprise one or more layers. In some embodiments, dielectric 306 comprises a first dielectric layer 307 and a second dielectric layer 309. Electrode 308 and insulator 310 are coupled to dielectric 306 between first dielectric layer 307 and second dielectric layer 309. In other words, electrode 308 and insulator 310 may be sandwiched between first dielectric layer 307 and second dielectric layer 309. In Fig. 3, first dielectric layer 307 may comprise a first glass layer, and second dielectric layer 309 may comprise a second glass layer, for example.

[0062] Interior electrical ground surfaces 318 are configured to provide an electrical ground for clamping system 300 such that dielectric 306 is grounded (base 304 and dielectric 306 are separately grounded). If there were no ground on the inside of the holes 316 in dielectric 306, a field would exist both in insulator 310 and the hole 316 (e.g., in a vacuum between dielectric 306 and the burl 312 of base 304). This is undesirable, as contamination and particles may accumulate there. In combination with an electric field, these particles can become charged and mobile, forming a defect risk. In addition, when gas is present (e.g., back fill gas for cooling) discharges may occur, causing also a defect and charging risk. The grounded burl 312 holes 316 ensure that the electric field inside the holes 316 (around the burls 312) is zero.

[0063] Insulator 310 is (or multiple insulators 310 are) positioned between electrode 308 and ground surfaces 318. Insulator 310 is configured to electrically insulate electrode 308 from ground surfaces 318. Insulator 310 may be formed from an insulating material such as a polymer, a ceramic, and / or other materials. For example, in some embodiments, insulator 310 may be an adhesive configured to couple first and second dielectric layers 307 and 309 together. Note that burls 312 and / or other components of clamping system 300 may comprise similar electrical ground surfaces (even though they are not shown in Fig. 3).

[0064] Adhesive 314 and / or other coupling devices (screws, nuts, bolts, clips, clamps, etc.) may be used to couple dielectric 306 to base 304. In some embodiments, base 304 may comprise and / or be coupled to a chuck and / or other components. For example, although not shown in Fig. 3, clamping system 300 may comprise a second dielectric and the chuck. The second dielectric may comprise a second electrode configured to couple base 304 to the chuck. The chuck may be configured to hold base 304 and dielectric 306 (e.g., which form a clamp), and object 302, and facilitate movement of the clamp and object 302, and / or perform other operations.

[0065] Fig. 4 illustrates an enlarged portion of clamping system 300, showing dielectric 306 comprising first dielectric layer 307 and second dielectric layer 309, with electrode 308 and insulator 310 coupled to dielectric 306 between first dielectric layer 307 and second dielectric layer 309. Fig. 4 also illustrates object 302 (e.g., a wafer), a burl 312, a channel or hole 316, and a ground surface 318. As described above with respect to Fig. 3, electrode 308 is configured to generate an electric field to provide a clamping force to hold object 302 against burl 312. Interior electrical ground surface 318 is configured to provide an electrical ground for clamping system 300. Insulator 310 is positioned between electrode 308 and ground surface 318, and configured to electrically insulate electrode 308 from ground surface 318.

[0066] This arrangement may cause a local increase in electric field strength at or near the edge 400 of electrode 308 (near channel or hole 316). Because of this local increase, charge may build up in insulator 310 and / or dielectric layers 307 and / or 309, in an interface between them, and / or in other interfacial layers, charge may unexpectedly dissipate, insulator 310 and / or other components of clamping system 300 may break down, and / or the local increases in electric field strength can have other undesired effects. These undesired effects cause object 302 to stick or slip unexpectedly during processing, introduce particles into the lithographic apparatus (e.g., after a full breakdown), prevent use of an otherwise higher clamping force, limit lifetime of one or more components of system 300, and / or have other disadvantages.

[0067] For example, Fig. 5 illustrates a simulation 500 of a local increase in electric field strength at or near edge 400 of electrode 308. Electric field strength is indicated by the shading in Fig. 5, with darker shading corresponding to stronger portions of the electric field. Simulation 500 is a two dimensional electric field simulation. Fig. 5 illustrates a distribution 502 of electric field lines 504 around edge 400 of electrode 308. In simulation 500, there is a “hot spot” 510 - a local electric field strength concentration, or local maximum. Hot spot 510 can have various negative effects including charge build up in insulator 310, as indicated by arrow 520 in Fig. 5, for example (among the other possible negative effects described herein). In this region charge can creep, which may lead to local sticking forces on wafers, for example.

[0068] Fig. 6 illustrates another embodiment of clamping system 300, with a capping layer 600 coupled to electrode 308. In Fig. 6, capping layer 600 is illustrated at edge 400 of electrode 308. This is not intended to be limiting. Capping layer 600 may be coupled edge 400, and / or additional portions of electrode 308, up to an entirety of electrode 308, so long as capping layer 600 functions as described herein. Capping layer 600 may have other features such as angular or rounded corners, different thicknesses, etc., that facilitate the described functionality.

[0069] Capping layer 600 is configured to reduce a local maximum (e.g., hot spot 510 shown in Fig. 5) in the electric field strength, located at or near edge 400 of electrode 308. Capping layer 600 causes a redistribution of electric field lines (e.g., electric field lines 504 shown in Fig. 5) around edge 400 of electrode 308, which locally reduces the electric field strength. Capping layer 600 has a higherpermittivity, resulting in a higher capacity to store electrostatic energy, which reduces the local field strength. Redistribution simply means that the field lines, which normally converge more tightly around the electrode edge, spread out or fan out more inside a high permittivity material compared to a material with lower permittivity. This redistribution or fanning out reduces the local electric field intensity and smooths out the field distribution near the electrode edge.

[0070] This local reduction in electric field strength reduces or prevents “hot spots” 510 shown in Fig. 5 (local maximums in electric field strength concentrations). In addition, capping layer 600 may act as a shield around edge 400 of electrode 308 that provides a gradual transition between (the metal) electrode 308 and the surrounding medium (e.g., dielectric 306 and / or insulator 310). This facilitates increased clamping pressure, reduces the risk of particle generation and / or clamp failure, reduces or prevents residual clamp holding forces, and / or has other advantages.

[0071] As shown in Fig. 6, clamping system 300 includes dielectric 306 (coupled to base 304 shown in Fig. 3, which is configured to removably hold object 302 such as a wafer, a reticle, etc.), electrode 308 coupled to dielectric 306, capping layer 600 coupled to electrode 308, and / or other components. Reiterating the description above, dielectric 306 comprises first dielectric layer 307 and second dielectric layer 309. Electrode 308 is configured to generate the electric field to provide the clamping force to hold object 302 against burl 312 (of base 304). Dielectric 306 comprises a channel or hole 316 configured to receive burl 312 such that burl 312 protrudes through dielectric 306, with the channel or hole 316 comprising interior electrical ground surface 318. Dielectric 306 comprises insulator 310 positioned between electrode 308 and interior electrical ground surface 318. Channel or hole 316 is oriented generally perpendicular to first dielectric layer 307 and second dielectric layer 309. Electrode 308, capping layer 600, and insulator 310 are oriented generally parallel to first dielectric layer 307 and second dielectric layer 309, with insulator 310 positioned between electrode 308 and capping layer 600 on one side, and channel or hole 316 on an opposite side. Electrode 308 and capping layer 600 and / or insulator 310 are coupled to dielectric 306 between first dielectric layer 307 and second dielectric layer 309 (e.g., sandwiched between first dielectric layer 307 and second dielectric layer 309).

[0072] In this embodiment, dielectric 306 (including layers 307 and 309 in this example) has a first permittivity, and capping layer 600 has a second permittivity higher than the first permittivity, such that capping layer 600 is configured to locally reduce the strength of the electric field. Insulator 310 has a third permittivity. The second permittivity (of capping layer 600) is higher than (e.g., at least two, three, four, or five times higher than) the first permittivity (of dielectric 306) and the third permittivity (of insulator 310). For example, in some embodiments, capping layer 600 comprises a relatively high dielectric constant (k) material, having a dielectric constant greater than that of dielectric 306 including first and / or second dielectric layers 307 and / or 309, and insulator 310. In some embodiments, capping layer 600 has a dielectric constant greater than about 5.75, for example.

[0073] In some embodiments (e.g., as described above), first dielectric layer 307 comprises a firstglass layer; and second dielectric layer 309 comprises a second glass layer. Electrode 308 may be coupled to the first glass layer. Capping layer 600 may comprise a dielectric coating disposed on electrode 308 between electrode 308 and the second glass layer. For example, capping layer 600 may comprise titanium oxide, barium titanium oxide, aluminum oxide, lanthanum oxide, zirconium oxide, hafnium oxide, strontium titanium oxide, and / or other materials. Capping layer 600 may be coupled to dielectric 306 (e.g., on electrode 308) using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other processes.

[0074] In some embodiments, there may be a plurality of burls 312, and a plurality of corresponding channels or holes 316, with each burl 312 and corresponding channel or hole 316 combination comprising corresponding electrodes 308, capping layers 600, and insulators 310. In some embodiments, base 304, dielectric 306, electrode 308, insulator 310, and capping layer 600 form a portion of an electrostatic clamp, and the electrostatic clamp is configured to releasably clamp object 302 (e.g., a wafer or a reticle) for a semiconductor processing operation.

[0075] In some embodiments, the clamping force may be an electrostatic force that creates electrostatic pressure on the object. Reducing the local maximum electric field strength facilitates enhanced overall clamping pressure.

[0076] Fig. 7 illustrates a graph 700 of electric field strength 702 verses location 704 relative to electrode edge 400 (see Fig. 6). Fig. 7 illustrates electric field strength 702, with 706 and without 708 a capping layer (e.g., capping layer 600 shown in Fig. 6), at locations 704 closer to 710 and further from 712 electrode edge 400. The electric field strength at edge 400 is about l-2x lower 720 for the same clamping pressure for a given distance from electrode edge 400 (e.g., up to about lum). This means that the clamping pressure can be increased 722. The situation is still improved at further distances (moving to the right in graph 700) from the electrode edge.

[0077] For example, for a capping layer (e.g., capping layer 600 shown in Fig. 6), with high relative permittivity (e.g., > 5.75) relative to insulator 310 (Fig. 3-6) and dielectric 306 (Fig. 3-6), the electric field strength at electrode edge 400 may be about 1.3x lower compared to an embodiment without a capping layer, for the same clamping pressure at object 302 (e.g., wafer) level for a distance from the electrode of up to about lum. This facilitates increasing the electrode voltage before the baseline-equivalent electric field strength is reached. This is equivalent to increasing the clamping pressure by about 1.7x, assuming all other factors stay the same, thereby realizing a higher clamping force.

[0078] Fig. 8 illustrates a clamping method 800. Method 800 may be performed with a clamping system and / or other components, as described herein (e.g., clamping system 300 shown in Fig. 6). The system may include a base configured to removably hold an object (e.g., a reticle, a wafer, etc.), a dielectric coupled to the base, an electrode coupled to the dielectric, a capping layer coupled to the electrode, an insulator, and / or other components. The clamping system may be part of a lithography apparatus, a metrology apparatus, and / or other systems. For example, the clamping system may bepart of a lithography apparatus used in semiconductor manufacturing. In some embodiments, one or more operations of method 800 are controlled by one or more processors and / or a computing system, as described below (see Fig. 9). The operations of method 800 presented below are intended to be illustrative. In some embodiments, method 800 may be accomplished with one or more additional operations not described, and / or without one or more of the operations discussed. Additionally, the order in which the operations of method 800 are illustrated in Fig. 8 and described below is not intended to be limiting.

[0079] In some embodiments, one or more operations of method 800 may be implemented in and / or controlled by one or more processing devices (e.g., a digital processor, an analog processor, a digital circuit designed to process information, an analog circuit designed to process information, a state machine, and / or other mechanisms for electronically processing information, as described with respect to Fig. 9 below). The one or more processing devices may include one or more devices executing some or all of the operations of method 800 in response to instructions stored electronically on an electronic storage medium. The one or more processing devices may include one or more devices configured through hardware, firmware, and / or software to be specifically designed for execution of one or more of the operations of method 800 (e.g., see discussion related to Fig. 9 below). For example, the one or more processing devices may run software configured to control energization of an electrode of the clamping system, and / or perform other operations in the clamping system.

[0080] At an operation 802, a base removably contacts an object. The object may be a patterning device such as a reticle, a wafer, etc.. The base is coupled to a dielectric. At an operation 804, an electric field is generated with an electrode coupled to the dielectric to provide a clamping force to hold the object against the base. At an operation 806, a strength of the electric filed is locally reduced with a capping layer. The capping layer is coupled to the electrode. The capping layer is configured to reduce a local maximum in the electric field strength, located at or near the edge of the electrode. The capping layer causes a redistribution of electric field lines around the edge of the electrode, as material of the capping layer is configured to store more electric energy, which locally reduces the electric field strength. This local reduction in electric field strength reduces or prevents “hot spots” (local electric field strength concentrations), which facilitates increased clamping pressure, reduces the risk of clamp failure, reduces or prevents residual clamp holding forces, and / or has other advantages.

[0081] In some embodiments, the base comprises a burl configured to removably contact the object. The dielectric may comprise a channel configured to receive the burl such that the burl protrudes through the dielectric, with the channel comprising an interior electrical ground surface. The dielectric may comprise an insulator positioned between the electrode and the interior electrical ground surface. The channel may be oriented generally perpendicular to the first dielectric layer and the second dielectric layer. The electrode, the capping layer, and the insulator may be orientedgenerally parallel to the first dielectric layer and the second dielectric layer, with the insulator between the electrode and the capping layer on one side, and the channel on an opposite side.

[0082] The dielectric has a first permittivity. The insulator has a third permittivity. The capping layer has a second permittivity higher than the first permittivity and the third permittivity, such that the capping layer is configured to locally reduce the strength of the electric field generated by the electrode. The second permittivity (of the capping layer) is higher than (e.g., at least two, three, four, or five times higher than) the first permittivity (of the dielectric) and the third permittivity (of the insulator). For example, in some embodiments, the capping layer comprises a relatively high dielectric constant (k) material, having a dielectric constant greater than that of a first and / or second dielectric layer and the insulator. In some embodiments, the capping layer has a dielectric constant greater than about 5.75.

[0083] In some embodiments, the dielectric comprises a first dielectric layer and a second dielectric layer. The electrode and capping layer and / or the insulator are coupled to the dielectric between the first dielectric layer and the second dielectric layer. For example, the electrode, the capping layer, and the insulator may be sandwiched between the first dielectric layer and the second dielectric layer.

[0084] In some embodiments, the first dielectric layer comprises a first glass layer; and the second dielectric layer comprises a second glass layer. The electrode may be coupled to the first glass layer. The capping layer may comprise a dielectric coating disposed on the electrode between the electrode and the second glass layer. For example, the capping layer may comprise titanium oxide, barium titanium oxide, aluminum oxide, lanthanum oxide, zirconium oxide, hafnium oxide, strontium titanium oxide, and / or other materials. The capping layer may be coupled to the dielectric using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other processes.

[0085] In some embodiments, the insulator comprises an adhesive layer disposed between (1) the first glass layer and the second glass layer, and (2) between the electrode and the capping layer and the electrical ground surface.

[0086] In some embodiments, the capping layer covers at least an edge of the electrode, proximate to the insulator and / or the interior electrical ground surface of the channel. As described above, the capping layer is configured to reduce a local maximum in the electric field strength, located at or near the edge of the electrode. The capping layer causes a redistribution of electric field lines around the edge of the electrode, as material of the capping layer is configured to store more electric energy, which locally reduces the electric field strength.

[0087] In some embodiments, there may be a plurality of burls, and a plurality of corresponding channels, with each burl and corresponding channel combination comprising corresponding electrodes, capping layers, and insulators.

[0088] In some embodiments, the clamping force comprises a clamping pressure, and reducing thelocal maximum electric field strength facilitates enhanced overall clamping pressure. The clamping force may be an electrostatic force that creates electrostatic pressure on the object, for example.

[0089] In some embodiments, the base, the dielectric, the electrode, and the capping layer form a portion of an electrostatic clamp, and the electrostatic clamp is configured to releasably clamp the object for a semiconductor processing operation.

[0090] In some embodiments, the system comprises a second dielectric and a chuck, with the second dielectric comprising a second electrode, optionally with a second capping layer, configured to couple the base to the chuck. The chuck is configured to hold the clamp, and the object, and facilitate movement of the clamp, and the object.

[0091] Fig. 9 is a block diagram that illustrates a computer system 900 that can assist in implementing the methods, flows, or the system(s) disclosed herein. Computer system 900 may be included in and / or electronically coupled to lithography apparatus LA described above (Fig. 1, Fig. 3, etc.), system(s) 300 shown in Fig. 3-6 and described above, and / or other systems. Computer system 900 includes a bus 902 or other communication mechanism for communicating information, and a processor 904 (or multiple processors 904, 905, etc.) coupled with bus 902 for processing information. Computer system 900 also includes a main memory 906, such as a random access memory (RAM) or other dynamic storage device, coupled to bus 902 for storing information and instructions to be executed by processor 904. Main memory 906 also may be used for storing temporary variables or other intermediate information during execution of instructions to be executed by processor 904. Computer system 900 further includes a read only memory (ROM) 908 or other static storage device coupled to bus 902 for storing static information and instructions for processor 904. A storage device 910, such as a magnetic disk or optical disk, is provided and coupled to bus 902 for storing information and instructions.

[0092] Computer system 900 may be coupled via bus 902 to a display 912, such as a flat panel or touch panel display for displaying information to a computer user. An input device 914, including alphanumeric and other keys, is coupled to bus 902 for communicating information and command selections to processor 904. Another type of user input device is cursor control 916, such as a mouse, a trackball, or cursor direction keys for communicating direction information and command selections to processor 904 and for controlling cursor movement on display 912. This input device typically has two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y), that allows the device to specify positions in a plane. A touch panel (screen) display may also be used as an input device.

[0093] According to one embodiment, portions of one or more flows and / or methods described herein may be performed by computer system 900 in response to processor 904 executing one or more sequences of one or more instructions contained in main memory 906. Such instructions may be read into main memory 906 from another computer-readable medium, such as storage device 910. Execution of the sequences of instructions contained in main memory 906 causes processor 904 toperform the flows and / or process steps described herein. One or more processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in main memory 906. In an alternative embodiment, hard-wired circuitry may be used in place of or in combination with software instructions. Thus, the description herein is not limited to any specific combination of hardware circuitry and software.

[0094] The term “computer-readable medium” or “machine readable medium” refers to any medium that participates in providing instructions to processor 904 for execution. Such a medium may take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 910. Volatile media include dynamic memory, such as main memory 906. Transmission media include coaxial cables, copper wire and fiber optics, including the wires that comprise bus 902. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM, DVD, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH- EPROM, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium from which a computer can read.

[0095] Various forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to processor 904 for execution. For example, the instructions may initially be borne on a magnetic disk of a remote computer. The remote computer can load the instructions into its dynamic memory and send the instructions over a network. Computer system 900 can receive the data. Bus 902 carries the data to main memory 906, from which processor 904 retrieves and executes the instructions. The instructions received by main memory 906 may optionally be stored on storage device 910 either before or after execution by processor 904.

[0096] Computer system 900 may also include a communication interface 918 coupled to bus 902. Communication interface 918 provides a two-way data communication coupling to a network link 920 that is connected to a local network 922. For example, communication interface 918 may be an integrated services digital network (ISDN) card or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, communication interface 918 may be a local area network (LAN) card to provide a data communication connection to a compatible LAN. Wireless links may also be implemented. In any such implementation, communication interface 918 sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.

[0097] Network link 920 typically provides data communication through one or more networks to other data devices. For example, network link 920 may provide a connection through local network 922 to a host computer 924 or to data equipment operated by an Internet Service Provider (ISP) 926.ISP 926 in turn provides data communication services through the worldwide packet data communication network, now commonly referred to as the “Internet” 928. Local network 922 and Internet 928 both use electrical, electromagnetic, or optical signals that carry digital data streams. The signals through the various networks and the signals on network link 920 and through communication interface 918, which carry the digital data to and from computer system 900, are exemplary forms of carrier waves transporting the information.

[0098] Computer system 900 can send messages and receive data, including program code, through the network(s), network link 920, and communication interface 918. In the Internet example, a server 930 might transmit a requested code for an application program through Internet 928, ISP 926, local network 922 and communication interface 918. One such downloaded application may provide all or part of a method described herein, for example. The received code may be executed by processor 904 as it is received, and / or stored in storage device 910, or other non-volatile storage for later execution. In this manner, computer system 900 may obtain application code in the form of a carrier wave.

[0099] Various embodiments of the present systems and methods are disclosed in the subsequent list of numbered clauses:1. A clamping system, comprising: a base configured to removably contact an object; a dielectric coupled to the base, the dielectric having a first permittivity; an electrode coupled to the dielectric, configured to generate an electric field to provide a clamping force to hold the object against the base; and a capping layer coupled to the electrode, the capping layer having a second permittivity higher than the first permittivity, such that the capping layer is configured to locally reduce a strength of the electric field.2. The system of clause 1 , wherein the dielectric comprises a first dielectric layer and a second dielectric layer, and the electrode and capping layer are coupled to the dielectric between the first dielectric layer and the second dielectric layer.3. The system of any of the previous clauses, wherein the electrode and the capping layer are sandwiched between the first dielectric layer and the second dielectric layer.4. The system of any of the previous clauses, wherein: the base comprises a burl configured to removably contact the object; and the dielectric comprises: a channel configured to receive the burl such that the burl protrudes through the dielectric, the channel comprising an interior electrical ground surface; and an insulator positioned between the electrode and the interior electrical ground surface, the insulator having a third permittivity; wherein the second permittivity of the capping layer is higher than the first permittivity and the third permittivity.5. The system of any of the previous clauses, wherein the second permittivity of the capping layer is at least two, three, four, or five times higher than the first permittivity of the dielectric and the third permittivity of the insulator.6. The system of any of the previous clauses, wherein the capping layer comprises a relatively high dielectric constant (k) material, having a dielectric constant greater than that of a first and / or second dielectric layer and the insulator.7. The system of any of the previous clauses, wherein the capping layer has a dielectric constant greater than about 5.75.8. The system of any of the previous clauses, wherein the dielectric comprises a first dielectric layer and a second dielectric layer, and the electrode, the capping layer, and the insulator are coupled to the dielectric between the first dielectric layer and the second dielectric layer.9. The system of any of the previous clauses, wherein the channel is oriented generally perpendicular to the first dielectric layer and the second dielectric layer, and the electrode, the capping layer, and the insulator are oriented generally parallel to the first dielectric layer and the second dielectric layer, with the insulator between the electrode and the capping layer on one side, and the channel on an opposite side.10. The system of any of the previous clauses, wherein the first dielectric layer comprises a first glass layer; and the second dielectric layer comprises a second glass layer.11. The system of any of the previous clauses, wherein the electrode is coupled to the first glass layer, and the capping layer comprises a dielectric coating disposed on the electrode between the electrode and the second glass layer.12. The system of any of the previous clauses, wherein the insulator comprises an adhesive layer disposed between (1) the first glass layer and the second glass layer, and (2) between the electrode and the capping layer and the electrical ground surface.13. The system of any of the previous clauses, wherein the capping layer covers at least an edge of the electrode, proximate to the insulator and / or the interior electrical ground surface of the channel.14. The system of any of the previous clauses, wherein the capping layer is configured to reduce a local maximum in the electric field strength, located at or near the edge of the electrode.15. The system of any of the previous clauses, wherein the capping layer causes a redistribution of electric field lines around the edge of the electrode, as material of the capping layer is configured to store more electric energy, which locally reduces the electric field strength.16. The system of any of the previous clauses, further comprising a plurality of burls, and a plurality of corresponding channels, with each burl and corresponding channel combination comprising corresponding electrodes, capping layers, and insulators.17. The system of any of the previous clauses, wherein the clamping force comprises a clamping pressure, and wherein reducing a maximum local electric field strength facilitates enhanced overall clamping pressure.18. The system of any of the previous clauses, wherein the capping layer comprises titanium oxide, barium titanium oxide, aluminum oxide, lanthanum oxide, zirconium oxide, hafnium oxide, and / or strontium titanium oxide.19. The system of any of the previous clauses, wherein the capping layer is configured to be coupled to the dielectric using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).20. The system of any of the previous clauses, wherein the clamping force is an electrostatic force that creates electrostatic pressure on the object.21. The system of any of the previous clauses, wherein the base, the dielectric, the electrode, and the capping layer form a portion of an electrostatic clamp, and the electrostatic clamp is configured to releasably clamp the object for a semiconductor processing operation.22. The system of any of the previous clauses, further comprising a second dielectric and a chuck, wherein the second dielectric comprises a second electrode, optionally with a second capping layer, configured to couple the base to the chuck.23. The system of any of the previous clauses, wherein the chuck is configured to hold the clamp, and the object, and facilitate movement of the clamp, and the object.24. The system of any of the previous clauses, wherein the object comprises a wafer, and the clamping system is part of a lithography apparatus used in semiconductor manufacturing.25. The system of any of the previous clauses, wherein the object comprises a reticle, and the clamping system is part of a lithography apparatus used in semiconductor manufacturing.26. A clamping method, comprising: removably contacting an object with a base of a clamping system, wherein a dielectric is coupled to the base, the dielectric having a first permittivity; generating, with an electrode coupled to the dielectric, an electric field to provide a clamping force to hold the object against the base; and locally reducing, with a capping layer coupled to the electrode, a strength of the electric field, the capping layer having a second permittivity higher than the first permittivity.27. The method of clause 26, wherein the dielectric comprises a first dielectric layer and a second dielectric layer, and the electrode and capping layer are coupled to the dielectric between the first dielectric layer and the second dielectric layer.28. The method of any of the previous clauses, wherein the electrode and the capping layer are sandwiched between the first dielectric layer and the second dielectric layer.29. The method of any of the previous clauses, wherein: the base comprises a burl configured to removably contact the object; and the dielectric comprises: a channel configured to receive the burl such that the burl protrudes through the dielectric, the channel comprising an interior electrical ground surface; and an insulator positioned between the electrode and the interior electrical ground surface, the insulator having a third permittivity; wherein the second permittivity of the capping layer is higher than the first permittivity and the third permittivity.30. The method of any of the previous clauses, wherein the second permittivity of the capping layer is at least two, three, four, or five times higher than the first permittivity of the dielectric and the third permittivity of the insulator.31. The method of any of the previous clauses, wherein the capping layer comprises a relatively high dielectric constant (k) material, having a dielectric constant greater than that of a first and / or second dielectric layer and the insulator.32. The method of any of the previous clauses, wherein the capping layer has a dielectric constant greater than about 5.75.33. The method of any of the previous clauses, wherein the dielectric comprises a first dielectric layer and a second dielectric layer, and the electrode, the capping layer, and the insulator are coupled to the dielectric between the first dielectric layer and the second dielectric layer.34. The method of any of the previous clauses, wherein the channel is oriented generally perpendicular to the first dielectric layer and the second dielectric layer, and the electrode, the capping layer, and the insulator are oriented generally parallel to the first dielectric layer and the second dielectric layer, with the insulator between the electrode and the capping layer on one side, and the channel on an opposite side.35. The method of any of the previous clauses, wherein the first dielectric layer comprises a first glass layer; and the second dielectric layer comprises a second glass layer.36. The method of any of the previous clauses, wherein the electrode is coupled to the first glass layer, and the capping layer comprises a dielectric coating disposed on the electrode between the electrode and the second glass layer.37. The method of any of the previous clauses, wherein the insulator comprises an adhesive layer disposed between (1) the first glass layer and the second glass layer, and (2) between the electrode and the capping layer and the electrical ground surface.38. The method of any of the previous clauses, wherein the capping layer covers at least an edge of the electrode, proximate to the insulator and / or the interior electrical ground surface of the channel.39. The method of any of the previous clauses, wherein the capping layer is configured to reduce a local maximum in the electric field strength, located at or near the edge of the electrode.40. The method of any of the previous clauses, wherein the capping layer causes a redistribution of electric field lines around the edge of the electrode, as material of the capping layer is configured to store more electric energy, which locally reduces the electric field strength.41. The method of any of the previous clauses, wherein the base comprises a plurality of burls, and the dielectric comprises a plurality of corresponding channels, with each burl and corresponding channel combination comprising corresponding electrodes, capping layers, and insulators.42. The method of any of the previous clauses, wherein the clamping force comprises a clamping pressure, and wherein reducing a local maximum electric field strength facilitates enhanced overall clamping pressure.43. The method of any of the previous clauses, wherein the capping layer comprises titanium oxide, barium titanium oxide, aluminum oxide, lanthanum oxide, zirconium oxide, hafnium oxide, and / or strontium titanium oxide.44. The method of any of the previous clauses, wherein the capping layer is configured to be coupled to the dielectric using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).45. The method of any of the previous clauses, wherein the clamping force is an electrostatic force that creates electrostatic pressure on the object.46. The method of any of the previous clauses, wherein the base, the dielectric, the electrode, and the capping layer form a portion of an electrostatic clamp, and the electrostatic clamp is configured to releasably clamp the object for a semiconductor processing operation.47. The method of any of the previous clauses, further comprising providing a second dielectric and a chuck, wherein the second dielectric comprises a second electrode, optionally with a second capping layer, configured to couple the base to the chuck.48. The method of any of the previous clauses, wherein the chuck is configured to hold the clamp, and the object, and facilitate movement of the clamp, and the object.49. The method of any of the previous clauses, wherein the object comprises a wafer, and the clamping system is part of a lithography apparatus used in semiconductor manufacturing.50. The method of any of the previous clauses, wherein the object comprises a reticle, and the clamping system is part of a lithography apparatus used in semiconductor manufacturing.51. A semiconductor device manufacturing method comprising: receiving a substrate with a photoresist layer; directing radiation from a radiation source to transfer a pattern from a mask onto the photoresist layer; and removing a portion the photoresist layer to form the pattern over the substrate; wherein the substrate is held with a clamping system, the clamping system comprising: a base configured to removably contact an object; a dielectric coupled to the base, the dielectric having a first permittivity; an electrode coupled to the dielectric, configured to generate an electric field to provide a clamping force to hold the object against the base; and a capping layer coupled to the electrode, the capping layer having a second permittivity higher than the first permittivity, such that the capping layer is configured to locally reduce a strength of the electric field.

[0100] The concepts disclosed herein may be associated with any generic imaging system for imaging sub wavelength features, and may be especially useful with emerging imaging technologies capable of producing increasingly shorter wavelengths. Emerging technologies already in use include EUV (extreme ultra violet) lithography, deep ultra violet (DUV) lithography that is capable of producing a 193nm wavelength with the use of an ArF laser, and even a 157nm wavelength with the use of a Fluorine laser. Moreover, EUV lithography is capable of producing wavelengths within a range of 20-5nm by using a synchrotron or by hitting a material (either solid or a plasma) with high energy electrons in order to produce photons within this range.

[0101] While the concepts disclosed herein may be used for wafer manufacturing on a substrate such as a silicon wafer, it shall be understood that the disclosed concepts may be used with any type of manufacturing system, e.g., those used for manufacturing on substrates other than silicon wafers.In addition, the combination and sub-combinations of disclosed elements may comprise separate embodiments. For example, a wafer clamp alone, and / or the associated lithography apparatus may comprise separate embodiments, and / or these features may be used together in the same embodiment.

[0102] The descriptions above are intended to be illustrative, not limiting. Thus, it will be apparent to one skilled in the art that modifications may be made as described without departing from the scope of the claims set out below.

Claims

CLAIMS1. A clamping system, comprising: a base configured to removably contact an object; a dielectric coupled to the base, the dielectric having a first permittivity; an electrode coupled to the dielectric, configured to generate an electric field to provide a clamping force to hold the object against the base; and a capping layer coupled to the electrode, the capping layer having a second permittivity higher than the first permittivity, such that the capping layer is configured to locally reduce a strength of the electric field.

2. The system of claim 1 , wherein the dielectric comprises a first dielectric layer and a second dielectric layer, and the electrode and capping layer are coupled to the dielectric between the first dielectric layer and the second dielectric layer.

3. The system of any of claims 1-2, wherein: the base comprises a burl configured to removably contact the object; and the dielectric comprises: a channel configured to receive the burl such that the burl protrudes through the dielectric, the channel comprising an interior electrical ground surface; and an insulator positioned between the electrode and the interior electrical ground surface, the insulator having a third permittivity; wherein the second permittivity of the capping layer is higher than the first permittivity and the third permittivity.

4. The system of claim 3, wherein the dielectric comprises a first dielectric layer and a second dielectric layer, and the electrode, the capping layer, and the insulator are coupled to the dielectric between the first dielectric layer and the second dielectric layer.

5. The system of claim 4, wherein the channel is oriented generally perpendicular to the first dielectric layer and the second dielectric layer, and the electrode, the capping layer, and the insulator are oriented generally parallel to the first dielectric layer and the second dielectric layer, with the insulator between the electrode and the capping layer on one side, and the channel on an opposite side.

6. The system of any of claims 3-5, wherein the capping layer covers at least an edge of the electrode, proximate to the insulator and / or the interior electrical ground surface of the channel.

7. The system of any of claims 1-6, wherein the base, the dielectric, the electrode, and the capping layer form a portion of an electrostatic clamp, and the electrostatic clamp is configured to releasably clamp the object for a semiconductor processing operation.

8. A clamping method, comprising: removably contacting an object with a base of a clamping system, wherein a dielectric is coupled to the base, the dielectric having a first permittivity; generating, with an electrode coupled to the dielectric, an electric field to provide a clamping force to hold the object against the base; and locally reducing, with a capping layer coupled to the electrode, a strength of the electric field, the capping layer having a second permittivity higher than the first permittivity.

9. The method of claim 8, wherein the dielectric comprises a first dielectric layer and a second dielectric layer, and the electrode and capping layer are coupled to the dielectric between the first dielectric layer and the second dielectric layer.

10. The method of any of claims 8-9, wherein: the base comprises a burl configured to removably contact the object; and the dielectric comprises: a channel configured to receive the burl such that the burl protrudes through the dielectric, the channel comprising an interior electrical ground surface; and an insulator positioned between the electrode and the interior electrical ground surface, the insulator having a third permittivity; wherein the second permittivity of the capping layer is higher than the first permittivity and the third permittivity.

11. The method of claim 10, wherein the dielectric comprises a first dielectric layer and a second dielectric layer, and the electrode, the capping layer, and the insulator are coupled to the dielectric between the first dielectric layer and the second dielectric layer.

12. The method of claim 11, wherein the channel is oriented generally perpendicular to the first dielectric layer and the second dielectric layer, and the electrode, the capping layer, and the insulator are oriented generally parallel to the first dielectric layer and the second dielectric layer, with the insulator between the electrode and the capping layer on one side, and the channel on an opposite side.

13. The method of any of claims 10-12, wherein the capping layer covers at least an edge of the electrode, proximate to the insulator and / or the interior electrical ground surface of the channel.

14. The method of any of claims 8-13, wherein the base, the dielectric, the electrode, and the capping layer form a portion of an electrostatic clamp, and the electrostatic clamp is configured to releasably clamp the object for a semiconductor processing operation.

15. A semiconductor device manufacturing method comprising: receiving a substrate with a photoresist layer; directing radiation from a radiation source to transfer a pattern from a mask onto the photoresist layer; and removing a portion the photoresist layer to form the pattern over the substrate; wherein the substrate is held with a clamping system, the clamping system comprising: a base configured to removably contact an object; a dielectric coupled to the base, the dielectric having a first permittivity; an electrode coupled to the dielectric, configured to generate an electric field to provide a clamping force to hold the object against the base; and a capping layer coupled to the electrode, the capping layer having a second permittivity higher than the first permittivity, such that the capping layer is configured to locally reduce a strength of the electric field.

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