Semiconductor capacitor and method for manufacturing same

Abstract

A semiconductor capacitor according to the present invention includes a substrate, a plurality of dielectric films, a plurality of conductive films, a first electrode, and a second electrode. The substrate has a first main surface, a second main surface facing in an opposite direction to the first main surface, and a groove penetrating between the first main surface and the second main surface. The plurality of dielectric films and the plurality of conductive films are alternately stacked on a side surface of the groove. The first electrode is electrically connected to even-numbered layers of the conductive films counted from the side surface of the groove, and is electrically insulated from odd-numbered layers of the conductive films counted from the side surface of the groove. The second electrode is electrically connected to the odd-numbered layers of the conductive films and electrically insulated from the even-numbered layers of the conductive films. The odd-numbered layers of the conductive films are made of a material that has a higher etching rate with respect to a first etching liquid than the even-numbered layers of the conductive films. The even-numbered layers of the conductive films are made of a material that has a higher etching rate with respect to a second etching liquid than the odd-numbered layers of the conductive films.

Description

Semiconductor capacitor and method of manufacturing the same

[0001] The present invention relates to a semiconductor capacitor and a method for manufacturing the same.

[0002] As shown in FIG. 1A of Patent Document 1, a capacitor is known in which multiple dielectric layers and multiple conductive plates are alternately stacked on the inner surface of an opening penetrating the front and back surfaces of a substrate. On the front surface of the substrate, a portion of the even-numbered conductive film is removed from the inner surface of the opening to form a recess. On the back surface of the substrate, a portion of the odd-numbered conductive film is removed from the inner surface of the opening to form a recess. The recesses on the front and back surfaces of the substrate are backfilled with a dielectric film. On the front surface of the substrate, the odd-numbered conductive film layers are electrically connected to a first electrode, while the even-numbered conductive film layers are electrically insulated from the first electrode by the dielectric film. On the back surface of the substrate, the even-numbered conductive film layers are electrically connected to a second electrode, while the odd-numbered conductive film layers are electrically insulated from the second electrode by the dielectric film. This forms a capacitor structure between the odd-numbered conductive film layers and the even-numbered conductive film layers.

[0003] Special table 2014-505354 publication

[0004] However, the etching masks used to remove portions of the even-numbered conductive film on the front surface of the substrate and portions of the odd-numbered conductive film on the back surface of the substrate are typically formed using photolithography. Photolithography has limitations in processing accuracy, making it difficult to form detailed patterns. This can result in inaccurate formation of recesses on the front or back surface of the substrate, potentially resulting in electrical shorts between adjacent even-numbered conductive film and odd-numbered conductive film. To prevent this, the thickness of the conductive plate and dielectric layer must be increased, but this reduces the capacitance density of the capacitor.

[0005] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor capacitor with an increased capacitance density and a method for manufacturing the same.

[0006] A semiconductor capacitor according to one aspect of the present invention includes a substrate, a plurality of dielectric films, a plurality of conductive films, a first electrode, and a second electrode. The substrate has a first main surface, a second main surface facing in the opposite direction to the first main surface, and a groove penetrating between the first and second main surfaces. The plurality of dielectric films and the plurality of conductive films are alternately stacked on the side surfaces of the groove. The first electrode is electrically connected to the even-numbered conductive films counting from the side surfaces of the groove and electrically insulated from the odd-numbered conductive films counting from the side surfaces of the groove. The second electrode is electrically connected to the odd-numbered conductive films and electrically insulated from the even-numbered conductive films. The odd-numbered conductive films are made of a material having a higher etching rate with a first etching solution than the even-numbered conductive films. The even-numbered conductive films are made of a material having a higher etching rate with a second etching solution than the odd-numbered conductive films.

[0007] A method for manufacturing a semiconductor capacitor according to one aspect of the present invention includes the steps of: forming a trench penetrating between a first main surface and a second main surface facing in an opposite direction to the first main surface on a substrate; alternately stacking a plurality of dielectric films and a plurality of conductive films on side surfaces of the trench; removing the plurality of dielectric films and the plurality of conductive films stacked on the first main surface and the second main surface; and selectively etching a portion of the odd-layer conductive film exposed at a first opening of the trench using a first etching liquid having a higher etching rate for odd-layer conductive films counted from the side surfaces of the trench than for even-layer conductive films counted from the side surfaces of the trench. The method includes the steps of selectively etching a portion of the even-layer conductive film exposed in the second opening of the trench using a second etching liquid having a higher etching rate for the even-layer conductive film than for the odd-layer conductive film; forming an interlayer insulating film above the first and second main surfaces of the substrate and the first and second openings of the trench; removing the interlayer insulating film formed above the first and second openings of the trench; forming a first electrode electrically connected to the even-layer conductive film in the first opening of the trench; and forming a second electrode electrically connected to the odd-layer conductive film in the second opening of the trench.

[0008] According to the present invention, it is possible to provide a semiconductor capacitor with increased capacitance density and a method for manufacturing the same.

[0009] FIG. 1 is a cross-sectional view showing the configuration of a semiconductor capacitor 101 according to the first embodiment. FIG. 2 is a cross-sectional view showing a manufacturing process in a method for manufacturing the semiconductor capacitor 101 of FIG. 1 (part 1). FIG. 3 is a cross-sectional view showing a manufacturing process in a method for manufacturing the semiconductor capacitor 101 of FIG. 1 (part 2). FIG. 4 is a cross-sectional view showing a manufacturing process in a method for manufacturing the semiconductor capacitor 101 of FIG. 1 (part 3). FIG. 5 is a cross-sectional view showing a manufacturing process in a method for manufacturing the semiconductor capacitor 101 of FIG. 1 (part 4). FIG. 6 is a cross-sectional view showing a manufacturing process in a method for manufacturing the semiconductor capacitor 101 of FIG. 1 (part 5). FIG. 7 is a cross-sectional view showing the configuration of a semiconductor capacitor 102 according to a second embodiment. FIG. 8 is a cross-sectional view showing the configuration of a semiconductor capacitor 103 according to a third embodiment. FIG. 9 is a cross-sectional view showing the configuration of a semiconductor capacitor 104 according to a fourth embodiment. FIG. 10 is a cross-sectional view showing the configuration of a semiconductor capacitor 105 according to a fifth embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process in a method for manufacturing the semiconductor capacitor 105 of FIG. 10 (part 1). FIG. 12 is a cross-sectional view showing a manufacturing process in a method for manufacturing the semiconductor capacitor 105 of FIG. 10 (part 2). FIG. 13 is a cross-sectional view showing a manufacturing process in a method for manufacturing the semiconductor capacitor 105 of FIG. 10 (part 3). FIG. 14 is a cross-sectional view showing a manufacturing process in a method for manufacturing the semiconductor capacitor 105 of FIG. 10 (part 4). FIG. 15 is a cross-sectional view showing a configuration of a semiconductor capacitor 106 according to a sixth embodiment. FIG. 16A is a cross-sectional view showing a configuration of a semiconductor capacitor 107 according to a seventh embodiment. FIG. 16B is a cross-sectional view showing an enlarged region Mg of FIG. 16A. FIG. 17 is a cross-sectional view showing a configuration of a semiconductor capacitor 108 according to an eighth embodiment. FIG. 18 is a cross-sectional view showing a configuration of a semiconductor capacitor 201 according to a first comparative example. FIG. 19 is a cross-sectional view showing a manufacturing process of a semiconductor capacitor 202 according to a second comparative example.

[0010] The embodiments will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted.

[0011] First Embodiment [Configuration of Semiconductor Capacitor 100] The configuration of a semiconductor capacitor 101 according to the first embodiment will be described with reference to Figure 1. The semiconductor capacitor 101 includes a substrate 1. The substrate 1 has a first main surface 1A, a second main surface 1B facing in the opposite direction to the first main surface 1A, and a groove 8 penetrating between the first main surface 1A and the second main surface 1B.

[0012] A plurality of grooves 8 are formed in the flat substrate 1, penetrating its front and back surfaces (1A, 1B). Although not shown, the planar shape of the grooves 8 cut along the first main surface 1A is not particularly limited and may be rectangular or circular. If the planar shape of the grooves 8 is rectangular, it is desirable that the corners have a curved shape with a radius of curvature equal to or greater than a predetermined value. This makes it possible to avoid stress concentration or electric field concentration at the corners of the substrate 1. Furthermore, while FIG. 1 shows a case in which the side surfaces 8S of the grooves 8 are substantially perpendicular to the first main surface 1A and the second main surface 1B, this is not limiting and the side surfaces 8S of the grooves 8 may be inclined.

[0013] 1 shows a case in which the width of the first opening 8A of the groove 8 on the first main surface 1A side is approximately equal to the width of the second opening 8B of the groove 8 on the second main surface 1B side, but this is not limiting, and the width of the first opening 8A may be wider than the width of the second opening 8B, or the width of the second opening 8B may be wider than the width of the first opening 8A. In other words, the cross-sectional shape of the groove 8 may be a tapered shape widening from the second main surface 1B toward the first main surface 1A, or a tapered shape widening from the first main surface 1A toward the second main surface 1B.

[0014] The semiconductor capacitor 101 has multiple dielectric films 2 and multiple conductive films 3 and 4 alternately stacked on the side surface 8S of the groove 8. Specifically, the layers are stacked on the side surface 8S of the groove 8 in the following order: dielectric film 2, conductive film 3, dielectric film 2, conductive film 4, dielectric film 2, ... Counting from the side surface 8S of the groove 8, the odd-numbered conductive films 3 and the even-numbered conductive films 4 form a pair of electrodes of the semiconductor capacitor. Therefore, in the embodiment, the multiple conductive films 3 and 4 may be described separately as odd-numbered conductive films 3 and even-numbered conductive films 4. The thicknesses of the multiple dielectric films 2 and the multiple conductive films 3 and 4 are approximately uniform. The final layer backfilling the groove 8, i.e., the fifth conductive film 3 in the example of FIG. 1 , may be thicker than the other conductive films 3 and 4 and the dielectric film 2.

[0015] A "laminate structure" consisting of a plurality of dielectric films 2 and a plurality of conductive films 3, 4 is formed inside the groove 8, but is not formed on the first main surface 1A or the second main surface 1B of the substrate 1. In the first opening 8A and the second opening 8B of the groove 8, cross sections of each of the plurality of dielectric films 2 and the plurality of conductive films 3, 4 that make up the laminate structure are exposed.

[0016] The semiconductor capacitor 101 has a first electrode 6 electrically connected to the conductive film 4 of an even-numbered layer counting from the side surface 8S of the groove 8, and a second electrode 7 electrically connected to the conductive film 3 of an odd-numbered layer counting from the side surface 8S of the groove 8. The first electrode 6 is electrically connected to the conductive film 4 of the even-numbered layer near a first opening 8A of the groove 8 on the first main surface 1A side. The second electrode 7 is electrically connected to the conductive film 3 of the odd-numbered layer near a second opening 8B of the groove 8 on the second main surface 1B side.

[0017] The first electrode 6 is in contact with the cross section of the laminated structure exposed in the first opening 8A. In the first opening 8A, a first insulating film 5A is disposed between the odd-numbered conductive film 3 and the first electrode 6. In other words, in the cross section of the laminated structure exposed in the first opening 8A, a portion of the odd-numbered conductive film 3 is removed to form a recess, and the first insulating film 5A is buried in the recess. This first insulating film 5A electrically insulates the odd-numbered conductive film 3 from the first electrode 6. Therefore, in the first opening 8A, the first electrode 6 is electrically connected to the even-numbered conductive film 4 and electrically insulated from the odd-numbered conductive film 3.

[0018] The second electrode 7 is in contact with the cross section of the laminated structure exposed in the second opening 8B. In the second opening 8B, a second insulating film 5B is disposed between the even-numbered conductive film 4 and the second electrode 7. In other words, in the cross section of the laminated structure exposed in the second opening 8B, a portion of the even-numbered conductive film 4 is removed to form a recess, and the second insulating film 5B is filled in the recess. This second insulating film 5B electrically insulates the even-numbered conductive film 4 from the first electrode 6. Therefore, the second electrode 7 is electrically connected to the odd-numbered conductive film 3 and electrically insulated from the even-numbered conductive film 4 in the second opening 8B.

[0019] The semiconductor capacitor 101 has an interlayer insulating film 9 disposed on the first main surface 1A and the second main surface 1B of the substrate 1. An opening is formed in the interlayer insulating film 9 in a region where the groove 8 is formed, and a cross section of the laminated structure is exposed from the opening of the interlayer insulating film 9. The first electrode 6 and the second electrode 7 are disposed on the interlayer insulating film 9 and on the laminated structure exposed from the opening.

[0020] With the above-described configuration, the semiconductor capacitor 101 has a capacitor structure formed between the first conductive film 3 and the second conductive film 4 sandwiching the dielectric film 2. That is, the capacitor is formed between the first electrode 6 on the first main surface 1A side of the substrate 1 and the second electrode 7 on the second main surface 1B side of the substrate 1.

[0021] The basic operation of the semiconductor capacitor 101 will be described. A positive voltage relative to the second electrode 7 is applied to the first electrode 6, or a negative voltage relative to the first electrode 6 is applied to the second electrode 7. As a result, a positive charge is charged to the even-numbered conductive film 4 electrically connected to the first electrode 6, and a negative charge is charged to the odd-numbered conductive film 3 electrically connected to the second electrode 7. At this time, polarization occurs within the dielectric film 2, generating capacitance. A structure (capacitor structure) is formed in which capacitors made of multiple dielectric films 2 and multiple conductive films 3 and 4 alternately stacked on the side surface 8S of the groove 8 are connected in parallel. This significantly improves the capacitance density of the capacitor per unit area.

[0022] In the first embodiment, the odd-numbered conductive films 3 are made of a material having a higher etching rate with the first etching solution than the even-numbered conductive films 4. The even-numbered conductive films 4 are made of a material having a higher etching rate with the second etching solution than the odd-numbered conductive films 3. By using materials having such properties for the odd-numbered conductive films 3 and the even-numbered conductive films 4, the semiconductor capacitor 101 having the structure shown in FIG. 1 can be manufactured with a high yield. Specifically, without using photolithography, the first electrode 6 can be electrically connected to the even-numbered conductive film 4 in the first opening 8A and electrically insulated from the odd-numbered conductive film 3. Similarly, without using photolithography, the second electrode 7 can be electrically connected to the odd-numbered conductive film 3 in the second opening 8B and electrically insulated from the even-numbered conductive film 4. Therefore, the dielectric films 2 and the conductive films 3 and 4 can be made thinner, further improving the capacitor capacitance density per unit area.

[0023] Examples of specific materials having the above-mentioned properties are as follows: The odd-numbered conductive films 3 are made of polycrystalline silicon. Specifically, the odd-numbered conductive films 3 are made of conductive polycrystalline silicon doped with a high concentration of n-type impurities, but may also be made of conductive polycrystalline silicon doped with a high concentration of p-type impurities. The even-numbered conductive films 4 are made of titanium nitride (TiN). The first etching solution is potassium hydroxide solution (KOH) or tetramethylammonium hydroxide (TMAH). The second etching solution is ammonia hydrogen peroxide solution, which is a mixture of ammonia and hydrogen peroxide.

[0024] In the first embodiment, the substrate 1 is made of aluminum oxide (Al ２ O ３ The substrate 1 may be a single crystal sapphire substrate. The dielectric film 2 is made of silicon nitride (Si ３ N ４ The first electrode 6 and the second electrode 7 are made of aluminum (Al), but may be made of other metals, such as a single layer film or a laminate film of two or more metals selected from the group consisting of Al, titanium (Ti), nickel (Ni), molybdenum (Mo), tungsten (W), silver (Ag), and copper (Cu).

[0025] [Manufacturing Method of Semiconductor Capacitor 101] Next, an example of a manufacturing method of the semiconductor capacitor 101 of FIG. 1 will be described with reference to FIGS.

[0026] 2, first, a groove 8 is formed in the substrate 1 so as to penetrate between the first main surface 1A and the second main surface 1B. The groove 8 can be formed, for example, by using tetrafluoromethane (CF ４ ) or sulfur hexafluoride (SF ６ By using reactive ion etching (RIE) using an etching gas such as SiO 2 , a pattern of fine grooves 8 can be formed. Alternatively, ion beam etching, in which a high-energy ion beam is irradiated to physically remove the alumina surface, or laser ablation, in which a high-power laser is used to locally heat the alumina and remove part of the substrate 1, may be used.

[0027] 2, a plurality of dielectric films 2 and a plurality of conductive films 3 and 4 are alternately laminated on the first main surface 1A, the second main surface 1B, and the side surface 8S of the groove of the substrate 1. Specifically, silicon nitride (Si ３ N ４ 2, the fifth layer of conductive film 3 fills up the inside of trench 8.

[0028] The silicon nitride (dielectric film 2) can be deposited by atomic layer deposition (ALD) or thermal CVD. When using atomic layer deposition (ALD) or thermal CVD, the dielectric film 2 can be deposited with good coverage even when the trench 8 is deep by reducing the pressure.

[0029] The deposition method of polycrystalline silicon (the odd-numbered conductive film 3) can be a chemical vapor deposition (CVD) method such as low-pressure CVD (LPCVD) or plasma-enhanced CVD (PECVD), or a sputtering method. LPCVD allows for uniform control of the film thickness and high-quality crystallinity. On the other hand, sputtering allows for film formation at low temperatures. Atomic layer deposition (ALD) can also be used. The deposition method can be performed using trichlorosilane (SiHCl). ３ ), dichlorosilane (SiH ２ Cl ２ ), or tetrachlorosilane (SiCl ４ ), and silane (SiH ４ ) and hydrogen (H ２ The ALD method alternately introduces reducing agents such as SiO 2 and SiO 2 to deposit silicon atoms, followed by a high-temperature annealing process. The ALD method allows for extremely precise control of film thickness. Therefore, a thin conductive film 3 with high film thickness uniformity can be deposited even inside a trench 8 with a high aspect ratio.

[0030] The deposition method of titanium nitride (odd-numbered conductive film 4) can be a chemical vapor deposition (CVD) method such as LPCVD or PECVD, or a sputtering method. Sputtering can achieve a uniform film thickness and high film adhesion. Atomic layer deposition (ALD) can also be used. In ALD, a titanium precursor and a nitrogen source are alternately introduced and reacted atomic layer by atomic layer to form TiN. The ALD method allows for very precise film thickness control. Therefore, a thin conductive film 4 with high film thickness uniformity can be deposited even inside a trench 8 with a high aspect ratio.

[0031] As shown in FIG. 3 , the plurality of dielectric films 2 and the plurality of conductive films 3 and 4 stacked on the first main surface 1A are removed. Chemical mechanical polishing (CMP) can be used as the removal method. Similarly, the plurality of dielectric films 2 and the plurality of conductive films 3 and 4 stacked on the second main surface 1B are removed. The CMP process ends when the first main surface 1A and the second main surface 1B of the substrate 1 are exposed. This polishing process flattens the first main surface 1A and the second main surface 1B of the substrate 1, and the cross sections of the plurality of dielectric films 2 and the plurality of conductive films 3 and 4 constituting the above-described stacked structure are exposed in the first opening 8A and the second opening 8B of the groove 8, respectively.

[0032] As shown in FIG. 4 , first, a resist 17 is formed on the second main surface 1B and the second opening 8B as an etching mask. The resist 17 can be a photoresist material. Then, a first etching solution is used to selectively etch a portion of the odd-numbered conductive film 3 exposed in the first opening 8A of the groove 8. The odd-numbered conductive film 3 is made of a material that has a higher etching rate with the first etching solution than the even-numbered conductive film 4. Therefore, the odd-numbered conductive film 3 exposed in the first opening 8A is etched by the first etching solution, but the even-numbered conductive film 4 is not etched. Therefore, the odd-numbered conductive film 3 exposed in the first opening 8A can be selectively etched without masking the even-numbered conductive film 4 exposed in the first opening 8A. Furthermore, because the resist 17 is formed in the second opening 8B, the odd-numbered conductive film 3 exposed in the second opening 8B is not etched by the first etching solution. The etching process is continued until a first recess 3A is formed in the odd-numbered conductive film 3 in the first opening 8A of the trench 8. The depth of the first recess 3A need only be deep enough to bury the first insulating film 5A (described later). The resist 17 is then removed. In this manner, by using the etching characteristics of the first etching solution described above, the odd-numbered conductive film 3 exposed in the first opening 8A can be selectively etched to form the first recess 3A without using photolithography. Therefore, even if the dielectric film 2 and the conductive films 3 and 4 are thinned, it is possible to avoid accidentally etching the even-numbered conductive film 4 adjacent to the odd-numbered conductive film 3.

[0033] As shown in FIG. 5 , first, a resist 18 is formed on the first main surface 1A and the first opening 8A as an etching mask. The resist 18 can be a photoresist material. Then, a second etching solution is used to selectively etch a portion of the even-numbered conductive film 4 exposed in the second opening 8B of the groove 8. The even-numbered conductive film 4 is made of a material that has a higher etching rate with the second etching solution than the odd-numbered conductive film 3. Therefore, the even-numbered conductive film 4 exposed in the second opening 8B is etched by the second etching solution, but the odd-numbered conductive film 3 is not etched. Therefore, the odd-numbered and even-numbered conductive film 4 exposed in the second opening 8B can be selectively etched without masking the odd-numbered conductive film 3 exposed in the second opening 8B. Furthermore, because the resist 18 is formed in the first opening 8A, the even-numbered conductive film 4 exposed in the first opening 8A is not etched by the second etching solution. The etching process is continued until a second recess 4A is formed in the even-numbered conductive film 4 in the second opening 8B of the trench 8. The depth of the second recess 4A is sufficient to allow the second insulating film 5B, which will be described later, to be embedded therein. The resist 18 is then removed. By using the etching characteristics of the second etching solution described above, the even-numbered conductive film 4 exposed in the second opening 8B can be selectively etched to form the second recess 4A without using photolithography. Therefore, even if the dielectric film 2 and the conductive films 3 and 4 are thinned, it is possible to avoid accidentally etching the odd-numbered conductive film 3 adjacent to the even-numbered conductive film 4.

[0034] As shown in FIG. 6, a silicon oxide film (SiO ２ At this time, SiO ２ A portion of the film 15 is embedded in the first recess 3A and the second recess 4A.

[0035] An etching mask having an opening above the first opening 8A is formed by photolithography. Using the etching mask, SiO ２The etching process is completed when the even-numbered conductive film 4 is exposed in the first opening 8A. ２ The SiO film 15 is left in the first recess 3A. ２ The film 15 corresponds to the first insulating film 5A shown in FIG.

[0036] Similarly, an etching mask having an opening above the second opening 8B is formed by photolithography, and a SiO ２ The etching process is completed when the odd-numbered conductive film 3 is exposed in the second opening 8B. ２ The film 15 is left behind. ２ The film 15 corresponds to the second insulating film 5B shown in FIG. ２ The film 15 corresponds to the interlayer insulating film 9 in FIG.

[0037] 1, electrode films are formed on the first main surface 1A and the second main surface 1B and patterned to form a first electrode 6 and a second electrode 7. The first electrode 6 is electrically connected to the even-numbered conductive film 4 exposed from the first opening 8A. The first electrode 6 is electrically connected to the SiO ２ The film 15 (first insulating film 5A) electrically insulates the conductive film 3 from odd-numbered layers.

[0038] The second electrode 7 is electrically connected to the odd-numbered conductive film 3 exposed from the second opening 8B. ２ The film 15 (second insulating film 5B) electrically insulates the even-numbered conductive film 4.

[0039] Through these steps, the structure of the semiconductor capacitor 101 shown in FIG. 1 is realized.

[0040] According to the first embodiment, the following advantageous effects can be obtained.

[0041] The odd-numbered conductive films 3 are made of a material that has a higher etching rate with the first etching solution than the even-numbered conductive films 4. The even-numbered conductive films 4 are made of a material that has a higher etching rate with the second etching solution than the odd-numbered conductive films 3. This makes it possible to form the concave shapes of the conductive films 3 and 4 by utilizing the difference in etching rate between the conductive films 3 and 4 with each etching solution without using photolithography. Therefore, the capacitance density of the capacitor per unit area can be increased without thickening the dielectric film 2 and the conductive films 3 and 4.

[0042] By selecting the materials of the odd-numbered conductive films 3 and the even-numbered conductive films 4 as described above, it is possible to form a first electrode 6 electrically connected to the even-numbered conductive films 4 and electrically insulated from the odd-numbered conductive films 3 in the vicinity of the first opening 8A of the groove 8 on the first main surface 1A side. It is possible to form a second electrode 7 electrically connected to the odd-numbered conductive films 3 and electrically insulated from the even-numbered conductive films 4 in the vicinity of the second opening of the groove on the second main surface 1B side.

[0043] The first insulating film 5A is disposed between the odd-numbered conductive film 3 and the first electrode 6 in the first opening 8A. Therefore, the first electrode 6 can be electrically insulated from the odd-numbered conductive film 3 in the vicinity of the first opening 8A of the groove 8 on the first main surface 1A side. The second insulating film 5B is disposed between the even-numbered conductive film 4 and the second electrode 7 in the second opening 8B. Therefore, the second electrode 7 can be electrically insulated from the even-numbered conductive film 4 in the vicinity of the second opening 8B of the groove 8 on the second main surface 1B side.

[0044] The odd-numbered conductive film 3 is made of polycrystalline silicon, and the even-numbered conductive film 4 is made of titanium nitride (TiN). The first etching solution is potassium hydroxide solution (KOH) or tetramethylammonium hydroxide (TMAH), and the second etching solution is a mixture of ammonia and hydrogen peroxide, i.e., ammonia hydrogen peroxide. Polycrystalline silicon is etched with KOH or TMAH but not with ammonia hydrogen peroxide. TiN is not etched with KOH or TMAH but is etched with ammonia hydrogen peroxide. This allows selective formation of recesses 3A and 4A in the odd-numbered conductive film 3 and the even-numbered conductive film 4, respectively, without using photolithography. This eliminates the need to thicken the dielectric film 2 and the conductive films 3 and 4, thereby increasing the capacitance density of the capacitor per unit area.

[0045] The plurality of dielectric films 2 are made of a material that has a lower etching rate with respect to the first etching liquid than the odd-numbered conductive films 3 and a lower etching rate with respect to the second etching liquid than the even-numbered conductive films 4. This makes it difficult for the dielectric film 2 to be etched simultaneously with the conductive films 3 and 4 by the first etching liquid and the second etching liquid. This makes it possible to suppress short-circuit defects in which adjacent odd-numbered conductive films 3 and even-numbered conductive films 4 are short-circuited. In other words, electrical insulation performance is improved, and high reliability can be achieved.

[0046] The dielectric films 2 are made of silicon nitride. Silicon nitride is not etched by KOH, TMAH, or ammonia hydrogen peroxide. Therefore, the dielectric films 2 are unlikely to be etched simultaneously with the conductive films 3 and 4 by the first and second etching solutions.

[0047] If the substrate 1 is etched simultaneously with the conductive films 3 and 4, the substrate 1 becomes thinner, which reduces the depth of the grooves 8 and reduces the capacitance density of the capacitor. Therefore, the substrate 1 is made of a material that has a lower etching rate with the first etching liquid than the odd-numbered conductive films 3 and a lower etching rate with the second etching liquid than the even-numbered conductive films 4. Since the substrate 1 is less likely to be etched simultaneously with the conductive films 3 and 4, it is possible to suppress a decrease in the capacitance density of the capacitor per unit area.

[0048] The substrate 1 is made of aluminum oxide. Aluminum oxide is not etched by KOH, TMAH, or ammonia hydrogen peroxide. Therefore, the substrate 1 is unlikely to be etched simultaneously with the conductive films 3 and 4 by the first etching solution and the second etching solution.

[0049] Second Embodiment In the second embodiment, a semiconductor capacitor 102 will be described in which the dielectric film 2 and the substrate 1 are etched by a first etching solution simultaneously with the odd-numbered conductive film 3. The dielectric film 2 and the substrate 1 are each made of a material having an etching rate with respect to the first etching solution that is equal to or higher than that of the odd-numbered conductive film 3.

[0050] The difference from the first embodiment is that the substrate 1 is made of silicon (Si) and the dielectric film 2 is made of silicon oxide (SiO ２ ) and the first etching solution is KOH. Silicon and silicon oxide are etched by KOH. The substrate 1 may be a single crystal silicon substrate or a polycrystalline silicon substrate. By adding a high concentration of n-type or p-type impurities, the substrate 1 can function as a capacitor electrode.

[0051] 4, not only the odd-numbered conductive films 3 but also the dielectric films 2 on the first main surface 1A side and the substrate 1 are simultaneously etched by the first etching solution. Therefore, as shown in Fig. 7, the ends of the even-numbered conductive films 4 on the first main surface 1A side form convex portions that protrude from the first main surface 1A of the substrate 1 and the ends of the dielectric films 2. Thereafter, in the step shown in Fig. 6, SiO ２The film 15 is formed. ２ The film 15 corresponds to the interlayer insulating film 9 on the first main surface 1A side in FIG. 7. The interlayer insulating film 9 is embedded around the convex portions of the even-numbered conductive films 4. The interlayer insulating film 9 is not patterned, and the first electrode 6 is formed on the interlayer insulating film 9. The first electrode 6 is electrically connected to the convex portions of the even-numbered conductive films 4, and is electrically insulated from the odd-numbered conductive films 3 by the interlayer insulating film 9. SiO ２ After forming the film 15, SiO ２ A part of the film 15, that is, the part that will become the second opening 8B, is removed by a technique such as CMP (Chemical Mechanical Polishing) to form the interlayer insulating film 9 as shown in FIG.

[0052] When the interlayer insulating film 9 is patterned using photolithography, if the photolithography is not accurate, the first-layer dielectric film 2 in contact with the side surface 8S of the trench 8 is etched simultaneously with the interlayer insulating film 9. If the substrate 1 is a conductive substrate, a capacitor is also formed between the substrate 1 and the first-layer conductive film 3. If the first-layer dielectric film 2 is etched, a short circuit may occur between the first-layer conductive film 3 and the substrate 1.

[0053] According to the second embodiment, the interlayer insulating film 9 on the first main surface 1A side is not patterned, and therefore the first-layer dielectric film 2 is not etched simultaneously with the interlayer insulating film 9. Therefore, a short circuit between the first-layer conductive film 3 and the substrate 1 can be avoided.

[0054] The configuration of the semiconductor capacitor 102 on the second main surface 1B side is the same as that of the semiconductor capacitor 101, and a repeated description thereof will be omitted.

[0055] Third Embodiment In the third embodiment, a semiconductor capacitor 103 will be described in which the substrate 1 is etched by a first etching solution simultaneously with the odd-numbered conductive film 3. The substrate 1 is made of a material whose etching rate with respect to the first etching solution is equal to or higher than that of the odd-numbered conductive film 3.

[0056] The difference from the first embodiment is that the substrate 1 is made of silicon (Si), which is etched with KOH and TMAH.

[0057] 4, not only the odd-numbered conductive films 3 but also the substrate 1 on the first main surface 1A side are simultaneously etched by the first etching solution. Therefore, as shown in Fig. 8, a part of the stacked structure consisting of the plurality of dielectric films 2 and the plurality of conductive films 3 and 4 protrudes outside the groove 8 beyond the first main surface 1A of the substrate 1. Therefore, even if the first-layer dielectric film 2 and the interlayer insulating film 9 are etched simultaneously during patterning of the interlayer insulating film 9, the first main surface 1A of the substrate 1 is positioned lower than the stacked structure, making it difficult for the first-layer conductive film 3 and the substrate 1 to short-circuit.

[0058] The configuration of the semiconductor capacitor 102 on the second main surface 1B side is the same as that of the semiconductor capacitor 101, and a repeated description thereof will be omitted.

[0059] Fourth Embodiment In the fourth embodiment, a semiconductor capacitor 104 will be described in which the dielectric film 2 is etched by the first etching solution simultaneously with the odd-numbered conductive film 3. The dielectric film 2 is made of a material whose etching rate with respect to the first etching solution is equal to or higher than that of the odd-numbered conductive film 3.

[0060] The difference from the first embodiment is that the dielectric film 2 is made of silicon oxide (SiO ２ ) and the first etching solution is KOH. Silicon and silicon oxide are etched by KOH.

[0061] 4, not only the odd-numbered conductive films 3 but also the dielectric films 2 on the first main surface 1A side are simultaneously etched by the first etching solution. Therefore, as shown in Fig. 9, the ends of the even-numbered conductive films 4 on the first main surface 1A side form convex portions that protrude from the ends of the dielectric films 2. Thereafter, in the step shown in Fig. 6, SiO ２ The film 15 is formed. ２ 9. The interlayer insulating film 9 is embedded around the convex portion of the even-numbered conductive film 4. Then, the SiO 3 film located in the first opening 8A is removed by a process such as CMP so that the end of the even-numbered conductive film 4 is exposed. ２The film 15 is removed to form an interlayer insulating film 9. The interlayer insulating film 9 is not patterned, and a first electrode 6 is formed on the interlayer insulating film 9. The first electrode 6 is electrically connected to the convex portion of the even-numbered conductive film 4, and is electrically insulated from the odd-numbered conductive film 3 by the interlayer insulating film 9.

[0062] According to the fourth embodiment, as in the second embodiment, the interlayer insulating film 9 is not patterned, and therefore the first-layer dielectric film 2 is not etched simultaneously with the interlayer insulating film 9. Therefore, a short circuit between the first-layer conductive film 3 and the substrate 1 can be avoided.

[0063] The configuration of the semiconductor capacitor 104 on the second main surface 1B side is the same as that of the semiconductor capacitor 101, and a repeated description thereof will be omitted.

[0064] Fifth Embodiment In the fifth embodiment, a semiconductor capacitor 105 will be described in which a first-layer dielectric film 2 and a first-layer conductive film 3 are disposed on a second main surface 1B. It should be noted that the first main surface 1A and the second main surface 1B in FIGS. 10 to 14 related to the fifth embodiment are reversed from those in FIGS. 1 to 9. Furthermore, compared to the first to fourth embodiments, the materials of the odd-layer conductive films 3 and the even-layer conductive films 4, and the first and second etching solutions are interchanged. That is, in the fifth embodiment, the odd-layer conductive films 3 are made of titanium nitride (TiN), and the even-layer conductive films 4 are made of polycrystalline silicon. The first etching solution is ammonia hydrogen peroxide, and the second etching solution is KOH or TMAH.

[0065] The structure of the semiconductor capacitor 105 will be described with reference to Figure 10. The first-layer dielectric film 2 in contact with the side surface 8S of the trench 8 and the first-layer conductive film 3 counting from the side surface 8S of the trench 8 are disposed not only inside the trench 8 but also on the second main surface 1B. The interlayer insulating film 9 is disposed on the second main surface 1B via the first-layer dielectric film 2 and the first-layer conductive film 3. The substrate 1 is made of silicon. The other configuration is the same as that of the semiconductor capacitor 101 shown in Figure 1, and a repeated description will be omitted.

[0066] 11 to 14, an example of a method for manufacturing the semiconductor capacitor 105 of Fig. 10 will be described. Note that for steps that are the same as or similar to the method for manufacturing the semiconductor capacitor 101, the description of the first embodiment will be cited as appropriate.

[0067] First, as described with reference to FIG. 2, a groove 8 is formed in a substrate 1 made of silicon, and a plurality of dielectric films 2 and a plurality of conductive films 3 and 4 are alternately stacked on the first main surface 1A and the second main surface 1B of the substrate 1 and the side surface 8S of the groove 8.

[0068] 3, the plurality of dielectric films 2 and the plurality of conductive films 3 and 4 stacked on the first main surface 1A and the second main surface 1B are removed by CMP. However, as shown in FIG. 11, the first-layer dielectric film 2 and the first-layer conductive film 3 deposited on the second main surface 1B are left unremoved. In other words, the CMP process is completed when the first-layer conductive film 3 is exposed on the second main surface 1B.

[0069] Next, as shown in FIG. 12 , a resist 18 is formed on the first main surface 1A and the first opening 8A as an etching mask. Then, a second etching solution is used to selectively etch a portion of the even-numbered conductive film 4 exposed in the second opening 8B of the trench 8. The second etching solution etches the even-numbered conductive film 4 exposed in the second opening 8B, but not the odd-numbered conductive film 3. Therefore, the even-numbered conductive film 4 exposed in the second opening 8B can be selectively etched without masking the odd-numbered conductive film 3 exposed in the second opening 8B. Furthermore, because the resist 18 is formed in the first opening 8A, the even-numbered conductive film 4 exposed in the first opening 8A is not etched by the second etching solution. A second recess 4A is formed in the even-numbered conductive film 4 at the second opening 8B of the trench 8. At this time, since the first-layer dielectric film 2 and the first-layer conductive film 3 remain on the second main surface 1B, the substrate 1 made of silicon is not etched by the second etching solution. Thereafter, the resist 18 is removed.

[0070] Next, as shown in FIG. 13 , a resist 17 is formed on the second main surface 1B and the second opening 8B as an etching mask. Then, a first etching solution is used to selectively etch a portion of the odd-numbered conductive film 3 exposed in the first opening 8A of the trench 8. The first etching solution etches the odd-numbered conductive film 3 exposed in the first opening 8A, but not the even-numbered conductive film 4. Therefore, the odd-numbered conductive film 3 exposed in the first opening 8A can be selectively etched without masking the even-numbered conductive film 4 exposed in the first opening 8A. A first recess 3A is formed in the odd-numbered conductive film 3 in the first opening 8A of the trench 8. Then, the resist 17 is removed.

[0071] Next, as shown in FIG. 14, a silicon oxide film (SiO ２ At this time, SiO ２ A portion of the film 15 is embedded in the first recess 3A and the second recess 4A.

[0072] Thereafter, in the same manner as in the first embodiment, SiO ２ The film 15 is patterned to form an interlayer insulating film 9, and then a first electrode 6 and a second electrode 7. Through these steps, the structure of the semiconductor capacitor 105 shown in FIG.

[0073] Since the first-layer dielectric film 2 and the first-layer conductive film 3 remain on the second main surface 1B, the silicon substrate 1 is not etched by the second etching solution. Therefore, even if silicon is used for the substrate 1, the substrate 1 is not etched and the depth of the grooves 8 can be maintained. This makes it possible to suppress a decrease in the capacitance density of the capacitor per unit area.

[0074] Since the first-layer conductive film 3 remains on the second main surface 1B, the first-layer dielectric film 2 is not etched simultaneously when the interlayer insulating film 9 is patterned, thereby preventing short-circuit defects between the first-layer conductive film 3 and the substrate 1.

[0075] Sixth Embodiment In the sixth embodiment, a semiconductor capacitor 106 will be described in which the thickness of the first-layer dielectric film 2 in contact with the side surface 8S of the groove 8 is formed thicker than the thickness of the second and subsequent dielectric films 2. The interlayer insulating film 9 is patterned using photolithography to form an opening. If the patterning accuracy is poor, the first-layer dielectric film 2 may be etched during the etching process to form the opening. If the first-layer dielectric film 2 is etched, the substrate 1 and the first-layer conductive film 3 will be short-circuited via the second electrode 7, the capacitor between the substrate 1 and the first-layer conductive film 3 will no longer function, and the capacitance density will decrease.

[0076] Therefore, by forming the first layer of dielectric film 2 thicker than the second and subsequent layers of dielectric film 2, the first layer of dielectric film 2 is less likely to be etched even if the patterning accuracy is poor, and electrical insulation between the substrate 1 and the first layer of conductive film 3 can be maintained.

[0077] Seventh Embodiment In a seventh embodiment, as shown in FIGS. 16A and 16B, a semiconductor capacitor 107 will be described in which the second opening 8B of the groove 8 on the second main surface 1B side has an arc shape.

[0078] The corners R1 of the second opening 8B of the trench 8 on the second main surface 1B side are rounded. The first-layer dielectric film 2 in contact with the side surface 8S of the trench 8 is deposited along the rounded corners R1. Therefore, the width b of the first-layer dielectric film 2 exposed in the second opening 8B can be made wider than the film thickness a of the first-layer dielectric film 2 (a<b). Therefore, even if the patterning accuracy of the interlayer insulating film 9 is poor, the first-layer dielectric film 2 is less likely to be etched, and electrical insulation between the substrate 1 and the first-layer conductive film 3 can be maintained.

[0079] In addition, wet processing (isotropic etching) or H ２ Corners R1 of second opening 8B can be rounded by sublimating silicon in substrate 1 through heat treatment in the ambient atmosphere. The corners of first opening 8A may also be rounded at the same time as second opening 8B.

[0080] Eighth Embodiment In an eighth embodiment, as shown in FIG. 17, a semiconductor capacitor 108 will be described in which both a first electrode 6 and a second electrode 7 are formed on the first main surface 1A side of the substrate.

[0081] In the semiconductor capacitor 108, the first electrode 6 is electrically connected to the even-numbered conductive film 4 near the first opening 8A of the groove 8 on the first main surface 1A side, and is electrically insulated from the odd-numbered conductive film 3. The second electrode 7 is electrically connected to the odd-numbered conductive film 3 near the third opening 8C of the groove 8 on the first main surface 1A side, and is electrically insulated from the even-numbered conductive film 4.

[0082] A first insulating film 5A is disposed between the first electrode 6 and the odd-numbered conductive film 3. A second insulating film 5B is disposed between the second electrode 7 and the even-numbered conductive film 4.

[0083] A stacked structure consisting of multiple dielectric films 2 and multiple conductive films 3 and 4 is formed on the second main surface 1B. In one example of a method for manufacturing a semiconductor capacitor 108, the CMP process described with reference to FIG. 3 is performed on the first main surface 1A side but not on the second main surface 1B side. In the etching process described with reference to FIG. 4, resist 17 is formed not only on the second main surface 1B but also in the third opening 8C in FIG. 17. This allows the odd-numbered conductive film 3 exposed through the third opening 8C to remain without being removed. In the etching process described with reference to FIG. 5, resist 18 is formed on the second main surface 1B and the first opening 8A in FIG. 17. This allows the even-numbered conductive film 4 exposed through the first opening 8A to remain without being removed.

[0084] (First Comparative Example) FIG. 18 is a cross-sectional view showing the configuration of a semiconductor capacitor 201 according to a first comparative example. A multilayer structure is formed in which multiple dielectric films 22 and multiple conductive films 23 and 24 are alternately stacked inside a groove 28 formed in a substrate and on the front and back surfaces of the substrate. In a region (contact region) on the substrate different from the region where the groove 28 is formed (the groove region), an electrode 26 connected to the odd-numbered conductive film 23 and an electrode 27 connected to the even-numbered conductive film 24 are formed. In the semiconductor capacitor 201, contact holes 30 must be formed in the contact region to embed the electrodes 26 and 27. This limits the area in which the groove 28 can be formed, making it difficult to increase the capacitance density of the capacitor. Furthermore, the need to form a contact hole 30 for each conductive film 23 and 24 increases the number of steps in the manufacturing process.

[0085] In contrast, in the semiconductor capacitors 101 to 108 according to the embodiments, the electrodes 6 and 7 can be connected to the conductive films 3 and 4 in the trench regions. This eliminates the need for the contact regions shown in FIG. 18, and increases the capacitance density of the capacitor per unit area. Furthermore, since the conductive films 3 and 4 are connected to the electrodes 6 and 7 at the openings 8A and 8B of the trench 8, parasitic resistance can also be reduced. This reduces the number of steps in the manufacturing process, thereby reducing manufacturing costs.

[0086] 19 is a cross-sectional view showing a manufacturing process of a semiconductor capacitor 202 according to a second comparative example. Specifically, an etching mask 37 having openings corresponding to the even-numbered conductive films 23 on the first main surface 21A of the substrate 21 and an etching mask 38 having openings corresponding to the odd-numbered conductive films 24 on the second main surface 21B of the substrate 21 are formed. Then, a portion of the even-numbered conductive films 23 on the first main surface 21A is etched using the etching mask 37 to form recesses 23A, and a portion of the odd-numbered conductive films 24 on the second main surface 21B is etched using the etching mask 38 to form recesses 24A. The even-numbered conductive films 23 and the odd-numbered conductive films 24 are made of the same material (e.g., polycrystalline silicon).

[0087] The etching masks 37 and 38 are formed using photolithography. Because photolithography has limitations on processing accuracy, it may be difficult to accurately form openings at the positions of the even-numbered conductive films 23 on the first main surface 21A side. If the openings in the etching masks 37 and 38 extend to adjacent conductive films, the even-numbered conductive films 23 and the odd-numbered conductive films 24 may be electrically connected. In particular, if the conductive films 23 and 24 are thinned to increase the capacitor capacitance, the above-mentioned short-circuit defect between the even-numbered conductive films 23 and the odd-numbered conductive films 24 is likely to occur.

[0088] In contrast, in the semiconductor capacitors 101-108 according to the embodiment, the odd-numbered conductive films 3 are made of a material having a higher etching rate with the first etching solution than the even-numbered conductive films 4. The even-numbered conductive films 4 are made of a material having a higher etching rate with the second etching solution than the odd-numbered conductive films 3. This allows the odd-numbered conductive films 3 exposed in the first opening 8A and the even-numbered conductive films 4 exposed in the second opening 8B to be selectively etched to form the first recess 3A and the second recess 4A, respectively, without using photolithography (see FIGS. 4 and 5). Therefore, even if the dielectric film 2 and the conductive films 3 and 4 are thinned, it is possible to avoid accidentally etching adjacent conductive films 3 and 4.

[0089] As described above, according to the embodiment, the manufacturing process of the capacitor can be simplified, resulting in cost reduction, and miniaturization can be achieved, thereby increasing capacitance density.

[0090] Although the embodiments of the present invention have been described above, the descriptions and drawings that form part of this disclosure should not be understood to limit the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0091] REFERENCE SIGNS LIST 1 Substrate 1A First main surface 1B Second main surface 2 Dielectric film 3 First conductive film 3A First recess 4 Second conductive film 4A Second recess 5A First insulating film 5B Second insulating film 6 First electrode 7 Second electrode 8 Groove 8A First opening 8B Second opening 8C Third opening 8S Side surface 9 Interlayer insulating film 15 Silicon oxide film (SiO ２ Film) 17, 18 Resist

Claims

a substrate having a first main surface, a second main surface facing in a direction opposite to the first main surface, and a groove penetrating between the first main surface and the second main surface; a plurality of dielectric films and a plurality of conductive films alternately stacked on the side surfaces of the groove; a first electrode electrically connected to the conductive film in an even-numbered layer counted from a side surface of the groove and electrically insulated from the conductive film in an odd-numbered layer counted from a side surface of the groove; a second electrode electrically connected to the odd-numbered conductive film and electrically insulated from the even-numbered conductive film, the odd-numbered conductive film is made of a material having a higher etching rate with respect to a first etching solution than the even-numbered conductive film; the even-numbered conductive films are made of a material having a higher etching rate with respect to a second etching solution than the odd-numbered conductive films; Semiconductor capacitor.

2. The semiconductor capacitor according to claim 1, the first electrode is electrically connected to the conductive film of the even-numbered layer in the vicinity of the first opening of the groove on the first main surface side, the second electrode is electrically connected to the odd-numbered conductive film in the vicinity of the second opening of the groove on the second main surface side; Semiconductor capacitor.

3. The semiconductor capacitor according to claim 2, a first insulating film disposed in the first opening between the odd-numbered conductive film and the first electrode; a second insulating film disposed in the second opening between the even-numbered conductive film and the second electrode; The semiconductor capacitor further comprises: 　 The semiconductor capacitor according to any one of claims 1 to 3, the odd-numbered conductive film is made of polycrystalline silicon, the even-numbered conductive film is made of titanium nitride, the first etching solution is a potassium hydroxide solution or tetramethylammonium; the second etching solution is an ammonia hydrogen peroxide mixture, which is a mixture of ammonia and hydrogen peroxide; Semiconductor capacitor. 　 The semiconductor capacitor according to any one of claims 1 to 4, the plurality of dielectric films are made of a material having a lower etching rate with respect to the first etching liquid than the odd-numbered conductive films and a lower etching rate with respect to the second etching liquid than the even-numbered conductive films; Semiconductor capacitor.

6. The semiconductor capacitor according to claim 5, the plurality of dielectric films are made of silicon nitride; the odd-numbered conductive film is made of polycrystalline silicon, the even-numbered conductive film is made of titanium nitride, the first etching solution is a potassium hydroxide solution or tetramethylammonium; the second etching solution is an ammonia hydrogen peroxide mixture, which is a mixture of ammonia and hydrogen peroxide; Semiconductor capacitor. 　 The semiconductor capacitor according to any one of claims 1 to 5, the substrate is made of a material having a lower etching rate with respect to the first etching liquid than the odd-numbered conductive film layers and a lower etching rate with respect to the second etching liquid than the even-numbered conductive film layers; Semiconductor capacitor.

8. The semiconductor capacitor according to claim 7, the odd-numbered conductive film is made of polycrystalline silicon, the even-numbered conductive film is made of titanium nitride, the first etching solution is a potassium hydroxide solution or tetramethylammonium; the second etching solution is an ammonia hydrogen peroxide mixture, which is a mixture of ammonia and hydrogen peroxide; The substrate is made of aluminum oxide. Semiconductor capacitor. 　 The semiconductor capacitor according to any one of claims 1 to 3, the substrate and the even-numbered conductive film have higher etching rates with respect to the second etching solution than the odd-numbered conductive film; a first layer of the conductive film, counted from a side surface of the groove, is disposed on the second main surface of the substrate; Semiconductor capacitor.

10. The semiconductor capacitor according to claim 9, the odd-numbered conductive film layers are made of titanium nitride, the even-numbered conductive film is made of polycrystalline silicon, the first etching solution is an ammonia hydrogen peroxide mixture, which is a mixture of ammonia and hydrogen peroxide; the second etching solution is a potassium hydroxide solution or tetramethylammonium; The substrate is made of silicon. Semiconductor capacitor. 　 The semiconductor capacitor according to any one of claims 1 to 8, a thickness of the first dielectric film in contact with the side surface of the groove is greater than a thickness of the second or subsequent dielectric films; Semiconductor capacitor. 　 The semiconductor capacitor according to any one of claims 1 to 8, The second opening of the groove on the second main surface side has an arc shape. Semiconductor capacitor.

2. The semiconductor capacitor according to claim 1, the first electrode is electrically connected to the even-numbered conductive film and electrically insulated from the odd-numbered conductive film in the vicinity of the first opening of the groove on the first main surface side; the second electrode is electrically connected to the odd-numbered conductive film and electrically insulated from the even-numbered conductive film in the vicinity of a third opening of the groove on the first main surface side; Semiconductor capacitor. 　 forming a groove penetrating between a first main surface and a second main surface facing in an opposite direction to the first main surface in a substrate; stacking a plurality of dielectric films and a plurality of conductive films alternately on the side surfaces of the groove; removing the plurality of dielectric films and the plurality of conductive films stacked on the first main surface and the second main surface; selectively etching a portion of the odd-numbered conductive film exposed at a first opening of the groove using a first etching solution having a higher etching rate for odd-numbered conductive films counted from a side surface of the groove than for even-numbered conductive films counted from a side surface of the groove; selectively etching a portion of the even-numbered conductive film exposed in a second opening of the groove using a second etching solution having a higher etching rate for the even-numbered conductive film than for the odd-numbered conductive film; forming an interlayer insulating film above the first and second main surfaces of the substrate and the first and second openings of the trench; removing the interlayer insulating film formed above the first opening and the second opening of the trench; forming a first electrode electrically connected to the even-numbered conductive film in the first opening of the groove; forming a second electrode electrically connected to the odd-numbered conductive film in the second opening of the groove; A method for manufacturing a semiconductor capacitor having the above structure.

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