Method for fabricating semiconductor device

Abstract

The present disclosure relates to a method for fabricating a semiconductor device, and the objective is to provide a method for fabricating a semiconductor device in which the reliability of a field effect transistor to be applied can be enhanced. A method for fabricating a semiconductor device according to the present disclosure comprises: a step for forming a laminate structure by sequentially epitaxially growing a p-type GaN sacrificial layer, a n-type or undoped GaN layer, an AlGaN layer, and a buffer layer on a n-type GaN substrate; a step for attaching a support substrate to the buffer layer of the laminate structure; and a step for immersing the laminate structure attached to the support substrate in an etchant, irradiating the laminate structure with light, and selectively etching the GaN sacrificial layer from the lateral surface of the laminate structure. The irradiation range over which to irradiating the laminated structure with light is set so that light does not strike a superficial layer of the lateral surface of the laminate structure.

Description

Semiconductor device manufacturing method

[0001] The present invention relates to a method for manufacturing a semiconductor device.

[0002] To realize high-speed, high-capacity wireless communications, a power amplifier that can operate in the millimeter band (30 GHz to 100 GHz) and generate high output power of 10 W or so is required. GaN materials are considered promising semiconductor materials that can realize such power amplifiers. Semiconductor materials with an N-polar AlGaN heteroepitaxial layer structure are particularly promising.

[0003] However, conventional techniques have had the problem that it is difficult to obtain a high-quality N-polarity GaN / AlGaN heteroepitaxial stacked structure. To solve this problem, Patent Document 1 discloses a technique in which a Ga-polarity GaN / AlGaN heteroepitaxial stacked structure is grown in the conventional manner, and only the necessary structure is separated and inverted.

[0004] Patent Application No. 2007-511360

[0005] In the above-mentioned technology, a sacrificial layer made of a different material is formed at the interface between the growth substrate and the structure to be grown. That is, the lattice constant of the sacrificial layer is different from that of the structure to be grown. As a result, there is a problem that many crystal defects occur on the surface of the grown structure that is separated due to lattice mismatch during epitaxial growth.

[0006] Furthermore, in the above-mentioned technology, physical or thermal damage is applied when separating the grown structure from the growth substrate, which results in a problem of reduced reliability on the separated surface of the grown structure.

[0007] To solve the above-mentioned problems, the present disclosure first forms a sacrificial layer made of the same material at the interface between the growth substrate and the structure to be grown. When separating the growth substrate from the structure to be grown, photoelectrochemical etching is used to selectively etch only the sacrificial layer. This avoids the occurrence of crystal defects and physical or thermal damage on the surface of the grown structure that is separated. As a result, the present disclosure aims to provide a method for manufacturing a semiconductor device that can improve the reliability of the field-effect transistor to which it is applied.

[0008] An aspect of the present disclosure is a method for manufacturing a semiconductor device, comprising the steps of epitaxially growing a p-type GaN sacrificial layer, an n-type or undoped GaN layer, an AlGaN layer, and a buffer layer in that order on an n-type GaN substrate to form a stacked structure; attaching a support substrate to the buffer layer of the stacked structure; and immersing the stacked structure attached to the support substrate in an etching solution and irradiating the stacked structure with light to selectively etch the GaN sacrificial layer from the side surfaces of the stacked structure, wherein the irradiation range for irradiating the stacked structure with light is set so that the light does not hit the surface layers of the side surfaces of the stacked structure.

[0009] According to aspects of the present disclosure, the reliability of applied field effect transistors can be improved by avoiding the occurrence of crystal defects and physical or thermal damage on the separated side of the grown structure.

[0010] 11 is a first diagram illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present disclosure. FIG. 12 is a diagram illustrating band edge energy of a heteroepitaxial stacked layer structure according to a first embodiment of the present disclosure. FIG. 13 is a second diagram illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present disclosure. FIG. 14 is a third diagram illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present disclosure. FIG. 15 is a fifth diagram illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present disclosure. FIG. 16 is a first diagram illustrating the movement of electrons and holes in an npn junction according to a first embodiment of the present disclosure. FIG. 17 is a diagram illustrating an energy band in the substrate of FIG. 7. FIG. 18 is a diagram illustrating an energy band in the GaN sacrificial layer of FIG. 7. FIG. 19 is a diagram illustrating an energy band in the GaN layer of FIG. 7. FIG. 19 is a second diagram illustrating the movement of electrons and holes in an npn junction according to a first embodiment of the present disclosure. FIG. 19 is a diagram illustrating an energy band in the substrate of FIG. 11. FIG. 19 is a diagram illustrating an energy band in the GaN sacrificial layer of FIG. 11. FIG. 19 is a diagram illustrating an energy band in the GaN layer of FIG. FIG. 20 is a diagram illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present disclosure. FIG. 21 is a diagram illustrating a manufacturing process of a semiconductor device according to a third embodiment of the present disclosure. FIG. 22 is an enlarged view showing a wafer edge of a semiconductor device according to a comparative example.

[0011] A semiconductor device and a method for manufacturing the semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0012] 1 is a first diagram illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present disclosure. The present disclosure relates to a semiconductor device having a heteroepitaxial stacked structure that is applied to, for example, an N-polarity GaN / AlGaN field effect transistor, and a manufacturing method thereof.

[0013] The semiconductor device 100 includes a substrate 1, which is a growth substrate. The substrate 1 has, for example, a Ga surface and an n-type impurity concentration of 1×10 １８ cm －３The substrate 1 may be a free-standing GaN substrate, or may be a substrate such as SiC or sapphire on which GaN is epitaxially grown to a sufficient thickness so as to reduce the dislocation density from the substrate.

[0014] A GaN sacrificial layer 2 is formed on the substrate 1. The GaN sacrificial layer 2 has a thickness of, for example, 500 nm and a p-type impurity concentration of 1×10 １８ cm －３ This is the sacrificial layer.

[0015] A GaN layer 3 is formed on the GaN sacrificial layer 2. The GaN layer 3 is, for example, an n-type or undoped GaN layer having a thickness of 500 nm. An AlGaN layer 4 is formed on the GaN layer 3. The AlGaN layer 4 is, for example, an undoped layer having a thickness of 10 nm and an Al composition ratio of 30%. A buffer layer 5 is formed on the AlGaN layer 4. The buffer layer 5 is, for example, a 500 nm thick buffer layer made of semi-insulating GaN or AlGaN.

[0016] The GaN sacrificial layer 2, GaN layer 3, AlGaN layer 4, and buffer layer 5 are epitaxially grown in sequence on the substrate 1 by, for example, MOCVD. This epitaxial growth results in a GaN / AlGaN heteroepitaxial stacked structure. Hereinafter, this structure will be simply referred to as a heteroepitaxial stacked structure.

[0017] 2 is a diagram illustrating the band edge energy of the heteroepitaxial stacked structure according to the first embodiment of the present disclosure. As shown in FIG. 2, a two-dimensional gas 50 is formed at the boundary between the GaN layer 3 and the AlGaN layer 4. Furthermore, a built-in potential similar to that of an npn junction is formed by the two-dimensional gas 50, the p-type GaN sacrificial layer 2, and the n-type substrate 1.

[0018] 3 is a second diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. In this example, a support substrate 6 is attached onto the buffer layer 5. The support substrate 6 is attached by applying, for example, a UV-curable resin as an adhesive. The material of the support substrate 6 may be, for example, a semi-insulating semiconductor such as SiC, Si, sapphire, or diamond, or may be a resin film or metal.

[0019] 4 is a third diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. Here, the semiconductor device 100 is first immersed in a container filled with an etching solution 7. The etching solution is, for example, KOH containing peroxodisulfate ions (S ２ O ８ ２－ ) is added to the liquid. Next, the container is irradiated with light 8 having a wavelength of 365 nm or less. The light 8 is, for example, UV light. The irradiation range of the light 8 is set to a range that does not hit the surface of the edge of the heteroepitaxial stacked structure. The irradiation range of the light 8 can be controlled by using, for example, an iris diaphragm mechanism.

[0020] In this way, by irradiating the semiconductor device 100 with light while avoiding the surface at the edge of the wafer, it is possible to selectively etch only the GaN sacrificial layer 2. Details of the etching will be described later.

[0021] Although the embodiment in which the light 8 is irradiated from the substrate 1 side has been shown, if the support substrate 6 is made of a light-transmitting material, the light 8 may be irradiated from the support substrate 6 side. An example of the light-transmitting material is quartz glass.

[0022] 5 is a fourth diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. As described above, the semiconductor device 100 is in a state in which only the GaN sacrificial layer 2 has been etched. More specifically, the GaN sacrificial layer 2 is selectively etched except for the transition region formed between the GaN sacrificial layer 2 and the substrate 1 and the transition region formed between the GaN sacrificial layer 2 and the GaN layer 3. As a result, the heteroepitaxial stacked structure attached to the support substrate 6 is separated from the substrate 1.

[0023] 6 is a fifth diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. A semiconductor element is formed on the surface on the GaN layer 3 side. Here, a drain electrode 9 and a source electrode 10 are formed by, for example, a vacuum deposition method. The drain electrode 9 and the source electrode 10 are further subjected to a heat treatment to become ohmic electrodes.

[0024] Furthermore, a gate electrode 11 is formed on the surface of the GaN layer 3 by, for example, vacuum deposition. At this time, the GaN layer 3 in the portion where the gate electrode 11 is to be formed may be etched to a thickness that provides good pinch-off characteristics. Furthermore, if the desired gate leakage current cannot be achieved with the GaN layer 3 alone, an insulating film may be formed on the surface of the GaN layer 3 before forming the gate electrode 11. The insulating film may be formed by, for example, chemical vapor deposition.

[0025] Before describing the effects of this embodiment, we will describe the problems associated with a semiconductor device and a method for manufacturing the semiconductor device according to a comparative example. Technologies related to Beyond 5G / 6G are being considered to realize high-speed, high-capacity wireless communications in the future. For use in these base stations, there is a demand for a power amplifier that can operate in the millimeter band from 30 GHz to 100 GHz and obtain a high output power of 10 W or so.

[0026] GaN materials are considered promising semiconductor materials for realizing the power amplifiers described above. GaN materials have a high electron saturation velocity, a high electric field strength at which impact ionization occurs, and strong piezoelectricity and spontaneous polarization. Therefore, when GaN materials are used, for example, in a GaN / AlGaN heterostructure, a high concentration of two-dimensional gas can be induced at the interface. As a result, operation at high currents and high breakdown voltages can be expected.

[0027] However, conventional field-effect transistors using a Ga-polar GaN / AlGaN heteroepitaxial stack structure have had the challenge of achieving both higher frequencies and higher power output. To achieve both higher frequencies and higher power output, it is necessary to shorten the gate length and thin the gate barrier layer based on scaling laws. However, in conventional Ga-polar GaN / AlGaN heteroepitaxial stack structures, the AlGaN layer that induces two-dimensional electron gas also serves as the gate barrier layer. In other words, it is not possible to thin the AlGaN layer while maintaining the two-dimensional electron gas concentration required for high power output.

[0028] As a method for solving the above-mentioned problems, a technology of applying an N-polarity GaN / AlGaN heteroepitaxial stacked structure to a field-effect transistor is known. The N-polarity GaN / AlGaN heteroepitaxial stacked structure is a structure obtained by inverting a Ga-polarity GaN / AlGaN heteroepitaxial stacked structure. In the N-polarity AlGaN heteroepitaxial stacked structure, the AlGaN layer that induces two-dimensional electron gas is located on the opposite side of the gate electrode from the two-dimensional electron gas. Therefore, it is possible to shorten the gate length and thin the gate barrier layer based on the scaling law without thinning the AlGaN layer.

[0029] The N-polarity GaN / AlGaN heteroepitaxial stack structure described above can be obtained by epitaxially growing appropriate layers in sequence on the C-face of a SiC substrate, for example. However, epitaxial growth of GaN with N-polarity poses the problem of prone to abnormal growth called hillocks.

[0030] One known method for reducing the density of hillocks is to create a large off-axis angle on the SiC substrate. However, this technique tends to create steps in the crystal, which causes anisotropy in the mobility and results in non-uniform field-effect transistor characteristics. Therefore, it is not desirable to apply this technique to field-effect transistors.

[0031] Another problem is that it is difficult to achieve a high-resistance buffer layer because oxygen, which acts as an n-type dopant, is easily incorporated as an impurity during epitaxial growth. One known method for solving this problem is to intentionally add impurities such as iron.

[0032] However, the doping impurities act as carrier traps, which can cause instability in electrical characteristics, such as drain lag in field-effect transistors, making this technique unsuitable for use in field-effect transistors.

[0033] As described above, conventional techniques have had the problem of difficulty in obtaining a high-quality N-polar GaN / AlGaN heteroepitaxial stacked structure. As a method for solving this problem, a technique has been proposed in which a Ga-polar GaN / AlGaN heteroepitaxial stacked structure is grown in the conventional manner, and only the necessary structure is separated and inverted.

[0034] A specific example is shown below. First, graphene is formed by heat-treating the surface of a growth substrate at high temperature. Next, a Ga-polar GaN / AlGaN heteroepitaxial stacked structure is grown on the graphene. Next, an appropriate support substrate is attached to the grown structure. Next, a force is applied horizontally to the interface to separate the growth substrate from the grown structure. By inverting this separated structure upside down, an N-polar GaN / AlGaN heteroepitaxial stacked structure can be obtained.

[0035] Another method for separating the growth substrate from the grown structure is to provide a sacrificial layer with a different bandgap at the interface between the growth substrate and the grown structure, which can be selectively removed by, for example, photoelectrochemical etching or laser ablation.

[0036] However, in the above-mentioned technology, a sacrificial layer made of a different material is formed at the interface between the growth substrate and the structure to be grown. That is, the lattice constant of the sacrificial layer is different from that of the structure to be grown. As a result, there is a problem that many crystal defects occur on the surface of the grown structure that is separated due to lattice mismatch during epitaxial growth.

[0037] Furthermore, in the above-mentioned technology, physical or thermal damage is applied when separating the grown structure from the growth substrate, which results in a problem of reduced reliability on the separated surface of the grown structure.

[0038] One possible method for avoiding the occurrence of the above-mentioned crystal defects and damage is to remove a thin sacrificial layer grown on a growth substrate using a method that does not cause physical or thermal damage. This method involves thinning the sacrificial layer to pseudo-match the lattice constants of the growth substrate and the sacrificial layer, which are made of materials with different lattice constants. Examples of methods that do not cause physical or thermal damage include wet etching and photoelectrochemical etching.

[0039] However, the thickness at which the lattice constant can be pseudo-matched varies depending on the degree of lattice mismatch, but is only a few tens to a few nanometers. In other words, because the sacrificial layer described above can only be made to that thickness, it is not possible to etch the sacrificial layer in the horizontal direction at a practical speed, making practical application difficult. The present disclosure solves this problem.

[0040] To explain the effects of this embodiment, the selective etching of the GaN sacrificial layer 2 will be described in detail. First, the mechanism of GaN etching by photoelectrochemical etching will be described.

[0041] First, GaN is irradiated with light 8. Light 8, which has a wavelength of 365 nm or less, has energy higher than the band gap of GaN, and thus generates electron-hole pairs in the GaN. The generated electron-hole pairs also change the Fermi level of the GaN.

[0042] In particular, when GaN is immersed in an electrolyte and irradiated with light 8, as in this embodiment, the potential barrier at the interface between the GaN and the electrolyte is reduced, and carriers are supplied to the electrolyte. Of the supplied carriers, holes react with GaN to become Ga ions. This reaction is expressed by the following formula:

[0043]

[0044] The Ga ions react with the oxidizing species present in the electrolyte to form Ga ２ O ３ The oxidizing species is, for example, H2O or O2. This reaction is shown in the following formula:

[0045]

[0046] This Ga ２ O ３ Since GaN dissolves in acid or alkali, etching of GaN progresses. That is, when holes are supplied to GaN, etching progresses in that region.

[0047] On the other hand, among the supplied carriers, electrons react with water to form H ２ This reaction is shown in the following equation:

[0048]

[0049] As described above, when electrons are supplied to GaN, the electrons are converted into H ２ That is, when electrons are supplied to GaN, etching does not proceed in that region.

[0050] The reaction of Chemical Formula 3 can also be promoted by providing a large-area cathode separate from the area to be etched.

[0051] Due to the above mechanism, etching proceeds selectively depending on the type of carriers supplied to GaN. Next, as a comparative example to this embodiment, the movement of electrons and holes when light 8 is irradiated from the wafer edge side of the semiconductor device 100 will be shown.

[0052] 7 is a first diagram illustrating the movement of electrons and holes in an npn junction according to the first embodiment of the present disclosure. As shown in FIG. 7, when light 8 is irradiated from the wafer edge side, holes are supplied to the surfaces of the substrate 1 and the GaN layer 3. On the other hand, in the same case, electrons are supplied to the surface of the GaN sacrificial layer 2.

[0053] 8 is a diagram showing the energy band of the substrate of FIG. 7. When light 8 is irradiated from the wafer edge side of the substrate 1, a photovoltaic force 20 is generated. Then, as shown in the energy band, holes are supplied to the surface of the substrate 1. As a result, oxidation and etching of the surface progress.

[0054] 9 is a diagram showing the energy band of the GaN sacrificial layer of FIG. 7. When light 8 is irradiated from the wafer edge side of the GaN sacrificial layer 2, a photovoltaic force 20 is generated. Then, as shown in the energy band, electrons are supplied to the surface of the GaN sacrificial layer 2. As a result, the electrons react with water to generate hydrogen.

[0055] 10 is a diagram showing the energy band of the GaN layer in FIG. 7. When light 8 is irradiated from the wafer edge side of the GaN layer 3, a photovoltaic force 20 is generated. Then, as shown in the energy band, holes are supplied to the surface of the GaN layer 3. As a result, oxidation and etching of the surface progress.

[0056] Next, as an example according to this embodiment, the movement of electrons and holes when light 8 is irradiated from the bulk side of the semiconductor device 100 will be shown. That is, the movement of electrons and holes when the irradiation range of light 8 is narrowed so as not to hit the surface at the wafer edge will be shown.

[0057] 11 is a second diagram illustrating the movement of electrons and holes in the npn junction according to the first embodiment of the present disclosure. As shown in FIG. 11 , when light 8 is irradiated from the bulk side, electrons are generated due to the diffusion potential at the npn junction. At this time, the generated electrons move toward the n-type GaN side, and the holes move toward the p-type GaN side, generating a photovoltaic force. As a result, electrons are supplied to the surfaces of the substrate 1 and the GaN layer 3, and holes are supplied to the surface of the GaN sacrificial layer 2.

[0058] Fig. 12 is a diagram showing the energy band of the substrate of Fig. 11. When light 8 is irradiated from the bulk side of the substrate 1, a photovoltaic force 20 is generated. Then, as shown in the energy band, electrons are supplied to the surface of the substrate 1. As a result, the electrons react with water to generate hydrogen.

[0059] Fig. 13 is a diagram showing the energy band of the GaN sacrificial layer of Fig. 11. When light 8 is irradiated from the bulk side of the GaN sacrificial layer 2, a photovoltaic force 20 is generated. Then, as shown in the energy band, holes are supplied to the surface of the GaN sacrificial layer 2. As a result, oxidation and etching of the surface progress.

[0060] Fig. 14 is a diagram showing the energy band in the GaN layer of Fig. 11. When light 8 is irradiated from the bulk side of the GaN layer 3, a photovoltaic force 20 is generated. Then, as shown in the energy band, electrons are supplied to the surface of the GaN layer 3. As a result, the electrons react with water to generate hydrogen.

[0061] As described above, in this embodiment, the GaN sacrificial layer 2, which is a sacrificial layer made of the same material, GaN, is formed at the interface between the substrate 1, which is the growth substrate, and the structure to be grown. Therefore, the lattice constant of the sacrificial layer is the same as that of the structure to be grown. As a result, it is possible to prevent crystal defects from occurring on the surface on the separated side of the grown structure.

[0062] Furthermore, in this embodiment, by irradiating the semiconductor device 100 with light while avoiding the surface at the edge of the wafer, it is possible to selectively etch only the GaN sacrificial layer 2. As a result, it is possible to avoid physical or thermal damage to the surface on the separated side of the grown structure.

[0063] Furthermore, according to this embodiment, the separated substrate can be reused, thereby reducing manufacturing costs.

[0064] 15 is a diagram showing a manufacturing process of a semiconductor device according to a second embodiment of the present disclosure. The manufacturing method of a semiconductor device according to this embodiment differs from the first embodiment in that light 8a with a variable irradiation range is used.

[0065] First, the semiconductor device 100 is immersed in a container filled with an etching solution 7. Subsequently, the container is irradiated with light 8a having a wavelength of 365 nm or less. The irradiation range of this light 8 is gradually narrowed depending on the degree of progress of etching of the GaN sacrificial layer 2 in the horizontal direction so as not to impinge on the surface of the edge of the heteroepitaxial stacked structure.

[0066] If the irradiation range of the light 8a is not changed, as etching of the GaN sacrificial layer 2 progresses, the surfaces of the substrate 1 and the outer edge region of the GaN layer 3 come into contact with the etching solution 7. When the light 8a is irradiated onto the contacting surfaces, etching also progresses on the substrate 1 and the GaN layer 3 due to the mechanism described above. As a result, the GaN layer 3 becomes thinner closer to the outer edge, which poses a problem of reduced in-plane uniformity.

[0067] In this embodiment, the irradiation range of light 8a is narrowed over time depending on the progress of horizontal etching of GaN sacrificial layer 2 so as not to impinge on the surface of the edge of the heteroepitaxial stacked structure. In other words, even if the surfaces of the substrate 1 and the GaN layer 3 in the outer edge region come into contact with the etching solution 7, light 8a is not irradiated onto the contacting surfaces. As a result, it is possible to prevent etching of substrate 1 and GaN layer 3 from progressing.

[0068] As described above, in this embodiment, the occurrence of crystal defects and physical or thermal damage can be prevented, thereby improving the reliability of the field-effect transistor to which it is applied. Furthermore, in this embodiment, the progress of etching of the GaN layer 3 can be prevented, thereby preventing a decrease in the in-plane uniformity of the GaN layer 3.

[0069] 16 is a diagram showing a manufacturing process of a semiconductor device according to a third embodiment of the present disclosure. This embodiment is applied to a semiconductor device in a wafer state. The manufacturing method of a semiconductor device according to this embodiment differs from the first embodiment in that the surface of the wafer edge is exposed before the step of irradiating with light 8.

[0070] Before describing the effects of this embodiment, a problem with a semiconductor device according to a comparative example will be described below. Fig. 17 is an enlarged view showing the wafer edge of a semiconductor device according to the comparative example.

[0071] At the wafer edge of the semiconductor device 500, successively grown layers grow so as to cover the layer grown immediately before. Therefore, the edge of the GaN sacrificial layer 2 is also covered by the subsequently grown GaN layer 3, AlGaN layer 4, and buffer layer 5. As a result, even when the semiconductor device 500 is immersed in a container filled with etching solution 7, the edge of the GaN sacrificial layer 2 does not come into contact with the etching solution 7. In other words, there was a problem in that etching did not progress effectively in the initial stage of the process of irradiating light 8.

[0072] In the manufacturing process of the semiconductor device according to this embodiment, the surface of the wafer edge of the semiconductor device 100b is exposed before the semiconductor device 100b is immersed in a container filled with the etching solution 7. This exposure is achieved by removing the peripheral wafer region of the semiconductor device 100b, for example, by dry etching. As a result, when the semiconductor device 100b is immersed in the container filled with the etching solution 7, the edge of the GaN sacrificial layer 2 comes into contact with the etching solution 7. In other words, etching progresses effectively even in the early stages of the process of irradiating the semiconductor device with light 8.

[0073] As described above, in this embodiment, the occurrence of crystal defects and physical or thermal damage can be avoided, thereby improving the reliability of the field-effect transistor to which the present invention is applied. Furthermore, in this embodiment, etching can be effectively progressed even in the early stages of the process of irradiating light 8.

[0074] Note that the compositions and thicknesses of the semiconductors shown in this disclosure are merely examples and are subject to change depending on the electrical characteristics of the transistor ultimately obtained by this disclosure.

[0075] REFERENCE SIGNS LIST 1 Substrate 2 GaN sacrificial layer 3 GaN layer 4 AlGaN layer 5 Buffer layer 6 Support substrate 7 Etching solution 8 Light 8a Light 100 Semiconductor device 100b Semiconductor device 500 Semiconductor device

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: forming a layered structure by epitaxially growing a p-type GaN sacrificial layer, an n-type or undoped GaN layer, an AlGaN layer, and a buffer layer in that order on an n-type GaN substrate; attaching a support substrate to the buffer layer of the layered structure; and immersing the layered structure attached to the support substrate in an etching solution and irradiating the layered structure with light to selectively etch the GaN sacrificial layer from the side of the layered structure, wherein the irradiation range of the layered structure with light is set so that the light does not hit the surface layer of the side of the layered structure.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the wavelength of the light is 365 nm or less.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the irradiation range is narrowed over time depending on the degree of progress of etching of the GaN sacrificial layer from the side surface of the laminated structure, so as not to hit the surface layer of the side surface of the GaN sacrificial layer.

4. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of exposing the surface layer of the side surface of the laminated structure before the light irradiation.

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