Semiconductor device and power conversion device

Abstract

A semiconductor device (100) is provided with a base material (10), a semiconductor chip (20), and a bonding layer (30). The semiconductor chip is disposed on the base material with the bonding layer interposed therebetween. The bonding layer includes an outer peripheral portion (31) and a central portion (32) located inside the outer peripheral portion in a plan view. The porosity in the outer peripheral portion is lower than the porosity in the central portion, and is 50% or less.

Description

Semiconductor device and power conversion device

[0001] The present disclosure relates to a semiconductor device and a power conversion device.

[0002] International Publication No. WO 2023 / 286432 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 includes an insulating circuit substrate, a sintered layer, and a semiconductor chip. The semiconductor chip is disposed on a conductor pattern of the insulating circuit substrate with the sintered layer interposed therebetween.

[0003] International Publication No. 2023 / 286432

[0004] In the semiconductor device described in Patent Document 1, cracks are prevented from occurring in the semiconductor chip by preferentially destroying the sintered layer. However, if the semiconductor substrate used in the semiconductor chip is made of a material that is prone to cracking (e.g., gallium oxide), this method is insufficient to prevent cracks in the semiconductor chip. The present disclosure provides a semiconductor device that can improve the heat dissipation of the semiconductor chip while suppressing cracks in the semiconductor chip.

[0005] The semiconductor device of the present disclosure includes a substrate, a semiconductor chip, and a bonding layer. The semiconductor chip is disposed on the substrate with the bonding layer interposed therebetween. The bonding layer has, in a plan view, an outer peripheral portion and a central portion located inside the outer peripheral portion. The porosity of the outer peripheral portion is lower than the porosity of the central portion and is 50% or less.

[0006] According to the semiconductor device of the present disclosure, it is possible to improve the heat dissipation performance of the semiconductor chip while suppressing cracking of the semiconductor chip.

[0007] 1 is a cross-sectional view of a semiconductor device 100. FIG. 2 is a partially enlarged view of FIG. 1. FIG. 3 is an enlarged cross-sectional view of a semiconductor device 100 according to a first modification. FIG. 4 is a plan view of a semiconductor device 100 according to a second modification. FIG. 5 is a plan view of a semiconductor device 100 according to a third modification. FIG. 6 is an enlarged cross-sectional view of a semiconductor device 100 according to a fourth modification. FIG. 7 is a block diagram showing a configuration of a power conversion system to which a power conversion device 200 is applied.

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] First Embodiment A semiconductor device according to a first embodiment will be described. The semiconductor device according to the first embodiment is designated as a semiconductor device 100.

[0010] (Configuration of semiconductor device 100) Fig. 1 is a cross-sectional view of the semiconductor device 100. Fig. 2 is a partially enlarged view of Fig. 1. As shown in Figs. 1 and 2, the semiconductor device 100 has a base material 10, a semiconductor chip 20, a bonding layer 30, wiring members 40, 41, 42, and 43, bonding layers 50, 51, and 52, a case 60, and a sealing material 61.

[0011] The substrate 10 is, for example, an insulating circuit board. However, the substrate 10 is not limited to this. The substrate 10 may be, for example, a heat spreader. In the following, an insulating circuit board will be described as an example of the substrate 10. The substrate 10 (insulating circuit board) has an insulating layer 11 and conductor patterns 12, 13, and 14.

[0012] The insulating layer 11 is made of an electrically insulating material. The insulating layer 11 is made of a ceramic material such as alumina. The insulating layer 11 has a principal surface 11a and a principal surface 11b. The principal surface 11b is the surface opposite to the principal surface 11a. The principal surface 11a and the principal surface 11b are end surfaces of the insulating layer 11 in the thickness direction.

[0013] The conductor patterns 12 and 13 are arranged on the main surface 11a. The conductor pattern 14 is arranged on the main surface 11b. The conductor patterns 12, 13, and 14 are made of a conductive material. For example, the conductor patterns 12, 13, and 14 are made of copper.

[0014] The semiconductor chip 20 has a semiconductor substrate 21, an insulating film 22, and electrodes 23, 24, and 25. The semiconductor substrate 21 is formed of a single crystal of a semiconductor material. The semiconductor substrate 21 is formed of, for example, a compound semiconductor. In the semiconductor substrate 21, the arrangement direction of defects (e.g., dislocations, stacking faults, etc.) is anisotropic. A specific example of a compound semiconductor having anisotropic defect arrangement direction is gallium oxide. The semiconductor substrate 21 may be formed of silicon or silicon carbide. The semiconductor substrate 21 has a main surface 21a and a main surface 21b. The main surface 21b is the surface opposite to the main surface 21a. The main surface 21a and the main surface 21b are end surfaces in the thickness direction of the semiconductor substrate 21.

[0015] The insulating film 22 is disposed on the main surface 21a. The insulating film 22 is formed of, for example, silicon oxide. The electrodes 23 and 24 are disposed on the insulating film 22. The electrode 25 is disposed on the main surface 21b. The electrodes 23, 24, and 25 are formed of a conductive material. The semiconductor chip 20 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this case, the electrodes 23, 24, and 25 are a source electrode, a gate electrode, and a drain electrode, respectively. The semiconductor chip 20 is an IGBT (Insulated Gate Bipolar Transistor). In this case, the electrodes 23, 24, and 25 are an emitter electrode, a gate electrode, and a collector electrode, respectively.

[0016] The semiconductor chip 20 is disposed on the substrate 10 with the bonding layer 30 interposed therebetween. More specifically, the semiconductor chip 20 is disposed on the conductor pattern 12 so that the electrodes 25 face the conductor pattern 12 with the bonding layer 30 interposed therebetween. This allows the semiconductor chip 20 to be mechanically and electrically connected to the conductor pattern 12.

[0017] The bonding layer 30 is, for example, a sintered layer. The sintered layer is a layer formed of a sintered body of metal particles. The metal particles are, for example, silver particles or copper particles. The bonding layer 30 may be a liquid phase diffusion bonding layer. The liquid phase diffusion bonding layer is a layer formed of an alloyed insert metal. For example, the liquid phase diffusion bonding layer is a layer formed in an insert metal containing low melting point metal particles and silver particles or copper particles, by melting the low melting point metal particles and alloying them with the silver particles or copper particles.

[0018] The bonding layer 30 is a sintered layer or a liquid phase diffusion bonding layer, and therefore contains voids (the voids are shown schematically in FIG. 2 ). The bonding layer 30 has an outer peripheral portion 31 and a central portion 32. The outer peripheral portion 31 is located at the outer peripheral edge of the bonding layer 30 in a planar view. The width of the outer peripheral portion 31 is, for example, 1 mm or less. The width of the outer peripheral portion 31 may be, for example, approximately 0.1 mm. The central portion 32 is located inside the outer peripheral portion 31 in a planar view. The porosity of the outer peripheral portion 31 is higher than the porosity of the central portion 32. The porosity of the outer peripheral portion 31 is, for example, 50% or less. The porosity of the outer peripheral portion 31 is, for example, 5% or more. The porosity of the outer peripheral portion 31 may be 10% or more. The average size of the voids in the outer peripheral portion 31 is, for example, larger than the average size of the voids in the central portion 32.

[0019] The porosity in the outer peripheral portion 31 is measured by the following method. First, a cross-sectional SEM (Scanning Electron Microscope) image of the bonding layer 30 is acquired. Second, the area ratio of voids is measured in the acquired cross-sectional SEM image. In the acquired cross-sectional SEM image, voids appear black, and everything other than the voids appears whitish. Therefore, the area of ​​the voids in the cross-sectional SEM image can be measured by performing a binarization process on the acquired cross-sectional SEM image to calculate the area of ​​the black parts. Third, the area of ​​the voids measured as described above is divided by the area of ​​the cross-sectional SEM image, and the result is multiplied by 100. In this way, the porosity in the outer peripheral portion 31 is measured. The porosity in the central portion 32 is measured in the same manner.

[0020] The average size of the voids in the outer peripheral portion 31 is measured by the following method. First, a cross-sectional SEM image of the bonding layer 30 is acquired. Second, the number of pixels contained in a black area surrounded by a white area on the acquired cross-sectional SEM image is counted. A set of multiple pixels contained in a black area surrounded by a white area is called a pixel group. Third, the number of pixels contained in each of the multiple pixel groups included in the cross-sectional SEM image is added up and divided by the number of pixel groups. This value is considered to be the average size of the voids in the outer peripheral portion 31. The average size of the voids in the central portion 32 is measured in a similar manner.

[0021] The thickness of the bonding layer 30 is defined as thickness T. The thickness T is, for example, 10 nm or more and 500 μm or less. The thermal conductivity of the central portion 32 is, for example, 100 W / m·K or more. Note that the thermal conductivity of the solder alloy is 40 W / m·K to 50 W / m·K, so the thermal conductivity of the central portion 32 is greater than the thermal conductivity of the solder alloy, for example.

[0022] The wiring member 40 is disposed on the electrode 23 with a bonding layer 50 interposed therebetween. As a result, the wiring member 40 is electrically and mechanically connected to the electrode 23. The wiring member 41 is, for example, a bonding wire. One end of the wiring member 41 is connected to the conductor pattern 13, and the other end is connected to the electrode 24. The wiring member 42 is disposed on the conductor pattern 13 with a bonding layer 51 interposed therebetween. As a result, the wiring member 42 is electrically and mechanically connected to the conductor pattern 13. The wiring member 43 is disposed on the conductor pattern 12 with a bonding layer 52 interposed therebetween. As a result, the wiring member 43 is electrically and mechanically connected to the conductor pattern 12.

[0023] Each of the bonding layers 50, 51, and 52 has an outer periphery and a central portion inside the outer periphery in plan view, and the porosity of the outer periphery is lower than the porosity of the central portion and may be 50% or less. Each of the bonding layers 50, 51, and 52 may be, for example, a sintered layer or a liquid phase diffusion bonding layer.

[0024] The case 60 is disposed on the substrate 10. More specifically, the case 60 is disposed on the principal surface 11a. The case 60 rises from the principal surface 11a along the normal direction of the principal surface 11a. In a plan view, the case 60 extends along the outer periphery of the principal surface 11a. The sealing material 61 fills the space defined by the case 60 and the principal surface 11a. This seals the conductor pattern 12, the conductor pattern 13, the semiconductor chip 20, the bonding layer 30, the wiring member 40, the wiring member 41, the wiring member 42, the wiring member 43, the bonding layer 50, the bonding layer 51, and the bonding layer 52. However, the ends of the wiring member 40, the wiring member 42, and the wiring member 43 are exposed from the sealing material 61. These exposed ends function as external connection terminals of the semiconductor device 100. The sealing material 61 is, for example, an electrically insulating resin material.

[0025] (Method of Manufacturing the Semiconductor Device 100) A method of manufacturing the semiconductor device 100 will be described below.

[0026] The manufacturing method of the semiconductor device 100 includes a preparation step, a first bonding material application step, a semiconductor chip mounting step, a second bonding material application step, a wiring member mounting step, a heating step, a wire bonding step, and a sealing material filling step. In the preparation step, the substrate 10 and the semiconductor chip 20 are prepared. After the preparation step, the first bonding material application step is performed.

[0027] In the first bonding material application process, a bonding material is applied onto the conductor patterns 12 and 13. The bonding material is, for example, a paste containing silver particles or copper particles, or a paste containing an insert metal. After the first bonding material application process, a semiconductor chip mounting process is performed. In the semiconductor chip mounting process, the semiconductor chip 20 is mounted on the conductor pattern 12 with the bonding material applied as described above interposed therebetween. At this time, the wiring members 42 and 43 are also mounted on the conductor patterns 13 and 12, respectively, with the bonding material applied as described above interposed therebetween. After the semiconductor chip mounting process, a second bonding material application process is performed.

[0028] In the second bonding material application process, bonding material is applied onto the electrode 23. After the second bonding material application process, a wiring member mounting process is performed. In the wiring member mounting process, the wiring member 40 is mounted on the electrode 23 with the bonding material applied as described above interposed therebetween. After the wiring member mounting process, a heating process is performed.

[0029] In the heating process, silver particles or copper particles in the bonding material are heated and sintered, or an insert metal in the bonding material is heated and alloyed. As a result, the bonding material applied as described above becomes bonding layers 30, 50, 51, and 52, which bond the semiconductor chip 20 (electrodes 25) to the conductor pattern 12, the wiring member 40 to the electrode 23, the wiring member 42 to the conductor pattern 13, and the wiring member 43 to the conductor pattern 12. During the heating process, the semiconductor chip 20 may be pressed toward the conductor pattern 12, the wiring member 40 may be pressed toward the electrode 23, the wiring member 42 may be pressed toward the conductor pattern 13, or the wiring member 43 may be pressed toward the conductor pattern 12. Such pressing is not necessary. After the heating process, a wire bonding process is performed.

[0030] In the wire bonding process, wire bonding is performed to connect one end of the wiring member 41 to the conductor pattern 13 and the other end of the wiring member 41 to the electrode 24. After the wire bonding process, a sealant filling process is performed. In the sealant filling process, first, the case 60 is attached to the base material 10 (insulating layer 11). Second, the sealant 61 is poured into the space defined by the case 60 and the main surface 11a. At this stage, the sealant 61 is uncured. Third, heating is performed to cure the sealant 61. As a result of the above, the structure of the semiconductor device 100 shown in FIGS. 1 and 2 is formed.

[0031] (Effects of the Semiconductor Device 100) The effects of the semiconductor device 100 will be described below.

[0032] If the entire bonding layer 30 is a dense (low porosity) sintered body layer or liquid phase diffusion bonding layer, the thermal conductivity is excellent, but stress is not easily alleviated in the bonding layer 30, making the semiconductor chip 20 more susceptible to cracking. In this regard, in the semiconductor device 100, the porosity of the bonding layer 30 in the outer peripheral portion 31 is greater than the porosity in the central portion 32, so the elastic modulus of the bonding layer 30 in the outer peripheral portion 31 is lower, making it easier to alleviate stress in the outer peripheral portion 31. As a result, the semiconductor device 100 can suppress cracking of the semiconductor chip 20.

[0033] Furthermore, the porosity is higher in the central portion 32 than in the peripheral portion 31, and the thermal conductivity of the bonding layer 30 is maintained in the central portion 32. Therefore, the semiconductor device 100 ensures heat dissipation of the semiconductor chip 20. When the semiconductor substrate 21 is made of gallium oxide, the semiconductor chip 20 is prone to cracking due to anisotropy in the defect arrangement direction. On the other hand, when the semiconductor substrate 21 is made of gallium oxide, the thermal conductivity of gallium oxide is low, so it is highly necessary to ensure heat dissipation of the semiconductor chip 20. Therefore, the configuration of the semiconductor device 100 is particularly effective when the semiconductor substrate 21 is made of a compound semiconductor material such as gallium oxide, which is prone to cracking and has low thermal conductivity.

[0034] The smaller the thickness T, the more improved the heat dissipation of the semiconductor chip 20, but the more likely it is that cracks will occur in the semiconductor chip 20. On the other hand, the larger the thickness T, the more reduced the heat dissipation of the semiconductor chip 20, but the more unlikely it is that cracks will occur in the semiconductor chip 20. By setting the thickness T to be 10 nm or more and 500 μm or less, it is possible to achieve both the heat dissipation of the semiconductor chip 20 and the resistance to cracking of the semiconductor chip 20.

[0035] Even if the porosity is the same, the larger the average size of the voids, the greater the stress relaxation effect. Therefore, when the average size of the voids in the outer peripheral portion 31 is larger than the average size of the voids in the central portion 32, the semiconductor chip 20 can be made even less likely to crack.

[0036] (Modifications) Modifications of the semiconductor device 100 will be described below.

[0037] <Modification 1> Figure 3 is an enlarged cross-sectional view of a semiconductor device 100 according to Modification 1. As shown in Figure 3, the bonding layer 30 may extend beyond the outer periphery of the semiconductor chip 20 in a planar view. In this case, the portion of the bonding layer 30 that is beyond the outer periphery of the semiconductor chip 20 in a planar view is the outer periphery 31. That is, the porosity of the portion of the bonding layer 30 that is beyond the outer periphery of the semiconductor chip 20 in a planar view is lower than the porosity of the portion of the bonding layer 30 that is beyond the outer periphery of the semiconductor chip 20 in a planar view. In this case, stress is alleviated by the outer periphery 31, and the overlap between the central portion 32 and the semiconductor chip 20 in a planar view is increased, further improving the heat dissipation of the semiconductor chip 20.

[0038] <Modifications 2 and 3> Fig. 4A is a plan view of a semiconductor device 100 according to Modification 2. Fig. 4B is a plan view of a semiconductor device 100 according to Modification 3. As shown in Figs. 4A and 4B, at least one side of the outer periphery of the bonding layer 30 in plan view may be zigzag (see Fig. 4A) or curved (see Fig. 4B) rather than straight. In this case, stress tends to concentrate on the outer periphery of the bonding layer 30 in plan view, which reduces stress concentration in the semiconductor chip 20 and further reduces cracking of the semiconductor chip 20. Note that the outer periphery of the bonding layer 30 in plan view is achieved by zigzag or curved the outer periphery of the application shape of the bonding material in plan view in the first bonding material application step.

[0039] <Modification 4> FIG. 5 is an enlarged cross-sectional view of a semiconductor device 100 according to Modification 4. As shown in FIG. 5, the semiconductor chip 20 is disposed on the conductor pattern 12 so that the electrode 23, rather than the electrode 25, faces the conductor pattern 12 with the bonding layer 30 interposed therebetween. That is, the semiconductor chip 20 may be flip-chip bonded to the substrate 10. The electrode 23 is a source electrode if the semiconductor chip 20 is a MOSFET, and is an emitter electrode if the semiconductor chip 20 is an IGBT. That is, in this case, the electrode that generates the greatest amount of heat is closest to the substrate 10. Furthermore, because a cooler is connected to the substrate 10 (conductor pattern 14), the heat transfer distance between the electrode that generates the greatest amount of heat and the cooler is shortened. Therefore, in this case, the heat dissipation performance of the semiconductor chip 20 is further improved.

[0040] Second Embodiment A power conversion device according to a second embodiment will be described. The power conversion device according to the second embodiment is designated as a power conversion device 200.

[0041] In the second embodiment, the semiconductor device (semiconductor device 100) according to the first embodiment is applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, the second embodiment will be described with reference to a case where the present disclosure is applied to a three-phase inverter.

[0042] (Configuration of Power Conversion Device 200) The configuration of the power conversion device 200 will be described below.

[0043] 6 is a block diagram showing the configuration of a power conversion system to which the power conversion device 200 is applied. The power conversion system shown in FIG.

[0044] The power supply 210 is a DC power supply that supplies DC power to the power conversion device 200. The power supply 210 can be configured from various sources. For example, the power supply 210 can be configured from a DC system, a solar cell, or a storage battery. The power supply 210 may be configured from a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 210 may be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0045] The load 220 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 220 is not limited to a specific application. The load 220 is an electric motor mounted on various electrical devices. The load 220 is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0046] The power conversion device 200 is a three-phase inverter connected between a power source 210 and a load 220. The power conversion device 200 converts DC power supplied from the power source 210 into AC power and supplies the AC power to the load 220. As shown in Fig. 6 , the power conversion device 200 has a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal 204 to the main conversion circuit 201 to control the main conversion circuit 201.

[0047] (Detailed Configuration of Power Conversion Device 200) The configuration of the power conversion device 200 will be described in detail below.

[0048] The main conversion circuit 201 includes a switching element and a free wheel diode (not shown). The main conversion circuit 201 converts DC power supplied from the power source 210 into AC power by switching the switching element, and supplies the AC power to the load 220.

[0049] There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to the second embodiment is a two-level three-phase full-bridge circuit, and is composed of six switching elements and six freewheeling diodes connected in anti-parallel to each of the switching elements.

[0050] At least one of the switching element and each free wheel diode of the main conversion circuit 201 is the switching element or free wheel diode of the semiconductor device 202 corresponding to the semiconductor device of the first embodiment.

[0051] The six switching elements are connected in series in pairs to form upper and lower arms. Each upper and lower arm constitutes one phase (U phase, V phase, and W phase) of the half-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 220. Note that a freewheeling diode is not required for transistors that have a body diode, such as MOS transistors, or transistors that have a built-in diode and function as a freewheeling diode, such as RC-IGBTs. The switching elements themselves may also be composed of multiple transistors.

[0052] The main conversion circuit 201 has a drive circuit (not shown) that drives each switching element. This drive circuit may be built into the semiconductor device 202, or may be configured separately from the semiconductor device 202. This drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201, and supplies them to the control electrodes of the switching elements of the main conversion circuit 201.

[0053] More specifically, this drive circuit outputs to the control electrode of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off in accordance with a control signal 204 from a control circuit 203. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element. When maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0054] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 220. More specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 220. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 outputs a control command (control signal 204) to the drive circuit of the main conversion circuit 201 so that on signals and off signals are output to the switching elements that should be in the on state and the switching elements that should be in the off state at each point in time, respectively. The drive circuit of the main conversion circuit 201 outputs on or off signals as drive signals to the control electrodes of each switching element in accordance with the control signal 204.

[0055] In the second embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when power is supplied to a single-phase load, the present disclosure may also be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the present disclosure may also be applied to a DC / DC converter or an AC / DC converter.

[0056] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0057] 100 semiconductor device, 10 substrate, 11 insulating layer, 11a main surface, 11b main surface, 12 conductor pattern, 13 conductor pattern, 14 conductor pattern, 20 semiconductor chip, 21 semiconductor substrate, 21a main surface, 21b main surface, 22 insulating film, 23 electrode, 24 electrode, 25 electrode, 30 bonding layer, 31 outer periphery, 32 central portion, 40 wiring member, 41 wiring member, 42 wiring member, 43 wiring member, 50, 51, 52 bonding layer, 60 case, 61 sealing material, 202 semiconductor device, 200 power conversion device, 201 main conversion circuit, 203 control circuit, 204 control signal, 210 power supply, 220 load, T thickness.

Claims

1. A semiconductor device comprising: a substrate; a semiconductor chip; and a bonding layer, wherein the semiconductor chip is disposed on the substrate with the bonding layer interposed therebetween; the bonding layer has, in a plan view, an outer periphery and a central portion located inside the outer periphery; and the porosity of the outer periphery is lower than the porosity of the central portion and is 50 percent or less.

2. The semiconductor device according to claim 1, wherein the semiconductor chip has a semiconductor substrate made of a compound semiconductor, and the arrangement direction of the defects in the semiconductor substrate is anisotropic.

3. The semiconductor device according to claim 1 or 2, wherein the semiconductor chip is made of gallium oxide.

4. The semiconductor device according to any one of claims 1 to 3, wherein the bonding layer is a sintered layer or a liquid phase diffusion bonding layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein the thermal conductivity in the central portion is 100 W / m·K or more.

6. The semiconductor device according to any one of claims 1 to 5, wherein the thickness of the bonding layer is 10 nm or more and 500 μm or less.

7. The semiconductor device according to any one of claims 1 to 6, wherein the average size of the voids in the outer periphery is larger than the average size of the voids in the central portion.

8. The semiconductor device according to any one of claims 1 to 7, wherein the outer peripheral portion is located outside the outer peripheral edge of the semiconductor chip in a plan view.

9. The semiconductor device according to any one of claims 1 to 8, wherein at least one side of the outer periphery of the bonding layer in plan view is zigzag or curved.

10. A semiconductor device according to any one of claims 1 to 9, wherein the semiconductor chip has an electrode on its surface and is disposed on the substrate so that the electrode faces the substrate with the bonding layer interposed therebetween, and the electrode is an emitter electrode or a source electrode.

11. A power conversion device comprising the semiconductor device according to any one of claims 1 to 10, a main conversion circuit that converts input power and outputs it, and a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit.

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