Method for manufacturing semiconductor device

Abstract

This method for manufacturing a semiconductor device (100) comprises: a step (S2) for applying a first bonding material onto a base material (10); a step (S3) for disposing a semiconductor chip (20) having a semiconductor substrate (21) on the base material with the first bonding material interposed therebetween; and a step (S6) for bonding the semiconductor chip to the base material with the first bonding material while heating. In the step for bonding the semiconductor chip to the base material with the first bonding material while heating, the pressure applied to the semiconductor chip is less than 1 MPa.

Description

Semiconductor device manufacturing method

[0001] The present disclosure relates to a method for manufacturing a semiconductor device.

[0002] International Publication No. WO 2023 / 286432 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 includes an insulating circuit substrate, a sintered layer, and a semiconductor chip. The semiconductor chip is disposed on a conductor pattern of the insulating circuit substrate with the sintered layer interposed therebetween.

[0003] International Publication No. 2023 / 286432

[0004] In the semiconductor device manufacturing method described in Patent Document 1, a bonding material containing metal particles is applied to an insulating circuit board, a semiconductor chip is mounted on the insulating circuit board with the bonding material interposed therebetween, and the semiconductor chip is heated while being pressurized, thereby bonding the semiconductor chip to the insulating circuit board by a sintered layer. Therefore, in the semiconductor device manufacturing method described in Patent Document 1, the semiconductor chip may crack due to the pressurization. The present disclosure provides a semiconductor device manufacturing method that can suppress cracking of the semiconductor chip.

[0005] The method for manufacturing a semiconductor device according to the present disclosure includes the steps of applying a first bonding material to a substrate, placing a semiconductor chip having a semiconductor substrate on the substrate with the first bonding material interposed therebetween, and bonding the semiconductor chip to the substrate with the first bonding material while heating, wherein a pressure of less than 1 MPa is applied to the semiconductor chip during the step of bonding the semiconductor chip to the substrate with the first bonding material while heating.

[0006] According to the method for manufacturing a semiconductor device of the present disclosure, cracking of the semiconductor chip can be suppressed.

[0007] 1 is a plan view of the semiconductor device 100; FIG. 2 is a cross-sectional view of the semiconductor device 100; FIG. 3 is a manufacturing process diagram of the semiconductor device 100; FIG. 4 is an enlarged cross-sectional view of the semiconductor device 100 according to a first modification; FIG. 5 is a cross-sectional view of the semiconductor device 100 according to a third modification.

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] First Embodiment A semiconductor device according to a first embodiment will be described. The semiconductor device according to the first embodiment is designated as a semiconductor device 100.

[0010] (Configuration of Semiconductor Device 100) FIG. 1 is a plan view of the semiconductor device 100. Note that only the substrate 10 and the semiconductor chip 20 are shown in FIG. 1. Also, in FIG. 1, the bonding layer 30 is indicated by a dotted line. FIG. 2 is a cross-sectional view of the semiconductor device 100. As shown in FIGS. 1 and 2, the semiconductor device 100 has the substrate 10, the semiconductor chip 20, the bonding layer 30, the wiring members 40, 41, 42, and 43, the bonding layers 50, 51, and 52, the case 60, and the sealing material 61.

[0011] The substrate 10 is, for example, an insulating circuit board. However, the substrate 10 is not limited to this. The substrate 10 may be, for example, a heat spreader. In the following, an insulating circuit board will be described as an example of the substrate 10. The substrate 10 (insulating circuit board) has an insulating layer 11 and conductor patterns 12, 13, and 14.

[0012] The insulating layer 11 is made of an electrically insulating material. The insulating layer 11 is made of a ceramic material such as alumina. The insulating layer 11 has a principal surface 11a and a principal surface 11b. The principal surface 11b is the surface opposite to the principal surface 11a. The principal surface 11a and the principal surface 11b are end surfaces of the insulating layer 11 in the thickness direction.

[0013] The conductor patterns 12 and 13 are arranged on the main surface 11a. The conductor pattern 14 is arranged on the main surface 11b. The conductor patterns 12, 13, and 14 are made of a conductive material. For example, the conductor patterns 12, 13, and 14 are made of copper.

[0014] The semiconductor chip 20 has a semiconductor substrate 21, an insulating film 22, and electrodes 23, 24, and 25. The semiconductor substrate 21 is formed of a single crystal of a semiconductor material. The semiconductor substrate 21 is formed of, for example, a compound semiconductor. In the semiconductor substrate 21, the arrangement direction of defects (e.g., dislocations, stacking faults, etc.) is anisotropic. A specific example of a compound semiconductor having anisotropic defect arrangement direction is gallium oxide. The semiconductor substrate 21 may be formed of silicon or silicon carbide. The semiconductor substrate 21 has a main surface 21a and a main surface 21b. The main surface 21b is the surface opposite to the main surface 21a. The main surface 21a and the main surface 21b are end surfaces in the thickness direction of the semiconductor substrate 21.

[0015] The insulating film 22 is disposed on the main surface 21a. The insulating film 22 is formed of, for example, silicon oxide. The electrodes 23 and 24 are disposed on the insulating film 22. The electrode 25 is disposed on the main surface 21b. The electrodes 23, 24, and 25 are formed of a conductive material. The semiconductor chip 20 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this case, the electrodes 23, 24, and 25 are a source electrode, a gate electrode, and a drain electrode, respectively. The semiconductor chip 20 is an IGBT (Insulated Gate Bipolar Transistor). In this case, the electrodes 23, 24, and 25 are an emitter electrode, a gate electrode, and a collector electrode, respectively.

[0016] The semiconductor chip 20 is disposed on the substrate 10 with the bonding layer 30 interposed therebetween. More specifically, the semiconductor chip 20 is disposed on the conductor pattern 12 so that the electrodes 25 face the conductor pattern 12 with the bonding layer 30 interposed therebetween. From another perspective, the semiconductor chip 20 is disposed on the substrate 10 so that the back surface of the semiconductor chip 20 faces the substrate 10 (conductor pattern 12) with the bonding layer 30 interposed therebetween. In this way, the semiconductor chip 20 is mechanically and electrically connected to the conductor pattern 12.

[0017] Viewing the semiconductor device 100 along the normal direction of the main surface 11a is referred to as a plan view. The outer peripheral edge of the semiconductor chip 20 in plan view is, for example, rectangular. This rectangle has a pair of first sides extending along a first direction DR1 and a pair of second sides extending along a second direction DR2. The first direction DR1 is one of the directions perpendicular to the normal direction of the main surface 11a. The second direction DR2 is a direction perpendicular to the first direction DR1 in plan view.

[0018] The semiconductor substrate 21 has a cleavage plane. When the semiconductor substrate 21 is made of gallium oxide, the cleavage plane is a (100) plane or a (001) plane. The first direction DR1 is, for example, a direction parallel to the cleavage plane, and the second direction DR2 is, for example, a direction perpendicular to the cleavage plane. In other words, cleavage progresses along the first direction DR1. The width of the semiconductor chip 20 in the first direction DR1 is defined as width W1. The width of the semiconductor chip 20 in the second direction DR2 is defined as width W2.

[0019] The thickness of the semiconductor chip 20 is defined as thickness T. Thickness T is, for example, less than 100 μm. When the semiconductor substrate 21 is made of gallium oxide, gallium oxide has a high dielectric breakdown field strength, so that the dielectric strength of the semiconductor chip 20 can be ensured even if the on-resistance of the semiconductor chip 20 is reduced by reducing thickness T. Furthermore, gallium oxide has a low thermal conductivity, so that heat dissipation can be improved by reducing thickness T.

[0020] The bonding layer 30 is, for example, a sintered layer. The sintered layer is a layer formed of a sintered body of metal particles. The metal particles are, for example, silver particles or copper particles. The bonding layer 30 may also be a liquid-phase diffusion bonding layer. The liquid-phase diffusion bonding layer is a layer formed of an alloyed insert metal. For example, the liquid-phase diffusion bonding layer is a layer formed by melting low-melting-point metal particles and alloying them with the silver particles or copper particles in an insert metal containing low-melting-point metal particles and silver particles or copper particles. When the bonding layer 30 is a liquid-phase diffusion bonding layer, the main component of the bonding layer 30 is, for example, an intermetallic compound of silver or copper and a low-melting-point metal. When the bonding layer 30 is a sintered layer, the main component of the bonding layer is, for example, silver or copper. Here, the term "main component" refers to a component that accounts for more than 50 mass percent of the constituent material. When the bonding layer 30 is a sintered layer or a liquid-phase diffusion bonding layer, the linear expansion coefficient of the bonding layer 30 is lower than, for example, the linear expansion coefficient of a solder alloy.

[0021] The outer peripheral edge of the bonding layer 30 in plan view is, for example, rectangular. This rectangle has a pair of third sides extending along the first direction DR1 and a pair of fourth sides extending along the second direction DR2. The width of the bonding layer 30 in the first direction DR1 is defined as width W3. The width of the bonding layer 30 in the second direction DR2 is defined as width W2. Width W3 is smaller than width W1, and width W4 is smaller than width W2. That is, in plan view, the area of ​​the bonding layer 30 is smaller than the area of ​​the semiconductor chip 20. The value obtained by dividing width W3 by width W1 is different from, for example, the value obtained by dividing width W4 by width W2. The value obtained by dividing width W3 by width W1 is smaller than, for example, the value obtained by dividing width W4 by width W2.

[0022] The wiring member 40 is disposed on the electrode 23 with a bonding layer 50 interposed therebetween. As a result, the wiring member 40 is electrically and mechanically connected to the electrode 23. The wiring member 41 is, for example, a bonding wire. One end of the wiring member 41 is connected to the conductor pattern 13, and the other end is connected to the electrode 24. The wiring member 42 is disposed on the conductor pattern 13 with a bonding layer 51 interposed therebetween. As a result, the wiring member 42 is electrically and mechanically connected to the conductor pattern 13. The wiring member 43 is disposed on the conductor pattern 12 with a bonding layer 52 interposed therebetween. As a result, the wiring member 43 is electrically and mechanically connected to the conductor pattern 12. Each of the bonding layers 50, 51, and 52 may be, for example, a sintered layer containing silver or copper as a main component, or a liquid phase diffusion bonding layer containing an intermetallic compound of silver or copper and a low-melting point metal as a main component.

[0023] The case 60 is disposed on the substrate 10. More specifically, the case 60 is disposed on the principal surface 11a. The case 60 rises from the principal surface 11a along the normal direction of the principal surface 11a. In a plan view, the case 60 extends along the outer periphery of the principal surface 11a. The sealing material 61 fills the space defined by the case 60 and the principal surface 11a. This seals the conductor pattern 12, the conductor pattern 13, the semiconductor chip 20, the bonding layer 30, the wiring member 40, the wiring member 41, the wiring member 42, the wiring member 43, the bonding layer 50, the bonding layer 51, and the bonding layer 52. However, the ends of the wiring member 40, the wiring member 42, and the wiring member 43 are exposed from the sealing material 61. These exposed ends function as external connection terminals of the semiconductor device 100. The sealing material 61 is, for example, an electrically insulating resin material.

[0024] (Method of Manufacturing the Semiconductor Device 100) A method of manufacturing the semiconductor device 100 will be described below.

[0025] 3 is a manufacturing process diagram of the semiconductor device 100. As shown in FIG. 3, the manufacturing method of the semiconductor device 100 includes a preparation step S1, a first bonding material application step S2, a semiconductor chip mounting step S3, a second bonding material application step S4, a wiring member mounting step S5, a heating step S6, a wire bonding step S7, and an encapsulant filling step S8. In the preparation step S1, a substrate 10 and a semiconductor chip 20 are prepared. After the preparation step S1, a first bonding material application step S2 is performed.

[0026] In the first bonding material application process S2, a first bonding material is applied onto the conductor patterns 12 and 13. The first bonding material is, for example, a paste containing silver particles or copper particles, or a paste containing an insert metal. The value obtained by dividing the application width of the first bonding material in the first direction DR1 by the width W1 is different from the value obtained by dividing the application width of the first bonding material in the second direction DR2 by the width W2. The value obtained by dividing the application width of the first bonding material in the first direction DR1 by the width W1 is, for example, smaller than the value obtained by dividing the application width of the first bonding material in the second direction DR2 by the width W2. Furthermore, the application area of ​​the first bonding material in a planar view is, for example, smaller than the area of ​​the semiconductor chip 20 in a planar view. After the first bonding material application process S2, a semiconductor chip mounting process S3 is performed.

[0027] In the semiconductor chip mounting process S3, the semiconductor chip 20 is mounted on the conductor pattern 12 with the first bonding material applied as described above interposed therebetween. The semiconductor chip 20 is mounted, for example, so that the cleavage plane is parallel to the first direction DR1 and the cleavage plane is perpendicular to the second direction DR2. At this time, the wiring members 42 and 43 are also mounted on the conductor patterns 13 and 12, respectively, with the first bonding material applied as described above interposed therebetween. After the semiconductor chip mounting process S3, a second bonding material application process S4 is performed.

[0028] In the second bonding material applying step S4, the second bonding material is applied onto the electrode 23. After the second bonding material applying step S4, a wiring member mounting step S5 is performed. In the wiring member mounting step S5, the wiring member 40 is mounted on the electrode 23 with the second bonding material applied as described above interposed therebetween. After the wiring member mounting step S5, a heating step S6 is performed.

[0029] In the heating step S6, the silver particles or copper particles in the first and second bonding materials are heated and sintered, or the insert metals in the first and second bonding materials are heated and alloyed, whereby the first bonding material becomes bonding layer 30, bonding layer 51, and bonding layer 52, and the second bonding material becomes bonding layer 50, thereby bonding the semiconductor chip 20 (electrode 25) to the conductor pattern 12, bonding the wiring member 40 to the electrode 23, bonding the wiring member 42 to the conductor pattern 13, and bonding the wiring member 43 to the conductor pattern 12.

[0030] During the heating, the semiconductor chip 20 may be pressed toward the conductive pattern 12, the wiring member 40 may be pressed toward the electrode 23, the wiring member 42 may be pressed toward the conductive pattern 13, and the wiring member 43 may be pressed toward the conductive pattern 12. However, the pressure applied to the semiconductor chip 20 is set to less than 1 MPa. Pressurization of the semiconductor chip 20 does not have to be performed. When a sintered layer is formed as the bonding layer 30 using the first bonding material, a pressure-free paste is used as the first bonding material so that sintering proceeds without pressure or with a small pressure.

[0031] When the above-mentioned bonding is performed, the surface of the semiconductor chip 20 does not need to be covered with a cover or the like. That is, when the above-mentioned bonding is performed, the surface of the semiconductor chip 20 may be exposed. The heating temperature in the heating step S6 is, for example, less than 300°C. The heating time in the heating step S6 is, for example, 30 minutes or more. After the heating step S6, a wire bonding step S7 is performed.

[0032] In the wire bonding step S7, wire bonding is performed to connect one end of the wiring member 41 to the conductor pattern 13 and the other end of the wiring member 41 to the electrode 24. After the wire bonding step S7, a sealant filling step S8 is performed. In the sealant filling step S8, first, the case 60 is attached to the base material 10 (insulating layer 11). Second, sealant 61 is poured into the space defined by the case 60 and the main surface 11a. At this stage, the sealant 61 is uncured. Third, heating is performed to cure the sealant 61. As a result of the above, the structure of the semiconductor device 100 shown in FIGS. 1 and 2 is formed.

[0033] (Advantages of the Manufacturing Method of the Semiconductor Device 100) The advantages of the manufacturing method of the semiconductor device 100 will be described below.

[0034] When a semiconductor chip is bonded to a substrate such as an insulating circuit board, pressure may be applied to the semiconductor chip. However, in this case, if the semiconductor substrate of the semiconductor chip is made of a material that is easily cracked, the semiconductor chip may crack due to the above-mentioned pressure. In particular, when the semiconductor substrate of the semiconductor chip is made of gallium oxide, gallium oxide is easily cracked, and the thickness of the semiconductor chip is reduced from the viewpoints of dielectric strength, on-resistance, and heat dissipation, so cracking due to the pressure applied to the semiconductor chip becomes a problem.

[0035] In this regard, in the manufacturing method of the semiconductor device 100, the pressure applied to the semiconductor chip 20 in the heating step S6 is less than 1 MPa, or no pressure is applied to the semiconductor chip 20 in the heating step S6. Therefore, according to the manufacturing method of the semiconductor device 100, even when the semiconductor substrate 21 is formed of a fragile material such as gallium oxide or when the thickness T is small, cracking of the semiconductor chip 20 can be suppressed. Note that, because the pressure applied to the semiconductor chip 20 in the heating step S6 is less than 1 MPa, or no pressure is applied to the semiconductor chip 20 in the heating step S6, there is no need to cover the surface of the semiconductor chip 20 with a sheet or the like in the heating step S6.

[0036] When the semiconductor chip 20 is mounted on the first bonding material in the semiconductor chip mounting step S3, the semiconductor chip 20 is pressed toward the first bonding material to allow the semiconductor chip 20 to fit into the first bonding material. If a force is applied to the semiconductor chip 20 using the principle of leverage from the first bonding material, the semiconductor chip 20 may crack. In this regard, in the manufacturing method of the semiconductor device 100, the value obtained by dividing the application width of the first bonding material in the first direction DR1 by the width W1 is smaller than the value obtained by dividing the application width of the first bonding material in the second direction DR2 by the width W2, making it difficult to apply a force in a direction that advances cleavage. From this perspective, the manufacturing method of the semiconductor device 100 can also suppress cracking of the semiconductor chip 20.

[0037] By applying the first bonding material so that the value obtained by dividing the application width of the first bonding material in the first direction DR1 by the width W1 is smaller than the value obtained by dividing the application width of the first bonding material in the second direction DR2 by the width W2, the value obtained by dividing the width W3 by the width W1 becomes smaller than the value obtained by dividing the width W4 by the width W2. As a result, after bonding the semiconductor chip 20, the bonding layer 30 becomes more likely to crack selectively due to stress concentration on the bonding layer 30, and cracking of the semiconductor chip 20 can be suppressed.

[0038] In the manufacturing method of the semiconductor device 100, the heating temperature in the heating step S6 is set to less than 300°C, thereby reducing the thermal stress acting on the semiconductor chip 20 and suppressing cracking of the semiconductor chip 20. Furthermore, in the manufacturing method of the semiconductor device 100, the heating time in the heating step S6 is set to 30 minutes or more, which anneals and softens the bonding layer 30, thereby reducing the stress acting on the semiconductor chip 20 and suppressing cracking of the semiconductor chip 20. In the manufacturing method of the semiconductor device 100, the semiconductor chip 20 is bonded to the base material 10 by sintering or liquid phase diffusion bonding, i.e., the bonding layer 30 is a sintered layer or a liquid phase diffusion bonding layer. The linear expansion coefficients of the sintered layer and the liquid phase diffusion bonding layer are smaller than that of a solder alloy, thereby reducing the thermal stress acting on the semiconductor chip 20 and suppressing cracking of the semiconductor chip 20.

[0039] (Variation 1) Fig. 4 is an enlarged cross-sectional view of a semiconductor device 100 according to Variation 1. As shown in Fig. 4, the semiconductor chip 20 is disposed on the conductor pattern 12 so that the electrode 23, not the electrode 25, faces the conductor pattern 12 with the bonding layer 30 interposed therebetween. That is, the semiconductor chip 20 may be flip-chip bonded to the substrate 10. In this case, in the semiconductor chip mounting step S3, the semiconductor chip 20 is mounted on the substrate 10 so that the electrode 23 faces the substrate 10 with the first bonding material interposed therebetween, that is, so that the surface of the semiconductor chip 20 faces the substrate 10 with the first bonding material interposed therebetween.

[0040] When the semiconductor chip 20 is flip-chip bonded onto the substrate 10, the bonding area between the substrate 10 and the semiconductor chip 20 is reduced. Therefore, in this case, warping of the semiconductor chip 20 is reduced, and cracking of the semiconductor chip 20 due to the warping can be suppressed.

[0041] (Variation 2) In the above example, the first bonding material applying step S2, the semiconductor chip mounting step S3, the second bonding material applying step S4, and the wiring member mounting step S5 were performed before the heating step S6, but the second bonding material applying step S4 and the wiring member mounting step S5 may be performed after the heating step S6. In this case, a heating step separate from the heating step S6 is performed, so that the bonding between the wiring member 40 and the electrode 23, the bonding between the wiring member 42 and the conductor pattern 13, and the bonding between the wiring member 43 and the conductor pattern 12 are performed separately. Alternatively, a heating step separate from the heating step S6 may be performed after the second bonding material applying step S4 and the wiring member mounting step S5, and then the first bonding material applying step S2, the semiconductor chip mounting step S3, and the heating step S6 may be performed in sequence.

[0042] 5 is a cross-sectional view of the semiconductor device 100 according to Modification 3. In the examples shown in Figures 1 and 2, the area of ​​the bonding layer 30 is smaller than the area of ​​the semiconductor chip 20 in a plan view, but the area of ​​the bonding layer 30 may be larger than or equal to the area of ​​the semiconductor chip 20 in a plan view.

[0043] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0044] 100 semiconductor device, 10 substrate, 11 insulating layer, 11a main surface, 11b main surface, 12 conductive pattern, 13 conductive pattern, 14 conductive pattern, 20 semiconductor chip, 21 semiconductor substrate, 21a main surface, 21b main surface, 22 insulating film, 23, 24, 25 electrode, 30 bonding layer, 40, 41, 42, 43 wiring member, 50, 51, 52 bonding layer, 60 case, 61 sealing material, DR1 first direction, DR2 second direction, S1 preparation step, S2 first bonding material application step, S3 semiconductor chip mounting step, S4 second bonding material application step, S5 wiring member mounting step, S6 heating step, S7 wire bonding step, S8 sealing material filling step, T thickness, W1, W2, W3, W4 width.

Claims

1. A method for manufacturing a semiconductor device, comprising: a step of applying a first bonding material onto a base material; a step of placing a semiconductor chip having a semiconductor substrate on the base material with the first bonding material interposed therebetween; and a step of bonding the semiconductor chip to the base material with the first bonding material while heating, wherein a pressure applied to the semiconductor chip is less than 1 MPa during the step of bonding the semiconductor chip to the base material with the first bonding material while heating.

2. The method for manufacturing a semiconductor device according to claim 1, wherein no pressure is applied to the semiconductor chip during the step of bonding the semiconductor chip to the base material with the first bonding material while heating.

3. The method for manufacturing a semiconductor device according to claim 1 or claim 2, wherein the semiconductor substrate is made of a compound semiconductor, and the arrangement direction of the defects in the semiconductor substrate is anisotropic.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the semiconductor substrate is made of gallium oxide.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the thickness of the semiconductor chip is less than 100 μm.

6. A method for manufacturing a semiconductor device according to any one of claims 1 to 5, further comprising the steps of: applying a second bonding material onto the semiconductor chip after the step of placing the semiconductor chip on the base material with the first bonding material interposed therebetween and before the step of bonding the semiconductor chip to the base material with the first bonding material while heating; and placing a first wiring member on the semiconductor chip with the second bonding material interposed therebetween, wherein in the step of bonding the semiconductor chip to the base material with the first bonding material while heating, the first wiring member is bonded to the semiconductor chip with the second bonding material.

7. A method for manufacturing a semiconductor device according to any one of claims 1 to 5, further comprising the steps of: applying a second bonding material onto the semiconductor chip after bonding the semiconductor chip to the substrate with the first bonding material while heating; arranging a first wiring member on the semiconductor chip with the second bonding material interposed therebetween; and bonding the first wiring member to the semiconductor chip with the second bonding material while heating.

8. A method for manufacturing a semiconductor device according to any one of claims 1 to 6, further comprising the step of bonding a second wiring member to the semiconductor chip after the step of bonding the semiconductor chip to the substrate with the first bonding material while heating.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 8, further comprising the step of encapsulating the semiconductor chip with an encapsulant.

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the outer peripheral edge of the semiconductor chip in a planar view is rectangular having a pair of first sides extending along a first direction and a pair of second sides extending along a second direction perpendicular to the first direction, the application area of ​​the first bonding material in a planar view is smaller than the area of ​​the semiconductor chip in a planar view, and the value obtained by dividing the application width of the first bonding material in the first direction by the width of the semiconductor chip is different from the value obtained by dividing the application width of the first bonding material in the second direction by the width of the semiconductor chip.

11. The method for manufacturing a semiconductor device described in claim 10, wherein the semiconductor substrate has a cleavage plane, the first direction is parallel to the cleavage plane, the second direction is perpendicular to the cleavage plane, and the value obtained by dividing the application width of the first bonding material in the first direction by the width of the semiconductor chip is smaller than the value obtained by dividing the application width of the first bonding material in the second direction by the width of the semiconductor chip.

12. The method for manufacturing a semiconductor device according to any one of claims 1 to 11, wherein the substrate is an insulating circuit board.

13. A method for manufacturing a semiconductor device according to any one of claims 1 to 12, wherein the main component of the first bonding material is silver, copper, or an intermetallic compound of silver or copper and a low-melting-point metal.

14. A method for manufacturing a semiconductor device according to any one of claims 1 to 13, wherein in the step of bonding the semiconductor chip to the substrate with the first bonding material while heating, the surface of the semiconductor chip is exposed.

15. A method for manufacturing a semiconductor device according to any one of claims 1 to 14, wherein in the step of bonding the semiconductor chip to the base material with the first bonding material while heating, the heating temperature is less than 300°C.

16. A method for manufacturing a semiconductor device according to any one of claims 1 to 15, wherein in the step of bonding the semiconductor chip to the base material with the first bonding material while heating, the heating time is 30 minutes or more.

17. A method for manufacturing a semiconductor device according to any one of claims 1 to 16, wherein in the step of bonding the semiconductor chip to the substrate with the first bonding material while heating, the first bonding material becomes a sintered layer or a liquid phase diffusion bonding layer.

18. A method for manufacturing a semiconductor device according to any one of claims 1 to 16, wherein in the step of placing the semiconductor chip on the substrate with the first bonding material interposed therebetween, the semiconductor chip is placed on the substrate so that the surface of the semiconductor chip faces the substrate with the first bonding material interposed therebetween.

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