Semiconductor thin film structure

Abstract

This semiconductor thin film structure comprises: a Si layer (102) formed on an insulating layer (101); and a semiconductor layer (103). The Si layer (102) is formed from monocrystalline Si, and the plane orientation of the main surface is (001). The semiconductor layer (103) is formed from a III-V compound semiconductor. The semiconductor layer (103) is obtained by crystal growth in a direction parallel to the surface of the insulating layer (101) from a lateral surface (104) extending in a direction inclined at an angle Θ with respect to the <110> direction of the Si layer (102). Furthermore, the lateral surface (104) is an {X11} plane of the Si layer (102), where X = 1 / tan(π / 4-Θ).

Description

Semiconductor Thin Film Structure

[0001] The present invention relates to semiconductor thin film structures.

[0002] As a technology to realize miniaturization, low power consumption, and low cost of optical transceivers, attention is being paid to the technology of integrating passive elements such as Si waveguides with active elements such as lasers, photodetectors, and modulators on Si substrates, which can be made large-diameter at low cost. Until now, mature Si microfabrication technology has already realized the technology to monolithically integrate small, low-loss Si optical waveguide elements, photodetectors, modulators, etc. on large-diameter Si substrates.

[0003] Regarding the integration of lasers on Si substrates, it has been difficult to fabricate lasers using indirect transition semiconductors such as Si and Ge, which have been used in conventional silicon platforms, and there has been a problem in that a different material, a direct transition semiconductor such as a III-V compound semiconductor, must be integrated. However, a thin-film structure laser integration has been realized, as shown in Non-Patent Document 1. In this structure, the thickness of the III-V compound semiconductor layer on Si is typically set to 350 nm or less so that it does not exceed the critical thickness. In this case, the effective refractive index of the III-V compound semiconductor layer is roughly matched to the effective refractive index of a 220 nm thick Si waveguide commonly used in the field of silicon photonics, which has the advantage of facilitating optical coupling between the III-V compound semiconductor layer and the Si waveguide.

[0004] The above-described Si waveguide-coupled thin-film laser integration has been realized using so-called heterogeneous integration techniques, such as direct bonding and transfer printing. However, unlike monolithic integration, processing steps using heterogeneous integration techniques such as direct bonding require the use of expensive, small-sized III-V compound semiconductor substrates, which creates bottlenecks in material costs and throughput. To resolve these bottlenecks, the realization of monolithic integration of high-performance thin-film semiconductor laser structures, as shown in Non-Patent Document 1, is desired.

[0005] On the other hand, because Si and III-V compound semiconductors have different lattice constants and thermal expansion coefficients, it is generally difficult to monolithically integrate high-quality III-V compound semiconductors on Si. One solution to this problem is to insert a thick buffer layer of several micrometers on Si. However, the presence of this buffer layer has the fatal drawback of making it difficult to optically couple the active layer to the Si optical circuit layer. Therefore, it is necessary to integrate high-quality III-V compound semiconductors on a thin-film buffer or without a buffer. As a solution to this problem, the lateral aspect ratio trapping (ART) growth method on the {111} plane of silicon has recently attracted attention (Non-Patent Document 2).

[0006] This technology forms a hollow structure surrounded by a top selective growth mask, a bottom BOX layer of an SOI (silicon-on-insulator) substrate, and side Si{111} planes. Lateral selective growth of III-V compound semiconductors is then performed starting from the Si{111} planes. Growth starting from the Si{111} planes, which forms a double-step structure, suppresses anti-phase boundaries (APBs). Lateral selective growth in a trench structure with a longer horizontal width (w) than the vertical width (h) of the hollow structure is expected to terminate threading dislocations generated at the Si / III-V compound semiconductor interface onto the top and bottom selective growth masks. This technology enables the integration of III-V compound semiconductor crystals free of APBs and threading dislocations via an ultrathin buffer layer that is essentially bufferless. This may also enable the integration of III-V optical devices fabricated using this structure with Si optical circuit layers.

[0007] Fabrication techniques based on this technology have been used to demonstrate Si waveguide-coupled photodiodes (PDs) (Non-Patent Document 3) and optically injected distributed feedback (DFB) lasers (Non-Patent Document 4). However, current injection lasers have yet to be demonstrated. To achieve this, efforts are needed to improve this technology and further increase the quality and yield of III-V compound semiconductor crystal integration.

[0008] Furthermore, although the background to the above has been explained with application to optical devices in mind, this technology can also be applied to the monolithic integration on Si of electronic devices such as transistors that utilize heterojunctions made of III-V compound semiconductors.

[0009] T. Aihara, T. Hiraki, T. Fujii, K. Takeda, T. Kakitsuka, T. Tsuchizawa, and S. Matsuo, "Membrane III-V / Si DFB Laser Using Uniform Grating and Width-Modulated Si Waveguide," J. Lightwave Technol. 38, 2961-2967 , 2020.Yu Han, Ying Xue, Kei May Lau; Selective lateral epitaxy of dislocation-free InP on silicon-on-insulator. Appl. Phys. Lett. 13 May 2019.P. Wen, P. Tiwari, S. Mauthe, H. Schmid, M. Sousa, M. Scherrer, M. Baumann, B.I. Bitachon, J. Leuthold, B. Gotsmann, K.E. Moselund, “Waveguide coupled III-V photodiodes monolithically integrated on Si,” Nature Communications, 13(1), pp.1-11, 2022.Y. Xue, J. Li, Y. Wang, K. Xu, Z. Xing, K. S. Wong, H. K. Tsang, K. M. Lau, In-Plane 1.5 μm Distributed Feedback Lasers Selectively Grown on (001) SOI. Laser Photonics Rev 2024, 18, 2300549.S. C. Lee, L. R. Dawson, S. R. J. Brueck, Y.-B. Jiang; GaAs on Si(111)-crystal shape and strain relaxation in nanoscale patterned growth. Appl. Phys. Lett. 11 July 2005; 87 (2): 023101.T. S. Kuan, S. S.Iyer; Strain relaxation and ordering in SiGe layers grown on (100), (111), and (110) Si surfaces by molecular‐beam epitaxy. Appl. Phys. Lett. , 59 (18), 1991.

[0010] When III-V compound semiconductors are grown laterally on a Si {111} surface using the lateral ART method, the occurrence of APBs is suppressed at the interface between the Si {111} surface and the III-V compound semiconductor layer, but rotational twins occur with a certain frequency. The occurrence of rotational twins in III-V compound semiconductor growth on a Si {111} surface is not limited to the lateral ART method, but is a phenomenon that generally occurs during lattice-mismatched heteroepitaxy on the Si {111} surface (Non-Patent Documents 5 and 6).

[0011] As shown in Figure 11, growth nuclei (microcrystals) 301 of III-V compound semiconductors are generated sparsely on the Si{111} plane in the initial stage of crystal growth. Rotational twins 302 occur with a certain frequency, resulting in a mixture of III-V compound semiconductor microcrystals 303 whose crystal orientation is aligned with that of the Si seed crystal and III-V compound semiconductor microcrystals 304 whose crystal orientation is not aligned. During the crystal growth process, the microcrystals 303 and 304 combine to form a III-V compound semiconductor thin film 305, which becomes polycrystalline. Once the thin film 305 has become polycrystalline, it becomes extremely difficult to apply it to optical devices, including lasers.

[0012] In order to suppress the polycrystallization of III-V compound semiconductors, it is necessary to solve the problem of the occurrence of rotational twins at the interface between the Si surface and the III-V compound semiconductor.

[0013] The present invention has been made to solve the above problems, and has as its object to suppress the occurrence of rotational twins at the interface between the Si surface and the III-V compound semiconductor.

[0014] The semiconductor thin film structure according to the present invention includes a Si layer formed on an insulating layer and made of single-crystal Si with a (001) plane orientation on a main surface, and a semiconductor layer made of a III-V compound semiconductor crystal-grown in a direction parallel to the surface of the insulating layer from a side surface extending in a direction tilted at an angle Θ with respect to the <110> direction of the Si layer, the side surface being the {X11} plane [X=1 / tan(π / 4-Θ)] of the Si layer.

[0015] As described above, according to the present invention, a semiconductor layer made of a III-V compound semiconductor is provided, which is crystal-grown from a side surface of a Si layer having a (001) plane orientation and an {X11} plane [X=1 / tan(π / 4−Θ)] of the Si layer, and therefore, the generation of rotational twins at the interface between the Si surface and the III-V compound semiconductor can be suppressed.

[0016] FIG. 1 is a cross-sectional view (a) and a plan view (b) illustrating the configuration of a semiconductor thin film structure according to an embodiment of the present invention. FIG. 2A is a cross-sectional view (a) and a plan view (b) illustrating a method for fabricating a semiconductor thin film structure according to an embodiment of the present invention. FIG. 2B is a cross-sectional view (a) and a plan view (b) illustrating a method for fabricating a semiconductor thin film structure according to an embodiment of the present invention. FIG. 3 is an explanatory diagram illustrating the growth of a III-V compound semiconductor on a Si{211} plane (a) and a Si{511} plane (b). FIG. 4 is an optical microscope image of InP grown using the {X11} side surface of a Si layer. FIG. 5A is a cross-sectional view (a) and a plan view (b) illustrating the state of a laser in an intermediate process for illustrating a method for fabricating a laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 5B is a cross-sectional view (a) and a plan view (b) illustrating the state of a laser in an intermediate process for illustrating a method for fabricating a laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 5C is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 5D is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 5E is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 5F is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 5G is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 5H is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 5I is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a laser using a semiconductor thin film structure according to an embodiment of the present invention.FIG. 5J is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 5K is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 6 is a cross-sectional view showing the configuration of a laser fabricated using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 7 is an optical microscope image (a) and a cross-sectional SEM image (b) showing the results of observing the state of an opening formed using tetramethyl ammonium hydroxide (TMAH). FIG. 8 is an explanatory diagram illustrating how to determine the plane orientation of the side surface 104. FIG. 9A is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining another method for manufacturing a laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 9B is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining another method for manufacturing a laser using a semiconductor thin film structure according to an embodiment of the present invention. 9C is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing another laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 9D is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing another laser using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 10 is a cross-sectional view showing the configuration of another laser fabricated using a semiconductor thin film structure according to an embodiment of the present invention. FIG. 11 is an explanatory diagram showing the growth state of a III-V group compound semiconductor on a Si{111} plane at the initial stage of crystal growth.

[0017] A semiconductor thin film structure according to an embodiment of the present invention will be described below with reference to Fig. 1. This semiconductor thin film structure comprises an Si layer 102 formed on an insulating layer 101, and a semiconductor layer 103.

[0018] The Si layer 102 is made of single-crystal Si, and the plane orientation of the main surface is (001). The semiconductor layer 103 is made of a III-V compound semiconductor. The semiconductor layer 103 undergoes crystal growth in a direction parallel to the surface of the insulating layer 101 from a side surface 104 extending in a direction inclined at an angle Θ with respect to the <110> direction of the Si layer 102. The side surface 104 is the {X11} plane of the Si layer 102, where X = 1 / tan(π / 4 - Θ). The angle Θ of the side surface 104 with respect to the <110> direction of the Si layer 102 can be in the range of 15° / 180°×π≦Θ≦32° / 180°×π.

[0019] For example, by using a well-known SOI substrate, the side surface 104 of the Si layer 102 can be formed as the {X11} plane of the Si layer 102 .

[0020] First, as shown in FIG. 2A , an SOI substrate is prepared that includes an insulating layer 101 as a buried insulating layer on a base portion 111 and a Si layer 102 as a surface Si layer. Next, an upper insulating layer 121 that serves as a selective growth mask is formed on the Si layer 102. An opening 121a is also formed in the upper insulating layer 121. The opening 121a penetrates the Si layer 102 to expose the surface of the insulating layer 101. Here, the opening 121a is formed in a rectangular shape when viewed from the normal direction to the plane of the insulating layer 101, with the long side of the rectangle tilted by Θ (where 0<Θ<π / 4) from the <110> direction. The relationship between X and Θ can be expressed by the relational equation X = 1 / tan(π / 4 - Θ).

[0021] The Si layer 102 is etched (side-etched) through the opening 121a formed in this manner using an anisotropic Si etchant, thereby forming a space 121b between the insulating layer 101 and the upper insulating layer 121, as shown in FIG. 2B , and a side surface 104 of the Si layer 102 that is the {X11} plane. As will be described later, the side surface 104 that is the {311} plane can be formed by appropriately setting conditions. Note that the lower surface of the upper insulating layer 121 on the insulating layer 101 side is parallel to the surface of the insulating layer 101, and a space 121b is formed therebetween. The semiconductor layer 103 grows in the space 121b thus formed. In this case, the semiconductor layer 103 is formed between the insulating layer 101 and the upper insulating layer 121.

[0022] Here, we will explain the effect of suppressing anti-phase boundaries (APBs) and rotational twins when growing a III-V compound semiconductor using Si with an exposed {X11} plane as a starting point (seed crystal).

[0023] First, the APB suppression effect will be explained. As described in Reference 1, when GaAs, a III-V compound semiconductor with a zinc-blende structure, is grown on Ge with a (113) surface, APBs self-annihilate within a few atomic layers from the growth interface, and the propagation of APBs in the growth direction is suppressed. A similar effect is thought to be obtained when InP is grown on a Si (113) surface.

[0024] Next, we will explain the suppression of rotational twins. As shown in Reference 2, rotational twins can sometimes occur when semiconductors with diamond or zinc blende structures are grown on the Si {111} plane, as a result of the zinc blende stacking being rotated by 60° in-plane. In other words, rotational twins cannot occur structurally when growing on a plane other than the {111} plane.

[0025] The suppression of APB and rotational twinning is not limited to the growth on the (131) plane described above, but also functions in the case of growth of III-V compound semiconductors on Si{X11} planes such as Si{211} and Si{511}, as shown in FIG. 3.

[0026] We will consider, based on experimental results, in which range of 0 < Θ < π / 4 APBs and rotational twins are actually suppressed when InP is grown using the {X11} plane side of the Si layer. When the surface of InP containing APBs or rotational twins is etched with sulfuric acid, etch pits with unique characteristics for each defect are generated. The presence or absence of defects can be determined by checking for the presence or absence of etch pits with each characteristic.

[0027] As shown in Figure 4, if the range of Θ is between 15° / 180°×π≦Θ≦32° / 180°×π (15° to 32° in terms of angle), no etch pits due to APBs and rotational twins are observed over a sufficiently wide region, for example, about 50 μm, and the defect suppression effect is functioning. However, since whether defects occur or not depends on the growth conditions, it should be noted that defects are not necessarily suppressed within the above-mentioned effective range.

[0028] Based on the experimental results and various defect suppression mechanisms described above, according to the embodiment, not only the ART effect and the APB suppression effect but also the rotational twin suppression effect can be obtained, and as a result, it becomes possible to grow a high-quality III-V compound semiconductor in which polycrystallization is suppressed.

[0029] Next, a method for manufacturing a laser using the semiconductor thin film structure according to the embodiment will be described with reference to Figures 5A to 5K. In Figures 5A to 5K, (a) shows a cross section taken along line aa' in the plan view shown in (b).

[0030] First, an SOI substrate is prepared that includes an insulating layer 101 as a buried insulating layer on a base portion 111 and an Si layer 102 as a surface Si layer, and the Si layer 102 is patterned as shown in Fig. 5A. The edge of the Si layer 102 is patterned so that it is tilted at an angle Θ from the <110> orientation of the Si layer 102. Next, as shown in Fig. 5B, an upper insulating layer 121 made of, for example, SiO2 is formed on the Si layer 102.

[0031] 5C, opening 121a is formed. Opening 121a is formed in a rectangular shape when viewed from the normal direction of the plane of insulating layer 101, with the long side of the rectangle tilted by Θ (where 0<Θ<π / 4) from the <110> direction. The opening width of opening 121a in the long side direction can be set to, for example, approximately the resonator length of the laser to be formed, e.g., 50 μm.

[0032] 5D , the Si layer 102 is side-etched using an anisotropic etchant to form a space 121b between the insulating layer 101 and the upper insulating layer 121, and a side surface 104, which is the {X11} plane of the Si layer 102, is formed at the back of the space 121b. The depth of the space 121b to the location where the side surface 104 is formed can be, for example, about 10 μm.

[0033] 5E, a semiconductor layer 103 made of a III-V compound semiconductor is grown laterally starting from the side surface 104. The semiconductor layer 103 may be made of, for example, InP.

[0034] 5F, an upper opening 121c is formed by opening a portion of upper insulating layer 121 above semiconductor layer 103, thereby exposing the upper surface of semiconductor layer 103. Here, semiconductor layer 103 can be further thinned using a known etching technique or the like in accordance with the desired laser structure.

[0035] Next, as shown in FIG. 5G, crystal growth of a semiconductor layer 105 for forming an active layer is performed in the direction perpendicular to the substrate (thickness direction) starting from the upper surface of the semiconductor layer 103. The active layer can be, for example, an InGaAsP bulk, a multi-quantum well (MQW) made of InGaAsP / InGaAsP, or an MQW made of InGaAs / InP. It is also possible to form a double heterostructure by forming an upper semiconductor layer 106 made of InP, whose energy gap is larger than that of the material of the barrier layer of the MQW, on the active layer.

[0036] Next, in order to form a buried heterostructure (BH) of the active layer by selective growth, an insulating material layer for forming a hard mask made of an insulating material such as SiO is formed, and this layer is patterned by dry etching or the like to form a hard mask 107, as shown in Fig. 5H. The dimensions of the hard mask 107 can be determined taking into consideration the dimensions of the desired laser structure, etc.

[0037] Next, a dry etching process using the hard mask 107 as a mask is performed to form a core-shaped active layer 105a and an upper semiconductor layer 106, as shown in Fig. 5I. Next, buried regrowth is performed on the semiconductor layer 103 on the sides of the active layer 105a, and the active layer 105a is buried with a semiconductor layer 108, as shown in Fig. 5J. For example, the buried growth can be performed using InP.

[0038] Thereafter, for example, by ion implantation and thermal diffusion, an n-type impurity is introduced into the semiconductor layer 108 on one side of the active layer 105a, and a p-type impurity is introduced into the semiconductor layer 108 on the other side of the active layer 105a, thereby forming an n-type layer 108a and a p-type layer 108b, as shown in Fig. 5K. An n-electrode 109a and a p-electrode 109b are formed on the n-type layer 108a and the p-type layer 108b via contact layers 108c and 108d, respectively. A diffraction grating 110 is formed above the active layer 105a, and an insulating layer 112 is formed thereon, thereby completing the thin-film semiconductor laser shown in Fig. 6A.

[0039] 6B, an optical waveguide made of a Si core 102a is formed in another region on the insulating layer 101. Here, the extension direction (waveguiding direction) of the active layer 105a of the semiconductor laser formed as described above is formed to be inclined at an angle Θ from the <110> direction of the Si layer 102 in a plan view, and the crystal orientation is aligned with the Si layer 102. For this reason, the optical waveguide made of the Si core 102a formed in another region can be formed by butt joints or SiO x Optical coupling can be achieved through an optical waveguide with a core made of SiON or the like.

[0040] Although the above description omits the process of removing the portion of the Si layer 102 that is continuous with the side surface 104, it is possible to remove the portion by etching, for example, after growing the semiconductor layer 103 laterally starting from the side surface 104.

[0041] Next, FIG. 7 shows an example of the state after side etching of Si using tetramethyl ammonium hydroxide (TMAH) as an anisotropic etchant for forming the side surface 104. FIG. 7(a) is an optical microscope image, and FIG. 7(b) is a cross-sectional SEM image. The angle Θ was set to 26.5°. As shown in FIG. 7(a), the Si surface after side etching has a linear shape and is parallel to the edge of the opening 121a in the upper insulating layer 121, indicating that the Si surface is formed from a single plane orientation.

[0042] 8, if the angle formed between the underlying insulating layer 101 and the side surface 104 is α and the angle formed between the insulating layer (BOX) 101 and the side surface 104 observed in the cross-sectional SEM image is β, the relationship between these parameters is expressed by the following equation: Since β can be determined from the SEM image, α and C can be found.

[0043]

[0044] When the plane orientation of the side surface 104 is calculated by applying the measured value of 71° for β to this relational expression, it is found that the (3-11) plane (X=3) is exposed in the above process.

[0045] Next, another method for manufacturing a laser using the semiconductor thin film structure according to the embodiment will be described with reference to Figures 9A to 9D. First, as described with reference to Figures 5A to 5D, a space 121b is formed between the insulating layer 101 and the upper insulating layer 121, and a side surface 104 of the Si layer 102, which is the {X11} plane, is formed at the back of the space 121b.

[0046] 9A, a p-type semiconductor layer 103c, an active layer 103b, and an n-type layer 103a made of III-V compound semiconductor are sequentially grown laterally starting from the side surface 104. During the growth of the p-type layer 103c and the n-type layer 103a, dopants are added to impart each conductivity type. In this example, a pin junction is formed by adding dopants during the lateral growth of the III-V compound semiconductor starting from the side surface 104.

[0047] It should be noted that the lateral growth described above refers to growth in the <X10> direction, i.e., growth in the direction of a high-index plane. Generally, when crystal growth is performed in a direction perpendicular to a high-index plane, unstable high-index planes are unlikely to form facets, and a phenomenon known as faceting occurs, in which facets are formed by the combination of multiple low-index planes (Reference 3). Therefore, as shown in Reference 3, it is important to suppress faceting by appropriately adjusting growth parameters such as the growth temperature and V / III ratio. It is important to optimize the growth conditions and grow a plane (flat surface) perpendicular to the growth direction in a planar view as a facet, thereby forming a linear active layer 103b.

[0048] 9B, upper insulating layer 121 is partially opened above n-type layer 103 a, active layer 103 b, and p-type layer 103 c to form upper opening 121 c, thereby exposing the top surfaces of n-type layer 103 a, active layer 103 b, and p-type layer 103 c. The dimensions of upper opening 121 c can be determined according to the desired laser structure.

[0049] Next, as shown in Fig. 9C, an upper semiconductor layer 103d that functions as an upper cladding layer is formed on the active layer 103b by, for example, regrowth. Next, a diffraction grating 110 is formed on the upper semiconductor layer 103d. The upper semiconductor layer 103d can be made of, for example, InP. Thereafter, as shown in Fig. 9D, an n-electrode 109a and a p-electrode 109b are formed on the n-type layer 103a and the p-type layer 103c, respectively, to form the thin-film semiconductor laser shown in Fig. 10(a).

[0050] To establish ohmic contact with the p-electrode 109b, the p-type layer 103c can be made of, for example, InGaAs or InGaAsP with a high As composition. Note that in this example, the active layer 103b is in contact with the underlying insulating layer 101. Furthermore, an n-electrode 109a and a p-electrode 109b can be formed on the n-type layer 103a and the p-type layer 103c via contact layers for current injection.

[0051] 10B, an optical waveguide made of a Si core 102a is formed in another region on the insulating layer 101. Here, the extension direction (waveguiding direction) of the active layer 105a of the semiconductor laser formed as described above is formed at an angle Θ from the <110> direction of the Si layer 102 in a plan view, and the crystal orientation is aligned with the Si layer 102. For this reason, the optical waveguide made of the Si core 102a formed in another region can be formed by butt joints or SiO x Optical coupling can be achieved through an optical waveguide with a core made of SiON or the like.

[0052] Furthermore, a field effect transistor can be fabricated using the semiconductor thin film structure according to the embodiment as follows.

[0053] 5A to 5C, an upper insulating layer is formed on the Si layer on the insulating layer, and an opening is formed in the upper insulating layer. The width of the opening in the long side direction may be approximately the same as the dimension in the gate length direction of the transistor to be formed, and may be, for example, 50 μm.

[0054] 5D, a space is formed between the insulating layer and the upper insulating layer, and a side surface of the Si layer, which is the {X11} plane, is formed at the back of the space. The depth to the location where the side surface of the space is formed can be, for example, about 10 μm.

[0055] In a manner similar to that described with reference to FIG. 5E, a semiconductor layer made of a III-V compound semiconductor is grown laterally, starting from the {X11} side surface of the Si layer. The semiconductor layer can be, for example, InP. Next, in a manner similar to that described with reference to FIG. 5F, an opening is formed in a portion of the upper insulating layer above the laterally grown semiconductor layer, thereby exposing the top surface of the semiconductor layer. Here, an opening having an area required for transistor fabrication may be appropriately formed.

[0056] Next, a semiconductor heterojunction structure constituting a heterojunction field-effect transistor is deposited on the semiconductor layer exposed through the opening by a crystal growth method. For example, a 10 nm thick InP buffer layer, a 200 nm thick InAlAs buffer layer, a 15 nm thick InGaAs channel layer, a 10 nm thick InAlAs barrier layer, a 5 nm thick InP recess etching stop layer, a 20 nm thick InAlAs contact layer, and a 20 nm thick InGaAs contact layer are sequentially deposited on the InP semiconductor layer. The barrier layers and contact layers may be doped with Si as appropriate to achieve desired transistor characteristics.

[0057] Next, a gate electrode, a source electrode, and a drain electrode are formed on the heterojunction stacked as described above using a known technique, for example, as described in Reference 4, to obtain a heterojunction field effect transistor. While the heterojunction field effect transistor has been described above as an example, a heterojunction stacked structure, such as a stacked structure constituting a heterojunction bipolar transistor, can also be formed by a crystal growth method. In this case, a heterojunction bipolar transistor can also be fabricated by forming appropriate electrodes using known techniques.

[0058] As described above, according to the embodiment of the present invention, a semiconductor layer made of a III-V compound semiconductor is provided, which is crystal-grown from a side surface of a Si layer having a (001) plane orientation and an {X11} plane [X=1 / tan(π / 4−Θ)] of the Si layer, and therefore, it is possible to suppress the generation of rotational twins at the interface between the Si surface and the III-V compound semiconductor.

[0059] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0060] [Literature] [Reference 1] Xiangmeng Lu, Naoto Kumagai, Yasuo Minami and Takahiro Kitada; Sublattice reversal in GaAs / Ge / GaAs heterostructures grown on (113)B GaAs substrates. Appl. Phys. Express 1 November 2018; 11 (1): 015501. [Reference 2] F. Ernst, P. Pirouz; Formation of planar defects in the epitaxial growth of GaP on Si substrate by metal organic chemical‐vapor deposition. J. Appl. Phys. 1 November 1988; 64 (9): 4526-4530. [Reference 3] Masanori Yamamoto Masanori Yamamoto, Masataka Higashiwaki Masataka Higashiwaki, Satoshi Shimomura Satoshi Shimomura, Naokatsu Sano Naokatsu Sano and Satoshi Hiyamizu Satoshi Hiyamizu; Surface Corrugation of GaAs Layers Grown on (775)B-Oriented GaAs Substrates by Molecular Beam Epitaxy. 1997 Jpn. J. Appl. Phys. 36 6285. [Reference 4] Takatomo Enoki, Haruki Yokoyama, Yohtaro Umeda and Taiichi Otsuji: “Ultrahigh-Speed Integrated Circuits Using InP-Based HEMTs” Japanese Journal of Applied Physics, 37, 1359 (1998).

[0061] 101... Si layer, 102... Si layer, 103... semiconductor layer, 104... side surface.

Claims

1. A semiconductor thin film structure comprising: a Si layer formed on an insulating layer and made of single-crystal Si with a (001) plane orientation on its main surface; and a semiconductor layer made of a III-V compound semiconductor grown in a direction parallel to the surface of the insulating layer from a side surface of the Si layer extending in a direction tilted at an angle Θ with respect to the <110> direction, wherein the side surface is the {X11} plane [X=1 / tan(π / 4-Θ)] of the Si layer.

2. A semiconductor thin film structure according to claim 1, wherein the side surface has an angle Θ with respect to the <110> direction of the Si layer in the range of 15° / 180°×π≦Θ≦32° / 180°×π.

3. A semiconductor thin film structure according to claim 1 or 2, further comprising an upper insulating layer formed on the Si layer and extending laterally from the side surface in a direction parallel to the surface of the insulating layer, and the semiconductor layer is formed between the insulating layer and the upper insulating layer.

4. A semiconductor thin film structure according to claim 3, wherein the lower surface of said upper insulating layer on said insulating layer side is parallel to the surface of said insulating layer.

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