Semiconductor device and method for manufacturing same

Abstract

A semiconductor device (1) comprises: a semiconductor substrate (12); a metal electrode (13) that is provided on the semiconductor substrate; a protective film (18) that is provided on the semiconductor substrate, that covers the outer peripheral edge of the metal electrode, and that has formed therein an opening (18a) for exposing a portion of the metal electrode; a plating electrode (14) that is provided on the metal electrode exposed through the opening of the protective film; and a solder layer (34) provided on the plating electrode. The protective film has a polyimide film (17) and an interposed film (16) that is interposed between the polyimide film and the metal electrode and that is made of a material different from that of the polyimide film. In the inner circumferential surface that defines the opening of the protective film, the inner circumferential surface (17a) of the polyimide film is located at a more recessed position relative to the inner circumferential surface (16a) of the interposed film.

Description

Semiconductor device and manufacturing method thereof CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a related application of Japanese Patent Application No. 2024-102039 filed on June 25, 2024, and claims priority based on this Japanese patent application, the entire contents of which are incorporated herein by reference.

[0002] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

[0003] A metal electrode functioning as a pad is provided on the upper surface of the semiconductor substrate. The outer periphery of the metal electrode is covered with a polyimide protective film, and a portion of the metal electrode located inside the protective film is exposed through an opening in the protective film. A conductor block is joined to the metal electrode exposed through the opening in the protective film via a plated electrode and a solder layer. In a semiconductor device having such a structure, the lower edge of the inner periphery defining the opening in the protective film contacts both the metal electrode and the plated electrode, forming a triple point where the protective film, the metal electrode, and the plated electrode contact each other. As described in Japanese Patent Application Laid-Open No. 2023-105546, it is known that stress strain is large near the triple point of the metal electrode when exposed to a thermal cycle.

[0004] The present specification provides a technique for reducing the maximum stress strain near the triple point where the protective film, the metal electrode, and the plated electrode contact each other.

[0005] The semiconductor device disclosed herein may include a semiconductor substrate, a metal electrode provided on the semiconductor substrate, a protective film provided on the semiconductor substrate, covering the outer periphery of the metal electrode and having an opening exposing a portion of the metal electrode, a plated electrode provided on the metal electrode exposed through the opening in the protective film, and a solder layer provided on the plated electrode. The protective film may include a polyimide film and an intervening film made of a material different from the polyimide film, interposed between the polyimide film and the metal electrode. At an inner periphery defining the opening in the protective film, the inner periphery of the polyimide film may be recessed from the inner periphery of the intervening film.

[0006] In the semiconductor device described above, the inner peripheral surface of the polyimide film is recessed from the inner peripheral surface of the interposing film, so that the polyimide film is positioned away from the metal electrode. With this structure, stress strain near the triple point where the protective film, metal electrode, and plated electrode meet is dispersed, reducing the maximum stress strain.

[0007] The method for manufacturing a semiconductor device disclosed in this specification may include the steps of forming a metal electrode on a semiconductor substrate, and forming a protective film on the semiconductor substrate by covering the metal electrode, where the protective film is composed of a laminate of an intervening film and a polyimide film, forming a protective film, removing a portion of the polyimide film to form an opening and exposing the intervening film from the opening, and removing the intervening film exposed from the opening by isotropic etching to expose the metal electrode.

[0008] According to the above-described manufacturing method, the intervening film can be etched using the polyimide film as a mask. Furthermore, when the intervening film is removed by isotropic etching to expose the metal electrode, the inner peripheral surface of the polyimide film is also etched at the same time. Therefore, the polyimide film can be processed so that the inner peripheral surface of the polyimide film is recessed from the inner peripheral surface of the intervening film. According to the above-described manufacturing method, the semiconductor device disclosed in this specification can be manufactured with a small number of steps.

[0009] 1. A diagram showing a schematic cross-sectional view of a semiconductor device. FIG. 2 is an enlarged cross-sectional view of a main part of a semiconductor element mounted on the semiconductor device, corresponding to the area surrounded by the dashed line "II" in FIG. 1. FIG. 3 is a diagram showing the relationship between offset distance and metal electrode distortion. FIG. 4 is an enlarged cross-sectional view of a main part of a semiconductor element mounted on a semiconductor device of a modified example, corresponding to the area surrounded by the dashed line "II" in FIG. 1. FIG. 5 is an enlarged cross-sectional view of a main part of an example of an intervening film. FIG. 6 is an enlarged cross-sectional view of a main part of an example of an intervening film. FIG. 7 is an enlarged cross-sectional view of a main part of an example of an intervening film. FIG. 8 is an enlarged cross-sectional view of a main part of an example of an intervening film. FIG. 9 is an enlarged cross-sectional view of a main part of an example of an intervening film. FIG. 10 is an enlarged cross-sectional view of a main part of an example of an intervening film. FIG. 11 is an enlarged cross-sectional view of a main part of an example of an intervening film.

[0010] In this specification, expressions such as "upper," "lower," "upper surface," and "lower surface" are used for convenience to indicate positional relationships in opposite directions and do not limit the orientation of the semiconductor device during use or manufacture. For example, the upper surface of a semiconductor substrate simply refers to one of a pair of main surfaces of the semiconductor substrate, and the lower surface of a semiconductor substrate simply refers to the other main surface of the semiconductor substrate located opposite the upper surface. Furthermore, in this specification, expressions such as "inside" and "outside" refer to the direction toward the center of the semiconductor substrate as the inside and the direction toward the periphery as the outside when viewed from a direction perpendicular to the main surface of the semiconductor substrate.

[0011] The semiconductor device of this embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is not particularly limited, and may be used, for example, in a power conversion device mounted on an electric vehicle. Here, an electric vehicle broadly refers to a vehicle that runs on a road surface and has a traction motor that drives the wheels. Examples of such electric vehicles include hybrid vehicles, fuel cell vehicles, and rechargeable electric vehicles.

[0012] As shown in FIG. 1, the semiconductor device 1 includes a semiconductor element 10 and a sealing body 20 that seals the semiconductor element 10. For the purpose of clarity, hatching of the sealing body 20 has been omitted. In this example, one semiconductor element 10 is sealed within the sealing body 20. Alternatively, the semiconductor device 1 may include a plurality of semiconductor elements 10. In this case, the plurality of semiconductor elements 10 may be connected to form a parallel circuit or a series circuit.

[0013] The semiconductor element 10 includes a semiconductor substrate 12 having an upper surface 12a and a lower surface 12b, a lower electrode 11 covering the lower surface 12b of the semiconductor substrate 12, an upper electrode 15 covering a portion of the upper surface 12a of the semiconductor substrate 12, and a protective film 18 provided on the upper surface 12a of the semiconductor substrate 12 and covering the outer periphery of the upper electrode 15. The semiconductor element 10 is not particularly limited, but may be, for example, a power semiconductor element. Examples of power semiconductor elements include diodes, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and IGBTs (Insulated Gate Bipolar Transistors). Various semiconductor regions and gate structures for constituting the power semiconductor element are formed on the semiconductor substrate 12. The semiconductor substrate 12 is not particularly limited, but may be composed of a semiconductor material such as silicon, silicon carbide, or a nitride semiconductor.

[0014] The sealing body 20 is made of an insulating material. The insulating material that makes up the sealing body 20 is not particularly limited, but may be, for example, a thermosetting resin material such as an epoxy resin.

[0015] The semiconductor device 1 further includes a lower conductor plate 22, an upper conductor plate 24, and a conductor block 26. The lower conductor plate 22 is bonded to the lower electrode 11 of the semiconductor element 10. More specifically, the lower conductor plate 22 is bonded to the lower electrode 11 of the semiconductor element 10 via a solder layer 32. The lower conductor plate 22 may be made of a metal such as, but not limited to, copper. As a result, the lower conductor plate 22 is electrically connected to the semiconductor element 10 and constitutes part of the electrical circuit in the semiconductor device 1. The lower conductor plate 22 is exposed on the lower surface 20a of the encapsulant 20 and also functions as a heat sink that dissipates heat generated by the semiconductor element 10 to the outside of the encapsulant 20.

[0016] The upper conductor plate 24 is bonded to the top electrode 15 of the semiconductor element 10 via a conductor block 26. More specifically, the upper conductor plate 24 and the conductor block 26 are bonded via a solder layer 36, and the conductor block 26 is bonded to the top electrode 15 of the semiconductor element 10 via a solder layer 34. The upper conductor plate 24 and the conductor block 26 may be made of, but are not limited to, a metal such as copper. As a result, the upper conductor plate 24 is electrically connected to the semiconductor element 10 via the conductor block 26 and forms part of the electrical circuit in the semiconductor device 1. The upper conductor plate 24 is exposed on the top surface 20b of the encapsulant 20 and also functions as a heat sink that dissipates heat from the semiconductor element 10 to the outside. That is, the semiconductor device 1 of this embodiment has a double-sided cooling structure in which heat sinks are exposed on both surfaces 20a and 20b of the encapsulant 20.

[0017] FIG. 2 is a schematic enlarged cross-sectional view of the area enclosed by the dashed line "II" in FIG. 1 . The top electrode 15 provided on the top surface 12a of the semiconductor substrate 12 is composed of a metal electrode 13 and a plating electrode 14 stacked together. The metal electrode 13 is provided on a portion of the top surface 12a of the semiconductor substrate 12 and may have, for example, a rectangular shape when the semiconductor substrate 12 is viewed from above. The metal electrode 13 may be made of, but is not limited to, a material containing aluminum. An example of an aluminum-containing material is aluminum silicon (AlSi). The plating electrode 14 coats the top surface of the metal electrode 13 and is provided to improve the wettability of the solder layer 34. The plating electrode 14 may be made of, but is not limited to, a material containing nickel. The top surface of the plating electrode 14 may also be coated with gold.

[0018] The outer periphery of the metal electrode 13 of the upper electrode 15 is covered with a protective film 18 (see FIG. 1 ). The protective film 18 is provided around the metal electrode 13 along the outer periphery of the metal electrode 13. For this reason, an opening 18a is formed in the protective film 18, and the central portion of the metal electrode 13 is exposed through the opening 18a. The metal electrode 13 exposed through the opening 18a in the protective film 18 is not covered with the protective film 18, and its upper surface is covered with the plated electrode 14.

[0019] The protective film 18 includes an intervening film 16 and a polyimide film 17. The intervening film 16 covers a portion of the upper surface of the metal electrode 13 and is provided between the metal electrode 13 and the polyimide film 17 to separate the metal electrode 13 and the polyimide film 17. The intervening film 16 is made of a material different from that of the polyimide film 17. The intervening film 16 is not particularly limited, but may be made of a material having a smaller linear expansion coefficient than the polyimide film 17. An example of the material for the intervening film 16 is silicon nitride (SiN). The thickness of the intervening film 16 is smaller than the thickness of the polyimide film 17. The polyimide film 17 covers the upper surface of the intervening film 16 and is stacked on the intervening film 16.

[0020] The inner circumferential surface defining the opening 18a of the protective film 18 is composed of the inner circumferential surface 16a of the intervening film 16 and the inner circumferential surface 17a of the polyimide film 17. Both the inner circumferential surface 16a of the intervening film 16 and the inner circumferential surface 17a of the polyimide film 17 are inclined by isotropic etching, which will be described later. More specifically, both the inner circumferential surface 16a of the intervening film 16 and the inner circumferential surface 17a of the polyimide film 17 are inclined so as to approach the outside as they move away from the metal electrode 13. The inner circumferential surface 17a of the polyimide film 17 is located further back than the inner circumferential surface 16a of the intervening film 16. As a result, a portion of the inner circumferential side of the upper surface of the intervening film 16 is not covered with the polyimide film 17, and a step is formed between the inner circumferential surface 16a of the intervening film 16 and the inner circumferential surface 17a of the polyimide film 17. In this manner, the polyimide film 17 is laminated on the intervening film 16 at a position spaced apart from the metal electrode 13 .

[0021] The plating electrode 14 extends outward beyond the inner circumferential surface 16a of the intervening film 16 and contacts the lower end of the inner circumferential surface 17a of the polyimide film 17. When the plating electrode 14 extends to the lower end of the inner circumferential surface 17a of the polyimide film 17, the interface distance from the outside of the semiconductor element 10 to the metal electrode 13, i.e., the sum of the distance along the interface between the plating electrode 14 and the polyimide film 17 and the distance along the interface between the plating electrode 14 and the intervening film 16, becomes large. This makes it possible to prevent moisture and foreign matter from penetrating the metal electrode 13 from the outside of the semiconductor element 10, thereby preventing corrosion of the metal electrode 13.

[0022] As explained in the background art, in a structure in which a plated electrode 14 and a solder layer 34 are provided on a metal electrode 13 exposed from an opening 18a in a protective film 18, it is known that when exposed to a thermal cycle, stress distortion is large near the triple point (i.e., see "TP" in Figure 2) where the metal electrode 13, the plated electrode 14, and the protective film 18 meet.

[0023] 3 shows the results of a simulation of the relationship between the offset distance and the metal electrode distortion. The offset distance is the shortest distance between the inner peripheral surface 16 a of the intervening film 16 and the inner peripheral surface 17 a of the polyimide film 17 when measured in a direction parallel to the upper surface 12 a of the semiconductor substrate 12. When the inner peripheral surface 17 a of the polyimide film 17 is located outside the inner peripheral surface 16 a of the intervening film 16, i.e., in the present embodiment, the offset distance is a negative value. When the inner peripheral surface 17 a of the polyimide film 17 is located inside the inner peripheral surface 16 a of the intervening film 16, i.e., when the polyimide film 17 is configured to extend beyond the inner peripheral surface 16 a of the intervening film 16 and contact the upper surface of the metal electrode 13, the triple point is the point where the metal electrode 13, the plating electrode 14, and the intervening film 16 meet, as indicated by “TP” in FIG. 2 . When the offset distance is in the positive range, the triple point is the point where the metal electrode 13, the plated electrode 14, and the polyimide film 17 come into contact. The metal electrode strain is the stress strain generated in the metal electrode 13. Figure 3 shows the maximum stress strain generated in the metal electrode 13, the average stress strain in the portion of the metal electrode 13 outside the triple point, and the average stress strain in the portion of the metal electrode 13 inside the triple point.

[0024] As shown in Figure 3, when the offset distance is in the positive range, the stress strain is high in the metal electrode 13 outside the triple point, and as a result, the maximum stress strain is also high. On the other hand, when the offset distance is in the negative range, the stress strain is dispersed to the metal electrode 13 inside the triple point, and as a result, the maximum stress strain is reduced. As such, when the inner circumferential surface 17a of the polyimide film 17 is located further back than the inner circumferential surface 16a of the intervening film 16, the maximum stress strain near the triple point of the metal electrode 13 is reduced. In particular, when the inner circumferential surface 17a of the polyimide film 17 is located further back than the inner circumferential surface 16a of the intervening film 16 by 1 μm or more, the maximum stress strain near the triple point of the metal electrode 13 is significantly reduced.

[0025] As described above, the intervening film 16 is made of a material having a smaller linear expansion coefficient than the polyimide film 17. The intervening film 16 made of such a material can restrain the deformation of the metal electrode 13 in the planar direction, and therefore can more effectively reduce the maximum stress strain of the metal electrode 13.

[0026] FIG. 4 shows a modified example of the intervening film 16. The intervening film 16 includes a lower silicon nitride film 162 made of semi-insulating silicon nitride, i.e., SInSiN (Semi-Insulating Silicon Nitride), and an upper silicon nitride film 164 made of insulating silicon nitride. The lower silicon nitride film 162 can achieve semi-insulating properties by adjusting the impurity concentration added during film formation. The stack of the lower silicon nitride film 162 and the upper silicon nitride film 164 is interposed between the metal electrode 13 and the polyimide film 17, with the lower silicon nitride film 162 in contact with the metal electrode 13 and the upper silicon nitride film 164 in contact with the polyimide film 17. The insulating upper silicon nitride film 164 can prevent ions in the polyimide film 17 from penetrating into the semiconductor substrate 12. Furthermore, the semi-insulating lower silicon nitride film 162 can migrate and be expelled to the outside. Therefore, if the intervening film 16 is configured by a combination of the semi-insulating lower silicon nitride film 162 and the insulating upper silicon nitride film 164, a decrease in the breakdown voltage of the semiconductor device 1 can be suppressed.

[0027] As shown in FIG. 4 , a V-shaped groove 160 is formed on the inner circumferential surface 16 a of the intervening film 16 between the lower silicon nitride film 162 and the upper silicon nitride film 164. This groove 160 is formed by isotropic etching, as will be described later in the manufacturing method, progressing at the interface between the lower silicon nitride film 162 and the upper silicon nitride film 164. The plating electrode 14 is filled into this groove 160 so as to penetrate in the surface direction. With this structure, the interface between the plating electrode 14 and the intervening film 16 moves back and forth in the surface direction, increasing the interfacial distance from the outside of the semiconductor element 10 to the metal electrode 13. This prevents moisture and foreign matter from penetrating the metal electrode 13 from the outside of the semiconductor element 10, thereby preventing corrosion of the metal electrode 13.

[0028] The cross-sectional shapes of the lower silicon nitride film 162 and the upper silicon nitride film 164 can be controlled by adjusting the manufacturing conditions when etching the intervening film 16. Therefore, the cross-sectional shapes of the lower silicon nitride film 162 and the upper silicon nitride film 164 can be formed into various shapes. For example, as shown in FIG. 5A , the groove 160 formed between the lower silicon nitride film 162 and the upper silicon nitride film 164 may have a rounded shape. Furthermore, as shown in FIGS. 5B and 5C , the groove 160 formed between the lower silicon nitride film 162 and the upper silicon nitride film 164 may be formed only in a part of the inner circumferential surface 16 a of the intervening film 16. Thus, the groove 160 referred to here includes various shapes in which at least a portion of the inner circumferential surface of the lower silicon nitride film 162 and at least a portion of the inner circumferential surface of the upper silicon nitride film 164 are inclined in opposite directions, and at least a portion of the inner circumferential surface of the lower silicon nitride film 162 and at least a portion of the inner circumferential surface of the upper silicon nitride film 164 face each other. Furthermore, the groove 160 does not necessarily have to be formed between the lower silicon nitride film 162 and the upper silicon nitride film 164. For example, as shown in FIG. 5D , the inner circumferential surfaces of the lower silicon nitride film 162 and the upper silicon nitride film 164 may be offset, forming a step 161 between the inner circumferential surfaces of the lower silicon nitride film 162 and the upper silicon nitride film 164. A cross-sectional shape including the groove 160 or the step 161 can be said to be a cross-sectional shape in which the inner circumferential surface 16 a of the intervening film 16 is not flush between the lower silicon nitride film 162 and the upper silicon nitride film 164. 5E, the inner peripheral surface 16a of the intervening film 16 may be inclined in a forward tapered manner, or as shown in FIG. 5F, the inner peripheral surface 16a of the intervening film 16 may be inclined in a reverse tapered manner. In all of the cases illustrated in FIGS. 5A to 5F, the interfacial distance from the outside of the semiconductor element 10 to the metal electrode 13 is longer than when the inner peripheral surface 16a of the intervening film 16 is a flat surface perpendicular to the metal electrode 13, thereby preventing corrosion of the metal electrode 13. In particular, when the inner peripheral surface 16a of the intervening film 16 includes a groove 160, the interfacial distance from the outside of the semiconductor element 10 to the metal electrode 13 is longer, thereby effectively preventing corrosion of the metal electrode 13.

[0029] 6 to 10, the steps of forming the metal electrode 13, the plated electrode 14, and the protective film 18 included in the manufacturing method of the semiconductor device 1 will be described below. For the other steps, known manufacturing methods can be appropriately adopted.

[0030] 6, a metal electrode 13 is formed on a part of the upper surface 12a of the semiconductor substrate 12. The thickness of the metal electrode 13 is not particularly limited, but may be, for example, 5 to 6 μm.

[0031] Next, as shown in FIG. 7 , an intervening film 16 is formed on the upper surface 12 a of the semiconductor substrate 12 so as to cover the entire metal electrode 13. The thickness of the intervening film 16 is not particularly limited, but may be, for example, approximately 1 μm. Note that by adjusting the impurity concentration during film formation, a semi-insulating lower silicon nitride film 162 and an insulating upper silicon nitride film 164 may be sequentially stacked (see FIG. 4 ). Next, a polyimide film 17 is applied to the upper surface of the intervening film 16. The thickness of the polyimide film 17 is not particularly limited, but may be, for example, approximately 10 μm. In this way, a protective film 18, which is a stack of the intervening film 16 and the polyimide film 17, is formed over the entire upper surface 12 a of the semiconductor substrate 12.

[0032] 8, a portion of the polyimide film 17 is etched to form an opening 18a, and the intervening film 16 is exposed through the opening 18a. Specifically, a photoresist is applied to the surface of the polyimide film 17, and then the photoresist is developed to remove the unexposed portion of the photoresist corresponding to the opening 18a in the protective film 18. When the unexposed portion of the photoresist is removed, a portion of the polyimide film 17 is also removed at the same time. After the photoresist remaining on the polyimide film 17 is peeled off, the polyimide film 17 is baked to harden.

[0033] 9, the intervening film 16 exposed from the opening 18a of the protective film 18 is removed by isotropic etching to expose the metal electrode 13. ４ and O ２The intervening film 16 exposed through the opening 18a in the protective film 18 is removed using a dry etching technique using a mixed gas of the polyimide film 17 and the polyimide film 17. In this manner, a portion of the intervening film 16 can be removed by using the polyimide film 17 as a mask. Because the etching proceeds isotropically, the polyimide film 17 is processed so that the inner circumferential surface 17a of the polyimide film 17 is recessed from the inner circumferential surface 16a of the intervening film 16. Furthermore, the inner circumferential surfaces 16a of the intervening film 16 and the polyimide film 17 can each be inclined depending on the manufacturing conditions. When the intervening film 16 is composed of a laminate of a lower silicon nitride film 162 and an upper silicon nitride film 164, the cross-sectional shapes of the lower silicon nitride film 162 and the upper silicon nitride film 164 can be controlled by adjusting the manufacturing conditions of this isotropic etching.

[0034] 10, a plating electrode 14 is formed on the upper surface of the metal electrode 13 exposed from the opening 18a of the protective film 18. The plating electrode 14 grows on the upper surface of the metal electrode 13 but does not grow on the protective film 18. Therefore, the upper surface of the portion of the plating electrode 14 located above the metal electrode 13 exposed from the opening 18a of the protective film 18 is parallel to the upper surface of the metal electrode 13, and the upper surface of the portion located outside this portion is curved downward (see FIGS. 2 and 4). The plating electrode 14 is formed so that its outer end extends beyond the inner circumferential surface of the intervening film 16 and contacts the lower end of the inner circumferential surface of the polyimide film 17.

[0035] In the above manufacturing method, the intervening film 16 can be etched using the polyimide film 17 as a mask. Furthermore, when the intervening film 16 is removed by isotropic etching to expose the metal electrode 13, the inner circumferential surface of the polyimide film 17 is also etched at the same time, and therefore the polyimide film 17 is processed so that the inner circumferential surface of the polyimide film 17 is positioned recessed from the inner circumferential surface of the intervening film 16. According to the above manufacturing method, the semiconductor device 1 disclosed in this specification can be manufactured with a small number of steps.

[0036] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical usefulness either alone or in various combinations.

[0037] (Aspect 1) A semiconductor device comprising: a semiconductor substrate (12); a metal electrode (13) provided on the semiconductor substrate; a protective film (18) provided on the semiconductor substrate, covering the outer periphery of the metal electrode and having an opening (18a) exposing a portion of the metal electrode; a plated electrode (14) provided on the metal electrode exposed from the opening in the protective film; and a solder layer (34) provided on the plated electrode, wherein the protective film has a polyimide film (17) and an intervening film (16) made of a material different from the polyimide film, interposed between the polyimide film and the metal electrode, and wherein, on an inner periphery defining the opening of the protective film, the inner periphery (17a) of the polyimide film is positioned recessed from the inner periphery (16a) of the intervening film.

[0038] (Aspect 2) The semiconductor device according to aspect 1, wherein the intervening film includes silicon nitride.

[0039] (Aspect 3) The semiconductor device according to aspect 2, wherein the intervening film comprises: an insulating first silicon nitride film (164); and a semi-insulating second silicon nitride film (162).

[0040] (Aspect 4) The semiconductor device according to aspect 3, wherein the inner circumferential surface of the intervening film is not flush with the first silicon nitride film and the second silicon nitride film.

[0041] (Aspect 5) The semiconductor device according to aspect 4, wherein a groove (160) is formed on the inner circumferential surface of the intervening film between the first silicon nitride film and the second silicon nitride film.

[0042] (Aspect 6) The semiconductor device according to any one of aspects 1 to 5, wherein the plating electrode extends outward beyond the inner circumferential surface of the intervening film.

[0043] (Aspect 7) The semiconductor device according to aspect 6, wherein the plating electrode is in contact with the inner circumferential surface of the polyimide film.

[0044] (Embodiment 8) The semiconductor device according to any one of embodiments 1 to 7, wherein the metal electrode contains aluminum.

[0045] (Aspect 9) A method for manufacturing a semiconductor device, comprising: a step of forming a metal electrode (13) on a semiconductor substrate (12); a step of forming a protective film (18) on the semiconductor substrate by covering the metal electrode, the protective film being composed of an intervening film (16) and a polyimide film (17) laminated together; a step of removing a portion of the polyimide film to form an opening (18a) and exposing the intervening film from the opening; and a step of removing the intervening film exposed from the opening by isotropic etching to expose the metal electrode.

[0046] (Aspect 10) The method for manufacturing a semiconductor device according to aspect 9, wherein the intervening film includes silicon nitride.

[0047] (Aspect 11) The method for manufacturing a semiconductor device according to aspect 10, wherein the intervening film has an insulating first silicon nitride film (164) and a semi-insulating second silicon nitride film (162).

[0048] Although specific examples of the technology disclosed in this specification have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or in the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology exemplified in this specification or in the drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility.

Claims

1. A semiconductor device comprising: a semiconductor substrate (12); a metal electrode (13) provided on the semiconductor substrate; a protective film (18) provided on the semiconductor substrate, covering the outer periphery of the metal electrode and having an opening (18a) exposing a portion of the metal electrode; a plated electrode (14) provided on the metal electrode exposed from the opening in the protective film; and a solder layer (34) provided on the plated electrode, wherein the protective film has a polyimide film (17) and an intervening film (16) made of a material different from the polyimide film, interposed between the polyimide film and the metal electrode, and wherein, on an inner periphery defining the opening of the protective film, the inner periphery (17a) of the polyimide film is positioned recessed from the inner periphery (16a) of the intervening film.

2. The semiconductor device according to claim 1, wherein said intervening film includes silicon nitride.

3. The semiconductor device according to claim 2, wherein the intervening film comprises: an insulating first silicon nitride film (164); and a semi-insulating second silicon nitride film (162).

4. The semiconductor device according to claim 3, wherein the inner peripheral surface of the intervening film is not flush between the first silicon nitride film and the second silicon nitride film.

5. The semiconductor device according to claim 4, wherein a groove (160) is formed on the inner peripheral surface of the intervening film between the first silicon nitride film and the second silicon nitride film.

6. The semiconductor device according to claim 1, wherein said plating electrode extends outward beyond said inner peripheral surface of said intervening film.

7. The semiconductor device according to claim 6, wherein said plating electrode is in contact with said inner peripheral surface of said polyimide film.

8. The semiconductor device according to any one of claims 1 to 7, wherein the metal electrode contains aluminum.

9. A method for manufacturing a semiconductor device, comprising the steps of: forming a metal electrode (13) on a semiconductor substrate (12); forming a protective film (18) on the semiconductor substrate by covering the metal electrode, the protective film being composed of an intervening film (16) and a polyimide film (17) laminated together; removing a portion of the polyimide film to form an opening (18a) and exposing the intervening film from the opening; and removing the intervening film exposed from the opening by isotropic etching to expose the metal electrode.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the intervening film includes silicon nitride.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the intervening film comprises: an insulating first silicon nitride film (164); and a semi-insulating second silicon nitride film (162).

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