Semiconductor device

Abstract

Provided is a semiconductor device in which the positional accuracy of a component disposed inside a case can be improved. The semiconductor device includes: an insulating plate (6); conductive plates (51-53) provided on the insulating plate (6) and provided with first recesses (51a, 51b, 52a, 52b); semiconductor chips (41a-41f, 42a-42f) provided on the conductive plates (51-53); a printed board (2a) provided above the semiconductor chips (41a-41f, 42a-42f), having connection members (71a-71f, 72a-72f, 73a-73f, 74a-74f), and provided with through-holes (21a-21d); a terminal holding part (31) that holds terminals (61-66) inserted into the printed board (2a); and a terminal block having legs (32a-32d) extending downward from the terminal holding part (31) and engaged with the first recesses (51a, 51b, 52a, 52b) via the through-holes (21a-21d).

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device (power semiconductor module).

[0002] Patent document 1 discloses that a semiconductor device comprises a printed circuit board, a plurality of pins press-fitted into the printed circuit board, a resin block formed with a plurality of through holes into which the plurality of pins are respectively press-fitted, and a resin case covering at least a portion of the printed circuit board and the resin block, and that a method for manufacturing the semiconductor device comprises the steps of pressing the plurality of pins into the printed circuit board, preparing a resin block formed with a plurality of through holes, fitting the resin block onto the plurality of pins so that the plurality of pins are press-fitted into the plurality of through holes, and resin-molding the resin case so as to cover at least a portion of the printed circuit board and the resin block.

[0003] Patent Document 2 discloses a semiconductor device in which a power circuit and a control circuit are housed in a two-story structure in a package consisting of a metal base, a terminal-integrated outer case, and a top cover, and sealed with a gel filler. The control terminals leading out to the control circuit are inserted into a control terminal block, which is an independent component, as pin terminals arranged in accordance with the user's specifications, and the control terminal block is then fixed across and bridged near the center of the top surface of the outer case, and a printed circuit board for the control circuit is bridged and connected between terminal leads that rise from the block toward the inside of the case and terminal leads that rise from a relay terminal block arranged inside the case.

[0004] Patent Document 3 discloses a power module structure using a heat sink-integrated insulating circuit board.

[0005] JP 2018-107395 A JP 2003-249624 A International Publication No. 2023 / 090013

[0006] In a power semiconductor module, the various components placed inside the case must be positioned using a carbon jig, etc. However, variations in the jig and position occur, making it difficult to improve positional accuracy.

[0007] In view of the above-mentioned problems, an object of the present disclosure is to provide a semiconductor device that can improve the positional accuracy of components arranged inside a case.

[0008] One aspect of the present disclosure is a semiconductor device comprising: an insulating plate; a plurality of conductive plates provided on the insulating plate, each having a plurality of first recesses; a semiconductor chip provided on one of the plurality of conductive plates; a printed circuit board provided above the semiconductor chip, having a plurality of connecting members conductively connected to the semiconductor chip and having a plurality of through holes; a terminal holding portion that holds a plurality of terminals inserted into the printed circuit board; and a terminal block extending downward from the terminal holding portion and having a plurality of legs that engage with a plurality of first recesses via the plurality of through holes.

[0009] In one aspect of the present disclosure, a protrusion that engages with the first recess may be provided at the lower end of the leg.

[0010] In one aspect of the present disclosure, the first recess may be provided in an upper portion of the conductive plate.

[0011] In one aspect of the present disclosure, the first recess may extend through the conductive plate.

[0012] In one aspect of the present disclosure, the first recess may be a groove that is annular in plan view, and the leg portion may be cylindrical.

[0013] In one aspect of the present disclosure, a plurality of second recesses may be provided in any of the plurality of conductive plates, and the device may further include a case that houses a semiconductor chip and a printed circuit board inside and has a plurality of engaging portions that engage with the plurality of second recesses.

[0014] In one aspect of the present disclosure, the insulating plate may be rectangular in plan view, and the plurality of second recesses may be provided at diagonal positions of the rectangle.

[0015] In one aspect of the present disclosure, a main terminal may be integrally provided with the case, and the main terminal may be joined to any one of the plurality of conductive plates.

[0016] In one aspect of the present disclosure, the device may further include a cooler provided below the insulating plate.

[0017] It should be noted that the above summary of the invention does not list all of the necessary features of the present disclosure, and that subcombinations of these features may also constitute inventions.

[0018] According to the present disclosure, it is possible to provide a semiconductor device that can improve the positional accuracy of components arranged inside a case.

[0019] FIG. 1 is a top view of a semiconductor device according to a first embodiment. FIG. 2 is a top view of a component of a semiconductor device according to the first embodiment. FIG. 3 is a perspective view of a semiconductor device according to the first embodiment, corresponding to FIG. 2. FIG. 4 is a perspective view of a semiconductor device according to the first embodiment, corresponding to FIG. 4. FIG. 5 is a top view of a component of a semiconductor device according to the first embodiment. FIG. 6 is a perspective view of a component of a semiconductor device according to the first embodiment. FIG. 7 is a top view of a component of a semiconductor device according to the first embodiment. FIG. 8 is a perspective cross-sectional view of a semiconductor device according to the first embodiment. FIG. 9 is a perspective view of a semiconductor device according to the first embodiment. FIG. 10 is an exploded perspective view of a semiconductor device according to the first embodiment. FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 12 is a cross-sectional view of a semiconductor device according to a third embodiment. FIG. 13 is a cross-sectional view of a semiconductor device according to a fourth embodiment. FIG. 14 is a plan view of a conductive plate of a semiconductor device according to a fifth embodiment. FIG. 15 is a plan view of a conductive plate of a semiconductor device according to a sixth embodiment. FIG. 16 is a plan view of a conductive plate of a semiconductor device according to a seventh embodiment. FIG. 17 is a plan view of a conductive plate of a semiconductor device according to an eighth embodiment. FIG. 18 is a cross-sectional view of a semiconductor device according to a ninth embodiment.

[0020] Hereinafter, first to ninth embodiments of the present disclosure will be described with reference to the drawings. In the drawings referred to in the following description, identical or similar parts are designated by identical or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, and the like may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0021] Furthermore, the definitions of directions such as "up," "down," "up and down," "left," "right," and "left and right" in the following description are merely definitions for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, "up and down" is converted and read as "left and right," and of course, if an object is rotated 180 degrees and observed, "up and down" is read in reverse.

[0022] In the following description, the terms "top surface" and "bottom surface" may be read as "front surface" and "back surface," respectively. The "first main surface" and "second main surface" of each member are main surfaces that face each other; for example, if the "first main surface" is the top surface, the "second main surface" is the bottom surface. The terms "first main surface" and "second main surface" may be read as "one main surface" and "the other main surface," respectively.

[0023] (First Embodiment) <Structure of Semiconductor Device> As an example of a semiconductor device according to the first embodiment, a 6-in-1 power semiconductor module constituting three phases, namely, a U phase, a V phase, and a W phase, is shown. FIG. 1 is a plan view of the semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device according to the first embodiment includes a case 8, and main terminals (positive terminals) 11a to 11c, main terminals (negative terminals) 12a to 12c, and main terminals (output terminals) 13a to 13c that are integrally provided with the case 8 and exposed outside the case 8.

[0024] The case 8 has a substantially rectangular outer shape in a plan view and is made of a resin material such as polyphenylene sulfide (PPS). The case 8 has through holes 8a to 8h for screw fastening.

[0025] In Fig. 1, the longitudinal direction of the approximately rectangular case 8 (left-right direction in Fig. 1) is defined as the X-axis direction, and one direction in the X-axis direction (rightward in Fig. 1) is defined as the positive direction. Furthermore, the direction perpendicular to the X-axis direction (upward in Fig. 1), which is the short-side direction of the case 8, is defined as the Y-axis direction, and one direction in the Y-axis direction (upward in Fig. 1) is defined as the positive direction. Furthermore, the direction perpendicular to the X-axis direction and the Y-axis direction (front and depth directions in Fig. 1) is defined as the Z-axis direction, and the top of the case 8 (frontward in Fig. 1) is defined as the positive direction of the Z-axis. The definitions of directions and orientations shown in Fig. 2 and subsequent figures are the same as those in Fig. 1.

[0026] The positive electrode terminals 11a to 11c, the negative electrode terminals 12a to 12c, and the output terminals 13a to 13c are formed integrally with the case 8 by insert molding or the like. The positive electrode terminals 11a to 11c, the negative electrode terminals 12a to 12c, and the output terminals 13a to 13c are made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy.

[0027] The positive electrode terminals 11a to 11c and the negative electrode terminals 12a to 12c are arranged on one side in the short-side direction (Y-axis direction) of the case 8. The positive electrode terminals 11a to 11c and the negative electrode terminals 12a to 12c are arranged alternately along the longitudinal direction (X-axis direction) of the case 8. The positive electrode terminals 11a to 11c and the negative electrode terminals 12a to 12c are external connection terminals and can be connected to external members such as capacitors by screw fastening, laser welding, or the like. The positive electrode terminals 11a to 11c have joints 11d to 11i extending inside the case 8. The negative electrode terminals 12a to 12c have joints 12d to 12f extending inside the case 8.

[0028] The output terminals 13a to 13c are arranged on the other side in the short direction (Y-axis direction) of the case 8. The output terminals 13a to 13c are arranged along the longitudinal direction (X-axis direction) of the case 8. The output terminals 13a to 13c are external connection terminals and can be connected to external members such as a motor by screw fastening, laser welding, or the like. The output terminals 13a to 13c have joints 13d to 13f that extend inside the case 8.

[0029] A plurality of (two) protrusions (locking portions) 81, 82 are provided at diagonal positions on the inside of the case 8. Printed circuit boards (wiring boards) 2a to 2c and terminal blocks (terminal manifolds) 3a to 3c are arranged inside the case 8. Note that Fig. 1 does not show the sealing resin, such as silicone gel or epoxy resin, that is provided inside the case 8 and seals the printed circuit boards 2a to 2c and terminal blocks 3a to 3c, etc.

[0030] FIG. 2 is a top view of the semiconductor device according to the first embodiment, omitting the case 8, in which the positive terminals 11a-11c, negative terminals 12a-12c, and output terminals 13a-13c of FIG. 1 are integrated, the printed circuit boards 2a-2c, and terminal blocks 3a-3c. FIG. 3 is a perspective view of the semiconductor device according to the first embodiment, corresponding to FIG. 2. As shown in FIGS. 2 and 3, the semiconductor device according to the first embodiment includes a cooler (heat sink) 7, an insulating plate 6 provided on the upper surface of the cooler 7, and a plurality of conductive plates (circuit patterns) 51-59 provided on the upper surface of the insulating plate 6. The cooler 7, the insulating plate 6, and the conductive plates 51-59 constitute a cooler-integrated substrate (51-59, 6, 7).

[0031] The cooler 7 is made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy. Although not shown in Figures 2 and 3, cooling fins are provided on the underside of the cooler 7. Note that cooling fins do not necessarily have to be provided on the underside of the cooler 7. Through holes 7a to 7h for screw fastening are provided on the outer periphery of the cooler 7. The positions of the through holes 7a to 7h in the cooler 7 correspond to the positions of the through holes 8a to 8h in the case 8 shown in Figure 1.

[0032] The insulating plate 6 has a substantially rectangular planar pattern. The insulating plate 6 is made of an insulating material. The insulating plate 6 may be made of a resin insulating layer (resin insulating sheet) made of, for example, liquid crystal polymer (LCP) or epoxy resin. Alternatively, the insulating plate 6 may be made of aluminum oxide (Al ２ O ３ ), aluminum nitride (AlN), silicon nitride (Si ３ N ４ ) or a ceramic substrate made of boron nitride (BN) or the like.

[0033] The conductive plates 51 to 59 are made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy. The conductive plates 51 to 59 may be bonded to the upper surface of the insulating plate 6 by thermocompression bonding or the like. The number and arrangement of the conductive plates 51 to 59 are not particularly limited. A conductive plate (heat sink) may be provided on the lower surface of the insulating plate 6, and the insulating plate 6, the conductive plates 51 to 59 on the upper surface of the insulating plate 6, and the conductive plate (heat sink) on the lower surface of the insulating plate 6 may form an insulated circuit board such as a direct copper bonding (DCB) board or an active metal bonding (AMD) board.

[0034] 1 may be provided on the upper surface side of the insulating plate 6. Alternatively, the insulating plate 6 may be housed inside the case 8, and the case 8 may be provided on the upper surface side of the cooler 7 and bonded thereto with an adhesive.

[0035] The upper surface of the conductive plate 51 is connected by ultrasonic bonding or the like to the joint 13d of the output terminal 13a shown in FIG. 1, which extends toward the inside of the case 8. The semiconductor chips 41a to 41f constituting the lower arm of one phase (e.g., the U-phase) are provided on the upper surface of the conductive plate 51 via a joint material (not shown), such as solder or a sintered material. The upper surface of the conductive plate 51 is provided with positioning recesses (holes) 51a, 51b, and 51x. The recesses 51a and 51b are provided between the semiconductor chips 41a and 41d. The recess 51x is provided at a corner of the conductive plate 51 and at a corner of the substantially rectangular insulating plate 6.

[0036] The bonding portions 11d and 11e of the positive terminal 11a shown in FIG. 1, which extend toward the inside of the case 8, are connected to the upper surface of the conductive plate 52 by ultrasonic bonding or the like. The semiconductor chips 42a to 42f that constitute the upper arm of one phase (e.g., the U-phase) are provided on the upper surface of the conductive plate 52 via a bonding material (not shown) such as solder or a sintered material. Positioning recesses (holes) 52a and 52b are provided on the upper surface of the conductive plate 52. The recesses 52a and 52b are provided between the semiconductor chips 42a and 42d.

[0037] The upper surface of the conductive plate 53 is connected by ultrasonic bonding or the like to the joint 12d of the negative electrode terminal 12a shown in FIG. 1, which extends to the inside of the case 8.

[0038] 1, is connected to the upper surface of the conductive plate 54 by ultrasonic bonding or the like. The semiconductor chips 43a to 43f that form the lower arm of one phase (e.g., the V-phase) are provided on the upper surface of the conductive plate 54 via a bonding material (not shown) such as solder or a sintered material. Positioning recesses (holes) 54a and 54b are provided on the upper surface of the conductive plate 54. The recesses 54a and 54b are provided between the semiconductor chips 43a and 43d.

[0039] The bonding portions 11f and 11g of the positive terminal 11b shown in FIG. 1, which extend toward the inside of the case 8, are connected to the upper surface of the conductive plate 55 by ultrasonic bonding or the like. The semiconductor chips 44a to 44f constituting the upper arm of one phase (for example, the V phase) are provided on the upper surface of the conductive plate 55 via a bonding material (not shown) such as solder or a sintered material. The upper surface of the conductive plate 55 is provided with positioning recesses (holes) 55a and 55b. The recesses 55a and 55b are provided between the semiconductor chips 44a and 44d.

[0040] The upper surface of the conductive plate 56 is connected by ultrasonic bonding or the like to the joint 12e of the negative electrode terminal 12b shown in FIG. 1, which extends to the inside of the case 8.

[0041] 1, is connected to the upper surface of the conductive plate 57 by ultrasonic bonding or the like. The semiconductor chips 45a to 45f constituting the lower arm of one phase (for example, the W-phase) are provided on the upper surface of the conductive plate 57 via a bonding material (not shown) such as solder or a sintered material. Positioning recesses (holes) 57a and 57b are provided on the upper surface of the conductive plate 57. The recesses 57a and 57b are provided between the semiconductor chips 45a and 45d.

[0042] The upper surface of the conductive plate 58 is connected to the joints 11h and 11i of the positive terminal 11c shown in FIG. 1, which extend inside the case 8, by ultrasonic bonding or the like. The semiconductor chips 46a to 46f constituting the upper arm of one phase (e.g., the W-phase) are provided on the upper surface of the conductive plate 58 via a bonding material (not shown), such as solder or a sintered material. The upper surface of the conductive plate 58 is provided with positioning recesses (holes) 58a, 58b, and 58x. The recesses 58a and 58b are provided between the semiconductor chips 46a and 46d. The recess 58x is located at a corner of the conductive plate 58 and at a corner of the substantially rectangular insulating plate 6. The recesses 51x and 58x are provided at diagonal corners of the substantially rectangular insulating plate 6.

[0043] The upper surface of the conductive plate 59 is connected by ultrasonic bonding or the like to the joint 12f of the negative electrode terminal 12c shown in FIG. 1, which extends to the inside of the case 8.

[0044] The semiconductor chips 41a to 41f, 42a to 42f, 43a to 43f, 44a to 44f, 45a to 45f, and 46a to 46f are made of, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga ２ O ３ The semiconductor chips 41a to 41f, 42a to 42f, 43a to 43f, 44a to 44f, 45a to 45f, and 46a to 46f may be field-effect transistors (FETs) such as metal-oxide semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), reverse-conducting insulated-gate bipolar transistors (RC-IGBTs) in which a diode is connected in antiparallel to an IGBT, static induction (SI) thyristors, gate turn-off (GTO) thyristors, or the like. The types, numbers, and arrangement positions of the semiconductor chips 41a to 41f, 42a to 42f, 43a to 43f, 44a to 44f, 45a to 45f, and 46a to 46f are not particularly limited.

[0045] Here, the semiconductor chips 41a to 41f, 42a to 42f, 43a to 43f, 44a to 44f, 45a to 45f, and 46a to 46f constitute IGBTs, for example. The semiconductor chips 41a to 41f, 42a to 42f, 43a to 43f, 44a to 44f, 45a to 45f, and 46a to 46f each have a collector electrode (not shown) on the lower surface and a gate electrode 41 and an emitter electrode 42 on the upper surface.

[0046] Of the six semiconductor chips 41a to 41f, three semiconductor chips 41a to 41c and three semiconductor chips 41d to 41f are provided spaced apart from one another in the longitudinal direction (X-axis direction) of the insulating plate 6. Of the three semiconductor chips 41a to 41c, one semiconductor chip 41a and two semiconductor chips 41b and 41c are provided spaced apart from one another in the lateral direction (Y-axis direction) of the insulating plate 6 so that their gate electrodes 41 face each other. Of the three semiconductor chips 41d to 41f, one semiconductor chip 41d and two semiconductor chips 41e and 41f are provided spaced apart from one another in the lateral direction (Y-axis direction) of the insulating plate 6 so that their gate electrodes 41 face each other. The semiconductor chips 42a to 42f, 43a to 43f, 44a to 44f, 45a to 45f, and 46a to 46f are also provided in the same positions as the semiconductor chips 41a to 41f.

[0047] FIG. 4 is a top view of the semiconductor device according to the first embodiment shown in FIG. 2 , with printed circuit boards 2a to 2c added to the top surfaces of the cooler 7, insulating plate 6, and conductive plates 51 to 59. FIG. 5 is a perspective view of the semiconductor device according to the first embodiment corresponding to FIG. 4 . As shown in FIGS. 4 and 5 , a printed circuit board 2a is provided above and facing the conductive plates 51 to 53 and the semiconductor chips 41a to 41f, 42a to 42f. A printed circuit board 2b is provided above and facing the conductive plates 54 to 56 and the semiconductor chips 43a to 43f, 44a to 44f. A printed circuit board 2c is provided above and facing the conductive plates 57 to 59 and the semiconductor chips 45a to 45f, 46a to 46f.

[0048] 6 is a top view of an enlarged portion of the top view of the semiconductor device according to the first embodiment shown in FIG. 4 , showing conductive plates 51-53 and a printed circuit board 2a above the conductive plates 51-53. The printed circuit board 2a includes an insulating layer 21 having a substantially rectangular planar pattern and multiple conductive layers 22a-22h provided on the upper surface of the insulating layer 21. The printed circuit board 2a may be a multilayer wiring board having multiple wiring layers interposed between the insulating layer 21. For example, the printed circuit board 2a may further include one or more conductive layers provided inside the insulating layer 21 and a conductive layer provided on the lower surface of the insulating layer 21, in addition to the conductive layers 22a-22h provided on the upper surface of the insulating layer 21.

[0049] Through holes 21a to 21d are provided in the insulating layer 21 of the printed circuit board 2a. The positions of the through holes 21a and 21b correspond to the positions of the recesses 51a and 51b of the conductive plate 51. The positions of the through holes 21c and 21d correspond to the positions of the recesses 52a and 52b of the conductive plate 52. Furthermore, through holes 25a to 25f are provided in the printed circuit board 2a. The insulating layer 21 is made of an insulating resin material such as an epoxy resin. The conductive layers 22a to 22h are made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy.

[0050] Pin-shaped connection members (pins) 72a to 72f are conductively connected to the conductive layer 22a. The connection members 72a to 72f are made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy. The connection members 72a to 72f are inserted into through holes provided in the printed circuit board 2a and fixed by press-fitting. The upper ends of the connection members 72a to 72f protrude from the upper surface of the printed circuit board 2a and extend upward. The lower ends of the connection members 72a to 72f are conductively connected to the emitter electrodes 42 of the semiconductor chips 41a to 41f shown in FIG. 2 via a bonding material (not shown), such as solder or a sintered material.

[0051] Pin-shaped connection members (pins) 74a to 74c, 74g are conductively connected to the conductive layer 22b. The connection members 74a to 74c, 74g are press-fit into through holes provided in the printed circuit board 2a. The upper ends of the connection members 74a to 74c, 74g protrude from the upper surface of the printed circuit board 2a and extend upward. The lower ends of the connection members 74a to 74c are conductively connected to the emitter electrodes 42 of the semiconductor chips 42a to 42c shown in FIG. 2 via a bonding material (not shown) such as solder or a sintered material. The lower end of the connection member 74g is conductively connected to the conductive plate 51 via a bonding material (not shown) such as solder or a sintered material.

[0052] Pin-shaped connection members (pins) 74d-74f, 74h are conductively connected to the conductive layer 22c. The connection members 74d-74f, 74h are press-fit into through holes provided in the printed circuit board 2a. The upper ends of the connection members 74d-74f, 74h protrude from the upper surface of the printed circuit board 2a and extend upward. The lower ends of the connection members 74d-74f are conductively connected to the emitter electrodes 42 of the semiconductor chips 42d-42f shown in FIG. 2 via a bonding material (not shown) such as solder or a sintered material. The lower end of the connection member 74h is conductively connected to the conductive plate 51 via a bonding material (not shown) such as solder or a sintered material.

[0053] Pin-shaped connection members (pins) 71a to 71f are conductively connected to the conductive layer 22d. The connection members 71a to 71f are press-fitted into through holes provided in the printed circuit board 2a. The upper ends of the connection members 71a to 71f protrude from the upper surface of the printed circuit board 2a and extend upward. The lower ends of the connection members 71a to 71f are conductively connected to the gate electrodes 41 of the semiconductor chips 41a to 41f shown in FIG. 2 via a bonding material (not shown), such as solder or a sintered material.

[0054] Pin-shaped connection members (pins) 73a to 73f are conductively connected to the conductive layer 22e. The connection members 73a to 73f are press-fit into through holes provided in the printed circuit board 2a. The upper ends of the connection members 73a to 73f protrude from the upper surface of the printed circuit board 2a and extend upward. The lower ends of the connection members 73a to 73f are conductively connected to the gate electrodes 41 of the semiconductor chips 42a to 42f shown in FIG. 2 via a bonding material (not shown), such as solder or a sintered material.

[0055] A pin-shaped connecting member (pin) 74f is conductively connected to the conductive layer 22f. The connecting member 74f is press-fitted into a through-hole provided in the printed circuit board 2a. The upper end of the connecting member 74f protrudes from the upper surface of the printed circuit board 2a and extends upward. The lower end of the connecting member 74f is conductively connected to the conductive plate 53 via a bonding material (not shown) such as solder or a sintered material. Although not shown, the conductive layer 22f is conductively connected to the conductive layer 22a via a conductive layer inside the insulating layer 21.

[0056] A pin-shaped connecting member (pin) 77 is conductively connected to the conductive layer 22g. The connecting member 77 is press-fitted into a through-hole provided in the printed circuit board 2a. Pin-shaped connecting members (pins) 76a and 76b are conductively connected to the conductive layer 22h. The connecting members 76a and 76b are press-fitted into through-holes provided in the printed circuit board 2a.

[0057] 7 is a top view of the semiconductor device according to the first embodiment, in which terminal blocks 3a to 3c are added to the perspective view of the semiconductor device shown in FIG. 5. Terminal block 3a is provided on the upper surface of printed circuit board 2a. Terminal block 3b is provided on the upper surface of printed circuit board 2b. Terminal block 3c is provided on the upper surface of printed circuit board 2c.

[0058] 8 is a top view of the printed circuit board 2a and the terminal block 3a. The terminal block 3a includes a plurality of terminals (control terminals) 61 to 66, a terminal holder 31 that holds the control terminals 61 to 66, and legs 32a to 32d that extend downward from the terminal holder 31.

[0059] The control terminals 61 to 66 are provided integrally with the terminal holder 31 by insert molding or the like. The control terminals 61 to 66 are made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy. Here, the control terminals 61 to 66 are illustrated as having the shape of press-fit terminals, but the shape of the control terminals 61 to 66 is not particularly limited. The control terminals 61 to 66 may be, for example, pin-shaped, rod-shaped, cylindrical, or polygonal prism-shaped. The number of control terminals 61 to 66 is also not limited.

[0060] The control terminals 61 to 66 protrude from the upper surface of the terminal holder 31 and extend upward. The control terminals 61 to 66 are external connection terminals, and their upper portions can be connected to external components such as a control board. The control terminals 61 to 66 protrude from the lower surface of the terminal holder 31, extend downward, and are inserted into the through-holes 25a to 25f of the printed circuit board 2a shown in FIG. 6 and fixed by press-fitting. The lower ends of the control terminals 61 to 66 may remain inside the through-holes 25a to 25f of the printed circuit board 2a, or may pass through the through-holes 25a to 25f of the printed circuit board 2a and be exposed from the lower surface of the printed circuit board 2a. The lower ends of the control terminals 61 to 66 do not reach the upper surfaces of the conductive plates 51 to 53 and are separated from the upper surfaces of the conductive plates 51 to 53.

[0061] The lower end of the control terminal 61 is press-fitted into the through hole 25a of the printed circuit board 2a shown in Fig. 6 and is conductively connected to the conductive layer 22h. The lower end of the control terminal 62 is press-fitted into the through hole 25b of the printed circuit board 2a shown in Fig. 6 and is conductively connected to the conductive layer 22g.

[0062] The lower end of the control terminal 63 is press-fitted into the through hole 25c of the printed circuit board 2a shown in FIG. 6. The control terminal 63 is conductively connected to the gate electrodes 41 of the semiconductor chips 41a to 41f via the conductive layer 22d, and functions as a gate terminal. The control terminal 63 applies a control signal to the gate electrodes 41 of the semiconductor chips 41a to 41f. The lower end of the control terminal 64 is press-fitted into the through hole 25d of the printed circuit board 2a shown in FIG. 6. The control terminal 64 is conductively connected to the emitter electrodes 42 of the semiconductor chips 41a to 41f via the printed circuit board 2a, and functions as an auxiliary emitter terminal.

[0063] The lower end of the control terminal 65 is press-fitted into the through-hole 25e of the printed circuit board 2a shown in FIG. 6. The lower end of the control terminal 66 is press-fitted into the through-hole 25f of the printed circuit board 2a. The control terminal 65 is conductively connected to the emitter electrodes 42 of the semiconductor chips 42a to 42f via the printed circuit board 2a, and functions as an auxiliary emitter terminal. The control terminal 66 is conductively connected to the gate electrodes 41 of the semiconductor chips 42a to 42f via the conductive layer 22e shown in FIG. 6, and functions as a gate terminal. The control terminal 66 applies a control signal to the gate electrodes 41 of the semiconductor chips 42a to 42f.

[0064] As shown in Fig. 8, the terminal holding portion 31 has a planar pattern that is generally H-shaped or generally I-shaped. The planar pattern of the terminal holding portion 31 is not particularly limited. In plan view, the terminal holding portion 31 is provided at a position sandwiched between the semiconductor chips 41a to 41c and the semiconductor chips 41d to 41f shown in Fig. 2, and between the semiconductor chips 42a to 42c and the semiconductor chips 42d to 42f. The terminal holding portion 31 is made of an insulating resin material, for example, an epoxy resin.

[0065] The portion of the terminal holding portion 31 that holds the control terminals 61 to 66 is provided with protrusions (projections) 33a to 33c that protrude from the upper surface of the terminal holding portion 31. The protrusions 33a to 33c are provided integrally with the terminal holding portion 31 and are made of the same material as the terminal holding portion 31.

[0066] The protrusion 33a covers part of the outer periphery of the control terminals 61 and 62. The protrusion 33b covers part of the outer periphery of the control terminals 63 and 64. The protrusion 33c covers part of the outer periphery of the control terminals 65 and 66. The protrusions 33a to 33c ensure the insulation distance (creepage distance) of the control terminals 61 to 66. Note that the protrusions 33a to 33c do not necessarily have to be provided.

[0067] The terminal holding portion 31 is provided with a plurality of (four) legs 32a to 32d. The legs 32a to 32d are provided integrally with the terminal holding portion 31 and are made of the same material as the terminal holding portion 31. The leg 32a extends downward, passes through the through hole 21a of the printed circuit board 2a shown in FIG. 6, and is inserted into and engaged with the recess 51a of the conductive plate 51. The leg 32b extends downward, passes through the through hole 21b of the printed circuit board 2a shown in FIG. 6, and is inserted into and engaged with the recess 51b of the conductive plate 51. The leg 32c extends downward, passes through the through hole 21c of the printed circuit board 2a shown in FIG. 6, and is inserted into and engaged with the recess 52a of the conductive plate 52. The leg portion 32d extends downward, passes through the through hole 21d of the printed circuit board 2a shown in FIG. 6, and is inserted into and engaged with the recess 52b of the conductive plate 52.

[0068] By engaging (fitting) the legs 32a to 32d with the recesses 51a, 51b, 52a, and 52b, it becomes easier to position the semiconductor chips 41a to 41f, 42a to 42f and the conductive plates 51 to 59 relative to the connecting members 71a to 71f, 72a to 72f, 73a to 73f, 74a to 74h, 76a, 76b, 77, 78a, and 78b of the printed circuit board 2a.

[0069] Fig. 9 is a perspective cross-sectional view taken along line A-A', which passes through legs 32c and 32d of terminal block 3a in Fig. 8. As shown in Fig. 9, cooling fins 7x are provided on the lower surface side of cooler 7. Recesses 52a and 52b of conductive plate 52 are provided in the upper part of conductive plate 52. Recesses 52a and 52b can be formed by etching conductive plate 52.

[0070] The leg 32c has an extension 321 extending downward from the terminal holding portion 31 and a protrusion 322 protruding from the lower end of the extension 321 and having a width narrower than that of the extension 321. The protrusion 322 is inserted into and engaged with a recess 52a of the conductive plate 52. The leg 32d has an extension 323 extending downward from the terminal holding portion 31 and a protrusion 324 protruding from the lower end of the extension 323 and having a width narrower than that of the extension 323. The protrusion 324 is inserted into and engaged with a recess 52b of the conductive plate 52. The protrusions 322 and 324 may or may not reach the bottom surfaces of the recesses 52a and 52b of the conductive plate 52.

[0071] The configuration of the legs 32a and 32b of the terminal block 3a shown in Fig. 8 is substantially the same as that of the legs 32c and 32d of the terminal block 3a, so a duplicated description will be omitted. Also, the configuration of the terminal blocks 3b and 3c shown in Fig. 7 is substantially the same as that of the terminal block 3a shown in Figs. 8 and 9, so a duplicated description will be omitted.

[0072] FIG. 10 is an enlarged perspective view of the periphery of the protrusion 81 on the inside of the case 8 in FIG. 1 . As shown in FIG. 10 , the protrusion 81 has a protruding portion 81a that protrudes toward the inside of the case 8 and an extending portion 81b that extends downward from the protruding portion 81a. In FIG. 10 , the protruding portion 81a has an upper surface that is flush with the upper surface of the case 8, but it may also be provided below the upper surface of the case 8, for example, in the central or lower portion of the inner wall. The lower end of the extending portion 81b is inserted into and engaged with a recess 51x of the conductive plate 51. Similar to the protrusion 322 at the lower end of the extending portion 321 in FIG. 9 , a protrusion may also be provided at the lower end of the extending portion 81b shown in FIG. 10 . The recess 51x of the conductive plate 51 may be provided at the top of the conductive plate 51 or may penetrate the conductive plate 51.

[0073] The protrusion 82 on the inside of the case 8 and the recess 58x on the conductive plate 58 shown in Figure 1 are substantially similar in configuration to the protrusion 81 on the inside of the case 8 and the recess 51x on the conductive plate 51 shown in Figure 10, so duplicated explanations will be omitted.

[0074] <Method for Manufacturing Semiconductor Device> Fig. 11 is an exploded perspective view of the semiconductor device according to the first embodiment. An example of a method for manufacturing (assembling) the semiconductor device according to the first embodiment will be described with reference to Fig. 11 and other figures.

[0075] First, as shown in Figure 8, the control terminals 61-66 are integrally formed with the terminal holder 31, legs 32a-32d, and protrusions 33a-33c by insert molding or the like to prepare the terminal block 3a. Then, the control terminals 61-66 of the terminal block 3a are press-fitted into the printed circuit board 2a, and the legs 32a-32d of the terminal block 3a are inserted through the through-holes 21a-21d of the printed circuit board 2a, thereby integrating the terminal block 3a with the printed circuit board 2a. Similarly, the terminal blocks 3b and 3c are integrated with the printed circuit boards 2b and 2c.

[0076] Also, a case 8 is prepared in which the positive electrode terminals 11a to 11c, the negative electrode terminals 12a to 12c, and the output terminals 13a to 13c are integrated by insert molding or the like. In this state, the inside of the case 8 is not filled with the sealing resin 9 shown in FIG.

[0077] Furthermore, by attaching the insulating plate 6 and the conductive plate 5 to the upper surface of the cooler 7, a cooler-integrated substrate (5 to 7) is formed that includes the cooler 7, the insulating plate 6, and the conductive plate 5. Here, the conductive plate 5 is a general term for the conductive plates 51 to 59 shown in FIG.

[0078] Next, the semiconductor chip 4 is placed via solder on the conductive plate 5 of the cooler-integrated substrate (5-7). Here, the semiconductor chip 4 is a collective term for the semiconductor chips 41a-41f, 42a-42f, 43a-43f, 44a-44f, 45a-45f, and 46a-46f shown in FIG. 2. Furthermore, the connection members (pins) of the printed circuit boards 2a-2c integrated with the terminal blocks 3a-3c are placed via solder on the conductive plate 5 and the semiconductor chip 4. At this time, the legs 32a-32d of the terminal block 3a engage (fit) with the recesses 51a, 51b, 52a, and 52b of the conductive plates 51 and 52, thereby easily positioning the semiconductor chip 4 and the printed circuit board 2a. Similarly, the legs of the terminal blocks 3b and 3c engage (fit) with the recesses of the conductive plate 5, thereby easily positioning the semiconductor chip 4 and the printed circuit boards 2b and 2c. Thereafter, the solder is reflowed by heating, and the conductive plate 5, the semiconductor chip 4, and the printed circuit boards 2a to 2c are joined together.

[0079] Next, the case 8 is adhered to the upper surface of the cooler 7 via an adhesive or the like so as to house the semiconductor chip 4, the printed circuit boards 2a to 2c, and the terminal blocks 3a to 3c inside. At this time, the protrusions 81 and 82 of the case 8 shown in FIG. 1 are engaged (fitted) with the recesses 51x and 58x of the conductive plates 51 and 58, thereby easily positioning the positive terminals 11a to 11c, the negative terminals 12a to 12c, and the output terminals 13a to 13c integrated with the case 8, and the conductive plate 5. Then, the positive terminals 11a to 11c, the negative terminals 12a to 12c, and the output terminals 13a to 13c are joined to the conductive plate 5 by ultrasonic bonding or the like.

[0080] Next, the inside of the case 8 is filled with sealing resin 9 such as silicone gel or epoxy resin by potting or the like to seal the semiconductor chip 4, printed circuit boards 2a to 2c, and terminal blocks 3a to 3c. At this time, the control terminals 61 to 66 of the terminal blocks 3a to 3c protrude from the upper surface side of the sealing resin 9. In this way, the semiconductor device according to the first embodiment is completed.

[0081] In the semiconductor device according to the first embodiment, the conductive plates 51 and 52 are provided with positioning recesses 51a, 51b, 52a, and 52b. The control terminals 61-66 held by the terminal block 3a are press-fitted into the printed circuit board 2a, and the legs 32a-32d of the terminal block 3a are inserted through the through-holes 21a-21d of the printed circuit board 2a and engaged with the recesses 51a, 51b, 52a, and 52b of the conductive plates 51 and 52. This facilitates positioning of the semiconductor chips 41a-41f, 42a-42f and the printed circuit board 2a. Furthermore, by inserting the legs 32a-32d of the terminal block 3a through the through-holes 21a-21d of the printed circuit board 2a, warping of the printed circuit board 2a can be suppressed.

[0082] Furthermore, in the semiconductor device according to the first embodiment, positioning recesses 51x and 58x are provided in the conductive plates 51 and 58. Then, the protrusions 81 and 82 of the case 8 are engaged (fitted) into the recesses 51x and 58x of the conductive plates 51 and 58. This makes it possible to easily position the case 8, the positive terminals 11a to 11c, the negative terminals 12a to 12c, and the output terminals 13a to 13c integrated with the case 8, and the conductive plate 5.

[0083] Second Embodiment FIG. 12 is a cross-sectional view of a semiconductor device according to a second embodiment, corresponding to the cross section taken along line A-A' in FIG. 8. As shown in FIG. 12, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that the legs 32c and 32d do not have protrusions at their lower ends. The lower ends of the legs 32c and 32d engage with recesses 52a and 52b of the conductive plate 52. The other legs 32a and 32b of the terminal block 3a also have the same configuration as the legs 32c and 32d of the terminal block 3a shown in FIG. 12. Other configurations of the semiconductor device according to the second embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.

[0084] Third Embodiment FIG. 13 is a cross-sectional view of a semiconductor device according to a third embodiment, corresponding to the cross section taken along line A-A' in FIG. 8. As shown in FIG. 13, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that recesses 52a and 52b of the conductive plate 52 penetrate the conductive plate 52. The recesses 52a and 52b can be formed, for example, by etching the conductive plate 52 from the top and bottom surfaces, respectively. The recesses 51a and 51b of the conductive plate 51 also have the same configuration as the recesses 52a and 52b of the conductive plate 52 shown in FIG. 13. Since the other configurations of the semiconductor device according to the third embodiment are substantially the same as those of the semiconductor device according to the first embodiment, redundant description will be omitted.

[0085] Fourth Embodiment FIG. 14 is a cross-sectional view of a semiconductor device according to a fourth embodiment, corresponding to the cross section taken along line A-A' in FIG. 8. As shown in FIG. 14, the semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment in that the recesses 52a, 52b of the conductive plate 52 are annular (circular) grooves in a plan view and the legs 32c, 32d of the terminal block 3a are cylindrical (cylindrical). The other legs 32a, 32b of the terminal block 3a also have the same configuration as the legs 32c, 32d of the terminal block 3a shown in FIG. 14. Since the other configurations of the semiconductor device according to the fourth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, redundant description will be omitted.

[0086] Fifth Embodiment Figure 15 is a plan view of an optional conductive plate 50a of a semiconductor device according to a fifth embodiment and a conductive plate 50b, which is a floating island spaced apart from and provided inside the conductive plate 50a. As shown in Figure 15, the semiconductor device according to the fifth embodiment differs from the semiconductor device according to the first embodiment in that recesses 501 and 502 are provided on either side of the conductive plate 50b. The legs 32a and 32b of the terminal block 3a are engaged (fitted) into the recesses 501 and 502. Other configurations of the semiconductor device according to the fifth embodiment are substantially similar to those of the semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.

[0087] Sixth Embodiment Figure 16 is a plan view of an arbitrary conductive plate 50a of a semiconductor device according to a sixth embodiment and a conductive plate 50b, which is a floating island spaced apart from and provided inside the conductive plate 50a. As shown in Figure 16, the semiconductor device according to the sixth embodiment differs from the semiconductor device according to the first embodiment in that recesses 501 and 502 are provided at the corners of the conductive plate 50a. The positions of the legs 32a and 32b of the terminal block 3a are adjusted so that they engage with the recesses 501 and 502. The other configurations of the semiconductor device according to the sixth embodiment are substantially similar to those of the semiconductor device according to the first embodiment, and therefore, a redundant description will be omitted.

[0088] Seventh Embodiment Figure 17 is a plan view of an arbitrary conductive plate 50a of a semiconductor device according to a seventh embodiment and a conductive plate 50b, which is a floating island spaced apart from and located inside the conductive plate 50a. As shown in Figure 17, the semiconductor device according to the seventh embodiment differs from the semiconductor device according to the first embodiment in that recesses 501 and 502 are provided at the corners of the conductive plate 50a, and the recesses 501 and 502 are annular (circular) grooves. The positions of the legs 32a and 32b of the terminal block 3a are adjusted and the legs 32a and 32b are formed cylindrically so as to engage with the recesses 501 and 502. Other configurations of the semiconductor device according to the seventh embodiment are substantially similar to those of the semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.

[0089] Eighth Embodiment Figure 18 is a plan view of an arbitrary conductive plate 50a of a semiconductor device according to an eighth embodiment, and a conductive plate 50b, which is a floating island spaced apart from and provided inside the conductive plate 50a. As shown in Figure 18, the semiconductor device according to the eighth embodiment differs from the semiconductor device according to the first embodiment in that recesses 501 and 502 are provided at the corners of the conductive plate 50b. The positions of the legs 32a and 32b of the terminal block 3a are adjusted so that they engage with the recesses 501 and 502. The other configurations of the semiconductor device according to the eighth embodiment are substantially similar to those of the semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.

[0090] 19 is a cross-sectional view of a semiconductor device according to a ninth embodiment, corresponding to the cross section taken along line A-A' in FIG. 8. As shown in FIG. 19, the semiconductor device according to the ninth embodiment differs from the semiconductor device according to the first embodiment in that it does not have a terminal block 3a, and connection members (pins) 78a, 78b press-fitted into a printed circuit board 2a engage (fit) with recesses 501, 502. Other configurations of the semiconductor device according to the ninth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and therefore redundant description will be omitted.

[0091] As described above, the present disclosure has been described with reference to the first to ninth embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0092] For example, in the first embodiment, the positions of the positive electrode terminals 11a to 11c and the negative electrode terminals 12a to 12c may be reversed.

[0093] Furthermore, in the first embodiment, the terminal block 3a has four legs 32a to 32d, but this is not limiting. The terminal block 3a may have one, two, three, or five or more legs. For example, the terminal block 3a may have only legs 32a and 32d, without legs 32b and 32c. While the recesses 51a, 51b, 52a, and 52b of the conductive plates 51 and 52 for positioning with the terminal block 3a are shown as examples, the number and positions of the recesses can be adjusted as appropriate.

[0094] Furthermore, although the first embodiment has been described with reference to a three-phase 6-in-1 power semiconductor module, the present invention is not limited to this and may be applied to, for example, a one-phase 2-in-1 power semiconductor module.

[0095] In the first embodiment, the number and positions of the protrusions 81, 82 of the case 8 can also be adjusted as needed. The number and positions of the recesses 51x, 58x of the conductive plates 51, 58 for positioning with the protrusions 81, 82 of the case 8 can also be adjusted as needed. The number of protrusions and corresponding recesses of the case 8 may each be one, or three or more.

[0096] Furthermore, the configurations disclosed in the first to ninth embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present disclosure naturally includes various embodiments not described here. Therefore, the technical scope of the present disclosure is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description.

[0097] 2a to 2c...Printed circuit board 3a to 3c...Terminal block 4...Semiconductor chip 5...Conductive plate 6...Insulating plate 7...Cooler 7a to 7h...Through hole 7x...Cooling fin 8...Case 8a to 8h...Through hole 9...Sealing resin 11a to 11c...Positive terminal 11d to 11i...Joint part 12a to 12c...Negative electrode terminal 12d to 12f...Joint part 13a to 13c...Output terminal 13d to 13f...Joint part 21...Insulating layer 21a to 21d...Through hole 22a to 22h...Conductive layer 25a to 25f...Through hole 31...Terminal holding part 32a to 32d...Leg part 33a to 33c...Protrusion part (protrusion) 41...Gate electrode 41a to 41f, 42a to 42f, 43a to 43f, 44a to 44f, 45a to 45f, 46a to 46f...Semiconductor chip 42...Emitter electrode 50a, 50b, 51 to 59...Conductive plates 51a, 51b, 51x, 52a, 52b, 54a, 54b, 55a, 55b, 57a, 57b, 58a, 58b, 58x...Recesses 61 to 66...Control terminals 71a to 71f, 72a to 72f, 73a to 73f, 74a to 74h, 76a, 76b, 77, 78a, 78b...Connecting members (pins) 81, 82...Protrusions (locking portions) 81a...Protruding portion 81b...Extension portion 321, 323...Extension portion 322, 324...convex portions 501, 502...concave portions

Claims

1. A semiconductor device comprising: an insulating plate; a plurality of conductive plates provided on the insulating plate, each having a plurality of first recesses; a semiconductor chip provided on one of the plurality of conductive plates; a printed circuit board provided above the semiconductor chip, the printed circuit board having a plurality of through holes and a plurality of connecting members conductively connected to the semiconductor chip; a terminal holding portion for holding a plurality of terminals inserted into the printed circuit board; and a terminal block extending downward from the terminal holding portion and having a plurality of legs that engage with the plurality of first recesses via the plurality of through holes.

2. The semiconductor device according to claim 1, wherein the lower ends of the legs are provided with protrusions that engage with the first recesses.

3. The semiconductor device according to claim 1 or 2, wherein the first recess is provided in an upper portion of the conductive plate.

4. The semiconductor device according to claim 1 or 2, wherein the first recess penetrates the conductive plate.

5. The semiconductor device according to claim 1 or 2, wherein the first recess is a groove having an annular shape in a plan view, and the leg portion is cylindrical.

6. The semiconductor device according to claim 1 or 2, further comprising: a case in which a plurality of second recesses are provided in any of the plurality of conductive plates, the case housing the semiconductor chip and the printed circuit board inside, and the case having a plurality of locking portions that lock into the plurality of second recesses.

7. The semiconductor device according to claim 6, wherein the insulating plate is rectangular in plan view, and the plurality of second recesses are provided at diagonal positions of the rectangle.

8. The semiconductor device according to claim 6, wherein a main terminal is integrally provided on the case, and the main terminal is joined to one of the plurality of conductive plates.

9. The semiconductor device according to claim 1 or 2, further comprising a cooler provided below the insulating plate.

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