Display device, manufacturing method of display device, and electronic device including display device

Abstract

This display device comprises: a first and a second light-emitting element disposed on a pixel circuit layer and spaced apart from each other; a first light extraction structure disposed on the pixel circuit layer to overlap the first light-emitting element in a plan view; a second light extraction structure disposed on the pixel circuit layer to overlap the second light-emitting element in a plan view and spaced apart from the first light extraction structure; a cover layer covering the first and second light extraction structures and the pixel circuit layer; a first reflective layer surrounding a side surface of the first light extraction structure; and a second reflective layer surrounding a side surface of the second light extraction structure.

Description

Display device, method for manufacturing display device, and electronic device including display device

[0001] The present disclosure relates to a display device, a method for manufacturing the display device, and an electronic device including the display device.

[0002] A display device includes a pixel having two or more sub-pixels. These sub-pixels of the pixel can emit light of various colors and luminances based on a combination of light emitted from each of the sub-pixels.

[0003] The information disclosed in the background art is solely intended to enhance understanding of the background of the present disclosure and may therefore include information that does not constitute prior art.

[0004] Aspects according to embodiments of the present disclosure provide a display device capable of preventing light mixing between adjacent sub-pixels and improving light output efficiency of each sub-pixel.

[0005] Aspects according to embodiments of the present disclosure provide a method for manufacturing the display device.

[0006] Additional aspects will be set forth in part in the description below, and in part will be obvious from the description or may be learned by practicing the presented embodiments of the present disclosure.

[0007] A display device according to embodiments of the present disclosure includes first and second light-emitting elements disposed on a pixel circuit layer and spaced apart from each other; a first light-extracting structure disposed on the pixel circuit layer so as to overlap the first light-emitting element in a plane; a second light-extracting structure disposed on the pixel circuit layer so as to overlap the second light-emitting element in a plane and spaced apart from the first light-extracting structure; a cover layer covering the first and second light-extracting structures and the pixel circuit layer; a first reflective layer disposed so as to surround a side surface of the first light-extracting structure, the cover layer being interposed between the first reflective layer and the side surface of the first light-extracting structure; and a second reflective layer disposed so as to surround a side surface of the second light-extracting structure, the cover layer being interposed between the second reflective layer and the side surface of the second light-extracting structure.

[0008] In one embodiment, the first reflective layer and the second reflective layer may be spaced apart from each other.

[0009] In one embodiment, the edge of the first light extraction structure may be arranged so as to completely surround the edge of the first light emitting element on a planar surface, and the edge of the second light extraction structure may be arranged so as to completely surround the edge of the second light emitting element on a planar surface.

[0010] In one embodiment, the first light-emitting element can generate light of a first color, and the second light-emitting element can generate light of a second color different from the first color.

[0011] In one embodiment, the first light extraction structure may be in direct contact with the entire side surface of the first light emitting element and in direct contact with the entire top surface of the first light emitting element, and the second light extraction structure may be in direct contact with the entire side surface of the second light emitting element and in direct contact with the entire top surface of the second light emitting element.

[0012] In one embodiment, the first light-emitting element may include a 1-1 semiconductor layer, a 1-2 semiconductor layer disposed on the 1-1 semiconductor layer, and a first active layer interposed between the 1-1 semiconductor layer and the 1-2 semiconductor layer, and the second light-emitting element may include a 2-1 semiconductor layer, a 2-2 semiconductor layer disposed on the 2-1 semiconductor layer, and a second active layer interposed between the 2-1 semiconductor layer and the 2-2 semiconductor layer.

[0013] In one embodiment, the display device may include a first anode electrode disposed between the first light-emitting element and the pixel circuit layer; and a second anode electrode disposed between the second light-emitting element and the pixel circuit layer.

[0014] In one embodiment, the first light extraction structure may overlap the first anode electrode in a plane, and the second light extraction structure may overlap the second anode electrode in a plane.

[0015] In one embodiment, the display device may further include a cathode electrode disposed between the first and second light-emitting elements and the pixel circuit layer.

[0016] In one embodiment, the first light extraction structure may overlap planarly with a portion of the cathode electrode, and the second light extraction structure may overlap planarly with another portion of the cathode electrode.

[0017] In one embodiment, the first light extraction structure may include a first overcoating layer and a first light extraction layer disposed on the first overcoating layer, and the second light extraction structure may include a second overcoating layer and a second light extraction layer disposed on the second overcoating layer.

[0018] In one embodiment, the first overcoating layer may be in direct contact with at least a portion of the lower surface of the first light-emitting element, and the second overcoating layer may be in direct contact with at least a portion of the lower surface of the second light-emitting element.

[0019] In one embodiment, the display device may further include a third light-emitting element disposed on the pixel circuit layer and spaced apart from the first and second light-emitting elements; a third light-extracting structure disposed on the pixel circuit layer so as to overlap the third light-emitting element in a plane and spaced apart from the first and second light-extracting structures; and a third reflective layer disposed to surround a side surface of the third light-extracting structure, wherein the cover layer may be interposed between the third reflective layer and the side surface of the third light-extracting structure.

[0020] In one embodiment, the color of light generated by the third light-emitting element may be different from the color of light generated by the first light-emitting element and the color of light generated by the second light-emitting element.

[0021] In one embodiment, the display device may further include a passivation layer arranged to cover the cover layer, the first reflective layer, and the second reflective layer; and a color filter layer arranged on the passivation layer.

[0022] In one embodiment, the upper surface of the passivation layer may be flat.

[0023] A method for manufacturing a display device according to embodiments of the present disclosure may include forming first and second light-extracting structures on a pixel circuit layer, the first and second light-emitting elements overlapping each other in a plane and spaced apart from each other; forming a cover layer covering the first and second light-extracting structures and the pixel circuit layer; and forming first and second reflective layers arranged to surround side surfaces of the first and second light-extracting structures, the cover layer being interposed between the first reflective layer and the side surface of the first light-extracting structure and between the second reflective layer and the side surface of the second light-extracting structure.

[0024] In one embodiment, the step of forming the first and second reflective layers may include the step of forming a reflective layer covering the cover layer; and the step of partially etching the reflective layer to form the first and second reflective layers.

[0025] In one embodiment, the step of forming the first and second light extraction structures may include: forming the first and second light emitting elements spaced apart from each other on the pixel circuit layer; forming an overcoating layer on the pixel circuit layer; forming a light extraction layer covering the first and second light emitting elements on the overcoating layer; and forming the first and second light extraction structures by partially etching the overcoating layer and the light extraction layer.

[0026] In one embodiment, in the step of forming the overcoating layer, the first and second light-emitting elements may be partially buried in the overcoating layer.

[0027] An electronic device according to embodiments of the present disclosure includes a processor that provides input image data; and a display device that displays an image based on the input image data. The display device includes first and second light-emitting elements disposed on a pixel circuit layer and spaced apart from each other; a first light-extracting structure disposed on the pixel circuit layer so as to overlap the first light-emitting element in a plane; a second light-extracting structure disposed on the pixel circuit layer so as to overlap the second light-emitting element in a plane and spaced apart from the first light-extracting structure; a cover layer that covers the first and second light-extracting structures and the pixel circuit layer; a first reflective layer disposed so as to surround a side surface of the first light-extracting structure, the cover layer being interposed between the first reflective layer and the side surface of the first light-extracting structure; and a second reflective layer disposed so as to surround a side surface of the second light-extracting structure, the cover layer being interposed between the second reflective layer and the side surface of the second light-extracting structure.

[0028] In the display device according to embodiments of the present disclosure, the first and second reflective layers surrounding the side surfaces of the first and second light-extracting structures can serve to cause light emitted from the first and second light-emitting elements to be emitted in a predetermined desired direction. Accordingly, a display device with improved light-extraction efficiency can be provided.

[0029] Additionally, the first and second reflective layers may serve to prevent light mixing between adjacent sub-pixels. Accordingly, a display device capable of preventing light mixing between adjacent sub-pixels may be provided.

[0030] FIG. 1 is a block diagram illustrating a display device according to embodiments of the present disclosure.

[0031] FIG. 2 is a block diagram for explaining one of the sub-pixels included in the display device of FIG. 1.

[0032] FIG. 3 is a plan view for explaining a display panel constituting the display device of FIG. 1.

[0033] FIG. 4 is a cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0034] FIG. 5 is a cross-sectional view illustrating another embodiment of the display panel of FIG. 3.

[0035] FIGS. 6 and 7 are plan views illustrating one embodiment of one of the pixels included in the display panel of FIG. 3.

[0036] Figure 8 is a cross-sectional view taken along line I1-I1' of Figure 7.

[0037] Figure 9 is a cross-sectional view taken along line I2-I2' of Figure 7.

[0038] Fig. 10 is a cross-sectional view taken along line I3-I3' of Fig. 7.

[0039] Fig. 11 is a cross-sectional view taken along line J1-J1' of Fig. 7.

[0040] FIG. 12 is a drawing for explaining a method of manufacturing a display device including the pixels of FIG. 6 and FIG. 7.

[0041] Figures 13 to 19 are cross-sectional views for explaining the manufacturing method of Figure 12.

[0042] FIG. 20 is a block diagram illustrating a display system according to one embodiment.

[0043] Figures 21 to 24 are perspective views illustrating application examples of the display system of Figure 20.

[0044] Hereinafter, preferred embodiments according to the present disclosure will be described in detail with reference to the attached drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the present disclosure will be described, and the description of other parts will be omitted so as not to obscure the gist of the present disclosure. Furthermore, the present disclosure is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to explain the technical concepts of the present disclosure in sufficient detail to enable those skilled in the art to easily implement them.

[0045] In this disclosure, “comprising A or B,” “A and / or B,” etc., represent A or B, or A and B.

[0046] The term "and / or" as used herein includes any and all combinations of one or more associated listed items. Expressions such as "at least one of," "one of," and "selected from," as used herein, when preceding a list of elements, modify the list of elements as a whole and do not modify individual elements of the list. For example, "at least one of a, b, or c," "at least one selected from a, b, and c," etc. can refer to a only, b only, c only, both (e.g., simultaneously) a and b, both (e.g., simultaneously) a and c, both (e.g., simultaneously) b and c, all of a, b, and c, or variations thereof.

[0047] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected" but also the case where it is "indirectly connected" with another element in between. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the present disclosure. Throughout the specification, when a part is said to "comprise" a certain element, this does not exclude other elements unless specifically stated to the contrary, but rather means that it can include other elements. "At least one of X, Y, and Z," and "at least one selected from the array consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Herein, "and / or" includes any combination of one or more of the configurations.

[0048] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0049] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features would instead be positioned "above" the other elements or features. Thus, in one embodiment, the term "below" can encompass both above and below. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are to be interpreted accordingly.

[0050] Various embodiments are described with reference to drawings illustrating ideal embodiments. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the present embodiments are not limited thereto.

[0051] FIG. 1 is a block diagram illustrating a display device according to embodiments of the present disclosure.

[0052] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0053] The display panel (DP) may include sub-pixels (SP). The sub-pixels (SP) may be connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) may be connected to a data driver (130) via first to n-th data lines (DL1 to DLn).

[0054] The sub-pixels (SP) can generate light of two or more colors. For example, each of the sub-pixels (SP) can generate light of red, green, blue, cyan, magenta, yellow, etc.

[0055] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). That is, one pixel (PXL) can include two or more sub-pixels among the sub-pixels (SP). For example, the pixel (PXL) can include three sub-pixels as illustrated in FIG. 1. The pixel (PXL) (e.g., the sub-pixels (SP) of the pixel (PXL)) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels (e.g., each sub-pixel) included therein.

[0056] The gate driver (120) may be connected to the sub-pixels (SP) arranged in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) may output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) may include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0057] The gate driver (120) may be arranged on one side of the display panel (DP). However, embodiments are not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be arranged on one side of the display panel (DP) and the other side of the display panel (DP) opposite to the one side. In this way, the gate driver (120) may be arranged around the display panel (DP) in various forms according to embodiments.

[0058] The data driver (130) can be connected to the sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) can receive image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) can operate in response to the data control signal (DCS). In embodiments, the data control signal (DCS) can include a source start signal, a source shift clock, a source output enable signal, and the like.

[0059] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can use the received voltages to apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn). When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0060] In embodiments, the gate driver (120) and the data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0061] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) can be configured to generate a plurality of voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate a plurality of voltages by receiving an input voltage from the outside of the display device (DD) and regulating the received voltage.

[0062] A voltage generator (140) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In other embodiments, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0063] In addition, the voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a predetermined reference voltage can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In embodiments, the voltage generator (140) can provide pixel control signals to the sub-pixels (SP) through the pixel control lines (PXCL). Although FIG. 1 illustrates that the pixel control lines (PXCL) are connected between the voltage generator (140) and the display panel (DP), embodiments are not limited thereto. For example, the pixel control lines (PXCL) may be connected between the gate driver (120) and the display panel (DP). In this case, pixel control signals may be transmitted from the voltage generator (140) to the pixel control lines (PXCL) through the gate driver (120).

[0064] The controller (150) can control all operations of the display device (DD). The controller (150) can receive input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0065] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (DATA). In embodiments, the controller (150) can output image data (DATA) by arranging the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit.

[0066] Two or more components of the data driver (130), the voltage generator (140), and the controller (150) may be mounted on a single integrated circuit. As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within a single driver integrated circuit (DIC). That is, the data driver (130), the voltage generator (140), and the controller (150) may be separated from each other within a single driver integrated circuit (DIC). In embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0067] Fig. 2 is a block diagram for explaining one of the sub-pixels included in the display device of Fig. 1. In Fig. 2, a sub-pixel (SPij) arranged in the ith row (i is an integer greater than or equal to 1 and less than or equal to m) and the jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 is illustrated as an example.

[0068] Referring to FIG. 2, a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0069] A light emitting element (LD) may be connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) may be connected to one of the power supply lines (PL) of FIG. 1 and may receive a first power supply voltage. The second power supply voltage node (VSSN) may be connected to another of the power supply lines (PL) of FIG. 1 and may receive a second power supply voltage. The first power supply voltage may have a higher voltage level than the second power supply voltage.

[0070] A light emitting element (LD) may be connected between an anode electrode (AE) and a cathode electrode (CE). The anode electrode (AE) may be connected to a first power voltage node (VDDN) through a sub-pixel circuit (SPC). For example, the anode electrode (AE) may be connected to the first power voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC). The cathode electrode (CE) may be connected to a second power voltage node (VSSN). The light emitting element (LD) may be configured to emit light according to a current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0071] The sub-pixel circuit (SPC) may be connected to an i-th gate line (GLi) among the first to m-th gate lines (GL1 to GLm) of FIG. 1 and a j-th data line (DLj) among the first to n-th data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the i-th gate line (GLi), the sub-pixel circuit (SPC) may control the light-emitting element (LD) to emit light according to a data signal received through the j-th data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the light-emitting element (LD) in response to pixel control signals received through the pixel control lines (PXCL).

[0072] For these operations, a sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0073] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Silicon Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0074] FIG. 3 is a plan view for explaining a display panel constituting the display device of FIG. 1.

[0075] Referring to FIG. 3, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) may display an image through the display area (DA). The non-display area (NDA) may be positioned around the display area (DA).

[0076] A display panel (DP) may include sub-pixels (SP) in a display area (DA). The sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). For example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0077] Among the plurality of sub-pixels (SP), two or more sub-pixels can constitute one pixel (PXL). That is, one pixel (PXL) can include two or more sub-pixels among the sub-pixels (SP). In FIG. 3, the pixel (PXL) is illustrated as including three sub-pixels (SP1, SP2, SP3), but embodiments are not limited thereto. For example, the pixel (PXL) can include two sub-pixels. Hereinafter, for convenience of explanation, it is assumed that the pixel (PXL) includes first to third sub-pixels (SP1, SP2, SP3).

[0078] Each of the first to third sub-pixels (SP1, SP2, SP3) can generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. Hereinafter, for the sake of clarity and concise explanation, it is assumed that the first sub-pixel (SP1) is configured to generate light of red color (first color), the second sub-pixel (SP2) is configured to generate light of green color (second color), and the third sub-pixel (SP3) is configured to generate light of blue color (third color).

[0079] Each of the first to third sub-pixels (SP1, SP2, SP3) may include at least one light-emitting element configured to generate light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate light of different colors. For example, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate light of red color, green color, and blue color, respectively.

[0080] As a display panel (DP), a self-luminous display panel such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements, can be used.

[0081] Components for controlling sub-pixels (SP) may be arranged in the non-display area (NDA). Wires connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1, may be arranged in the non-display area (NDA).

[0082] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) may be disposed in the non-display area (NDA). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120) may be implemented as a single integrated circuit that is separate from the display panel (DP) together with the data driver (130), the voltage generator (140), and the controller (150).

[0083] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have a closed-loop shape including straight and / or curved edges. For example, the display area (DA) may have shapes such as a polygon, a circle, a semicircle, or an ellipse.

[0084] In some embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface.

[0085] In embodiments, the display panel (DP) may be bendable, foldable, or rollable. In such cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0086] FIG. 4 is a cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0087] Referring to FIG. 4, the display panel (DP) may include a substrate (SUB), and a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (LFL) that are sequentially laminated in a third direction (DR3) intersecting the first and second directions (DR1, DR2) on the substrate (SUB).

[0088] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. As another example, the substrate (SUB) may include a polyimide (PI) substrate. As another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0089] In embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0090] A pixel circuit layer (PCL) may be disposed on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, etc.

[0091] The circuit elements of the pixel circuit layer (PCL) may include sub-pixel circuits (SPC, see FIG. 2) of each of the sub-pixels (SP) of FIG. 3. For example, the circuit elements of the pixel circuit layer (PCL) may be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0092] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines necessary to drive the display element layer (DPL).

[0093] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0094] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In embodiments, the light-converting patterns and the light-scattering patterns may be omitted.

[0095] The light function layer (LFL) may include a color filter layer including color filters. The color filter may selectively transmit light of a specific wavelength (or color). In some embodiments, the color filter layer may be omitted.

[0096] A window may be provided on a light-functional layer (LFL) to protect an exposed surface (or upper surface) of a display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded to the light-functional layer (LFL) via an optically transparent adhesive (or, bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0097] FIG. 5 is a cross-sectional view illustrating another embodiment of the display panel of FIG. 3.

[0098] Referring to FIG. 5, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light function layer (LFL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) may be configured similarly to the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) described with reference to FIG. 4. Hereinafter, any overlapping description may be omitted.

[0099] The input sensing layer (ISL) can detect a user's input on the upper surface (or display surface) of the display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting an external object, such as a user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0100] FIGS. 6 and 7 are plan views illustrating one embodiment of one of the pixels included in the display panel of FIG. 3.

[0101] Referring to FIG. 6, a pixel (PXL) may include first to third sub-pixels (SP1, SP2, SP3). The first to third sub-pixels (SP1, SP2, SP3) may be arranged in a first direction (DR1). However, the arrangement of the first to third sub-pixels (SP1, SP2, SP3) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1, SP2, SP3) may be arranged in a zigzag pattern.

[0102] First to third anode electrodes (AE1, AE2, AE3) may be arranged in the first to third sub-pixels (SP1, SP2, SP3), respectively. The first anode electrode (AE1) may be provided as an anode electrode (AE, see FIG. 2) connected to a sub-pixel circuit (SPC, see FIG. 2) of the first sub-pixel (SP1). The second anode electrode (AE2) may be provided as an anode electrode (AE) connected to a sub-pixel circuit (SPC) of the second sub-pixel (SP2). The third anode electrode (AE3) may be provided as an anode electrode (AE) connected to a sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0103] The cathode electrode (CE) can be spaced apart from the first to third anode electrodes (AE1, AE2, AE3). The cathode electrode (CE) can be arranged on the same layer as the first to third anode electrodes (AE1, AE2, AE3). The cathode electrode (CE) can be spaced apart from the first to third anode electrodes (AE1, AE2, AE3) in the second direction (DR2).

[0104] In the embodiments, the cathode electrode (CE) may extend in the first direction (DR1) and may be used as a common electrode for the pixel (PXL) and other pixels adjacent to the pixel (PXL). In the embodiments, the cathode electrode (CE) may extend in the second direction (DR2) as well as the first direction (DR1) and may be used as a common electrode for all of the sub-pixels (SP) of FIG. 3. That is, the cathode electrode (CE) may be used as a common electrode for the first to third sub-pixels (SP1, SP2, SP3). In this way, the cathode electrode (CE) may have various shapes.

[0105] First to third light-emitting elements (LD1, LD2, LD3) may be disposed on first to third anode electrodes (AE1, AE2, AE3) and a cathode electrode (CE). The first light-emitting element (LD1) may be electrically connected to the first anode electrode (AE1) and the cathode electrode (CE). The first light-emitting element (LD1) may be provided as a light-emitting element (LD, see FIG. 2) connected to a sub-pixel circuit (SPC) of a first sub-pixel (SP1). The second light-emitting element (LD2) may be electrically connected to the second anode electrode (AE2) and the cathode electrode (CE). The second light-emitting element (LD2) may be provided as a light-emitting element (LD) connected to a sub-pixel circuit (SPC) of a second sub-pixel (SP2). The third light-emitting element (LD3) may be electrically connected to the third anode electrode (AE3) and the cathode electrode (CE). The third light-emitting element (LD3) may be provided as a light-emitting element (LD) connected to the sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0106] The first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3) may be inorganic light-emitting diodes including inorganic light-emitting materials. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may also be used.

[0107] Referring to FIG. 7, first to third light extraction structures (LES1, LES2, LES3) may be arranged in first to third sub-pixels (SP1, SP2, SP3), respectively.

[0108] The first light extracting structure (LES1) can overlap the first light emitting element (LD1) in a planar manner. In this case, in a planar manner, the edge of the first light extracting structure (LES1) can completely surround the edge of the first light emitting element (LD1). In one embodiment, the first light extracting structure (LES1) can overlap the first anode electrode (AE1) in a planar manner. In this case, in a planar manner, the edge of the first light extracting structure (LES1) can completely surround the edge of the first anode electrode (AE1). In this disclosure, unless otherwise defined, “in a planar manner” is intended to refer to how a structure (e.g., the first light extracting structure (LES1)) overlaps another structure or structures (e.g., the first light emitting element (LD1) and the first anode electrode (AE1)) when viewed from above. This helps to visualize the position and alignment of these components in a flat plane.

[0109] The second light extraction structure (LES2) can be spaced apart from the first light extraction structure (LES1). The second light extraction structure (LES2) can overlap the second light emitting element (LD2) in a plan view. In this case, in a plan view, an edge of the second light extraction structure (LES2) can completely surround an edge of the second light emitting element (LD2). In one embodiment, the second light extraction structure (LES2) can overlap the second anode electrode (AE2) in a plan view. In this case, in a plan view, an edge of the second light extraction structure (LES2) can completely surround an edge of the second anode electrode (AE2).

[0110] The third light extraction structure (LES3) can be spaced apart from the first and second light extraction structures (LES1, LES2). The third light extraction structure (LES3) can overlap the third light emitting element (LD3) in a plan view. In this case, in a plan view, an edge of the third light extraction structure (LES3) can completely surround an edge of the third light emitting element (LD3). In one embodiment, the third light extraction structure (LES3) can overlap the third anode electrode (AE3) in a plan view. In this case, in a plan view, an edge of the third light extraction structure (LES3) can completely surround an edge of the third anode electrode (AE3).

[0111] In one embodiment, each of the first to third light extraction structures (LES1, LES2, LES3) may partially overlap the cathode electrode (CE) in a planar manner. The first light extraction structure (LES1) may overlap a portion of the cathode electrode (CE) in a planar manner. The second light extraction structure (LES2) may overlap another portion of the cathode electrode (CE) in a planar manner. The third light extraction structure (LES3) may overlap another portion of the cathode electrode (CE) in a planar manner.

[0112] Fig. 8 is a cross-sectional view taken along line I1-I1' of Fig. 7. Fig. 8 is a cross-sectional view for explaining the first sub-pixel.

[0113] Referring to FIGS. 6 to 8, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0114] A pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns stacked on a substrate (SUB). The insulating layers may include a buffer layer (BFL), one or more interlayer insulating layers (ILD), and one or more passivation layers (PSV1, PSV2). The semiconductor patterns and conductive patterns may be positioned between the insulating layers. The conductive patterns may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0115] As described with reference to FIG. 2, each of the first to third sub-pixels (SP1, SP2, SP3) may include a sub-pixel circuit (SPC, see FIG. 2) of transistors and one or more capacitors. The semiconductor patterns and conductive patterns of the pixel circuit layer (PCL) may function as transistors and capacitors of the sub-pixel circuit (SPC). In addition, the conductive patterns of the pixel circuit layer (PCL) may further function as wirings, for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1.

[0116] A buffer layer (BFL) may be disposed on one surface of a substrate (SUB). The buffer layer (BFL) may serve to prevent impurities from diffusing into circuit elements and wirings included in a pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer including an inorganic material. In embodiments, the buffer layer (BFL) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. The buffer layer (BFL) may be provided as a single layer or multiple layers. When the buffer layer (BFL) is provided as multiple layers, each layer may be formed of the same material or different materials.

[0117] In embodiments, one or more barrier layers may be disposed between the substrate (SUB) and the buffer layer (BFL). Each of the barrier layers may include polyimide.

[0118] A first transistor (T_SP1) may be placed on a buffer layer (BFL). The first transistor (T_SP1) may be any one of the transistors of a sub-pixel circuit (SPC) included in a first sub-pixel (SP1). The first transistor (T_SP1) may be a transistor connected to a first anode electrode (AE1) among the transistors of the sub-pixel circuit (SPC).

[0119] A first transistor (T_SP1) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (ET1), and a second terminal (ET2). The first terminal (ET1) may be either a source electrode or a drain electrode, and the second terminal (ET2) may be the other of the source electrode and the drain electrode. For example, the first terminal (ET1) may be a source electrode, and the second terminal (ET2) may be a drain electrode.

[0120] A semiconductor pattern (SCP) may be disposed on a buffer layer (BFL). The semiconductor pattern (SCP) may include a first contact region contacting a first terminal (ET1) and a second contact region contacting a second terminal (ET2). A region between the first contact region and the second contact region may be a channel region. The channel region may overlap with a gate electrode (GE) of the first transistor (T_SP1). The channel region may be a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. For example, a p-type impurity may be used as the impurity, but the embodiments are not limited thereto.

[0121] The semiconductor pattern (SCP) may include any one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a low temperature poly silicon semiconductor, and an oxide semiconductor.

[0122] Interlayer insulating layers (ILDs) may be sequentially stacked on a semiconductor pattern (SCP). The interlayer insulating layers (ILDs) may be inorganic insulating layers including inorganic materials. For example, each of the interlayer insulating layers (ILDs) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide. However, the interlayer insulating layers (ILDs) are not limited thereto. For example, any one of the interlayer insulating layers (ILDs) may include an organic insulating layer including an organic material.

[0123] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers (ILDs). For example, the interlayer insulating layers (ILDs) can include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) can be disposed between the semiconductor pattern (SCP) and the gate electrode (GE) such that the gate electrode (GE) is spaced apart from the semiconductor pattern (SCP). In embodiments, the gate insulating layer (GI) can be provided over the entire surface of the semiconductor pattern (SCP) and the buffer layer (BFL) to cover the semiconductor pattern (SCP) and the buffer layer (BFL). As the number of layers required for forming the conductive patterns and / or semiconductor patterns increases, the number of interlayer insulating layers (ILDs) can increase.

[0124] A gate electrode (GE) may be disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap a channel region of a semiconductor pattern (SCP). In embodiments, the gate electrode (GE) may be provided as a single layer including at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In embodiments, the gate electrode (GE) may be provided as a multilayer including at least one material selected from the group consisting of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag), which are low-resistance materials.

[0125] The first and second terminals (ET1, ET2) may be disposed on interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may contact a semiconductor pattern (SCP) through contact holes penetrating the interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may contact first and second contact regions of the semiconductor pattern (SCP), respectively. In embodiments, the first and second contact regions of the semiconductor pattern (SCP) may be spaced apart from each other in a first direction (DR1). In embodiments, the first and second contact regions of the semiconductor pattern (SCP) may be opposite sides of the semiconductor pattern (SCP). Each of the first and second terminals (ET1, ET2) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0126] In embodiments, the first transistor (T_SP1) may be formed of a low-temperature polysilicon transistor. However, the embodiments are not limited thereto. For example, the first transistor (T_SP1) may also be formed of an oxide semiconductor transistor. In embodiments, the sub-pixel circuit of the first sub-pixel (SP1) may include transistors of different types. For example, the first transistor (T_SP1) may be formed of a low-temperature polysilicon transistor, and the other transistors of the first sub-pixel (SP1) may be formed of oxide semiconductor transistors. In this case, the oxide semiconductor of the oxide semiconductor transistor may be formed on any one of the interlayer insulating layers (ILD) other than the insulating layer on which the semiconductor pattern (SCP) of the first transistor (T_SP1) is formed.

[0127] In the embodiments, the first transistor (T_SP1) is described as a transistor having a top gate structure, but the embodiments are not limited thereto. For example, the first transistor (T_SP1) may be a transistor having a bottom gate structure. In addition, the structure of the first transistor (T_SP1) may be changed in various ways.

[0128] At least some of the various wirings of the display panel (DP) and / or display device (DD) may be further arranged on the interlayer insulating layers (ILD).

[0129] A first passivation layer (PSV1) may be disposed over the interlayer insulating layers (ILD) and the first and second terminals (ET1, ET2). The passivation layer may also be referred to as a protective layer or a via layer. The first passivation layer (PSV1) protects components disposed beneath it and may provide a flat upper surface.

[0130] A first connection pattern (CP1) may be disposed on a first passivation layer (PSV1). The first connection pattern (CP1) may penetrate the first passivation layer (PSV1) and be connected to a first terminal (ET1) of a first transistor (T_SP1). The first connection pattern (CP1) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0131] At least some of the various wires of the display panel (DP) and / or the display device (DD) may be further arranged on the first passivation layer (PSV1).

[0132] A second passivation layer (PSV2) may be disposed on the first connection pattern (CP1) and the first passivation layer (PSV1). The second passivation layer (PSV2) may protect components disposed underneath it and provide a flat upper surface.

[0133] Each of the first and second passivation layers (PSV1, PSV2) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The organic insulating layer may include, for example, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0134] The first and second passivation layers (PSV1, PSV2) may comprise the same material as one of the interlayer insulating layers (ILD), but embodiments are not limited thereto. Each of the first and second passivation layers (PSV1, PSV2) may be provided as a single layer, but may also be provided as multiple layers.

[0135] A display element layer (DPL) may be disposed on a second passivation layer (PSV2). The display element layer (DPL) may include a first anode electrode (AE1), a cathode electrode (CE), a first light-emitting element (LD1), a first light extraction structure (LES1), a cover layer (CVL), and a first reflective layer (RFL1).

[0136] The first anode electrode (AE1) may be disposed on the pixel circuit layer (PCL). The first anode electrode (AE1) may be electrically connected to the first connection pattern (CP1) through a contact hole penetrating the second passivation layer (PSV2). In this way, the first anode electrode (AE1) may be electrically connected to the first transistor (T_SP1).

[0137] The cathode electrode (CE) may be disposed on the pixel circuit layer (PCL). The cathode electrode (CE) may be spaced apart from the first anode electrode (AE1). The cathode electrode (CE) may be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) may be transmitted to the cathode electrode (CE).

[0138] A first light-emitting element (LD1) may be disposed on a first anode electrode (AE1) and a cathode electrode (CE). The first light-emitting element (LD1) may include a first light-emitting stack (EST1), a first-first bonding electrode (BDE1a), a first-second bonding electrode (BDE2a), and a first insulating film (30a).

[0139] The first light-emitting stack (EST1) may be configured to be suitable for emitting light of a first color. The first light-emitting stack (EST1) may include a first-first semiconductor layer (10a), a first active layer (MQW1), and a first-second semiconductor layer (20a).

[0140] The first-first semiconductor layer (10a) may be configured to provide holes. The first-first semiconductor layer (10a) may have a first polarity. For example, the first-first semiconductor layer (10a) may include at least one p-type semiconductor layer. For example, the first-first semiconductor layer (10a) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc. However, the material constituting the first-first semiconductor layer (10a) is not limited thereto, and various other materials may constituting the first-first semiconductor layer (10a). In one embodiment of the present disclosure, the first-first semiconductor layer (10a) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0141] The first active layer (MQW1) may be disposed on the 1-1 semiconductor layer (10a). The first active layer (MQW1) may be interposed between the 1-1 semiconductor layer (10a) and the 1-2 semiconductor layer (20a) to provide a region where electrons and holes recombine. As electrons and holes recombine in the first active layer (MQW1), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The first active layer (MQW1) may be formed in a single or multiple quantum well structure. When the first active layer (MQW1) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcement layer, and a well layer may be repeatedly stacked to form the first active layer (MQW1). However, the first active layer (MQW1) is not limited to the above-described structure.

[0142] In one embodiment, the first active layer (MQW1) may be configured to emit light of a first color (e.g., red). In such a case, the first active layer (MQW1) may include a material suitable for emitting light of the first color.

[0143] The first-second semiconductor layer (20a) may be disposed on the first active layer (MQW1). The first-second semiconductor layer (20a) may include a first doped layer (21a) and a first auxiliary layer (22a) disposed on the first doped layer (21a).

[0144] The first doped layer (21a) may be disposed on the first active layer (MQW1). The first doped layer (21a) may be configured to provide electrons. The first doped layer (21a) may have a second polarity different from the first polarity. For example, the first doped layer (21a) may include at least one n-type semiconductor layer. For example, the first doped layer (21a) may include any one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first doped layer (21a) is not limited thereto, and various other materials may also constitute the first doped layer (21a). In one embodiment of the present disclosure, the first doped layer (21a) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant).

[0145] The first auxiliary layer (22a) may include a gallium nitride (GaN) semiconductor material that is substantially undoped with impurities or doped with impurities at a relatively low concentration. The first auxiliary layer (22a) may form an n-type semiconductor layer together with the first doped layer (21a).

[0146] The first-first bonding electrode (BDE1a) may be bonded and fixed on the first anode electrode (AE1). The first-first bonding electrode (BDE1a) may be connected to the first-first semiconductor layer (10a) and the first anode electrode (AE1). Through the first-first bonding electrode (BDE1a), the first-first semiconductor layer (10a) and the first anode electrode (AE1) may be electrically connected. In one embodiment, the first-first bonding electrode (BDE1a) may include a eutectic metal.

[0147] The first-second bonding electrode (BDE2a) may be bonded and fixed on the cathode electrode (CE). The first-second bonding electrode (BDE2a) may be connected to the first-second semiconductor layer (20a) and the cathode electrode (CE). Through the first-second bonding electrode (BDE2a), the first-second semiconductor layer (20a) and the cathode electrode (CE) may be electrically connected. In one embodiment, the first-second bonding electrode (BDE2a) may include a eutectic metal.

[0148] The first insulating film (30a) can cover at least a portion of the outer circumferential surface of the first light-emitting stack (EST1). The first insulating film (30a) is interposed between the first-second bonding electrode (BDE2a) and the first active layer (MQW1), and between the first-second bonding electrode (BDE2a) and the first-first semiconductor layer (10a), thereby preventing an electrical short circuit that may occur when the first-second bonding electrode (BDE2a) comes into contact with the first active layer (MQW1) and the first-first semiconductor layer (10a). The first insulating film (30a) can have a single-layer structure or a multi-layer structure including a transparent insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0149] A first light extraction structure (LES1) may be disposed on a pixel circuit layer (PCL) to cover a first light emitting element (LD1). The first light extraction structure (LES1) may be in direct contact with the entire side surface and the entire top surface of the first light emitting element (LD1).

[0150] In one embodiment, the first light extraction structure (LES1) may include a first overcoating layer (OCL1) and a first light extraction layer (NOC1) disposed on the first overcoating layer (OCL1).

[0151] The first overcoating layer (OCL1) can be in direct contact with at least a portion of the lower surface of the first light-emitting element (LD1). The first overcoating layer (OCL1) can be in direct contact with a portion of a side surface of the first light-emitting element (LD1) adjacent to the lower surface of the first light-emitting element (LD1). The first light-emitting element (LD1) can be partially buried in the first overcoating layer (OCL1). The first overcoating layer (OCL1) can fix the first light-emitting element (LD1) bonded to the first anode electrode (AE1) and the cathode electrode (CE) so as not to move. The first overcoating layer (OCL1) can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the first overcoating layer (OCL1) can include epoxy, but the embodiments are not limited thereto.

[0152] The first light extraction layer (NOC1) may be in direct contact with the entire upper surface of the first light-emitting element (LD1). The first light extraction layer (NOC1) may be in direct contact with a side surface of the first light-emitting element (LD1) that is not in contact with the first overcoating layer (OCL1). The first light extraction layer (NOC1) may include a transparent insulating material.

[0153] The cover layer (CVL) may cover the first light extraction structure (LES1) and the pixel circuit layer (PCL). The cover layer (CVL) may include, for example, an inorganic insulating layer including an inorganic material.

[0154] A first reflective layer (RFL1) may be arranged to surround a side surface of a first light extraction structure (LES1). A cover layer (CVL) may be interposed between the first reflective layer (RFL1) and the side surface of the first light extraction structure (LES1). The first reflective layer (RFL1) may include a material suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1) may be improved. In one embodiment, the first reflective layer (RFL1) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0155] A light functional layer (LFL) may be disposed on the cover layer (CVL) and the first reflective layer (RFL1). The light functional layer (LFL) may include a third passivation layer (PSV3) and a color filter layer (CFL).

[0156] The third passivation layer (PSV3) can cover the cover layer (CVL) and the first reflective layer (RFL1). The third passivation layer (PSV3) can include the same material as any one of the first and second passivation layers (PSV1, PSV2). For example, the first passivation layer (PSV1), the second passivation layer (PSV2), and the third passivation layer (PSV3) can include the same material. The third passivation layer (PSV3) can provide a flat upper surface.

[0157] A color filter layer (CFL) may be disposed on the third passivation layer (PSV3). The color filter layer (CFL) may include a first color filter (CF1) and light-blocking patterns (LBP). The first color filter (CF1) may selectively transmit light in a desired wavelength range. For example, the first color filter (CF1) may selectively transmit red light. The light-blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0158] Fig. 9 is a cross-sectional view taken along line I2-I2' of Fig. 7. Fig. 9 is a cross-sectional view for explaining the second sub-pixel.

[0159] Referring to FIGS. 6, 7, and 9, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0160] The pixel circuit layer (PCL) can be described in the same manner as described with reference to Fig. 8. For example, the pixel circuit layer (PCL) can include a second transistor (T_SP2) constituting a sub-pixel circuit (SPC) of a second sub-pixel (SP2), and a second connection pattern (CP2) connected thereto.

[0161] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include a second anode electrode (AE2), a cathode electrode (CE), a second light-emitting element (LD2), a second light extraction structure (LES2), a cover layer (CVL), and a second reflective layer (RFL2).

[0162] The second anode electrode (AE2) may be disposed on the pixel circuit layer (PCL). The second anode electrode (AE2) may be electrically connected to the second connection pattern (CP2) through a contact hole penetrating the second passivation layer (PSV2). In this way, the second anode electrode (AE2) may be electrically connected to the second transistor (T_SP2).

[0163] A second light-emitting element (LD2) may be disposed on the second anode electrode (AE2) and the cathode electrode (CE). The second light-emitting element (LD2) may include a second light-emitting stack (EST2), a second-first bonding electrode (BDE1b), a second-second bonding electrode (BDE2b), and a second insulating film (30b).

[0164] The second light-emitting stack (EST2) may be configured to emit light of a second color. The second light-emitting stack (EST2) may include a second-first semiconductor layer (10b), a second active layer (MQW2), and a second-second semiconductor layer (20b).

[0165] The second-first semiconductor layer (10b) may be configured to provide holes. The second-first semiconductor layer (10b) may have a first polarity. For example, the second-first semiconductor layer (10b) may include at least one p-type semiconductor layer. For example, the second-first semiconductor layer (10b) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like. However, the material constituting the second-first semiconductor layer (10b) is not limited thereto, and various other materials may constituting the second-first semiconductor layer (10b). In one embodiment of the present disclosure, the second-1 semiconductor layer (10b) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0166] The second active layer (MQW2) may be disposed on the 2-1 semiconductor layer (10b). The second active layer (MQW2) may be interposed between the 2-1 semiconductor layer (10b) and the 2-2 semiconductor layer (20b) to provide a region where electrons and holes recombine. As electrons and holes recombine in the second active layer (MQW2), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The second active layer (MQW2) may be formed in a single or multiple quantum well structure. When the second active layer (MQW2) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcement layer, and a well layer may be repeatedly stacked to form the second active layer (MQW2). However, the second active layer (MQW2) is not limited to the above-described structure.

[0167] In one embodiment, the second active layer (MQW2) may be configured to emit light of a second color (e.g., green). In such a case, the second active layer (MQW2) may include a material suitable for emitting light of the second color.

[0168] The second-second semiconductor layer (20b) may be disposed on the second active layer (MQW2). The second-second semiconductor layer (20b) may include a second doped layer (21b) and a second auxiliary layer (22b) disposed on the second doped layer (21b).

[0169] The second doped layer (21b) may be disposed on the second active layer (MQW2). The second doped layer (21b) may be configured to provide electrons. The second doped layer (21b) may have a second polarity. For example, the second doped layer (21b) may include at least one n-type semiconductor layer. For example, the second doped layer (21b) may include any one of a semiconductor material selected from gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the second doped layer (21b) is not limited thereto, and various other materials may also constitute the second doped layer (21b). In one embodiment of the present disclosure, the second doped layer (21b) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant).

[0170] The second auxiliary layer (22b) may include a gallium nitride (GaN) semiconductor material that is substantially undoped with impurities or doped with impurities at a relatively low concentration. The second auxiliary layer (22b) may form an n-type semiconductor layer together with the second doped layer (21b).

[0171] The second-first bonding electrode (BDE1b) may be bonded and fixed on the second anode electrode (AE2). The second-first bonding electrode (BDE1b) may be connected to the second-first semiconductor layer (10b) and the second anode electrode (AE2). Through the second-first bonding electrode (BDE1b), the second-first semiconductor layer (10b) and the second anode electrode (AE2) may be electrically connected. In one embodiment, the second-first bonding electrode (BDE1b) may include a eutectic metal.

[0172] The second-second bonding electrode (BDE2b) may be bonded and fixed on the cathode electrode (CE). The second-second bonding electrode (BDE2b) may be connected to the second-second semiconductor layer (20b) and the cathode electrode (CE). Through the second-second bonding electrode (BDE2b), the second-second semiconductor layer (20b) and the cathode electrode (CE) may be electrically connected. In one embodiment, the second-second bonding electrode (BDE2b) may include a eutectic metal.

[0173] The second insulating film (30b) can cover at least a portion of the outer circumferential surface of the second light-emitting stack (EST2). The second insulating film (30b) is interposed between the 2-2 bonding electrode (BDE2b) and the second active layer (MQW2), and between the 2-2 bonding electrode (BDE2b) and the 2-1 semiconductor layer (10b), thereby preventing an electrical short circuit that may occur when the 2-2 bonding electrode (BDE2b) comes into contact with the second active layer (MQW2) and the 2-1 semiconductor layer (10b). The second insulating film (30b) can have a single-layer structure or a multi-layer structure including a transparent insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0174] A second light extraction structure (LES2) may be disposed on the pixel circuit layer (PCL) to cover the second light emitting element (LD2). The second light extraction structure (LES2) may be in direct contact with the entire side surface and the entire top surface of the second light emitting element (LD2).

[0175] In one embodiment, the second light extraction structure (LES2) may include a second overcoating layer (OCL2) and a second light extraction layer (NOC2) disposed on the second overcoating layer (OCL2).

[0176] The second overcoating layer (OCL2) can be in direct contact with at least a portion of the lower surface of the second light-emitting element (LD2). The second overcoating layer (OCL2) can be in direct contact with a portion of a side surface of the second light-emitting element (LD2) adjacent to the lower surface of the second light-emitting element (LD2). The second light-emitting element (LD2) can be partially buried in the second overcoating layer (OCL2). The second overcoating layer (OCL2) can fix the second light-emitting element (LD2) bonded to the second anode electrode (AE2) and the cathode electrode (CE) so as not to move. The second overcoating layer (OCL2) can include the same material as the first overcoating layer (OCL1). That is, the first overcoating layer (OCL1) and the second overcoating layer (OCL2) can include the same material.

[0177] The second light extraction layer (NOC2) can be in direct contact with the entire upper surface of the second light-emitting element (LD2). The second light extraction layer (NOC2) can be in direct contact with a side surface of the second light-emitting element (LD2) that is not in contact with the second overcoating layer (OCL2). The second light extraction layer (NOC2) can include the same material as the first light extraction layer (NOC1). That is, the first light extraction layer (NOC1) and the second light extraction layer (NOC2) can include the same material.

[0178] The cover layer (CVL) can cover the second light extraction structure (LES2) and the pixel circuit layer (PCL).

[0179] The second reflective layer (RFL2) may be arranged to surround a side surface of the second light extraction structure (LES2). A cover layer (CVL) may be interposed between the second reflective layer (RFL2) and the side surface of the second light extraction structure (LES2). The second reflective layer (RFL2) may be spaced apart from the first reflective layer (RFL1). The second reflective layer (RFL2) may include the same material as the first reflective layer (RFL1). That is, the first reflective layer (RFL1) and the second reflective layer (RFL2) may include the same material.

[0180] A light functional layer (LFL) may be disposed on the cover layer (CVL) and the second reflective layer (RFL2). The light functional layer (LFL) may include a third passivation layer (PSV3) and a color filter layer (CFL).

[0181] The third passivation layer (PSV3) can cover the cover layer (CVL) and the second reflective layer (RFL2). The third passivation layer (PSV3) can provide a flat upper surface.

[0182] A color filter layer (CFL) may be disposed on the third passivation layer (PSV3). The color filter layer (CFL) may include a second color filter (CF2) and light-blocking patterns (LBP). The second color filter (CF2) may selectively transmit light in a desired wavelength range. For example, the second color filter (CF2) may selectively transmit green light. The light-blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0183] Fig. 10 is a cross-sectional view taken along line I3-I3' of Fig. 7. Fig. 10 is a cross-sectional view for explaining the third sub-pixel.

[0184] Referring to FIGS. 6, 7, and 10, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0185] The pixel circuit layer (PCL) can be described in the same manner as described with reference to Fig. 8. For example, the pixel circuit layer (PCL) can include a third transistor (T_SP3) constituting a sub-pixel circuit (SPC) of a third sub-pixel (SP3), and a third connection pattern (CP3) connected thereto.

[0186] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include a third anode electrode (AE3), a cathode electrode (CE), a third light-emitting element (LD3), a third light extraction structure (LES3), a cover layer (CVL), and a third reflective layer (RFL3).

[0187] The third anode electrode (AE3) may be disposed on the pixel circuit layer (PCL). The third anode electrode (AE3) may be electrically connected to the third connection pattern (CP3) through a contact hole penetrating the third passivation layer (PSV2). In this way, the third anode electrode (AE3) may be electrically connected to the third transistor (T_SP3).

[0188] A third light-emitting element (LD3) may be placed on the third anode electrode (AE3) and the cathode electrode (CE). The third light-emitting element (LD3) may include a third light-emitting stack (EST3), a third-first bonding electrode (BDE1c), a third-second bonding electrode (BDE2c), and a third insulating film (30c).

[0189] The third light-emitting stack (EST3) may be configured to emit light of a third color. The third light-emitting stack (EST3) may include a third-first semiconductor layer (10c), a third active layer (MQW3), and a third-second semiconductor layer (20c).

[0190] The 3-1 semiconductor layer (10c) may be configured to provide holes. The 3-1 semiconductor layer (10c) may have a first polarity. For example, the 3-1 semiconductor layer (10c) may include at least one p-type semiconductor layer. For example, the 3-1 semiconductor layer (10c) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like. However, the material constituting the 3-1 semiconductor layer (10c) is not limited thereto, and various other materials may constituting the 3-1 semiconductor layer (10c). In one embodiment of the present disclosure, the 3-1 semiconductor layer (10c) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0191] The third active layer (MQW3) may be disposed on the third-first semiconductor layer (10c). The third active layer (MQW3) may be interposed between the third-first semiconductor layer (10c) and the third-second semiconductor layer (20c) to provide a region where electrons and holes recombine. As electrons and holes recombine in the third active layer (MQW3), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The third active layer (MQW3) may be formed in a single or multiple quantum well structure. When the third active layer (MQW3) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcement layer, and a well layer may be repeatedly stacked to form the third active layer (MQW3). However, the third active layer (MQW3) is not limited to the above-described structure.

[0192] In one embodiment, the third active layer (MQW3) may be configured to emit light of a third color (e.g., blue). In such a case, the third active layer (MQW3) may include a material suitable for emitting light of the third color.

[0193] The third-second semiconductor layer (20c) may be disposed on the third active layer (MQW3). The third-second semiconductor layer (20c) may include a third doped layer (21c) and a third auxiliary layer (22c) disposed on the third doped layer (21c).

[0194] The third doped layer (21c) may be disposed on the third active layer (MQW3). The third doped layer (21c) may be configured to provide electrons. The third doped layer (21c) may have a second polarity. For example, the third doped layer (21c) may include at least one n-type semiconductor layer. For example, the third doped layer (21c) may include any one of a semiconductor material selected from gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the third doped layer (21c) is not limited thereto, and various other materials may also constitute the third doped layer (21c). In one embodiment of the present disclosure, the third doped layer (21c) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant).

[0195] The third auxiliary layer (22c) may include a gallium nitride (GaN) semiconductor material that is substantially undoped with impurities or doped with impurities at a relatively low concentration. The third auxiliary layer (22c) may form an n-type semiconductor layer together with the third doped layer (21c).

[0196] The third-first bonding electrode (BDE1c) may be bonded and fixed on the third anode electrode (AE3). The third-first bonding electrode (BDE1c) may be connected to the third-first semiconductor layer (10c) and the third anode electrode (AE3). Through the third-first bonding electrode (BDE1c), the third-first semiconductor layer (10c) and the third anode electrode (AE3) may be electrically connected. In one embodiment, the third-first bonding electrode (BDE1b) may include a eutectic metal.

[0197] The third-second bonding electrode (BDE2c) may be bonded and fixed on the cathode electrode (CE). The third-second bonding electrode (BDE2c) may be connected to the third-second semiconductor layer (20c) and the cathode electrode (CE). Through the third-second bonding electrode (BDE2c), the third-second semiconductor layer (20c) and the cathode electrode (CE) may be electrically connected. In one embodiment, the third-second bonding electrode (BDE2c) may include a eutectic metal.

[0198] The third insulating film (30c) can cover at least a portion of the outer surface of the third light-emitting stack (EST3). The third insulating film (30c) is interposed between the third-second bonding electrode (BDE2c) and the third active layer (MQW3), and between the third-second bonding electrode (BDE2c) and the third-first semiconductor layer (10c), thereby preventing an electrical short circuit that may occur when the third-second bonding electrode (BDE2c) comes into contact with the third active layer (MQW3) and the third-first semiconductor layer (10c). The third insulating film (30c) can have a single-layer structure or a multi-layer structure including a transparent insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0199] A third light extraction structure (LES3) may be disposed on the pixel circuit layer (PCL) to cover the third light emitting element (LD3). The third light extraction structure (LES3) may be in direct contact with the entire side surface and the entire top surface of the third light emitting element (LD3).

[0200] In one embodiment, the third light extraction structure (LES3) may include a third overcoating layer (OCL3) and a third light extraction layer (NOC3) disposed on the third overcoating layer (OCL3).

[0201] The third overcoating layer (OCL3) can be in direct contact with at least a portion of the lower surface of the third light-emitting element (LD3). The third overcoating layer (OCL3) can be in direct contact with a portion of a side surface of the third light-emitting element (LD3) adjacent to the lower surface of the third light-emitting element (LD3). The third light-emitting element (LD3) can be partially buried in the third overcoating layer (OCL3). The third overcoating layer (OCL3) can fix the third light-emitting element (LD3) bonded to the third anode electrode (AE3) and the cathode electrode (CE) so as not to move. The third overcoating layer (OCL3) can include the same material as the first overcoating layer (OCL1). That is, the first overcoating layer (OCL1) and the third overcoating layer (OCL3) can include the same material.

[0202] The third light extraction layer (NOC3) can be in direct contact with the entire upper surface of the third light-emitting element (LD3). The third light extraction layer (NOC3) can be in direct contact with a side of the third light-emitting element (LD3) that is not in contact with the third overcoating layer (OCL3). The third light extraction layer (NOC3) can include the same material as the first light extraction layer (NOC1). That is, the first light extraction layer (NOC1) and the third light extraction layer (NOC3) can include the same material.

[0203] The cover layer (CVL) can cover the third light extraction structure (LES3) and the pixel circuit layer (PCL).

[0204] The third reflective layer (RFL3) may be arranged to surround a side surface of the third light extraction structure (LES3). A cover layer (CVL) may be interposed between the third reflective layer (RFL3) and the side surface of the third light extraction structure (LES3). The third reflective layer (RFL3) may be spaced apart from the first and second reflective layers (RFL1, RFL2). The third reflective layer (RFL3) may include the same material as the first reflective layer (RFL1). That is, the first reflective layer (RFL1) and the third reflective layer (RFL3) may include the same material.

[0205] A light functional layer (LFL) may be disposed on the cover layer (CVL) and the third reflective layer (RFL3). The light functional layer (LFL) may include a third passivation layer (PSV3) and a color filter layer (CFL).

[0206] The third passivation layer (PSV3) can cover the cover layer (CVL) and the third reflective layer (RFL3). The third passivation layer (PSV3) can provide a flat upper surface.

[0207] A color filter layer (CFL) may be disposed on the third passivation layer (PSV3). The color filter layer (CFL) may include a third color filter (CF3) and light-blocking patterns (LBP). The third color filter (CF3) may selectively transmit light in a desired wavelength range. For example, the third color filter (CF3) may selectively transmit blue light. The light-blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0208] Fig. 11 is a cross-sectional view taken along line J1-J1' of Fig. 7.

[0209] Referring to FIGS. 6 to 11, the color filter layer (CFL) may include first to third color filters (CF1, CF2, CF3) and light blocking patterns (LBP).

[0210] Each of the first to third color filters (CF1, CF2, CF3) can selectively transmit light of a desired wavelength range. In one embodiment, the first color filter (CF1) may be a red color filter, the second color filter (CF2) may be a green color filter, and the third color filter (CF3) may be a blue color filter.

[0211] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1, CF2, CF3). It can be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1, SP2, SP3) are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0212] In embodiments, the light-blocking patterns (LBP) may include at least one of various types of light-blocking materials. In one embodiment, each of the light-blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1, CF2, CF3) overlap. For example, each of the light-blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1, CF2, CF3). As another example, the light-blocking pattern between the first and second color filters (CF1, CF2) among the light-blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, and the light-blocking pattern between the second and third color filters (CF2, CF3) among the light-blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap. The light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of the neighboring pixel can be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1, CF2, CF3) can extend into the non-emitting area (NEMA) to form light blocking patterns (LBP).

[0213] In the present disclosure, the first light extraction structure (LES1) may overlap the first light emitting element (LD1), as illustrated in FIG. 7. In this case, the first reflective layer (RFL1) surrounding the side surface of the first light extraction structure (LES1) may be arranged to surround the first light emitting element (LD1), and the cover layer (CVL) may be interposed between the first reflective layer (RFL1) and the side surface of the first light extraction structure (LES1). Accordingly, red color light emitted from the first light emitting element (LD1) may be reflected by the first reflective layer (RFL1) and provided in a direction toward the first color filter (CF1). In addition, the red color light emitted from the first light emitting element (LD1) may be prevented from proceeding to the light emitting area (EMA) of other sub-pixels adjacent to the first sub-pixel (SP1), thereby preventing light mixing from occurring.

[0214] The second light extraction structure (LES2) may overlap the second light emitting element (LD2), as illustrated in FIG. 7. In this case, the second reflective layer (RFL2) surrounding the side surface of the second light extraction structure (LES2) may be arranged to surround the second light emitting element (LD2), and the cover layer (CVL) may be interposed between the second reflective layer (RFL2) and the side surface of the second light extraction structure (LES2). Accordingly, green color light emitted from the second light emitting element (LD2) may be reflected by the second reflective layer (RFL2) and provided in a direction toward the second color filter (CF2). In addition, the green color light emitted from the second light emitting element (LD2) may be prevented from proceeding to the light emitting area (EMA) of other sub-pixels adjacent to the second sub-pixel (SP2), thereby preventing light mixing from occurring.

[0215] The third light extraction structure (LES3) may overlap the third light emitting element (LD3), as illustrated in FIG. 7. In this case, the third reflective layer (RFL3) surrounding the side surface of the third light extraction structure (LES3) may be arranged to surround the third light emitting element (LD3), and the cover layer (CVL) may be interposed between the third reflective layer (RFL3) and the side surface of the third light extraction structure (LES3). Accordingly, blue color light emitted from the third light emitting element (LD3) may be reflected by the third reflective layer (RFL3) and provided in a direction toward the third color filter (CF3). In addition, it is possible to prevent blue color light emitted from the third light emitting element (LD3) from proceeding to the light emitting area (EMA) of other sub-pixels adjacent to the third sub-pixel (SP3), thereby preventing light mixing from occurring.

[0216] FIG. 12 is a drawing for explaining a method of manufacturing a display device including the pixels of FIG. 6 and FIG. 7.

[0217] Referring to FIG. 12, the method for manufacturing a display device may include steps 1 to 7 (ST1, ST2, ST3, ST4, ST5, ST6, ST7).

[0218] Figures 13 to 19 are cross-sectional views illustrating the manufacturing method of Figure 12. Hereinafter, descriptions of content overlapping with those described with reference to Figures 1 to 11 may be omitted.

[0219] Referring to FIG. 13, after forming first to third light-emitting elements (LD1, LD2, LD3) spaced apart from each other on a pixel circuit layer (PCL), an overcoating layer (OCL) can be formed to fix the first to third light-emitting elements (LD1, LD2, LD3) (ST1).

[0220] In this step, the first to third light-emitting elements (LD1, LD2, LD3) can be formed to be bonded to the first to third anode electrodes (AE1, AE2, AE3) and the cathode electrode (CE), as described with reference to FIGS. 8 to 10.

[0221] After the bonding of the first to third light-emitting elements (LD1, LD2, LD3) is completed, the first to third light-emitting elements (LD1, LD2, LD3) can be fixed to preset positions as an overcoat layer (OCL) is formed (or applied). In this case, the first to third light-emitting elements (LD1, LD2, LD3) can be partially buried in the overcoat layer (OCL).

[0222] Referring to FIG. 14, a light extraction layer (NOC) covering the first to third light-emitting elements (LD1, LD2, LD3) can be formed on the overcoating layer (OCL) (ST2). As the light extraction layer (NOC) is formed, the first to third light-emitting elements (LD1, LD2, LD3) can be buried by the light extraction layer (NOC).

[0223] Referring to FIG. 15, the overcoating layer (OCL) and the light extraction layer (NOC) may be partially etched to form first to third light extraction structures (LES1, LES2, LES3) that are spaced apart from each other (ST3). In this step, a trench (TR) may be defined between the first to third light extraction structures (LES1, LES2, LES3).

[0224] Referring to FIG. 16, a cover layer (CVL) covering the first to third light extraction structures (LES1, LES2, LES3) and the pixel circuit layer (PCL) can be formed (ST4). In this step, the cover layer (CVL) can be formed to have a shape corresponding to a cross-sectional profile of the first to third light extraction structures (LES1, LES2, LES3) defining the trench (TR).

[0225] Referring to Fig. 17, a reflective layer (RFL) covering a cover layer (CVL) can be formed (ST5). In this step, the reflective layer (RFL) can be formed to have a shape corresponding to the cross-sectional profile of the cover layer (CVL).

[0226] Referring to FIG. 18, the first to third reflective layers (RFL1, RFL2, RFL3) can be formed by partially etching the reflective layer (RFL) (ST6).

[0227] In this step, a portion of the reflective layer (RFL) overlapping with the upper surfaces of the first to third light extraction structures (LES1, LES2, LES3) can be removed by the etching. In addition, a portion of the reflective layer (RFL) overlapping with the lower surface of the trench (TR) can be removed by the etching. Accordingly, the first to third reflective layers (RFL1, RFL2, RFL3) can be provided as separate components.

[0228] In one embodiment, the etching may be performed using various known etching methods suitable for forming the first to third reflective layers (RFL1, RFL2, RFL3) described above without limitation. For example, the etching may be anisotropic dry etching or wet etching.

[0229] Referring to FIG. 19, a third passivation layer (PSV3) and a color filter layer (CFL) can be formed (ST7). Accordingly, a display device including first to third sub-pixels (SP1, SP2, SP3) can be provided.

[0230] FIG. 20 is a block diagram illustrating a display system according to one embodiment.

[0231] Referring to FIG. 20, the display system (1000) may include a processor (1100) and a display device (1200).

[0232] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor (1100) can be connected to other components of the display system (1000) via a bus system and control them.

[0233] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0234] The display system (1000) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. In addition, the display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0235] Figures 21 to 24 are perspective views illustrating application examples of the display system of Figure 20.

[0236] Referring to FIG. 21, the display system (1000) of FIG. 20 can be applied to a smart watch (2000) including a display portion (2100) and a strap portion (2200).

[0237] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0238] Referring to FIG. 22, the display system (1000) of FIG. 20 may be applied to an automotive display system (3000). Here, the automotive display system (3000) may include a computing system provided inside and / or outside a vehicle to provide image data.

[0239] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear seat display (3600) provided in a vehicle.

[0240] Referring to FIG. 23, the display system (1000) of FIG. 20 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0241] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0242] The frame (4100) may be equipped with a battery, a touch pad, a microphone, a camera, etc. In addition, the frame (4100) may be equipped with a projector that outputs light, a processor that controls light signals, etc.

[0243] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or the like.

[0244] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). At this time, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0245] Referring to FIG. 24, the display system (1000) of FIG. 20 can be applied to a head-mounted display device (5000).

[0246] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0247] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in the form of eyeglass frames, helmets, etc.

[0248] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0249] A display device, electronic device, electronic equipment or device, a manufacturing device for a display device, electronic device, electronic equipment or device, or other related device or component according to embodiments of the present disclosure may be implemented using suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the device may be formed on a single integrated circuit (IC) chip or separate IC chips. Furthermore, various components of the device may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCL), or formed on a single substrate. Furthermore, various components of the device may be processes or threads that execute computer program instructions on one or more computing devices running on one or more processors and interact with other system components to perform various functions described herein. The computer program instructions are stored in a memory that may be implemented on the computing device using a standard memory device such as, for example, a random access memory (RAM). The computer program instructions may also be stored on, for example, a CD-ROM, a flash drive, or other similar non-transitory computer-readable medium. Additionally, those skilled in the art should recognize that the functions of various computing devices may be combined or integrated into a single computing device, or that the functions of a particular computing device may be distributed across one or more other computing devices without departing from the scope of the embodiments of the present disclosure.

[0250] Considering the entire disclosure, it will be understood by those skilled in the art that suitable features of each of the various embodiments of the present disclosure may be partially or wholly combined or combined with one another, and may be technically interconnected and operated in various suitable ways, and that each embodiment may be implemented independently of one another or may be implemented in connection with one another in any suitable way, unless otherwise stated or implied.

[0251] Although the present disclosure has been described with reference to the above embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. First and second light-emitting elements arranged on a pixel circuit layer and spaced apart from each other; A first light extraction structure disposed on the pixel circuit layer so as to overlap the first light emitting element in a plane; A second light extraction structure disposed on the pixel circuit layer so as to overlap the second light emitting element in a plane, and spaced apart from the first light extraction structure; A cover layer covering the first and second light extraction structures and the pixel circuit layer; A first reflective layer arranged to surround a side surface of the first light extraction structure, the cover layer being interposed between the first reflective layer and the side surface of the first light extraction structure; and A display device comprising a second reflective layer arranged to surround a side surface of the second light extraction structure, wherein the cover layer is interposed between the second reflective layer and the side surface of the second light extraction structure.

2. In paragraph 1, A display device wherein the first reflective layer and the second reflective layer are spaced apart from each other.

3. In paragraph 1, On a plane, the edge of the first light extraction structure is arranged to completely surround the edge of the first light-emitting element, A display device, wherein, on a plane, the edge of the second light extraction structure is arranged to completely surround the edge of the second light-emitting element.

4. In paragraph 1, The first light-emitting element generates light of a first color, A display device wherein the second light-emitting element generates light of a second color different from the first color.

5. In paragraph 1, The first light extraction structure is in direct contact with the entire side surface of the first light-emitting element and in direct contact with the entire upper surface of the first light-emitting element, A display device wherein the second light extraction structure is in direct contact with the entire side surface of the second light-emitting element and in direct contact with the entire upper surface of the second light-emitting element.

6. In paragraph 1, The first light-emitting element includes a first semiconductor layer, a first semiconductor layer disposed on the first semiconductor layer, and a first active layer interposed between the first semiconductor layer and the first semiconductor layer. A display device, wherein the second light-emitting element includes a 2-1 semiconductor layer, a 2-2 semiconductor layer disposed on the 2-1 semiconductor layer, and a second active layer interposed between the 2-1 semiconductor layer and the 2-2 semiconductor layer.

7. In paragraph 1, a first anode electrode disposed between the first light-emitting element and the pixel circuit layer; and A display device comprising a second anode electrode disposed between the second light-emitting element and the pixel circuit layer.

8. In paragraph 7, The above first light extraction structure overlaps the first anode electrode in a plane, A display device in which the second light extraction structure overlaps the second anode electrode in a plane.

9. In paragraph 7, A display device further comprising a cathode electrode disposed between the first and second light-emitting elements and the pixel circuit layer.

10. In paragraph 9, The above first light extraction structure overlaps a portion of the cathode electrode in a plane, A display device wherein the second light extraction structure overlaps planarly with another portion of the cathode electrode.

11. In paragraph 1, The first light extraction structure includes a first overcoating layer and a first light extraction layer disposed on the first overcoating layer, A display device, wherein the second light extraction structure includes a second overcoating layer and a second light extraction layer disposed on the second overcoating layer.

12. In paragraph 11, The first overcoating layer is in direct contact with at least a portion of the lower surface of the first light-emitting element, A display device wherein the second overcoating layer is in direct contact with at least a portion of the lower surface of the second light-emitting element.

13. In paragraph 1, A third light-emitting element disposed on the pixel circuit layer and spaced apart from the first and second light-emitting elements; A third light extraction structure is disposed on the pixel circuit layer so as to overlap the third light emitting element in a plane, and is spaced apart from the first and second light extraction structures; and A display device further comprising a third reflective layer arranged to surround a side surface of the third light extraction structure, wherein the cover layer is interposed between the third reflective layer and the side surface of the third light extraction structure.

14. In paragraph 13, A display device in which the color of light generated from the third light-emitting element is different from the color of light generated from the first light-emitting element and the color of light generated from the second light-emitting element.

15. In paragraph 1, A passivation layer arranged to cover the cover layer, the first reflective layer, and the second reflective layer; and A display device further comprising a color filter layer disposed on the passivation layer.

16. In paragraph 15, The upper surface of the above passivation layer is flat, display device.

17. A step of forming first and second light extraction structures that overlap with the first and second light emitting elements on a pixel circuit layer and are spaced apart from each other; A step of forming a cover layer covering the first and second light extraction structures and the pixel circuit layer; and A method for manufacturing a display device, comprising: forming first and second reflective layers arranged to surround side surfaces of the first and second light extraction structures, wherein the cover layer is interposed between the first reflective layer and the side surface of the first light extraction structure and between the second reflective layer and the side surface of the second light extraction structure.

18. In the 17th paragraph, the step of forming the first and second reflective layers is A step of forming a reflective layer covering the above cover layer; and A method for manufacturing a display device, comprising the step of forming the first and second reflective layers by partially etching the reflective layer.

19. In the 17th paragraph, the step of forming the first and second light extraction structures is, A step of forming the first and second light-emitting elements spaced apart from each other on the pixel circuit layer; A step of forming an overcoating layer on the pixel circuit layer; A step of forming a light extraction layer covering the first and second light-emitting elements on the overcoating layer; and A method for manufacturing a display device, comprising the step of forming the first and second light extraction structures by partially etching the overcoating layer and the light extraction layer.

20. In the step of forming the overcoating layer in paragraph 19, A method for manufacturing a display device, wherein the first and second light-emitting elements are partially buried in the overcoating layer.

21. A processor providing input image data; and A display device that displays an image based on the above input image data is included, The above display device: First and second light-emitting elements are arranged on the pixel circuit layer and are spaced apart from each other; A first light extraction structure disposed on the pixel circuit layer so as to overlap the first light emitting element in a plane; A second light extraction structure disposed on the pixel circuit layer so as to overlap the second light emitting element in a plane, and spaced apart from the first light extraction structure; A cover layer covering the first and second light extraction structures and the pixel circuit layer; A first reflective layer arranged to surround a side surface of the first light extraction structure, the cover layer being interposed between the first reflective layer and the side surface of the first light extraction structure; and An electronic device comprising a second reflective layer arranged to surround a side surface of the second light extraction structure, wherein the cover layer is interposed between the second reflective layer and the side surface of the second light extraction structure.

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