Pixel, display device including same, and electronic device including same

Abstract

This pixel includes a light emitting element, a first switching element, a first capacitor, a second capacitor, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, and a seventh switching element. The first switching element includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node. The first capacitor includes a first electrode connected to the first node and a second electrode connected to a fourth node. The second capacitor includes a first electrode connected to the fourth node and a second electrode connected to the third node. The second switching element applies a data voltage to the first capacitor. The third switching element applies a reference voltage to the first node. The fourth switching element includes a control electrode to which an initialization gate signal is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to an anode electrode of the light emitting element. The fifth switching element includes a control electrode to which a first emission signal is applied, a first electrode to which a first power voltage is applied, and a second electrode connected to the second node. The sixth switching element includes a control electrode to which a second emission signal is applied, a first electrode connected to the third node, and a second electrode connected to the anode electrode. The seventh switching element applies a reference voltage to the fourth node.

Description

Pixels, display devices including the same, and electronic devices including the same

[0001] The present invention relates to pixels, display devices including the same, and electronic devices including the same, and more particularly, to pixels capable of improving display quality, display devices including the same, and electronic devices including the same.

[0002] In general, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver that provides a gate signal to the plurality of gate lines, a data driver that provides a data voltage to the data lines, an emission driver that provides an emission signal to the emission lines, and a drive control unit that controls the gate driver, the data driver, and the emission driver.

[0003] In conventional pixels, when data is written, the data voltage is written according to the ratio of the capacitance of the storage capacitor and the capacitance of the hold capacitor, so that the gate-source voltage of the driving transistor becomes smaller than the swing width of the data voltage, and accordingly, the sensitivity of the driving transistor increases, causing problems such as crosstalk occurring, image quality deterioration occurring due to touch noise, or cycle mura occurring.

[0004] An object of the present invention is to provide a pixel including a first capacitor and a second capacitor connected in series between a control electrode and a second electrode of a first switching element, and a seventh switching element applying a reference voltage to a node between the first capacitor and the second capacitor, and a data voltage being directly applied to the control electrode of the first switching element or the node between the first capacitor and the second capacitor, thereby improving display quality.

[0005] Another object of the present invention is to provide a display device including the above pixel.

[0006] Another object of the present invention is to provide an electronic device including the pixel.

[0007] According to one embodiment of the present invention for achieving the above object, a pixel includes a light-emitting element, a first switching element, a first capacitor, a second capacitor, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, and a seventh switching element. The first switching element includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node. The first capacitor includes a first electrode connected to the first node and a second electrode connected to a fourth node. The second capacitor includes a first electrode connected to the fourth node and a second electrode connected to the third node. The second switching element applies a data voltage to the first capacitor. The third switching element applies a reference voltage to the first node. The fourth switching element includes a control electrode to which an initialization gate signal is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to an anode electrode of the light-emitting element. The fifth switching element includes a control electrode to which a first emission signal is applied, a first electrode to which a first power voltage is applied, and a second electrode connected to the second node. The sixth switching element includes a control electrode to which a second emission signal is applied, a first electrode connected to the third node, and a second electrode connected to the anode electrode. The seventh switching element applies the reference voltage to the fourth node.

[0008] In one embodiment of the present invention, the second switching element may include a control electrode to which a write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the first node.

[0009] In one embodiment of the present invention, the seventh switching element may include a control electrode to which a first reference gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the fourth node.

[0010] In one embodiment of the present invention, the third switching element may include a control electrode to which a second reference gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the first node.

[0011] In one embodiment of the present invention, the first reference gate signal may be a reference gate signal of the nth stage. The second reference gate signal may be a reference gate signal of any one of the stages preceding the nth stage. n may be a natural number greater than or equal to 2.

[0012] In one embodiment of the present invention, in the initialization period, the first emission signal may have a deactivation level, the second emission signal may have an activation level, the initialization gate signal may have an activation level, and the write gate signal may have a deactivation level.

[0013] In one embodiment of the present invention, in a compensation period after the initialization period, the first emission signal may have an activation level, the second emission signal may have a deactivation level, the second reference gate signal may have an activation level, the first reference gate signal may have an activation level, the initialization gate signal may have a deactivation level, and the write gate signal may have the deactivation level.

[0014] In one embodiment of the present invention, in a write period after the compensation period, the first emission signal may have the deactivation level, the second emission signal may have the deactivation level, the second reference gate signal may have the deactivation level, the first reference gate signal may have the activation level, the initialization gate signal may have the deactivation level, and the write gate signal may have an activation pulse.

[0015] In one embodiment of the present invention, in the emission period after the writing period, the first emission signal may have the activation level, the second emission signal may have the activation level, the initialization gate signal may have the deactivation level, and the writing gate signal may have the deactivation level.

[0016] In one embodiment of the present invention, in a second initialization period between the writing period and the emitting period, the first emission signal may have the deactivation level, the second emission signal may have the activation level, the initialization gate signal may have the activation level, and the writing gate signal may have the deactivation level.

[0017] In one embodiment of the present invention, the second switching element and the seventh switching element can be turned on in the write section.

[0018] In one embodiment of the present invention, the pixel may further include an eighth switching element including a control electrode to which the initialization gate signal is applied, a first electrode to which a second initialization voltage is applied, and a second electrode connected to the third node.

[0019] In one embodiment of the present invention, in the initialization period, the first emission signal may have a deactivation level, the second emission signal may have a deactivation level, the initialization gate signal may have an activation level, and the write gate signal may have a deactivation level.

[0020] In one embodiment of the present invention, in a compensation period after the initialization period, the first emission signal may have an activation level, the second emission signal may have the deactivation level, the second reference gate signal may have an activation level, the first reference gate signal may have an activation level, the initialization gate signal may have a deactivation level, and the write gate signal may have the deactivation level. In a write period after the compensation period, the first emission signal may have the deactivation level, the second emission signal may have the deactivation level, the second reference gate signal may have the deactivation level, the first reference gate signal may have the activation level, the initialization gate signal may have the deactivation level, and the write gate signal may have an activation pulse. In the emission period after the above-mentioned writing period, the first emission signal may have the above-mentioned activation level, the second emission signal may have the above-mentioned activation level, the initialization gate signal may have the above-mentioned deactivation level, and the writing gate signal may have the above-mentioned deactivation level.

[0021] In one embodiment of the present invention, the second switching element may include a control electrode to which a write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the fourth node.

[0022] In one embodiment of the present invention, the seventh switching element may include a control electrode to which a second reference gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the fourth node.

[0023] In one embodiment of the present invention, the third switching element may include a control electrode to which a first reference gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the first node.

[0024] In one embodiment of the present invention, the first reference gate signal may be a reference gate signal of the nth stage. The second reference gate signal may be a reference gate signal of any one of the stages preceding the nth stage. n may be a natural number greater than or equal to 2.

[0025] In one embodiment of the present invention, the second switching element and the third switching element can be turned on in the write section.

[0026] In one embodiment of the present invention, an eighth switching element may further be included, including a control electrode to which the initialization gate signal is applied, a first electrode to which a second initialization voltage is applied, and a second electrode connected to the third node.

[0027] According to one embodiment of the present invention, a display device includes a display panel, a gate driver, a data driver, and an emission driver. The display panel includes a pixel. The gate driver outputs an initialization gate signal to the pixel. The data driver outputs a data voltage to the pixel. The emission driver includes an emission driver that outputs a first emission signal and a second emission signal to the pixel. The pixel includes a light-emitting element, a first switching element, a first capacitor, a second capacitor, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, and a seventh switching element. The first switching element includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node. The first capacitor includes a first electrode connected to the first node and a second electrode connected to a fourth node. The second capacitor includes a first electrode connected to the fourth node and a second electrode connected to the third node. The second switching element applies the data voltage to the first capacitor. The third switching element applies a reference voltage to the first node. The fourth switching element includes a control electrode to which the initialization gate signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the anode electrode of the light-emitting element. The fifth switching element includes a control electrode to which the first emission signal is applied, a first electrode to which the first power voltage is applied, and a second electrode connected to the second node. The sixth switching element includes a control electrode to which the second emission signal is applied, a first electrode connected to the third node, and a second electrode connected to the anode electrode. The seventh switching element applies the reference voltage to the fourth node.

[0028] According to one embodiment of the present invention, an electronic device includes a display panel, a gate driver, a data driver, an emission driver, a driving control unit, and a processor. The display panel includes a pixel. The gate driver outputs an initialization gate signal to the pixel. The data driver outputs a data voltage to the pixel. The emission driver includes an emission driver that outputs a first emission signal and a second emission signal to the pixel. The driving control unit controls the gate driver, the data driver, and the emission driver. The processor outputs input image data and an input control signal to the driving control unit. The pixel includes a light-emitting element, a first switching element, a first capacitor, a second capacitor, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, and a seventh switching element. The first switching element includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node. The first capacitor includes a first electrode connected to the first node and a second electrode connected to a fourth node. The second capacitor includes a first electrode connected to the fourth node and a second electrode connected to the third node. The second switching element applies the data voltage to the first capacitor. The third switching element applies a reference voltage to the first node. The fourth switching element includes a control electrode to which the initialization gate signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the anode electrode of the light-emitting element. The fifth switching element includes a control electrode to which the first emission signal is applied, a first electrode to which a first power voltage is applied, and a second electrode connected to the second node.The sixth switching element includes a control electrode to which the second emission signal is applied, a first electrode connected to the third node, and a second electrode connected to the anode electrode. The seventh switching element applies the reference voltage to the fourth node.

[0029] According to such a pixel, a display device including the pixel, and an electronic device including the pixel, the pixel includes the first capacitor and the second capacitor connected in series between the control electrode of the first switching element and the second electrode, and includes the seventh switching element that applies the reference voltage to a node between the first capacitor and the second capacitor, and the data voltage can be directly applied to the control electrode of the first switching element or the node between the first capacitor and the second capacitor.

[0030] Since the threshold voltage of the first switching element is written into the second capacitor and the data voltage based on the reference voltage is directly applied to the first capacitor, the swing range of the data voltage and the range of the gate-source voltage of the first switching element can be similar.

[0031] Since the swing range of the data voltage and the range of the gate-source voltage of the first switching element are similar, the slope of the current-voltage curve of the first switching element can be set low, thereby reducing the sensitivity of the first switching element.

[0032] By reducing the sensitivity of the first switching element, the display quality of the display panel can be improved by preventing crosstalk, deterioration of image quality due to touch noise, and cycle mura.

[0033] In addition, since only the second capacitor is initialized in the initialization section of the pixel, the amount of initializing voltage can be reduced.

[0034] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention.

[0035] Fig. 2 is a circuit diagram showing pixels of the display panel of Fig. 1.

[0036] Figure 3 is a timing diagram showing an example of input signals applied to the pixels of Figure 2.

[0037] Figure 4 is a timing diagram showing an example of input signals applied to the pixels of Figure 2.

[0038] FIG. 5 is a circuit diagram showing pixels of a display panel of a display device according to one embodiment of the present invention.

[0039] Fig. 6 is a timing diagram showing an example of input signals applied to the pixels of Fig. 5.

[0040] FIG. 7 is a circuit diagram showing pixels of a display panel of a display device according to one embodiment of the present invention.

[0041] Fig. 8 is a timing diagram showing an example of input signals applied to the pixels of Fig. 7.

[0042] FIG. 9 is a circuit diagram showing pixels of a display panel of a display device according to one embodiment of the present invention.

[0043] FIG. 10 is a circuit diagram showing pixels of a display panel of a display device according to one embodiment of the present invention.

[0044] FIG. 11 is a block diagram illustrating an electronic device according to one embodiment of the present invention.

[0045] Fig. 12 is a drawing showing an example in which the electronic device of Fig. 11 is implemented as a smartphone.

[0046] Fig. 13 is a drawing showing an example in which the electronic device of Fig. 11 is implemented as a monitor.

[0047] Hereinafter, the present invention will be described in more detail with reference to the attached drawings.

[0048] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention.

[0049] Referring to Fig. 1, the display device includes a display panel (100) and a display panel driver. The display panel driver includes a drive control unit (200), a gate driver (300), a gamma reference voltage generator (400), a data driver (500), and an emission driver (600).

[0050] For example, the drive control unit (200) and the data drive unit (500) may be formed integrally. For example, the drive control unit (200), the gamma reference voltage generation unit (400), and the data drive unit (500) may be formed integrally. A drive module in which at least the drive control unit (200) and the data drive unit (500) are formed integrally may be named a timing controller embedded data driver (TED).

[0051] The above display panel (100) includes a display portion (AA) that displays an image and a peripheral portion (PA) arranged adjacent to the display portion (AA).

[0052] The display panel (100) may include a plurality of gate lines (GWL, GIL, GRL), a plurality of data lines (DL), a plurality of emission lines (EL1, EL2), and a plurality of pixels electrically connected to each of the gate lines (GWL, GIL, GRL), the data lines (DL), and the emission lines (EL1, EL2). The gate lines (GWL, GIL, GRL) may extend in a first direction (D1), the data lines (DL) may extend in a second direction (D2) intersecting the first direction (D1), and the emission lines (EL1, EL2) may extend in the first direction (D1).

[0053] The driving control unit (200) may receive input image data (IMG) and an input control signal (CONT) from an external device. For example, the driving control unit (200) may receive the input image data (IMG) and the input control signal (CONT) from a host or an application processor. For example, the input image data (IMG) may include red image data, green image data, and blue image data. The input image data (IMG) may include white image data. The input image data (IMG) may include magenta image data, yellow image data, and cyan image data. The input control signal (CONT) may include a master clock signal and a data enable signal. The input control signal (CONT) may further include a vertical synchronization signal and a horizontal synchronization signal.

[0054] The above driving control unit (200) can generate a first control signal (CONT1), a second control signal (CONT2), a third control signal (CONT3), a fourth control signal (CONT4), and a data signal (DATA) based on the input image data (IMG) and the input control signal (CONT).

[0055] The above driving control unit (200) can generate the first control signal (CONT1) for controlling the operation of the gate driving unit (300) based on the input control signal (CONT) and output the first control signal (CONT1) to the gate driving unit (300). The first control signal (CONT1) can include a vertical start signal and a gate clock signal.

[0056] The above drive control unit (200) can generate the second control signal (CONT2) for controlling the operation of the data drive unit (500) based on the input control signal (CONT) and output it to the data drive unit (500). The second control signal (CONT2) can include a horizontal start signal and a load signal.

[0057] The above driving control unit (200) can generate a data signal (DATA) based on the input image data (IMG). The driving control unit (200) can output the data signal (DATA) to the data driving unit (500).

[0058] The above driving control unit (200) can generate the third control signal (CONT3) for controlling the operation of the gamma reference voltage generation unit (400) based on the input control signal (CONT) and output it to the gamma reference voltage generation unit (400).

[0059] The above drive control unit (200) can generate the fourth control signal (CONT4) for controlling the operation of the emission drive unit (600) based on the input control signal (CONT) and output it to the emission drive unit (600).

[0060] The gate driver (300) can generate gate signals for driving the gate lines (GWL, GIL, GRL) in response to the first control signal (CONT1) received from the drive control unit (200). The gate driver (300) can output the gate signals to the gate lines (GWL, GIL, GRL). For example, the gate driver (300) can be integrated on the peripheral portion (PA) of the display panel (100). For example, the gate driver (300) can be mounted on the peripheral portion (PA) of the display panel (100).

[0061] The gamma reference voltage generation unit (400) can generate a gamma reference voltage (VGREF) in response to the third control signal (CONT3) received from the driving control unit (200). The gamma reference voltage generation unit (400) can provide the gamma reference voltage (VGREF) to the data driving unit (500). The gamma reference voltage (VGREF) can have a value corresponding to each data signal (DATA).

[0062] For example, the gamma reference voltage generation unit (400) may be placed within the driving control unit (200) or within the data driving unit (500).

[0063] The data driving unit (500) may receive the second control signal (CONT2) and the data signal (DATA) from the driving control unit (200), and may receive the gamma reference voltage (VGREF) from the gamma reference voltage generation unit (400). The data driving unit (500) may convert the data signal (DATA) into an analog data voltage using the gamma reference voltage (VGREF). The data driving unit (500) may output the data voltage to the data line (DL).

[0064] The emission driving unit (600) can generate emission signals for driving the emission lines (EL1, EL2) in response to the fourth control signal (CONT4) received from the driving control unit (200). The emission driving unit (600) can output the emission signals to the emission lines (EL1, EL2). For example, the emission driving unit (600) can be integrated on the peripheral portion (PA) of the display panel (100). For example, the emission driving unit (600) can be mounted on the peripheral portion (PA) of the display panel (100).

[0065] In FIG. 1, for convenience of explanation, the gate driver (300) is illustrated as being disposed on the first side of the display panel (100) and the emission driver (600) is illustrated as being disposed on the second side of the display panel (100). However, the present invention is not limited thereto. For example, both the gate driver (300) and the emission driver (600) may be disposed on the first side of the display panel (100). For example, both the gate driver (300) and the emission driver (600) may be disposed on both sides of the display panel (100). For example, the gate driver (300) and the emission driver (600) may be formed integrally.

[0066] Fig. 2 is a circuit diagram showing pixels of the display panel (100) of Fig. 1.

[0067] Referring to FIGS. 1 and 2, the display panel (100) includes a plurality of pixels, each of which includes a light-emitting element (EE).

[0068] The above pixels receive a write gate signal (GW), an initialization gate signal (GI), a first reference gate signal (GR(n)), a second reference gate signal (GR(n-1)), the data voltage (VDATA), a first emission signal (EM1), and a second emission signal (EM2), and display the image by causing the light-emitting element (EE) to emit light according to the level of the data voltage (VDATA).

[0069] In this embodiment, the switching elements of the pixel may be oxide semiconductor thin film transistors. For example, the switching elements of the pixel may be N-type transistors.

[0070] For example, the pixel may include first, second, third, fourth, fifth, sixth and seventh switching elements (T1, T2, T3, T4, T5, T6 and T7), a first capacitor (CST1), a second capacitor (CST2) and the light emitting element (EE).

[0071] The first switching element (T1) includes a control electrode connected to a first node (N1), a first electrode connected to a second node (N2), and a second electrode connected to a third node (N3). The first switching element (T1) may be referred to as a driving switching element.

[0072] The first capacitor (CST1) includes a first electrode connected to the first node (N1) and a second electrode connected to a fourth node (N4).

[0073] The second capacitor (CST2) includes a first electrode connected to the fourth node (N4) and a second electrode connected to the third node (N3).

[0074] The second switching element (T2) applies the data voltage (VDATA) to the first capacitor (CST1).

[0075] The third switching element (T3) applies a reference voltage (VREF) to the first node (N1).

[0076] The fourth switching element (T4) includes a control electrode to which the initialization gate signal (GI) is applied, a first electrode to which the initialization voltage (VAINT) is applied, and a second electrode connected to the anode electrode of the light-emitting element (EE).

[0077] The fifth switching element (T5) includes a control electrode to which the first emission signal (EM1) is applied, a first electrode to which the first power supply voltage (ELVDD) is applied, and a second electrode connected to the second node (N2).

[0078] The sixth switching element (T6) includes a control electrode to which the second emission signal (EM2) is applied, a first electrode connected to the third node (N3), and a second electrode connected to the anode electrode.

[0079] The seventh switching element (T7) applies the reference voltage (VREF) to the fourth node (N4).

[0080] The light emitting element (EE) may include the anode electrode and the cathode electrode to which a second power supply voltage (ELVSS) is applied. For example, the first power supply voltage (ELVDD) may be greater than the second power supply voltage (ELVSS).

[0081] For example, the initialization voltage (VAINT) may be smaller than the first power supply voltage (ELVDD) and larger than the second power supply voltage (ELVSS).

[0082] In this embodiment, the second switching element (T2) may include a control electrode to which the write gate signal (GW) is applied, a first electrode to which the data voltage (VDATA) is applied, and a second electrode connected to the first node (N1).

[0083] In the present embodiment, the seventh switching element (T7) may include a control electrode to which the first reference gate signal (e.g., GR(n)) is applied, a first electrode to which the reference voltage (VREF) is applied, and a second electrode connected to the fourth node (N4).

[0084] In the present embodiment, the third switching element (T3) may include a control electrode to which the second reference gate signal (e.g., GR(n-1)) is applied, a first electrode to which the reference voltage (VREF) is applied, and a second electrode connected to the first node (N1).

[0085] In this embodiment, the white data voltage may be greater than the black data voltage. In this embodiment, the data voltage representing a high grayscale may be greater than the data voltage representing a low grayscale. For example, the reference voltage (VREF) may be lower than the white data voltage and higher than the black data voltage. For example, the reference voltage (VREF) may be lower than the first power supply voltage (ELVDD).

[0086] In the present embodiment, the first reference gate signal (GR(n)) may be a reference gate signal of the nth stage. The second reference gate signal (GR(n-1)) may be a reference gate signal of any one of the stages preceding the nth stage. n may be a natural number greater than or equal to 2. For example, the second reference gate signal (GR(n-1)) may be a reference gate signal of the stage immediately preceding the nth stage. The nth stage may mean a stage of a gate driving circuit corresponding to the nth pixel row of the display panel (100).

[0087] The write gate signal (GW), the initialization gate signal (GI), the first emission signal (EM1) and the second emission signal (EM2) not indicated by (n) in FIG. 2 may each be signals of the nth stage. That is, the write gate signal (GW of FIG. 2), the initialization gate signal (GI of FIG. 2), the first emission signal (EM1 of FIG. 2) and the second emission signal (EM2 of FIG. 2) may have substantially the same meaning as the write gate signal (GW(n) of FIG. 3), the initialization gate signal (GI(n) of FIG. 3), the first emission signal (EM1(n) of FIG. 3) and the second emission signal (EM2(n) of FIG. 3).

[0088] When the first reference gate signal (GR(n)) is a reference gate signal of the nth stage and the second reference gate signal (GR(n-1)) is a reference gate signal of any one of the previous stages of the nth stage, the first reference gate signal (GR(n)) and the second reference gate signal (GR(n-1)) are generated from the same gate driving circuit, so that the manufacturing cost of the display device can be reduced and the dead space of the display device can be reduced.

[0089] Figure 3 is a timing diagram showing an example of input signals applied to the pixels of Figure 2.

[0090] Referring to FIGS. 1 to 3, the driving timing of the pixel may include an initialization section, a compensation section, a writing section, and a light emission section.

[0091] In the initialization section (P2, P3 of FIG. 3), the first emission signal (EM1) may have a deactivation level, the second emission signal (EM2) may have an activation level, the initialization gate signal (GI) may have an activation level, and the write gate signal (GW) may have a deactivation level.

[0092] When the first emission signal (EM1), the second emission signal (EM2), the second reference gate signal (GR(n-1)), the first reference gate signal (GR(n)), the initialization gate signal (GI) and the write gate signal (GW) are applied to a P-type transistor, the activation levels of the first emission signal (EM1), the second emission signal (EM2), the second reference gate signal (GR(n-1)), the first reference gate signal (GR(n)), the initialization gate signal (GI) and the write gate signal (GW) may be a low level, and the deactivation levels of the first emission signal (EM1), the second emission signal (EM2), the second reference gate signal (GR(n-1)), the first reference gate signal (GR(n)), the initialization gate signal (GI) and the write gate signal (GW) may be a high level.

[0093] Conversely, when the first emission signal (EM1), the second emission signal (EM2), the second reference gate signal (GR(n-1)), the first reference gate signal (GR(n)), the initialization gate signal (GI) and the write gate signal (GW) are applied to an N-type transistor, the activation levels of the first emission signal (EM1), the second emission signal (EM2), the second reference gate signal (GR(n-1)), the first reference gate signal (GR(n)), the initialization gate signal (GI) and the write gate signal (GW) may be a high level, and the deactivation levels of the first emission signal (EM1), the second emission signal (EM2), the second reference gate signal (GR(n-1)), the first reference gate signal (GR(n)), the initialization gate signal (GI) and the write gate signal (GW) may be a low level.

[0094] In FIG. 2, the first to seventh switching elements (T1 to T7) may be N-type transistors, and accordingly, the activation levels of the first emission signal (EM1), the second emission signal (EM2), the second reference gate signal (GR(n-1)), the first reference gate signal (GR(n)), the initialization gate signal (GI) and the write gate signal (GW) may be high levels, and the deactivation levels of the first emission signal (EM1), the second emission signal (EM2), the second reference gate signal (GR(n-1)), the first reference gate signal (GR(n)), the initialization gate signal (GI) and the write gate signal (GW) may be low levels.

[0095] In the initialization section (P2, P3 of FIG. 3), the fourth switching element (T4) is turned on in response to the initialization gate signal (GI), so that the initialization voltage (VAINT) can be applied to the anode electrode of the light-emitting element (EE).

[0096] Additionally, in response to the second emission signal (EM2) in the initialization section (P2, P3 of FIG. 3), the sixth switching element (T6) is turned on, so that the initialization voltage (VAINT) can also be applied to the third node (N3).

[0097] In the compensation section (P5 of FIG. 3) after the initialization section (P2, P3 of FIG. 3), the first emission signal (EM1) may have an activation level, the second emission signal (EM2) may have a deactivation level, the second reference gate signal (GR(n-1)) may have an activation level, the first reference gate signal (GR(n)) may have an activation level, the initialization gate signal (GI) may have a deactivation level, and the write gate signal (GW) may have the deactivation level.

[0098] In the above compensation section (P5 of FIG. 3), the third switching element (T3) is turned on in response to the second reference gate signal (GR(n-1)), so that the reference voltage (VREF) can be applied to the first node (N1).

[0099] In the compensation section (P5 of FIG. 3), the seventh switching element (T7) is turned on in response to the first reference gate signal (GR(n)), so that the reference voltage (VREF) can be applied to the fourth node (N4).

[0100] In the compensation section (P5 of FIG. 3), the fifth switching element (T5) is turned on in response to the first emission signal (EM1(n)), so that the voltage level of the third node (N3) can be the sum of the absolute value of the reference voltage (VREF) and the threshold voltage of the first switching element (T1).

[0101] That is, the threshold voltage of the first switching element (T1) can be written to the second capacitor (CST2) in the compensation section (P5 in FIG. 3).

[0102] In the write section (P7 of FIG. 3) after the compensation section (P5 of FIG. 3), the first emission signal (EM1) may have the deactivation level, the second emission signal (EM2) may have the deactivation level, the second reference gate signal (GR(n-1)) may have the deactivation level, the first reference gate signal (GR(n)) may have the activation level, the initialization gate signal (GI) may have the deactivation level, and the write gate signal (GW) may have an activation pulse. (For example, the write gate signal (GW) may be changed to the activation level during the write section (P7) and then changed back to the deactivation level.)

[0103] In the above-mentioned write section (P7 of FIG. 3), the seventh switching element (T7) is turned on in response to the first reference gate signal (GR(n)), so that the reference voltage (VREF) can be applied to the fourth node (N4).

[0104] In response to the write gate signal (GW) in the above write section (P7 of FIG. 3), the second switching element (T2) is turned on, so that the data voltage (VDATA) can be applied to the first node (N1).

[0105] In the writing section (P7 of FIG. 3) of the present embodiment, the second switching element (T2) and the seventh switching element (T7) are turned on, so that the data voltage (VDATA) can be written to the first capacitor (CST1) based on the reference voltage (VREF).

[0106] In the emission section (P12 of FIG. 3) following the above-described writing section (P7 of FIG. 3), the first emission signal (EM1) may have the above-described activation level, the second emission signal (EM2) may have the above-described activation level, the initialization gate signal (GI) may have the above-described deactivation level, and the writing gate signal (GW) may have the above-described deactivation level.

[0107] In the above light-emitting section (P12 of FIG. 3), the light-emitting element (EE) can emit light through a current path formed along the fifth switching element (T5) turned on in response to the first emission signal (EM1), the first switching element (T1) turned on in response to the data voltage (VDATA), and the sixth switching element (T6) turned on in response to the second emission signal (EM2).

[0108] The driving timing of the pixel of the present embodiment may further include a second initialization section (P10 of FIG. 3).

[0109] In the present embodiment, in the second initialization section (P10 of FIG. 3) between the writing section (P7 of FIG. 3) and the emitting section (P12 of FIG. 3), the first emission signal (EM1) may have the deactivation level, the second emission signal (EM2) may have the activation level, the initialization gate signal (GI) may have the activation level, and the writing gate signal (GW) may have the deactivation level.

[0110] In the second initialization section (P10 of FIG. 3), the fourth switching element (T4) is turned on in response to the initialization gate signal (GI), so that the initialization voltage (VAINT) can be applied to the anode electrode of the light-emitting element (EE).

[0111] Additionally, in response to the second emission signal (EM2) in the second initialization section (P10 of FIG. 3), the sixth switching element (T6) is turned on, so that the initialization voltage (VAINT) can also be applied to the third node (N3).

[0112] Figure 4 is a timing diagram showing an example of input signals applied to the pixels of Figure 2.

[0113] The driving timing of the pixel in FIG. 4 is substantially the same as the driving timing of the pixel in FIG. 3, except that it does not include a second initialization period. That is, the driving timing of the pixel in FIG. 4 is substantially the same as the driving timing of the pixel in FIG. 3, except that the waveform of the initialization gate signal (GI) does not have a second activation period. Therefore, the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0114] Referring to FIGS. 1, 2 and 4, the driving timing of the pixel may include an initialization section, a compensation section, a writing section and a light emission section.

[0115] In the initialization section (P2, P3 of FIG. 4), the first emission signal (EM1) may have a deactivation level, the second emission signal (EM2) may have an activation level, the initialization gate signal (GI) may have an activation level, and the write gate signal (GW) may have a deactivation level.

[0116] In the compensation section (P5 of FIG. 4) after the initialization section (P2, P3 of FIG. 4), the first emission signal (EM1) may have an activation level, the second emission signal (EM2) may have a deactivation level, the second reference gate signal (GR(n-1)) may have an activation level, the first reference gate signal (GR(n)) may have an activation level, the initialization gate signal (GI) may have a deactivation level, and the write gate signal (GW) may have the deactivation level.

[0117] In the write section (P7 of FIG. 4) after the compensation section (P5 of FIG. 4), the first emission signal (EM1) may have the deactivation level, the second emission signal (EM2) may have the deactivation level, the second reference gate signal (GR(n-1)) may have the deactivation level, the first reference gate signal (GR(n)) may have the activation level, the initialization gate signal (GI) may have the deactivation level, and the write gate signal (GW) may have an activation pulse. (For example, the write gate signal (GW) may partially have the activation level in the write section (P7).)

[0118] In the emission section (P10 of FIG. 4) following the above-described writing section (P7 of FIG. 4), the first emission signal (EM1) may have the above-described activation level, the second emission signal (EM2) may have the above-described activation level, the initialization gate signal (GI) may have the above-described deactivation level, and the writing gate signal (GW) may have the above-described deactivation level.

[0119] According to the present embodiment, the pixel includes the first capacitor (CST1) and the second capacitor (CST2) connected in series between the control electrode and the second electrode of the first switching element (T1), and the seventh switching element (T7) applying the reference voltage (VREF) to the node (N4) between the first capacitor (CST1) and the second capacitor (CST2), and the data voltage (VDATA) can be directly applied to the control electrode (N1) of the first switching element (T1).

[0120] Since the threshold voltage of the first switching element (T1) is written to the second capacitor (CST2) and the data voltage (VDATA) based on the reference voltage (VREF) is directly applied to the first capacitor (CST1), the swing range of the data voltage (VDATA) and the range of the gate-source voltage of the first switching element (T1) can be similar.

[0121] Since the swing range of the data voltage (VDATA) and the range of the gate-source voltage of the first switching element (T1) are similar, the slope of the current-voltage curve of the first switching element (T1) can be set low, and accordingly, the sensitivity of the first switching element (T1) can be reduced.

[0122] By reducing the sensitivity of the first switching element (T1), the display quality of the display panel (100) can be improved by preventing crosstalk, deterioration of image quality due to touch noise, and cycle mura.

[0123] In addition, since only the second capacitor (CST2) is initialized during the initialization period of the pixel, the amount of initializing voltage can be reduced. (The first capacitor (CST1) is not initialized during the initialization period of the pixel.)

[0124] Fig. 5 is a circuit diagram showing a pixel of a display panel (100) of a display device according to one embodiment of the present invention. Fig. 6 is a timing diagram showing an example of input signals applied to the pixel of Fig. 5.

[0125] The display device according to the present embodiment is identical to the display device of FIGS. 1 to 4, except that the first reference gate signal and the second reference gate signal are separate signals generated from separate gate driving circuits. Therefore, the same reference numbers are used for the same or similar components, and redundant descriptions are omitted.

[0126] Referring to FIGS. 1, 5 and 6, for example, the pixel may include first, second, third, fourth, fifth, sixth and seventh switching elements (T1, T2, T3, T4, T5, T6 and T7), a first capacitor (CST1), a second capacitor (CST2) and the light emitting element (EE).

[0127] In the present embodiment, the seventh switching element (T7) may include a control electrode to which a first reference gate signal (e.g., GR1(n)) is applied, a first electrode to which the reference voltage (VREF) is applied, and a second electrode connected to the fourth node (N4).

[0128] In the present embodiment, the third switching element (T3) may include a control electrode to which a second reference gate signal (e.g., GR2(n)) is applied, a first electrode to which the reference voltage (VREF) is applied, and a second electrode connected to the first node (N1).

[0129] In this embodiment, unlike the embodiments of FIGS. 1 to 4, the first reference gate signal (e.g., GR1(n)) and the second reference gate signal (e.g., GR2(n)) may be separate signals generated in separate driving circuits.

[0130] According to the present embodiment, the pixel includes the first capacitor (CST1) and the second capacitor (CST2) connected in series between the control electrode and the second electrode of the first switching element (T1), and the seventh switching element (T7) applying the reference voltage (VREF) to the node (N4) between the first capacitor (CST1) and the second capacitor (CST2), and the data voltage (VDATA) can be directly applied to the control electrode (N1) of the first switching element (T1).

[0131] Since the threshold voltage of the first switching element (T1) is written to the second capacitor (CST2) and the data voltage (VDATA) based on the reference voltage (VREF) is directly applied to the first capacitor (CST1), the swing range of the data voltage (VDATA) and the range of the gate-source voltage of the first switching element (T1) can be similar.

[0132] Since the swing range of the data voltage (VDATA) and the range of the gate-source voltage of the first switching element (T1) are similar, the slope of the current-voltage curve of the first switching element (T1) can be set low, and accordingly, the sensitivity of the first switching element (T1) can be reduced.

[0133] By reducing the sensitivity of the first switching element (T1), the display quality of the display panel (100) can be improved by preventing crosstalk, deterioration of image quality due to touch noise, and cycle mura.

[0134] In addition, since only the second capacitor (CST2) is initialized in the initialization section of the pixel, the amount of initialization voltage can be reduced.

[0135] Fig. 7 is a circuit diagram showing a pixel of a display panel (100) of a display device according to one embodiment of the present invention. Fig. 8 is a timing diagram showing an example of input signals applied to the pixel of Fig. 7.

[0136] The display device according to the present embodiment is the same as the display device of FIGS. 1 to 4 except that the pixel further includes an eighth switching element, and therefore the same reference numbers are used for the same or similar components, and redundant descriptions are omitted.

[0137] Referring to FIGS. 1, 7 and 8, for example, the pixel may include first, second, third, fourth, fifth, sixth and seventh switching elements (T1, T2, T3, T4, T5, T6 and T7), a first capacitor (CST1), a second capacitor (CST2) and the light emitting element (EE). The pixel may further include an eighth switching element (T8).

[0138] The fourth switching element (T4) includes a control electrode to which the initialization gate signal (GI) is applied, a first electrode to which the initialization voltage (VAINT) is applied, and a second electrode connected to the anode electrode of the light-emitting element (EE).

[0139] The sixth switching element (T6) includes a control electrode to which the second emission signal (EM2) is applied, a first electrode connected to the third node (N3), and a second electrode connected to the anode electrode.

[0140] The eighth switching element (T8) may include a control electrode to which the initialization gate signal (GI) is applied, a first electrode to which a second initialization voltage (VINT) is applied, and a second electrode connected to the third node (N3).

[0141] For example, the initialization voltage (VAINT) may be less than the first power supply voltage (ELVDD) and greater than the second power supply voltage (ELVSS). For example, the second initialization voltage (VINT) may be less than the first power supply voltage (ELVDD) and greater than the second power supply voltage (ELVSS). For example, the second initialization voltage (VINT) may be greater than the initialization voltage (VAINT).

[0142] The optimal voltage for initializing the anode electrode of the light-emitting element (EE) and the optimal voltage for initializing the second electrode (third node (N3)) of the second capacitor (CST2) may be different from each other. In the present embodiment, the initialization voltage (VAINT) for initializing the anode electrode of the light-emitting element (EE) and the second initialization voltage (VINT) for initializing the second electrode (third node (N3)) of the second capacitor (CST2) may be set separately, so that the display quality of the display panel (100) can be further improved.

[0143] The driving timing of the above pixel may include an initialization section, a compensation section, a writing section, and a light emission section.

[0144] In the initialization section (P2, P3 of FIG. 8), the first emission signal (EM1) may have a deactivation level, the second emission signal (EM2) may have a deactivation level, the initialization gate signal (GI) may have an activation level, and the write gate signal (GW) may have a deactivation level.

[0145] In the initialization section (P2, P3 of FIG. 8), the fourth switching element (T4) is turned on in response to the initialization gate signal (GI), so that the initialization voltage (VAINT) can be applied to the anode electrode of the light-emitting element (EE).

[0146] In the initialization section (P2, P3 of FIG. 8), the eighth switching element (T8) is turned on in response to the initialization gate signal (GI), so that the second initialization voltage (VINT) can be applied to the third node (N3).

[0147] In the compensation section (P4 of FIG. 8) following the initialization section (P2, P3 of FIG. 8), the first emission signal (EM1) may have an activation level, the second emission signal (EM2) may have the deactivation level, the second reference gate signal (GR(n-1)) may have an activation level, the first reference gate signal (GR(n)) may have an activation level, the initialization gate signal (GI) may have a deactivation level, and the write gate signal (GW) may have the deactivation level.

[0148] In the write section (P6 of FIG. 8) after the compensation section (P4 of FIG. 8), the first emission signal (EM1) may have the deactivation level, the second emission signal (EM2) may have the deactivation level, the second reference gate signal (GR(n-1)) may have the deactivation level, the first reference gate signal (GR(n)) may have the activation level, the initialization gate signal (GI) may have the deactivation level, and the write gate signal (GW) may have the activation pulse.

[0149] In the emission section (P8 of FIG. 8) following the writing section (P6 of FIG. 8), the first emission signal (EM1) may have the activation level, the second emission signal (EM2) may have the activation level, the initialization gate signal (GI) may have the deactivation level, and the writing gate signal (GW) may have the deactivation level.

[0150] According to the present embodiment, the pixel includes the first capacitor (CST1) and the second capacitor (CST2) connected in series between the control electrode and the second electrode of the first switching element (T1), and the seventh switching element (T7) applying the reference voltage (VREF) to the node (N4) between the first capacitor (CST1) and the second capacitor (CST2), and the data voltage (VDATA) can be directly applied to the control electrode (N1) of the first switching element (T1).

[0151] Since the threshold voltage of the first switching element (T1) is written to the second capacitor (CST2) and the data voltage (VDATA) based on the reference voltage (VREF) is directly applied to the first capacitor (CST1), the swing range of the data voltage (VDATA) and the range of the gate-source voltage of the first switching element (T1) can be similar.

[0152] Since the swing range of the data voltage (VDATA) and the range of the gate-source voltage of the first switching element (T1) are similar, the slope of the current-voltage curve of the first switching element (T1) can be set low, and accordingly, the sensitivity of the first switching element (T1) can be reduced.

[0153] By reducing the sensitivity of the first switching element (T1), the display quality of the display panel (100) can be improved by preventing crosstalk, deterioration of image quality due to touch noise, and cycle mura.

[0154] In addition, since only the second capacitor (CST2) is initialized in the initialization section of the pixel, the amount of initialization voltage can be reduced.

[0155] FIG. 9 is a circuit diagram showing pixels of a display panel (100) of a display device according to one embodiment of the present invention.

[0156] The display device according to the present embodiment is the same as the display device of FIGS. 1 to 4 except that the second switching element is connected to the fourth node, the signal applied to the control electrode of the third switching element is the first reference gate signal, and the signal applied to the control electrode of the seventh switching element is the second reference gate signal. Therefore, the same reference numbers are used for the same or similar components, and redundant descriptions are omitted.

[0157] Referring to FIGS. 1, 3, 4 and 9, for example, the pixel may include first, second, third, fourth, fifth, sixth and seventh switching elements (T1, T2, T3, T4, T5, T6 and T7), a first capacitor (CST1), a second capacitor (CST2) and the light emitting element (EE).

[0158] The first switching element (T1) includes a control electrode connected to a first node (N1), a first electrode connected to a second node (N2), and a second electrode connected to a third node (N3). The first switching element (T1) may be referred to as a driving switching element.

[0159] The first capacitor (CST1) includes a first electrode connected to the first node (N1) and a second electrode connected to a fourth node (N4).

[0160] The second capacitor (CST2) includes a first electrode connected to the fourth node (N4) and a second electrode connected to the third node (N3).

[0161] The second switching element (T2) applies the data voltage (VDATA) to the first capacitor (CST1).

[0162] The third switching element (T3) applies a reference voltage (VREF) to the first node (N1).

[0163] The fourth switching element (T4) includes a control electrode to which the initialization gate signal (GI) is applied, a first electrode to which the initialization voltage (VAINT) is applied, and a second electrode connected to the anode electrode of the light-emitting element (EE).

[0164] The fifth switching element (T5) includes a control electrode to which the first emission signal (EM1) is applied, a first electrode to which the first power supply voltage (ELVDD) is applied, and a second electrode connected to the second node (N2).

[0165] The sixth switching element (T6) includes a control electrode to which the second emission signal (EM2) is applied, a first electrode connected to the third node (N3), and a second electrode connected to the anode electrode.

[0166] The seventh switching element (T7) applies the reference voltage (VREF) to the fourth node (N4).

[0167] The light emitting element (EE) may include the anode electrode and the cathode electrode to which a second power supply voltage (ELVSS) is applied. For example, the first power supply voltage (ELVDD) may be greater than the second power supply voltage (ELVSS).

[0168] For example, the initialization voltage (VAINT) may be smaller than the first power supply voltage (ELVDD) and larger than the second power supply voltage (ELVSS).

[0169] In this embodiment, the second switching element (T2) may include a control electrode to which the write gate signal (GW) is applied, a first electrode to which the data voltage (VDATA) is applied, and a second electrode connected to the fourth node (N4).

[0170] In this embodiment, the seventh switching element (T7) may include a control electrode to which the second reference gate signal (e.g., GR(n-1)) is applied, a first electrode to which the reference voltage (VREF) is applied, and a second electrode connected to the fourth node (N4).

[0171] In the present embodiment, the third switching element (T3) may include a control electrode to which the first reference gate signal (e.g., GR(n)) is applied, a first electrode to which the reference voltage (VREF) is applied, and a second electrode connected to the first node (N1).

[0172] In the present embodiment, the white data voltage may be lower than the black data voltage. In the present embodiment, the data voltage representing a high grayscale may be lower than the data voltage representing a low grayscale. For example, the reference voltage (VREF) may be lower than the black data voltage and higher than the white data voltage. For example, the reference voltage (VREF) may be lower than the first power voltage (ELVDD).

[0173] In the present embodiment, the first reference gate signal (GR(n)) may be a reference gate signal of the nth stage. The second reference gate signal (GR(n-1)) may be a reference gate signal of any one of the stages preceding the nth stage. n may be a natural number greater than or equal to 2. For example, the second reference gate signal (GR(n-1)) may be a reference gate signal of the stage immediately preceding the nth stage. The nth stage may mean a stage of a gate driving circuit corresponding to the nth pixel row of the display panel (100).

[0174] When the first reference gate signal (GR(n)) is a reference gate signal of the nth stage and the second reference gate signal (GR(n-1)) is a reference gate signal of any one of the previous stages of the nth stage, the first reference gate signal (GR(n)) and the second reference gate signal (GR(n-1)) are generated from the same gate driving circuit, so that the manufacturing cost of the display device can be reduced and the dead space of the display device can be reduced.

[0175] Alternatively, as in the embodiments of FIGS. 5 and 6, the first reference gate signal and the second reference gate signal may be separate signals generated in separate gate driving circuits.

[0176] The driving timing of FIG. 3 and the driving timing of FIG. 4 can also be applied to the pixel of FIG. 9.

[0177] In the writing section of the present embodiment, the second switching element (T2) and the third switching element (T3) are turned on, so that the data voltage (VDATA) can be written to the first capacitor (CST1) based on the reference voltage (VREF).

[0178] According to the present embodiment, the pixel includes the first capacitor (CST1) and the second capacitor (CST2) connected in series between the control electrode and the second electrode of the first switching element (T1), and the seventh switching element (T7) applying the reference voltage (VREF) to the node (N4) between the first capacitor (CST1) and the second capacitor (CST2), and the data voltage (VDATA) can be directly applied to the node (N4) between the first capacitor (CST1) and the second capacitor (CST2).

[0179] Since the threshold voltage of the first switching element (T1) is written to the second capacitor (CST2) and the data voltage (VDATA) based on the reference voltage (VREF) is directly applied to the first capacitor (CST1), the swing range of the data voltage (VDATA) and the range of the gate-source voltage of the first switching element (T1) can be similar.

[0180] Since the swing range of the data voltage (VDATA) and the range of the gate-source voltage of the first switching element (T1) are similar, the slope of the current-voltage curve of the first switching element (T1) can be set low, and accordingly, the sensitivity of the first switching element (T1) can be reduced.

[0181] By reducing the sensitivity of the first switching element (T1), the display quality of the display panel (100) can be improved by preventing crosstalk, deterioration of image quality due to touch noise, and cycle mura.

[0182] In addition, since only the second capacitor (CST2) is initialized in the initialization section of the pixel, the amount of initialization voltage can be reduced.

[0183] FIG. 10 is a circuit diagram showing pixels of a display panel (100) of a display device according to one embodiment of the present invention.

[0184] The display device according to the present embodiment is the same as the display device of FIG. 9 except that the pixel further includes an eighth switching element, and therefore the same reference numbers are used for the same or similar components, and redundant descriptions are omitted.

[0185] Referring to FIGS. 1, 8 and 10, for example, the pixel may include first, second, third, fourth, fifth, sixth and seventh switching elements (T1, T2, T3, T4, T5, T6 and T7), a first capacitor (CST1), a second capacitor (CST2) and the light emitting element (EE). The pixel may further include an eighth switching element (T8).

[0186] In this embodiment, the second switching element (T2) may include a control electrode to which the write gate signal (GW) is applied, a first electrode to which the data voltage (VDATA) is applied, and a second electrode connected to the fourth node (N4).

[0187] In this embodiment, the seventh switching element (T7) may include a control electrode to which the second reference gate signal (e.g., GR(n-1)) is applied, a first electrode to which the reference voltage (VREF) is applied, and a second electrode connected to the fourth node (N4).

[0188] In the present embodiment, the third switching element (T3) may include a control electrode to which the first reference gate signal (e.g., GR(n)) is applied, a first electrode to which the reference voltage (VREF) is applied, and a second electrode connected to the first node (N1).

[0189] In the present embodiment, the first reference gate signal (GR(n)) may be a reference gate signal of the nth stage. The second reference gate signal (GR(n-1)) may be a reference gate signal of any one of the stages preceding the nth stage. n may be a natural number greater than or equal to 2.

[0190] Alternatively, as in the embodiments of FIGS. 5 and 6, the first reference gate signal and the second reference gate signal may be separate signals generated in separate gate driving circuits.

[0191] The fourth switching element (T4) includes a control electrode to which the initialization gate signal (GI) is applied, a first electrode to which the initialization voltage (VAINT) is applied, and a second electrode connected to the anode electrode of the light-emitting element (EE).

[0192] The sixth switching element (T6) includes a control electrode to which the second emission signal (EM2) is applied, a first electrode connected to the third node (N3), and a second electrode connected to the anode electrode.

[0193] The eighth switching element (T8) may include a control electrode to which the initialization gate signal (GI) is applied, a first electrode to which a second initialization voltage (VINT) is applied, and a second electrode connected to the third node (N3).

[0194] For example, the initialization voltage (VAINT) may be less than the first power supply voltage (ELVDD) and greater than the second power supply voltage (ELVSS). For example, the second initialization voltage (VINT) may be less than the first power supply voltage (ELVDD) and greater than the second power supply voltage (ELVSS). For example, the second initialization voltage (VINT) may be greater than the initialization voltage (VAINT).

[0195] The optimal voltage for initializing the anode electrode of the light-emitting element (EE) and the optimal voltage for initializing the second electrode (third node (N3)) of the second capacitor (CST2) may be different from each other. In the present embodiment, the initialization voltage (VAINT) for initializing the anode electrode of the light-emitting element (EE) and the second initialization voltage (VINT) for initializing the second electrode (third node (N3)) of the second capacitor (CST2) may be set separately, so that the display quality of the display panel (100) can be further improved.

[0196] The driving timing of Fig. 8 can also be applied to the pixels of Fig. 10.

[0197] In the writing section of the present embodiment, the second switching element (T2) and the third switching element (T3) are turned on, so that the data voltage (VDATA) can be written to the first capacitor (CST1) based on the reference voltage (VREF).

[0198] According to the present embodiment, the pixel includes the first capacitor (CST1) and the second capacitor (CST2) connected in series between the control electrode and the second electrode of the first switching element (T1), and the seventh switching element (T7) applying the reference voltage (VREF) to the node (N4) between the first capacitor (CST1) and the second capacitor (CST2), and the data voltage (VDATA) can be directly applied to the node (N4) between the first capacitor (CST1) and the second capacitor (CST2).

[0199] Since the threshold voltage of the first switching element (T1) is written to the second capacitor (CST2) and the data voltage (VDATA) based on the reference voltage (VREF) is directly applied to the first capacitor (CST1), the swing range of the data voltage (VDATA) and the range of the gate-source voltage of the first switching element (T1) can be similar.

[0200] Since the swing range of the data voltage (VDATA) and the range of the gate-source voltage of the first switching element (T1) are similar, the slope of the current-voltage curve of the first switching element (T1) can be set low, and accordingly, the sensitivity of the first switching element (T1) can be reduced.

[0201] By reducing the sensitivity of the first switching element (T1), the display quality of the display panel (100) can be improved by preventing crosstalk, deterioration of image quality due to touch noise, and cycle mura.

[0202] In addition, since only the second capacitor (CST2) is initialized in the initialization section of the pixel, the amount of initialization voltage can be reduced.

[0203] FIG. 11 is a block diagram illustrating an electronic device (1000) according to one embodiment of the present invention. FIG. 12 is a diagram illustrating an example in which the electronic device (1000) of FIG. 11 is implemented as a smartphone. FIG. 13 is a diagram illustrating an example in which the electronic device (1000) of FIG. 11 is implemented as a monitor.

[0204] Referring to FIGS. 11 to 13, the electronic device (1000) may include a processor (1010), a memory device (1020), a storage device (1030), an input / output device (1040), a power supply (1050), and a display device (1060). In this case, the display device (1060) may be the display device of FIG. 1. In addition, the electronic device (1000) may further include several ports that can communicate with a video card, a sound card, a memory card, a USB device, etc., or communicate with other systems.

[0205] According to one embodiment, as illustrated in FIG. 12, the electronic device (1000) may be implemented as a smartphone. As illustrated in FIG. 13, the electronic device (1000) may be implemented as a monitor. However, this is merely exemplary, and the electronic device (1000) is not limited thereto. For example, the electronic device (1000) may be implemented as a television, a mobile phone, a video phone, a smart pad, a smart watch, a tablet PC, a vehicle navigation system, a laptop, a head-mounted display device, etc.

[0206] The processor (1010) may perform specific calculations or tasks. Depending on the embodiment, the processor (1010) may be a microprocessor, a central processing unit, an application processor, etc. The processor (1010) may be connected to other components via an address bus, a control bus, a data bus, etc. Depending on the embodiment, the processor (1010) may also be connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

[0207] The above processor (1010) can output the input image data (IMG) and the input control signal (CONT) to the drive control unit (200) of Fig. 1. The processor (1010) may also be referred to as a host.

[0208] The memory device (1020) can store data necessary for the operation of the electronic device (1000). For example, the memory device (1020) may include a non-volatile memory device such as an Erasable Programmable Read-Only Memory (EPROM) device, an Electrically Erasable Programmable Read-Only Memory (EEPROM) device, a flash memory device, a Phase Change Random Access Memory (PRAM) device, a Resistance Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a Polymer Random Access Memory (PoRAM) device, a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM) device, and / or a volatile memory device such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a mobile DRAM device, and the like.

[0209] The storage device (1030) may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The input / output device (1040) may include an input means such as a keyboard, a keypad, a touchpad, a touchscreen, a mouse, etc., and an output means such as a speaker, a printer, etc. In some embodiments, a display device (1060) may be included in the input / output device (1040). The power supply (1050) may supply power required for the operation of the electronic device (1000). The display device (1060) may be connected to other components via the buses or other communication links.

[0210] According to the pixel according to the present invention described above, the display device including the pixel, and the electronic device including the pixel, the display quality of the display panel can be improved.

[0211] Although the present invention has been described with reference to the above embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

[0212] <Explanation of symbols>

[0213] 100: Display panel 200: Drive control unit

[0214] 300: Gate driver 400: Gamma reference voltage generator

[0215] 500: Data drive unit 600: Emission drive unit

Claims

1. Light-emitting element; A first switching element comprising a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; A first capacitor including a first electrode connected to the first node and a second electrode connected to a fourth node; A second capacitor including a first electrode connected to the fourth node and a second electrode connected to the third node; A second switching element that applies a data voltage to the first capacitor; A third switching element that applies a reference voltage to the first node; A fourth switching element including a control electrode to which an initialization gate signal is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the anode electrode of the light-emitting element; A fifth switching element including a control electrode to which a first emission signal is applied, a first electrode to which a first power voltage is applied, and a second electrode connected to the second node; A sixth switching element comprising a control electrode to which a second emission signal is applied, a first electrode connected to the third node, and a second electrode connected to the anode electrode; and A pixel including a seventh switching element that applies the reference voltage to the fourth node.

2. A pixel according to claim 1, characterized in that the second switching element includes a control electrode to which a write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the first node.

3. A pixel according to claim 2, wherein the seventh switching element comprises a control electrode to which a first reference gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the fourth node.

4. A pixel according to claim 3, characterized in that the third switching element includes a control electrode to which a second reference gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the first node.

5. In the fourth paragraph, the first reference gate signal is a reference gate signal of the nth stage, A pixel characterized in that the second reference gate signal is a reference gate signal of any one of the previous stages of the nth stage (n is a natural number greater than or equal to 2).

6. A pixel characterized in that in the fourth paragraph, in the initialization section, the first emission signal has a deactivation level, the second emission signal has an activation level, the initialization gate signal has an activation level, and the write gate signal has a deactivation level.

7. A pixel characterized in that in the compensation section after the initialization section in the 6th paragraph, the first emission signal has an activation level, the second emission signal has a deactivation level, the second reference gate signal has an activation level, the first reference gate signal has an activation level, the initialization gate signal has a deactivation level, and the write gate signal has the deactivation level.

8. A pixel characterized in that in the write period after the compensation period in the 7th paragraph, the first emission signal has the deactivation level, the second emission signal has the deactivation level, the second reference gate signal has the deactivation level, the first reference gate signal has the activation level, the initialization gate signal has the deactivation level, and the write gate signal has an activation pulse.

9. A pixel characterized in that in the emission period after the writing period in the 8th paragraph, the first emission signal has the activation level, the second emission signal has the activation level, the initialization gate signal has the deactivation level, and the writing gate signal has the deactivation level.

10. A pixel according to claim 9, characterized in that in the second initialization period between the writing period and the emitting period, the first emission signal has the deactivation level, the second emission signal has the activation level, the initialization gate signal has the activation level, and the writing gate signal has the deactivation level.

11. A pixel characterized in that in the fourth paragraph, the second switching element and the seventh switching element are turned on in the writing section.

12. A pixel according to claim 4, characterized in that it further comprises an eighth switching element including a control electrode to which the initialization gate signal is applied, a first electrode to which the second initialization voltage is applied, and a second electrode connected to the third node.

13. A pixel characterized in that in the 12th paragraph, in the initialization section, the first emission signal has a deactivation level, the second emission signal has a deactivation level, the initialization gate signal has an activation level, and the write gate signal has a deactivation level.

14. In the 13th paragraph, in the compensation section after the initialization section, the first emission signal has an activation level, the second emission signal has the deactivation level, the second reference gate signal has an activation level, the first reference gate signal has an activation level, the initialization gate signal has a deactivation level, and the write gate signal has the deactivation level. In the write period after the compensation period, the first emission signal has the deactivation level, the second emission signal has the deactivation level, the second reference gate signal has the deactivation level, the first reference gate signal has the activation level, the initialization gate signal has the deactivation level, and the write gate signal has an activation pulse. A pixel characterized in that, in the emission period after the writing period, the first emission signal has the activation level, the second emission signal has the activation level, the initialization gate signal has the deactivation level, and the writing gate signal has the deactivation level.

15. A pixel according to claim 1, characterized in that the second switching element includes a control electrode to which a write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the fourth node.

16. A pixel according to claim 15, wherein the seventh switching element comprises a control electrode to which a second reference gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the fourth node.

17. A pixel according to claim 16, characterized in that the third switching element includes a control electrode to which a first reference gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the first node.

18. In the 17th paragraph, the first reference gate signal is a reference gate signal of the nth stage, A pixel characterized in that the second reference gate signal is a reference gate signal of any one of the previous stages of the nth stage (n is a natural number greater than or equal to 2).

19. A display panel containing pixels; A gate driver for outputting an initialization gate signal to the above pixel; A data driver that outputs a data voltage to the above pixel; and It includes an emission driver that outputs a first emission signal and a second emission signal to the above pixel, The above pixel is light emitting element; A first switching element comprising a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; A first capacitor including a first electrode connected to the first node and a second electrode connected to a fourth node; A second capacitor including a first electrode connected to the fourth node and a second electrode connected to the third node; A second switching element that applies the data voltage to the first capacitor; A third switching element that applies a reference voltage to the first node; A fourth switching element including a control electrode to which the initialization gate signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the anode electrode of the light-emitting element; A fifth switching element including a control electrode to which the first emission signal is applied, a first electrode to which the first power voltage is applied, and a second electrode connected to the second node; A sixth switching element including a control electrode to which the second emission signal is applied, a first electrode connected to the third node, and a second electrode connected to the anode electrode; and A display device characterized by including a seventh switching element that applies the reference voltage to the fourth node.

20. A display panel containing pixels; A gate driver for outputting an initialization gate signal to the above pixel; A data driver that outputs a data voltage to the above pixel; An emission driver that outputs a first emission signal and a second emission signal to the above pixel; A driving control unit that controls the gate driving unit, the data driving unit, and the emission driving unit; and Includes a processor that outputs input image data and input control signals to the above driving control unit, The above pixel is light emitting element; A first switching element comprising a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; A first capacitor including a first electrode connected to the first node and a second electrode connected to a fourth node; A second capacitor including a first electrode connected to the fourth node and a second electrode connected to the third node; A second switching element that applies the data voltage to the first capacitor; A third switching element that applies a reference voltage to the first node; A fourth switching element including a control electrode to which the initialization gate signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the anode electrode of the light-emitting element; A fifth switching element including a control electrode to which the first emission signal is applied, a first electrode to which the first power voltage is applied, and a second electrode connected to the second node; A sixth switching element including a control electrode to which the second emission signal is applied, a first electrode connected to the third node, and a second electrode connected to the anode electrode; and An electronic device characterized by including a seventh switching element that applies the reference voltage to the fourth node.

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