Display device, manufacturing method therefor, and electronic device comprising same

Abstract

This display device comprises a substrate and a display element layer arranged on the substrate, wherein the display element layer includes: an anode electrode and a cathode electrode; a first reflective electrode disposed on the anode electrode; a second reflective electrode disposed on the cathode electrode; a light-emitting element including a first protective electrode, a second protective electrode, a first element electrode disposed inside the first protective electrode, and a second element electrode disposed inside the second protective electrode; a first transparent electrode for electrically connecting the first reflective electrode and the first protective electrode; and a second transparent electrode for electrically connecting the second reflective electrode and the second protective electrode.

Description

Display device, method for manufacturing the same, and electronic device including the same

[0001] The embodiments relate to a display device, a method of manufacturing the same, and an electronic device including the same.

[0002] As information technology advances, the importance of display devices, which serve as a link between users and information, is growing. In response, the use of display devices such as liquid crystal displays (LCDs), organic light-emitting displays (OLEDs), and inorganic light-emitting displays (ILDs), is increasing.

[0003] During the transfer phase of a light-emitting device, some electrodes may be damaged. A method may be needed to increase the luminous efficiency of the light-emitting device while preventing damage to some electrodes.

[0004] Embodiments provide a display device in which damage to electrodes of a light-emitting element is prevented, a method for manufacturing the display device, and an electronic device including the display device.

[0005] However, the embodiments are not limited to those presented herein. The embodiments will become more apparent to those skilled in the art by reference to the detailed description of the disclosure provided below.

[0006] A display device according to embodiments of the present invention may include a substrate; and a display element layer disposed on the substrate, wherein the display element layer may include an anode electrode and a cathode electrode; a first reflective electrode disposed on the anode electrode; a second reflective electrode disposed on the cathode electrode; a light-emitting element including a first protective electrode, a second protective electrode, a first element electrode disposed on the inner side of the first protective electrode, and a second element electrode disposed on the inner side of the second protective electrode; a first transparent electrode electrically connecting the first reflective electrode and the first protective electrode; and a second transparent electrode electrically connecting the second reflective electrode and the second protective electrode.

[0007] In embodiments, the first element electrode may be formed on side surfaces of the light-emitting element adjacent to the anode electrode and on a portion of the lower surface of the light-emitting element adjacent to the anode electrode, and the second element electrode may be formed on side surfaces of the light-emitting element adjacent to the cathode electrode and on a portion of the lower surface of the light-emitting element adjacent to the cathode electrode.

[0008] In embodiments, the first element electrode and the second element electrode may have a hook shape.

[0009] In embodiments, the first protective electrode may be formed along side surfaces of the first element electrode and a lower surface of the first element electrode, and the second protective electrode may be formed along side surfaces of the second element electrode and a lower surface of the second element electrode.

[0010] In embodiments, the first protective electrode and the second protective electrode may have a hook shape.

[0011] In embodiments, the first element electrode and the second element electrode may include the same reflective conductive material, and the first protective electrode and the second protective electrode may include the same conductive material.

[0012] In embodiments, the first element electrode and the second element electrode may include at least one of aluminum and titanium, and the first protective electrode and the second protective electrode may include indium zinc oxide.

[0013] In embodiments, the first transparent electrode and the second transparent electrode may include the same transparent conductive material.

[0014] In embodiments, the display element layer further includes an overcoat layer that partially covers the first reflective electrode and the second reflective electrode, and the light-emitting element is disposed on the overcoat layer, and in a cross-section, the height of the first protective electrode is smaller than the height of the first transparent electrode, and the height of the first protective electrode and the height of the first transparent electrode may be heights based on the overcoat layer in the cross-section.

[0015] In embodiments, the display element layer further includes an overcoat layer that partially covers the first reflective electrode and the second reflective electrode, and the light emitting element is disposed on the overcoat layer, and in a cross-sectional view, an area that does not contact the first protective electrode may be provided at a lower portion of the first element electrode.

[0016] A method for manufacturing a display device according to embodiments of the present invention includes the steps of: manufacturing a pixel circuit layer disposed on a substrate; and manufacturing a display element layer on the pixel circuit layer; wherein the step of manufacturing the display element layer includes the steps of: patterning an anode electrode and a cathode electrode on the pixel circuit layer; patterning a first reflective electrode electrically connected to the anode electrode and a second reflective electrode electrically connected to the cathode electrode; patterning an overcoat layer on the first reflective electrode and the second reflective electrode; and disposing a light-emitting element including a protective layer, a first element electrode, and a second element electrode on the pixel circuit layer, wherein the protective layer is formed along side surfaces of the light-emitting element and a lower surface of the light-emitting element, and may be disposed to surround the first element electrode and the second element electrode.

[0017] In embodiments, the step of manufacturing the display element layer may further include the step of patterning a transparent electrode layer on the anode electrode, the first reflective electrode, the cathode electrode, the second reflective electrode, the overcoat layer, and the light-emitting element.

[0018] In embodiments, the step of manufacturing the display element layer may further include the step of patterning a photoresist layer on the transparent electrode layer.

[0019] In embodiments, the step of manufacturing the display element layer may further include the step of etching the transparent electrode layer and the protective layer using the photoresist layer as an etching mask; the step of providing the etched transparent electrode layer as a first transparent electrode and a second transparent electrode; and the step of removing the photoresist layer.

[0020] In embodiments, the step of manufacturing the display element layer further includes the step of heat-treating the display element layer, and the heat-treating temperature can be determined in a range in which the first and second transparent electrodes are crystallized and the protective layer is not crystallized.

[0021] In embodiments, the step of manufacturing the display element layer may further include the step of etching the protective layer except for the portion surrounded by the heat-treated first and second transparent electrodes; and the step of providing the etched protective layer as the first protective electrode and the second protective electrode.

[0022] In embodiments, the first protective electrode and the second protective electrode may have a hook shape.

[0023] In embodiments, the first element electrode and the second element electrode may include the same reflective conductive material, and the first protective electrode and the second protective electrode may include the same conductive material.

[0024] In embodiments, the first element electrode and the second element electrode may include at least one of aluminum and titanium, and the first protective electrode and the second protective electrode may include indium zinc oxide.

[0025] In embodiments, the first transparent electrode and the second transparent electrode may include the same transparent conductive material.

[0026] An electronic device according to embodiments of the present invention may include a display device including a display element layer disposed on a substrate, wherein the display element layer may include: an anode electrode and a cathode electrode; a first reflective electrode disposed on the anode electrode; a second reflective electrode disposed on the cathode electrode; a light-emitting element including a first protective electrode, a second protective electrode, a first element electrode disposed on an inner side of the first protective electrode, and a second element electrode disposed on an inner side of the second protective electrode; a first transparent electrode electrically connecting the first reflective electrode and the first protective electrode; and a second transparent electrode electrically connecting the second reflective electrode and the second protective electrode.

[0027] In embodiments, the electronic device may include at least one of a mobile phone, a smartphone, a portable computer, a tablet personal computer (PC), a watch phone, a portable multimedia player (PMP), a navigation system, an ultra mobile computer (UMPC), a virtual reality device, a mixed reality device, and an augmented reality device.

[0028] A display device according to an embodiment of the present disclosure can prevent damage to electrodes of a light-emitting element, increase the light-emitting efficiency of the light-emitting element, and reduce the manufacturing cost of the light-emitting element.

[0029] Hereinafter, exemplary embodiments will be described in more detail with reference to the attached drawings. However, these embodiments may be embodied in other forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to ensure that this disclosure is thorough and complete, and to fully convey the scope of the exemplary embodiments to those skilled in the art.

[0030] Dimensions in the drawings may be exaggerated for clarity. When an element is referred to as being "between" two elements, it should be understood that it may be the only element between the two elements, or that there may be one or more intervening elements. Identical reference numbers represent identical elements throughout.

[0031] Figure 1 is a block diagram showing an embodiment of a display device.

[0032] FIG. 2 is a block diagram showing an embodiment of one of the sub-pixels of FIG. 1.

[0033] FIG. 3 is a schematic plan view showing an embodiment of the display panel of FIG. 1.

[0034] FIG. 4 is a schematic cross-sectional view showing an embodiment of the display panel of FIG. 3.

[0035] FIG. 5 is a schematic cross-sectional view showing another embodiment of the display panel of FIG. 3.

[0036] FIG. 6 is a schematic plan view showing an embodiment of one of the pixels of FIG. 3.

[0037] Figure 7 is a schematic cross-sectional view along line II' of Figure 6.

[0038] Figure 8 is a schematic flowchart showing a method for manufacturing a display device according to an embodiment.

[0039] Figure 9 is a schematic flowchart showing steps for manufacturing a display element layer according to an embodiment.

[0040] Figures 10 to 13 are schematic cross-sectional views of the process steps according to Figure 9.

[0041] Figure 14 is a schematic flowchart showing steps for manufacturing first and second transparent electrodes according to an embodiment.

[0042] Figures 15 to 19 are schematic cross-sectional views of the process steps according to Figure 14.

[0043] Figure 20 is a block diagram showing an embodiment of a display system.

[0044] Figures 21 to 24 are schematic perspective views showing application examples of the display system of Figure 20.

[0045] In the following description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, the terms "embodiments" and "implementations" are interchangeable, referring to non-limiting examples of the devices or methods disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or in one or more equivalent arrangements. The various embodiments herein are not necessarily exclusive or limiting of the disclosure. For example, specific features, configurations, and characteristics of an embodiment may be used or implemented in other embodiments.

[0046] Unless otherwise specified, the described embodiments should be understood to provide features of the present invention. Accordingly, unless otherwise specified, features, components, modules, layers, films, panels, regions, and / or aspects of the various embodiments (hereinafter, individually or collectively referred to as “elements”) may be otherwise combined, separated, interchanged, and / or rearranged without departing from the scope of the invention.

[0047] The use of cross-hatching and / or shading in the accompanying drawings is generally intended to clarify boundaries between adjacent elements. Therefore, the presence or absence of cross-hatching or shading does not convey or indicate a preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between the depicted elements, and / or other characteristics, attributes, properties, etc. of the elements. Furthermore, the dimensions and relative sizes of elements in the accompanying drawings may be exaggerated for clarity and / or illustrative purposes. Where embodiments can be implemented differently, certain process sequences may be performed differently from the illustrated sequence. For example, two processes illustrated in succession may be performed substantially simultaneously or in the reverse order of the illustrated sequence. Additionally, like reference numerals indicate like elements.

[0048] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, connected to, or coupled to the other element or layer, or there may be intervening elements or layers present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. For this purpose, the term "connected" may refer to a physical, electrical, and / or fluid connection, with or without intervening elements. Furthermore, the axis in the first direction (DR1), the axis in the second direction (DR2), and the axis in the third direction (DR3) are not limited to the three axes of a Cartesian coordinate system, such as the X, Y, and Z axes, and may be interpreted in a broader sense. For example, the axis in the first direction (DR1), the axis in the second direction (DR2), and the axis in the third direction (DR3) may be perpendicular to each other, or may represent directions other than perpendicular to each other. For the purposes of this disclosure, “at least one of A and B” may be understood to mean A only, B only, or any combination of A and B. Additionally, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted to mean X only, Y only, Z only, or any combination of two or more of X, Y, and Z. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0049] While the terms "first," "second," and the like may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Accordingly, the first element discussed below may also be referred to as the second element, without departing from the present disclosure.

[0050] Spatially relative terms such as "beneath" (as in "beneath," below, under, lower), "above" (as in "upper," over), "higher," "side" (as in "sidewall"), and the like may be used herein for descriptive purposes to describe one element in relation to another, as depicted in the drawings. Spatially relative terms are intended to encompass various orientations of the device during use, operation, and / or manufacture, in addition to the orientation depicted in the drawings. For example, if the device is turned over in the drawings, an element described as being "beneath" another element or feature is positioned "above" the other element or feature. Thus, the term "beneath" can encompass both the above and below orientations. Furthermore, the device may be positioned in other orientations (e.g., rotated 90 degrees or positioned in other orientations), and spatially relative descriptors used herein should be interpreted accordingly.

[0051] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Furthermore, the terms "comprises," "comprising," "includes," and "including," as used herein, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms "substantially," "about," and other similar terms as used herein are used as terms of approximation rather than terms of degree, and are therefore used to account for inherent variations in measurements, calculations, and / or provided values ​​that would be recognizable to those of ordinary skill in the art.

[0052] Various embodiments are described herein with reference to cross-sectional and / or exploded views, which are schematic drawings of embodiments and / or intermediate structures. Therefore, variations in the shapes of the drawings are expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not be construed as necessarily limited to the specific depicted shapes of the regions, but should encompass, for example, variations in shape that occur during manufacturing. In this way, the regions depicted in the drawings may be schematic in nature, and the shapes of such regions may not reflect the actual shapes of the device regions and are therefore not necessarily intended to be limiting.

[0053] Figure 1 is a block diagram showing an embodiment of a display device.

[0054] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0055] The display panel (DP) includes sub-pixels (SP). The sub-pixels (SP) can be connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) can be connected to a data driver (130) via first to n-th data lines (DL1 to DLn).

[0056] The sub-pixels (SP) can generate light of two or more colors. For example, each of the sub-pixels (SP) can generate light of red, green, blue, cyan, magenta, yellow, etc.

[0057] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). For example, the pixel (PXL) can include three sub-pixels as illustrated in FIG. 1. For example, the pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels included in it.

[0058] The gate driver (120) is connected to the sub-pixels (SP) arranged in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) can output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) can include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0059] The gate driver (120) may be arranged on one side of the display panel (DP). However, embodiments are not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be arranged on one side of the display panel (DP) and the other side of the display panel (DP) opposite to the one side. For example, the gate driver (120) may be arranged on the periphery of the display panel (DP) in various forms according to embodiments.

[0060] The data driver (130) is connected to the sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) receives image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) operates in response to the data control signal (DCS). In embodiments, the data control signal (DCS) may include a source start signal, a source shift clock, a source output enable signal, etc.

[0061] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can use the received voltages to apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn). When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0062] In embodiments, the gate driver (120) and data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0063] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) is configured to generate a plurality of voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate a plurality of voltages by receiving an input voltage from the outside of the display device (DD) and regulating the received voltage.

[0064] A voltage generator (140) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In other embodiments, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0065] In addition, the voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a reference voltage can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In embodiments, the voltage generator (140) can provide pixel control signals to the sub-pixels (SP) through the pixel control lines (PXCL). Although FIG. 1 illustrates that the pixel control lines (PXCL) are connected between the voltage generator (140) and the display panel (DP), embodiments are not limited thereto. For example, the pixel control lines (PXCL) may be connected between the gate driver (120) and the display panel (DP). In this case, pixel control signals may be transmitted from the voltage generator (140) to the pixel control lines (PXCL) through the gate driver (120).

[0066] The controller (150) controls all operations of the display device (DD). The controller (150) receives input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0067] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (DATA). In embodiments, the controller (150) can output image data (DATA) by aligning the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit.

[0068] Two or more of the components of the data driver (130), the voltage generator (140), and the controller (150) may be implemented in an integrated circuit (e.g., a single integrated circuit). As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within the single driver integrated circuit (DIC). In other embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0069] Fig. 2 is a block diagram showing an embodiment of one of the sub-pixels of Fig. 1. In Fig. 2, a sub-pixel (SPij) arranged in an ith row (i is an integer greater than or equal to 1 and less than or equal to m) and a jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 is illustrated.

[0070] Referring to FIG. 2, a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0071] A light emitting element (LD) is connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) is connected to one of the power supply lines (PL) of FIG. 1 and receives a first power supply voltage. The second power supply voltage node (VSSN) is connected to another of the power supply lines (PL) of FIG. 1 and receives a second power supply voltage. The first power supply voltage may have a higher voltage level than the second power supply voltage.

[0072] A light emitting element (LD) is connected between an anode electrode (AE) and a cathode electrode (CE). The anode electrode (AE) may be connected to a first power supply voltage node (VDDN) through a sub-pixel circuit (SPC). For example, the anode electrode (AE) may be connected to the first power supply voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC). The cathode electrode (CE) may be connected to a second power supply voltage node (VSSN). The light emitting element (LD) is configured to emit light according to a current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0073] The sub-pixel circuit (SPC) may be connected to the ith gate line (GLi) among the first to mth gate lines (GL1 to GLm) of FIG. 1 and to the jth data line (DLj) among the first to nth data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the ith gate line (GLi), the sub-pixel circuit (SPC) controls the light-emitting element (LD) to emit light according to a data signal received through the jth data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the light-emitting element (LD) in response to pixel control signals received through the pixel control lines (PXCL).

[0074] For these operations, a sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0075] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Silicon Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0076] FIG. 3 is a schematic plan view showing an embodiment of the display panel of FIG. 1.

[0077] Referring to FIG. 3, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) displays an image through the display area (DA). The non-display area (NDA) is arranged around the display area (DA).

[0078] A display panel (DP) includes sub-pixels (SP) in a display area (DA). The sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). For example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on the embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0079] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL) (e.g., a single pixel). In FIG. 3, the pixel (PXL) is illustrated as including three sub-pixels (SP1 to SP3), but embodiments are not limited thereto. For example, the pixel (PXL) may include two sub-pixels. Hereinafter, for convenience of explanation, it is assumed that the pixel (PXL) includes first to third sub-pixels (SP1 to SP3).

[0080] Each of the first to third sub-pixels (SP1 to SP3) can generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. Hereinafter, for the sake of clarity and concise explanation, it is assumed that the first sub-pixel (SP1) is configured to generate red color light, the second sub-pixel (SP2) is configured to generate green color light, and the third sub-pixel (SP3) generates blue color light.

[0081] Each of the first to third sub-pixels (SP1 to SP3) may include at least one light-emitting element configured to generate light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of the same color. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate blue light. In other embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of different colors. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate red light, green light, and blue light, respectively.

[0082] As a display panel (DP), a self-luminous display panel such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements, can be used.

[0083] Components for controlling sub-pixels (SP) may be placed in the non-display area (NDA). Wires connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1, may be placed in the non-display area (NDA).

[0084] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) may be disposed in the non-display area (NDA). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120) may be implemented as an integrated circuit that is separate from the display panel (DP) together with the data driver (130), the voltage generator (140), and the controller (150).

[0085] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have the shape of a closed loop including straight and / or curved edges. For example, the display area (DA) may have shapes such as a polygon, a circle, a semicircle, or an ellipse.

[0086] In some embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface. In some embodiments, the display panel (DP) may be bendable, foldable, or rollable. In such cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0087] FIG. 4 is a schematic cross-sectional view showing an embodiment of the display panel of FIG. 3.

[0088] Referring to FIG. 4, the display panel (DP) may include a substrate (SUB), and a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (LFL) that are sequentially laminated in a third direction (DR3) intersecting the first and second directions (DR1, DR2) on the substrate (SUB).

[0089] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. As another example, the substrate (SUB) may include a polyimide (PI) substrate. As yet another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0090] In embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0091] A pixel circuit layer (PCL) is arranged on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns arranged between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, etc.

[0092] The circuit elements of the pixel circuit layer (PCL) may include sub-pixel circuits (SPC, see FIG. 2) of each of the sub-pixels (SP) of FIG. 3. For example, the circuit elements of the pixel circuit layer (PCL) may be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0093] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines necessary to drive the display element layer (DPL).

[0094] A display element layer (DPL) is arranged on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0095] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In embodiments, the light-converting patterns and the light-scattering patterns may be omitted.

[0096] The light function layer (LFL) may further include a color filter layer including color filters. The color filter may selectively transmit light of a specific wavelength (or color). In embodiments, the color filter layer may be omitted.

[0097] A window may be provided on a light-functional layer (LFL) to protect an exposed surface (or upper surface) of a display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded to the light-functional layer (LFL) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0098] FIG. 5 is a schematic cross-sectional view showing another embodiment of the display panel of FIG. 3.

[0099] Referring to FIG. 5, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light function layer (LFL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) are formed in the same or similar manner as the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) described with reference to FIG. 4. Hereinafter, overlapping descriptions are omitted.

[0100] An input sensing layer (ISL) can detect user input on the upper surface (or display surface) of a display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting external objects, such as a user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0101] FIG. 6 is a schematic plan view showing an embodiment of one of the pixels of FIG. 3.

[0102] Referring to FIG. 6, a pixel (PXL) may include first to third sub-pixels (SP1 to SP3). The first to third sub-pixels (SP1 to SP3) may be arranged in a first direction (DR1). However, the arrangement of the pixel (PXL) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1 to SP3) may be arranged in a zigzag shape.

[0103] First to third anode electrodes (AE1 to AE3) may be respectively disposed in the first to third sub-pixels (SP1 to SP3). The first anode electrode (AE1) may be provided as an anode electrode (AE, see FIG. 2) connected to a sub-pixel circuit (SPC, see FIG. 2) of the first sub-pixel (SP1). The second anode electrode (AE2) may be provided as an anode electrode (AE) connected to a sub-pixel circuit (SPC) of the second sub-pixel (SP2). The third anode electrode (AE3) may be provided as an anode electrode (AE) connected to a sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0104] The cathode electrode (CE) may be spaced apart from the first to third anode electrodes (AE1 to AE3). The cathode electrode (CE) may be arranged at the same height as the first to third anode electrodes (AE1 to AE3). The cathode electrode (CE) may be spaced apart from the first to third anode electrodes (AE1 to AE3) in a second direction (DR2). In embodiments, the cathode electrode (CE) may extend in the first direction (DR1) and may be used as a common electrode for the pixel (PXL) and other pixels adjacent to the pixel (PXL). For example, the cathode electrode (CE) may extend in the second direction (DR2) as well as the first direction (DR1) and may be used as a common electrode for all of the sub-pixels (SP) of FIG. 3. For example, the cathode electrode (CE) may have various shapes. In embodiments, the first to third anode electrodes (AE1 to AE3) and the cathode electrode (CE) may include the same conductive material.

[0105] First to third light-emitting elements (LD1 to LD3) may be arranged on first to third anode electrodes (AE1 to AE3) and a cathode electrode (CE). The first light-emitting element (LD1) may be electrically connected to the first anode electrode (AE1) and the cathode electrode (CE). The first light-emitting element (LD1) may be provided as a light-emitting element (LD, see FIG. 2) connected to a sub-pixel circuit (SPC) of a first sub-pixel (SP1). The second light-emitting element (LD2) may be electrically connected to the second anode electrode (AE2) and the cathode electrode (CE). The second light-emitting element (LD2) may be provided as a light-emitting element (LD) connected to a sub-pixel circuit (SPC) of a second sub-pixel (SP2). The third light-emitting element (LD3) may be electrically connected to the third anode electrode (AE3) and the cathode electrode (CE). The third light-emitting element (LD3) may be provided as a light-emitting element (LD) connected to the sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0106] The first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3) may be inorganic light-emitting diodes containing inorganic light-emitting materials. However, embodiments are not limited thereto, and for example, organic light-emitting diodes may be used.

[0107] Figure 7 is a schematic cross-sectional view along line II' of Figure 6.

[0108] Referring to FIGS. 6 and 7, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0109] In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1 to SP3) are provided, respectively.

[0110] As described with reference to FIG. 2, each of the first to third sub-pixels (SP1 to SP3) may include a sub-pixel circuit (SPC, see FIG. 2) including transistors and one or more capacitors. Semiconductor patterns and conductive patterns of the pixel circuit layer (PCL) may function as transistors and capacitors of the sub-pixel circuit (SPC). For example, the conductive patterns of the pixel circuit layer (PCL) may further function as wirings, for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1.

[0111] The pixel circuit layer (PCL) may include a buffer layer (BFL), an interlayer dielectric layer (ILD), a first passivation layer (PSV1), and a second passivation layer (PSV2).

[0112] A buffer layer (BFL) may be disposed on one surface of a substrate (SUB). The buffer layer (BFL) may prevent impurities from diffusing into circuit elements and wirings included in a pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer including an inorganic material. In embodiments, the buffer layer (BFL) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The buffer layer (BFL) may be provided as a single layer or multiple layers. When the buffer layer (BFL) is provided as multiple layers, each layer may be formed of the same material or different materials.

[0113] In embodiments, one or more barrier layers may be disposed between the substrate (SUB) and the buffer layer (BFL). Each of the barrier layers may comprise polyimide.

[0114] A transistor (T_SP1) may be placed on the buffer layer (BFL). The transistor (T_SP1) may be any one of the transistors of the sub-pixel circuit (SPC) included in the first sub-pixel (SP1). For example, the transistor (T_SP1) may be understood as a transistor connected to the first anode electrode (AE1) among the transistors of the sub-pixel circuit (SPC).

[0115] The transistor (T_SP1) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (ET1), and a second terminal (ET2). The first terminal (ET1) may be either a source electrode or a drain electrode, and the second terminal (ET2) may be the other of the source electrode and the drain electrode. For example, the first terminal (ET1) may be a source electrode, and the second terminal (ET2) may be a drain electrode.

[0116] A semiconductor pattern (SCP) may be disposed on a buffer layer (BFL). The semiconductor pattern (SCP) may include a first contact region contacting a first terminal (ET1) and a second contact region contacting a second terminal (ET2). A region between the first contact region and the second contact region may be a channel region. The channel region may overlap with a gate electrode (GE) of the transistor (T_SP1). The channel region may be a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. For example, a p-type impurity may be used as the impurity, but embodiments are not limited thereto.

[0117] The semiconductor pattern (SCP) may include any one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a low temperature poly silicon semiconductor, and an oxide semiconductor.

[0118] Interlayer insulating layers (ILDs) may be sequentially stacked on a semiconductor pattern (SCP). The interlayer insulating layers (ILDs) may be inorganic insulating layers including an inorganic material. For example, each of the interlayer insulating layers (ILDs) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the interlayer insulating layers (ILDs) are not limited thereto. For example, any one of the interlayer insulating layers (ILDs) may include an organic insulating layer including an organic material.

[0119] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers (ILDs). For example, the interlayer insulating layers (ILDs) can include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) can be disposed between the semiconductor pattern (SCP) and the gate electrode (GE) such that the gate electrode (GE) is spaced apart from the semiconductor pattern (SCP). In embodiments, the gate insulating layer (GI) can be provided (e.g., provided entirely) on the semiconductor pattern (SCP) and the buffer layer (BFL) to cover the semiconductor pattern (SCP) and the buffer layer (BFL). As the number of layers required for forming the conductive patterns and / or semiconductor patterns increases, the number of interlayer insulating layers (ILDs) can increase.

[0120] A gate electrode (GE) is disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap a channel region of a semiconductor pattern (SCP). In embodiments, the gate electrode (GE) may be provided as a single layer including at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In embodiments, the gate electrode (GE) may be provided as a multilayer including at least one material selected from the group consisting of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag), which are low-resistance materials.

[0121] The first and second terminals (ET1, ET2) are disposed on interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) can contact a semiconductor pattern (SCP) through contact holes penetrating the interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) can contact first and second contact areas of the semiconductor pattern (SCP), respectively. Each of the first and second terminals (ET1, ET2) can include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0122] Although the first and second terminals (ET1, ET2) are illustrated as separate electrodes electrically connected to the semiconductor pattern (SCP), embodiments are not limited thereto. In embodiments, the first terminal (ET1) may be a first contact region adjacent to one side of a channel region of the semiconductor pattern (SCP), and the second terminal (ET2) may be a second contact region adjacent to the other side of the channel region. In this case, the first terminal (ET1) may be electrically connected to the light emitting element (LD) via a connecting means, such as a bridge electrode, disposed on at least one of the interlayer insulating layers (ILD).

[0123] In embodiments, the transistor (T_SP1) may be formed of a low-temperature polysilicon transistor. However, embodiments are not limited thereto. For example, the transistor (T_SP1) may also be formed of an oxide semiconductor transistor. In embodiments, the sub-pixel circuit of the first sub-pixel (SP1) may include transistors of different types. For example, the transistor (T_SP1) may be formed of a low-temperature polysilicon transistor, and the other transistors of the first sub-pixel (SP1) may be formed of oxide semiconductor transistors. In this case, the oxide semiconductor of the oxide semiconductor transistor may be disposed on any one of the interlayer insulating layers (ILD) other than the insulating layer on which the semiconductor pattern (SCP) of the transistor (T_SP1) is disposed.

[0124] In the embodiments, the transistor (T_SP1) is described as an example of a transistor having a top gate structure, but the embodiments are not limited thereto. For example, the transistor (T_SP1) may be a transistor having a bottom gate structure. For example, the structure of the transistor (T_SP1) may be changed in various ways.

[0125] At least some of the various wirings of the display panel (DP) and / or display device (DD) may be further arranged on the interlayer insulating layers (ILD).

[0126] A first passivation layer (PSV1) may be disposed on the interlayer insulating layers (ILD) and the first and second terminals (ET1, ET2). The passivation layer may also be referred to as a protective layer or a via layer. The first passivation layer (PSV1) protects components disposed thereunder and may provide a flat upper surface.

[0127] A connection pattern (CP) may be arranged on the first passivation layer (PSV1). The connection pattern (CP) may penetrate the first passivation layer (PSV1) and be connected to the first terminal (ET1) of the transistor (T_SP1). The connection pattern (CP) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0128] At least some of the various wires of the display panel (DP) and / or the display device (DD) may be further arranged on the first passivation layer (PSV1).

[0129] A second passivation layer (PSV2) is disposed on the connection pattern (CP) and the first passivation layer (PSV1). The second passivation layer (PSV2) protects components disposed thereunder and can provide a flat upper surface.

[0130] Each of the first and second passivation layers (PSV1, PSV2) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The organic insulating layer may include, for example, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0131] The first and second passivation layers (PSV1, PSV2) may comprise the same material as one of the interlayer insulating layers (ILD), but embodiments are not limited thereto. Each of the first and second passivation layers (PSV1, PSV2) may be provided (or formed) as a single layer, but may also be provided (or formed) as multiple layers.

[0132] A display element layer (DPL) may be disposed on the second passivation layer (PSV2). The display element layer (DPL) may include a first anode electrode (AE1), a cathode electrode (CE), first and second reflective electrodes (RFE1, RFE2), a first light-emitting element (LD1), an overcoat layer (OCL), a third passivation layer (PSV3), and a capping layer (CPL).

[0133] A first anode electrode (AE1) and a cathode electrode (CE) are disposed on a pixel circuit layer (PCL). For example, the first anode electrode (AE1) and the cathode electrode (CE) may be disposed on a second passivation layer (PSV2).

[0134] The first anode electrode (AE1) can be electrically connected to the connection pattern (CP) through a contact hole penetrating the second passivation layer (PSV2). For example, the first anode electrode (AE1) can be electrically connected to the first transistor (T_SP1).

[0135] The cathode electrode (CE) may be spaced apart from the first anode electrode (AE1) in the second direction (DR2). The cathode electrode (CE) may be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) may be transmitted to the cathode electrode (CE).

[0136] A first reflective electrode (RFE1) may be disposed on the first anode electrode (AE1). For example, the first reflective electrode (RFE1) may be disposed on one side of the first anode electrode (AE1).

[0137] A second reflective electrode (RFE2) may be disposed on the cathode electrode (CE). For example, the second reflective electrode (RFE2) may be disposed on one side of the cathode electrode (CE).

[0138] The first and second reflective electrodes (RFE1, RFE2) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1) may be improved. The first and second reflective electrodes (RFE1, RFE2) may include the same reflective conductive material. In embodiments, the first and second reflective electrodes (RFE1, RFE2) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0139] An overcoat layer (OCL) may be disposed within a first opening (OP1) in which the first and second reflective electrodes (RFE1, RFE2) and the first light-emitting element (LD1) are disposed. The overcoat layer (OCL) may partially cover the first and second reflective electrodes (RFE1, RFE2).

[0140] The first light-emitting element (LD1) may be disposed on an overcoat layer (OCL). The overcoat layer (OCL) may fix the first light-emitting element (LD1) so that it does not move.

[0141] For example, the overcoat layer (OCL) can protect the components disposed thereunder from foreign substances such as dust, moisture, etc. For example, the overcoat layer (OCL) can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) can include epoxy, but embodiments are not limited thereto.

[0142] The first light-emitting element (LD1) includes first and second element electrodes (BDE1, BDE2) facing in the same direction (e.g., opposite to the third direction (DR3)).

[0143] The first and second element electrodes (BDE1, BDE2) may be spaced apart from each other in the second direction (DR2). The first element electrode (BDE1) may be arranged adjacent to the first anode electrode (AE1), and the second element electrode (BDE2) may be arranged adjacent to the cathode electrode (CE).

[0144] The first and second element electrodes (BDE1, BDE2) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1) may be improved. The first and second element electrodes (BDE1, BDE2) may include the same reflective conductive material. In embodiments, the first and second element electrodes (BDE1, BDE2) may include at least one of aluminum (Al), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0145] The first element electrode (BDE1) may be formed along the side surfaces of the first light-emitting element (LD1) that are adjacent to the first anode electrode (AE1). For example, the first element electrode (BDE1) may be formed on a portion of the lower surface of the first light-emitting element (LD1) that is adjacent to the first anode electrode (AE1). The first element electrode (BDE1) may not be disposed on the upper surface (LTS) of the first light-emitting element (LD1). For example, the first element electrode (BDE1) may have a hook shape.

[0146] The first element electrode (BDE1) may be electrically connected to a first semiconductor layer included in the first light-emitting element (LD1). The first semiconductor layer may include, for example, at least one p-type semiconductor layer. For example, the first semiconductor layer may include at least one semiconductor material selected from the group consisting of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like. However, the material constituting the first semiconductor layer is not limited thereto, and various other materials may also constitute the first semiconductor layer. In one embodiment, the first semiconductor layer may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant).

[0147] The second element electrode (BDE2) may be formed along the side surfaces of the first light-emitting element (LD1) that are adjacent to the cathode electrode (CE). For example, the second element electrode (BDE2) may be formed on a portion of the lower surface of the first light-emitting element (LD1) that is adjacent to the cathode electrode (CE). The second element electrode (BDE2) may not be disposed on the upper surface (LTS) of the first light-emitting element (LD1). For example, the second element electrode (BDE2) may have a hook shape.

[0148] The second element electrode (BDE2) may be connected to a second semiconductor layer. The second semiconductor layer may include, for example, at least one n-type semiconductor layer. For example, the second semiconductor layer may include any one of a semiconductor material selected from the group consisting of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant), such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the second semiconductor layer is not limited thereto, and various other materials may also constitute the second semiconductor layer. In one embodiment, the second semiconductor layer may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant).

[0149] For example, the first light-emitting element (LD1) includes first and second protective electrodes (EPL1, EPL2) facing in the same direction (e.g., opposite to the third direction (DR3)).

[0150] The first and second protective electrodes (EPL1, EPL2) may be spaced apart from each other in the second direction (DR2). The first protective electrode (EPL1) may be arranged adjacent to the first anode electrode (AE1), and the second protective electrode (EPL2) may be arranged adjacent to the cathode electrode (CE).

[0151] The first protective electrode (EPL1) may be formed along the side surfaces of the first element electrode (BDE1) and the lower surface of the first element electrode (BDE1). For example, the first protective electrode (EPL1) may have a hook shape. The first element electrode (BDE1) may be arranged on the inner side of the first protective electrode (EPL1).

[0152] In embodiments, a first protective electrode (EPL1) may be placed on an exposed portion of the first element electrode (BDE1).

[0153] The second protective electrode (EPL2) may be formed along the side surfaces of the second element electrode (BDE2) and the lower surface of the second element electrode (BDE2). For example, the second protective electrode (EPL2) may have a hook shape. The second element electrode (BDE2) may be arranged on the inner side of the second protective electrode (EPL2).

[0154] In embodiments, the second protective electrode (EPL2) may be disposed on an exposed portion of the second element electrode (BDE2).

[0155] Since the first element electrode (BDE1) is disposed on the inner side of the first protective electrode (EPL1) and the second element electrode (BDE2) is disposed on the inner side of the second protective electrode (EPL2), the first and second protective electrodes (EPL1, EPL2) can protect the first and second element electrodes (BDE1, BDE2) from an external cleaning solution during the transfer process of the first light-emitting element (LD1). Accordingly, the first and second element electrodes (BDE1, BDE2) can be manufactured not only from materials that are not damaged by an external cleaning solution, such as gold (Au) and chromium (Cr), but also from materials such as titanium (Ti) and aluminum (Al).

[0156] Titanium (Ti) and aluminum (Al) may have higher reflectivity than gold (Au) and chromium (Cr). Accordingly, the first and second element electrodes (BDE1, BDE2) made of titanium (Ti) and aluminum (Al) reflect light of the first light-emitting element (LD1) emitted downward (in the opposite direction of the third direction (DR3)) upward (in the third direction (DR3)), so that the brightness of the display device (DD) may increase. For example, since titanium (Ti) and aluminum (Al) are cheaper than gold (Au), the manufacturing cost of the first light-emitting element (LD1) may be reduced.

[0157] In embodiments, as the first protective electrode (EPL1) disposed under the first element electrode (BDE1) is etched, a region (AR1) may be provided where the first element electrode (BDE1) and the first protective electrode (EPL1) do not contact each other. For example, the region (AR1) may be provided between the first element electrode (BDE1) and the overcoat layer (OCL). For example, a region may be provided where the second element electrode (BDE2) and the second protective electrode (EPL2) do not contact each other. A more detailed description thereof will be described later with reference to FIG. 19.

[0158] In embodiments, the first and second protective electrodes (EPL1, EPL2) may be disposed on the same display element layer (DPL) and may include the same conductive material. In embodiments, the first and second protective electrodes (EPL1, EPL2) may include a conductive metal oxide, such as indium zinc oxide (IZO). However, the material of the first and second protective electrodes (EPL1, EPL2) is not limited thereto.

[0159] The first transparent electrode (ITO1) can electrically connect the first reflective electrode (RFE1) and the first protective electrode (EPL1). Accordingly, the first element electrode (BDE1) can be electrically connected to the first anode electrode (AE1) via the first protective electrode (EPL1), the first transparent electrode (ITO1), and the first reflective electrode (RFE1).

[0160] The first transparent electrode (ITO1) can be disposed on an exposed portion of the first protective electrode (EPL1), an exposed portion of the overcoat layer (OCL), and an exposed portion of the first reflective electrode (RFE1).

[0161] The second transparent electrode (ITO2) can electrically connect the second reflective electrode (RFE2) and the second protective electrode (EPL2). Accordingly, the second element electrode (BDE2) can be electrically connected to the cathode electrode (CE) via the second protective electrode (EPL2), the second transparent electrode (ITO2), and the second reflective electrode (RFE2).

[0162] The second transparent electrode (ITO2) can be disposed on the exposed portion of the second protective electrode (EPL2), the exposed portion of the overcoat layer (OCL), and the exposed portion of the second reflective electrode (RFE2).

[0163] In embodiments, the first and second transparent electrodes (ITO1, ITO2) may be configured to be substantially transparent or translucent to satisfy a certain light transmittance. The first transparent electrode (ITO1) and the second transparent electrode (ITO2) may be disposed on the same display element layer (DPL) and may include the same transparent conductive material. In embodiments, the first and second transparent electrodes (ITO1, ITO2) may include at least one of various transparent conductive materials, such as indium tin oxide (ITO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the material of the first and second transparent electrodes (ITO1, ITO2) is not limited thereto.

[0164] In the cross-sectional view, the height (H1) of the first protective electrode (EPL1) may be smaller than the height (H2) of the first transparent electrode (ITO1). At this time, the height (H1) of the first protective electrode (EPL1) and the height (H2) of the first transparent electrode (ITO1) may be heights based on the overcoat layer (OCL) in the cross-sectional view. A more detailed description of the height (H1) of the first protective electrode (EPL1) and the height (H2) of the first transparent electrode (ITO1) will be described later with reference to FIG. 19.

[0165] A third passivation layer (PSV3) is disposed on the first and second transparent electrodes (ITO1, ITO2). The third passivation layer (PSV3) protects components disposed thereunder and can provide a flat upper surface. The third passivation layer (PSV3) may include the same material as either of the first and second passivation layers (PSV1, PSV2), but embodiments are not limited thereto.

[0166] In embodiments, the third passivation layer (PSV3) may not be disposed on the upper surface (LTS) of the first light-emitting element (LD1). The first light-emitting element (LD1) may protrude into the light-functional layer (LFL). The first light-emitting element (LD1) may be disposed at least partially within the second opening (OP2) of the bank (BNK). For example, the height of the upper surface (LTS) of the first light-emitting element (LD1) from the substrate (SUB) may be higher than the lowermost end (RBE) of the reflective layer (RFL). Accordingly, light emitted from the first light-emitting element (LD1) may be provided to the light-functional layer (LFL) at a relatively high rate.

[0167] A capping layer (CPL) is disposed on a third passivation layer (PSV3). The capping layer (CPL) can protect components under the capping layer (CPL), such as the first light-emitting element (LD1), from external moisture and humidity. In embodiments, the capping layer (CPL) may not be disposed on an upper surface of the first light-emitting element (LD1). In other embodiments, the capping layer (CPL) may cover (e.g., entirely cover) the first light-emitting element (LD1) and the third passivation layer (PSV3). The capping layer (CPL) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the material of the capping layer (CPL) is not limited thereto.

[0168] The pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1) have been described above. Each of the second and third sub-pixels (SP2, SP3) of FIG. 6 may also be formed in the same or similar manner as the first sub-pixel (SP1), unless otherwise described herein.

[0169] A light-functional layer (LFL) is disposed on a capping layer (CPL). The light-functional layer (LFL) may include a bank (BNK), a reflective layer (RFL), a fourth passivation layer (PSV4), a first light conversion pattern (CCP1), a low-refractive-index layer (LRL), and a color filter layer (CFL).

[0170] A bank (BNK) may be arranged on a capping layer (CPL). The bank (BNK) may have a second opening (OP2) overlapping a first opening (OP1). The bank (BNK) may be configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In embodiments, the bank (BNK) may include an organic material. For example, the bank (BNK) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0171] A reflective layer (RFL) may be disposed on the side surfaces of the bank (BNK) adjacent to the second opening (OP2). The reflective layer (RFL) may reflect incident light, thereby improving light emission efficiency. The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0172] On the capping layer (CPL), a fourth passivation layer (PSV4) is disposed within the second opening (OP2). The fourth passivation layer (PSV4) protects components disposed thereunder and can provide a flat upper surface. The fourth passivation layer (PSV4) may include the same material as any one of the first to third passivation layers (PSV1 to PSV3), but embodiments are not limited thereto.

[0173] On the fourth passivation layer (PSV4), a first light conversion pattern (CCP1) can be arranged within a second opening (OP2).

[0174] The first light conversion pattern (CCP1) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. For example, the color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0175] The first sub-pixel (SP1) may be a red sub-pixel. When the first light-emitting element (LD1) emits blue light, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. When the first light-emitting element (LD1) emits red light, the first light conversion pattern (CCP1) may include scattering particles. For example, the particles included in the first light conversion pattern (CCP1) may vary depending on the first light-emitting element (LD1).

[0176] A low-refractive-index layer (LRL) may be disposed on the bank (BNK), the reflective layer (RFL), and the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) may have a lower refractive index than the first light conversion pattern (CCP1). The first color filter (CF1) may have a higher refractive index than the low-refractive-index layer (LRL). However, embodiments are not limited thereto, and the first color filter (CF1) may have a refractive index that is lower than or equal to the low-refractive-index layer (LRL). The low-refractive-index layer (LRL) may refract or totally reflect light depending on an incident angle of the light. For example, the low-refractive-index layer (LRL) may provide light that has passed through the first light conversion pattern (CCP1) back to the first light conversion pattern (CCP1). Accordingly, the light conversion efficiency of the first light conversion pattern (CCP1) may be improved.

[0177] A color filter layer (CFL) may be disposed on a low refractive index layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and light blocking patterns (LBP). The first color filter (CF1) may overlap a first light conversion pattern (CCP1). The first color filter (CF1) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0178] Hereinafter, a method for manufacturing a display device (DD) according to an embodiment will be described with reference to FIGS. 8 to 19. Any content that may overlap with the above will be briefly described or not repeated.

[0179] Figure 8 is a schematic flowchart showing a method for manufacturing a display device according to an embodiment.

[0180] Fig. 9 is a schematic flowchart illustrating steps for manufacturing a display element layer according to an embodiment. Figs. 10 to 13 are schematic cross-sectional views of each process step according to Fig. 9. For convenience of explanation, Figs. 10 to 13 schematically illustrate areas corresponding to the cross-sectional structures described above with reference to Figs. 6 and 7.

[0181] Referring to FIG. 8, a method for manufacturing a display device (DD) according to an embodiment may include a step of manufacturing a pixel circuit layer (S100), a step of manufacturing a display element layer (S200), and a step of manufacturing a light conversion layer (S300).

[0182] Referring to FIGS. 7 and 8, in the step of manufacturing a pixel circuit layer (S100), a pixel circuit layer (PCL) can be placed on a substrate (SUB).

[0183] According to an embodiment, the conductive layer or insulating layer on the substrate (SUB) may be formed based on a typical process for manufacturing a semiconductor device. For example, the conductive layer or insulating layer on the substrate (SUB) may be formed by a photolithography process, may be etched by various methods (e.g., wet etching, dry etching, etc.), and may be deposited by various methods (e.g., sputtering, chemical vapor deposition, etc.). The embodiments are not limited to specific examples.

[0184] At step S100, a transistor (T_SP) can be patterned on a substrate (SUB), and a buffer layer (BFL), an interlayer insulating layer (ILD), a first passivation layer (PSV1), and a second passivation layer (PSV2) can be formed.

[0185] Referring to FIG. 9, the step of manufacturing a display element layer (S200) may include a step of patterning an anode electrode and a cathode electrode (S2100), a step of patterning a first reflective electrode and a second reflective electrode (S2200), a step of patterning an overcoat layer (S2300), a step of arranging a light-emitting element (S2400), a step of arranging a light-emitting element on a pixel circuit layer (S2500), and a step of patterning a first transparent electrode and a second transparent electrode (S2600).

[0186] Referring to FIGS. 9 and 10, in the step of patterning the anode electrodes and the cathode electrode (S2100), a first anode electrode (AE1) and a cathode electrode (CE) may be formed on the pixel circuit layer (PCL) (or substrate (SUB)). For example, in the step S2100, a second anode electrode and a third anode electrode may be formed.

[0187] In this step (S2100), when the first anode electrode (AE1) is formed, a contact hole penetrating the second passivation layer (PSV2) may be formed. Accordingly, the first anode electrode (AE1) may be electrically connected to the transistor (T_SP).

[0188] Referring to FIGS. 9 and 11, in the step of patterning the first reflective electrode and the second reflective electrode (S2200), the first reflective electrode (RFE1) may be formed on the first anode electrode (AE1), and the second reflective electrode (RFE2) may be formed on the cathode electrode (CE).

[0189] For example, a first reflective electrode (RFE1) may be formed on one side of a first anode electrode (AE1), and a second reflective electrode (RFE2) may be formed on one side of a cathode electrode (CE). The first reflective electrode (RFE1) and the second reflective electrode (RFE2) may be spaced apart from each other in a second direction (DR2).

[0190] Referring to FIGS. 9 and 12, in the step of patterning the overcoat layer (S2300), an overcoat layer (OCL) can be formed on the first reflective electrode (RFE1) and the second reflective electrode (RFE2).

[0191] According to an embodiment, the overcoat layer (OCL) may be formed on the pixel circuit layer (PCL) (or substrate (SUB)) through a process such as deposition. For example, after forming the overcoat layer (OCL), an additional etching process may be performed on the overcoat layer (OCL). A more detailed description thereof will be provided below with reference to FIG. 19.

[0192] The overcoat layer (OCL) may be arranged to overlap a portion of the first anode electrode (AE1) and a portion of the cathode electrode (CE). For example, the overcoat layer (OCL) may be arranged to include a region (AR) that does not overlap both the first anode electrode (AE1) and the cathode electrode (CE). In the region (AR2), the overcoat layer (OCL) may be in contact with the pixel circuit layer (PCL). For example, in the region (AR2), the overcoat layer (OCL) may be in contact with the second passivation layer (PSV2).

[0193] Referring to FIGS. 9 and 13, in the step (S2400) of placing a light-emitting element on a pixel circuit layer, a first light-emitting element (LD1) including first and second element electrodes (BDE1, BDE2) and a protective layer (EPL) may be placed on the pixel circuit layer (PCL).

[0194] In an embodiment, a first light-emitting element (LD1) may be disposed on an overcoat layer (OCL). The first light-emitting element (LD1) may include first and second element electrodes (BDE1, BDE2) and a protective layer (EPL).

[0195] The first light-emitting element (LD1) may be arranged such that the first element electrode (BDE1) is adjacent to the first anode electrode (AE1) and the second element electrode (BDE2) is adjacent to the cathode electrode (CE). The first and second element electrodes (BDE1, BDE2) may be spaced apart from each other along the second direction (DR2).

[0196] The protective layer (EPL) may be formed along the side surfaces of the first light-emitting element (LD1) and the lower surface of the first light-emitting element (LD1), excluding the upper surface (LTS) of the first light-emitting element (LD1). For example, the protective layer (EPL) may be arranged to surround the first and second element electrodes (BDE1, BDE2). Accordingly, the protective layer (EPL) may be arranged in an area (AR3) where the first and second element electrodes (BDE1, BDE2) are spaced apart from each other along the second direction (DR2).

[0197] The protective layer (EPL) may be in contact with the overcoat layer (OCL) in a region overlapping the first and second element electrodes (BDE1, BDE2), and may be spaced apart from the overcoat layer (OCL) in a region (AR3) where the first and second element electrodes (BDE1, BDE2) are spaced apart from each other along the second direction (DR2).

[0198] The material of the protective layer (EPL) may include the same material as the material included in the first and second protective electrodes (EPL1, EPL2) (see FIG. 7).

[0199] Fig. 14 is a schematic flowchart illustrating steps for manufacturing first and second transparent electrodes according to an embodiment of the present invention. Figs. 15 to 19 are schematic cross-sectional views of each process step according to Fig. 14. For convenience of explanation, Figs. 15 to 19 schematically illustrate areas corresponding to the cross-sectional structures described above with reference to Figs. 6 and 7.

[0200] Referring to FIGS. 9 and 14, the step of patterning the first transparent electrode and the second transparent electrode (S2500) may include a step of disposing a transparent electrode layer (S2510), a step of patterning a photoresist layer (S2520), a step of performing a first etching process (S2530), a step of removing the photoresist layer (S2540), a heat treatment step (S2550), and a step of performing a second etching process (S2560).

[0201] Referring to FIGS. 14 and 15, in the step of placing a transparent electrode layer (S2510), a transparent electrode layer (ITO) can be placed on the first anode electrode (AE1), the cathode electrode (CE), and the first light-emitting element (LD1).

[0202] For example, a transparent electrode layer (ITO) may be disposed on an exposed upper surface of a first anode electrode (AE), an exposed portion of a first reflective electrode (RFE1), an exposed portion of an overcoat layer (OCL), an exposed protective layer (EPL), an upper surface (LTS) of a first light-emitting element (LD1), an exposed portion of a second reflective electrode (RFE2), and an exposed upper surface of a cathode electrode (CE).

[0203] In embodiments, a transparent electrode layer (ITO) may be disposed on the first anode electrode (AE1), the cathode electrode (CE), and the first light-emitting element (LD1) through a deposition process.

[0204] The transparent electrode layer (ITO) may include the same material as the material included in the first and second transparent electrodes (ITO1, ITO2) (see FIG. 7).

[0205] Referring to FIGS. 14 and 16, in the step of patterning the photoresist layer (S2520), the photoresist layer (PR) may be patterned on the transparent electrode layer (ITO). For example, the photoresist layer (PR) may be patterned in an area (AR3) where the protective layer (EPL) is spaced apart from the overcoat layer (OCL).

[0206] The area of ​​the photoresist layer (PR) patterned on the transparent electrode layer (ITO) can overlap with the area of ​​the first transparent electrode (ITO1) (see FIG. 7) to be manufactured and the area of ​​the second transparent electrode (ITO2) (see FIG. 7).

[0207] Referring to FIGS. 14 and 17, in the step (S2530) of performing the first etching process, the transparent electrode layer (ITO) may be etched using the photoresist layer (PR) as an etching mask to provide a first transparent electrode (ITO1) and a second transparent electrode (ITO2). For example, the protective layer (EPL) may also be etched along with the transparent electrode layer (ITO) according to the pattern of the photoresist layer (PR).

[0208] In an embodiment, the transparent electrode layer (ITO) and the protective layer (EPL) can be etched based on a wet etching process.

[0209] Referring to FIGS. 14 and 18, in the step of removing the photoresist layer (S2540), the photoresist layer (PR) can be removed. For example, after the first and second transparent electrodes (ITO1, ITO2) are manufactured, the photoresist layer (PR) can be removed.

[0210] As the photoresist layer (PR) is removed, an area (AR4) where the protective layer (EPL) and the overcoat layer (OCL) are separated can be provided.

[0211] For example, after removing the photoresist layer (PR), a heat treatment step (S2550) may be performed. In step S2550, the first and second transparent electrodes (ITO1, ITO2) may be crystallized. The heat treatment temperature may be determined within a range in which the first and second transparent electrodes (ITO1, ITO2) are crystallized and the protective layer (EPL) is not crystallized. For example, even if the heat treatment is performed, the protective layer (EPL) may not be crystallized and may maintain an amorphous characteristic.

[0212] Accordingly, even if a secondary etching process is performed in the subsequent S2560 step, the crystallized first and second transparent electrodes (ITO1, ITO2) are not etched, and only the protective layer (EPL) can be etched.

[0213] Referring to FIGS. 14, 18, and 19, in the step (S2560) of performing the secondary etching process, the protective layer (EPL) can be etched except for the portion surrounded by the heat-treated first and second transparent electrodes (ITO1, ITO2).

[0214] More specifically, the protective layer (EPL) may be etched in an area (AR3) where the protective layer (EPL) is exposed and spaced apart from the overcoat layer (OCL) to provide a first protective electrode (EPL1) and a second protective electrode (EPL2).

[0215] For example, as the protective layer (EPL) is etched in the region (AR4), a region (AR1) may be provided where the first element electrode (BDE1) and the first protective electrode (EPL1) do not contact each other. Similarly, a region may be provided where the second element electrode (BDE2) and the second protective electrode (EPL2) do not contact each other.

[0216] Since the non-heat-treated protective layer (EPL) is etched in step S2560 and the heat-treated first and second transparent electrodes (ITO1, ITO2) are not etched, the height (H1) of the first protective electrode (EPL1) may be smaller than the height (H2) of the first transparent electrode (ITO1) in the cross-section. At this time, the height (H1) of the first protective electrode (EPL1) and the height (H2) of the first transparent electrode (ITO1) may be the heights based on the overcoat layer (OCL) in the cross-section.

[0217] FIG. 20 is a block diagram showing an embodiment of a display system or electronic device.

[0218] Referring to FIG. 20, the display system (1000) (or electronic device) may include a processor (1100) and a display device (1200).

[0219] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor (1100) can be connected to other components of the display system (1000) via a bus system and control them.

[0220] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be formed similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0221] The display system (1000) (or electronic device) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. In addition, the display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0222] Figures 21 to 24 are schematic perspective views showing application examples of the display system of Figure 20.

[0223] Referring to FIG. 21, the display system (1000) of FIG. 20 can be applied to a smart watch (2000) including a display portion (2100) and a strap portion (2200).

[0224] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0225] Referring to FIG. 22, the display system (1000) of FIG. 20 may be applied to an automotive display system (3000). Here, the automotive display system (3000) may include a computing system provided inside and / or outside a vehicle to provide image data.

[0226] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear-seat display (3600) provided in a vehicle.

[0227] Referring to FIG. 23, the display system (1000) of FIG. 20 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0228] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0229] The frame (4100) may include a battery, a touch pad, a microphone, a camera, etc. For example, the frame (4100) may include a projector that outputs light, a processor that controls light signals, etc.

[0230] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or the like.

[0231] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). At this time, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0232] Referring to FIG. 24, the display system (1000) of FIG. 20 can be applied to a head-mounted display device (5000).

[0233] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0234] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in the form of eyeglass frames, helmets, etc.

[0235] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0236] In other embodiments, the display system (1000) illustrated in FIG. 16 may be applied to a mobile phone, a smartphone, a portable computer, a tablet personal computer (PC), a watch phone, a portable multimedia player (PMP), a navigation system, an ultra mobile computer (UMPC), a virtual reality device, a mixed reality device, and an augmented reality device.

[0237] In concluding this detailed description, it will be appreciated that those skilled in the art will appreciate that numerous variations and modifications can be made to the embodiments without significantly departing from the principles, spirit, and scope of the disclosure. Accordingly, the disclosed embodiments are used solely for general and illustrative purposes, not for purposes of limitation.

Claims

1. Substrate; and Including a display element layer disposed on the above substrate, The above display element layer is, Anode electrode and cathode electrode; A first reflective electrode disposed on the anode electrode; A second reflective electrode disposed on the cathode electrode; A light emitting element comprising a first protective electrode, a second protective electrode, a first element electrode disposed on the inner side of the first protective electrode, and a second element electrode disposed on the inner side of the second protective electrode; A first transparent electrode electrically connecting the first reflective electrode and the first protective electrode; and A display device including a second transparent electrode electrically connecting the second reflective electrode and the second protective electrode.

2. In paragraph 1, The first element electrode is formed on the side surfaces of the light-emitting element adjacent to the anode electrode and on the lower surface of the light-emitting element adjacent to the anode electrode, A display device in which the second element electrode is formed on the side surfaces of the light-emitting element adjacent to the cathode electrode and on the lower surface of the light-emitting element adjacent to the cathode electrode.

3. In paragraph 1, A display device in which the first element electrode and the second element electrode have a bracket shape.

4. In paragraph 1, The first protective electrode is formed along the side surfaces of the first element electrode and the lower surface of the first element electrode, A display device in which the second protective electrode is formed along the side surfaces of the second element electrode and the lower surface of the second element electrode.

5. In paragraph 1, A display device in which the first protective electrode and the second protective electrode have a bracket shape.

6. In paragraph 1, The first element electrode and the second element electrode include the same reflective conductive material, A display device wherein the first protective electrode and the second protective electrode include the same conductive material.

7. In paragraph 6, The first element electrode and the second element electrode include at least one of aluminum and titanium, A display device wherein the first protective electrode and the second protective electrode include indium zinc oxide.

8. In paragraph 7, A display device wherein the first transparent electrode and the second transparent electrode include the same transparent conductive material.

9. In paragraph 1, The display element layer further includes an overcoat layer that partially covers the first reflective electrode and the second reflective electrode, The light emitting element is disposed on the overcoat layer, In the cross-section, the height of the first protective electrode is smaller than the height of the first transparent electrode, A display device in which the height of the first protective electrode and the height of the first transparent electrode are heights based on the overcoat layer in a cross-section.

10. In paragraph 1, The display element layer further includes an overcoat layer that partially covers the first reflective electrode and the second reflective electrode, The light emitting element is disposed on the overcoat layer, A display device in which, on a cross-section, an area is provided below the first element electrode that does not contact the first protective electrode.

11. A step of manufacturing a pixel circuit layer arranged on a substrate; and A step of manufacturing a display element layer on the pixel circuit layer; including; The step of manufacturing the above display element layer is: A step of patterning an anode electrode and a cathode electrode on the pixel circuit layer; A step of patterning a first reflective electrode electrically connected to the anode electrode and a second reflective electrode electrically connected to the cathode electrode; A step of patterning an overcoat layer on the first reflective electrode and the second reflective electrode; and A step of arranging a light-emitting element including a protective layer, a first element electrode, and a second element electrode on the pixel circuit layer, A method for manufacturing a display device, wherein the protective layer is formed along the side surfaces of the light-emitting element and the lower surface of the light-emitting element, and is arranged to surround the first element electrode and the second element electrode.

12. In paragraph 11, The step of manufacturing the above display element layer is: A method for manufacturing a display device further comprising the step of patterning a transparent electrode layer on the anode electrode, the first reflective electrode, the cathode electrode, the second reflective electrode, the overcoat layer, and the light-emitting element.

13. In paragraph 12, The step of manufacturing the above display element layer is: A method for manufacturing a display device, further comprising the step of patterning a photoresist layer on the transparent electrode layer.

14. In paragraph 13, The step of manufacturing the above display element layer is: A step of etching the transparent electrode layer and the protective layer using the photoresist layer as an etching mask; A step in which the etched transparent electrode layer is provided as a first transparent electrode and a second transparent electrode; and A method for manufacturing a display device further comprising a step of removing the photoresist layer.

15. In paragraph 14, The step of manufacturing the above display element layer is: Further comprising a step of heat treating the above display element layer, A method for manufacturing a display device, wherein the heat treatment temperature is set within a range in which the first and second transparent electrodes are crystallized and the protective layer is not crystallized.

16. In paragraph 15, The step of manufacturing the above display element layer is: A step of etching the protective layer except for the portion surrounded by the first and second transparent electrodes subjected to heat treatment; and A method for manufacturing a display device further comprising a step of providing the etched protective layer as a first protective electrode and a second protective electrode.

17. In paragraph 16, A method for manufacturing a display device, wherein the first protective electrode and the second protective electrode have a bracket shape.

18. In paragraph 17, The first element electrode and the second element electrode include the same reflective conductive material, A method for manufacturing a display device, wherein the first protective electrode and the second protective electrode include the same conductive material.

19. In paragraph 18, The first element electrode and the second element electrode include at least one of aluminum and titanium, The first protective electrode and the second protective electrode comprise indium zinc oxide, A method for manufacturing a display device, wherein the first transparent electrode and the second transparent electrode include the same transparent conductive material.

20. A display device including a display element layer disposed on a substrate, The above display element layer is, Anode electrode and cathode electrode; A first reflective electrode disposed on the anode electrode; A second reflective electrode disposed on the cathode electrode; A light emitting element comprising a first protective electrode, a second protective electrode, a first element electrode disposed on the inner side of the first protective electrode, and a second element electrode disposed on the inner side of the second protective electrode; A first transparent electrode electrically connecting the first reflective electrode and the first protective electrode; and An electronic device comprising a second transparent electrode electrically connecting the second reflective electrode and the second protective electrode.

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