Transceiver for compensating local oscillator leakage signal and electronic device including same

Abstract

In embodiments, a radio frequency (RF) transceiver is provided. The RF transceiver may comprise: a transmission processing circuit including a mixer; and a phase locked loop (PLL) circuit. The PLL circuit may include: a voltage controlled oscillator (VCO) configured to provide a local oscillator (LO) frequency to the mixer on the basis of a comparison result of a reference clock signal and a feedback signal; and a frequency division circuit configured to provide the feedback signal on the basis of a signal from the VCO. The RF transceiver may include an additional frequency division circuit and a control circuit configured to activate the additional frequency division circuit on the basis of a control signal of a processor. The feedback signal may be generated from a signal of the VCO using only the frequency division circuit among the frequency division circuit and the additional frequency division circuit before the additional frequency division circuit is activated.

Description

Transmitter and receiver for compensating for local oscillator leakage signal and electronic device including same

[0001] The following descriptions relate to a transmitter / receiver and an electronic device including the same for compensating for LO (local oscillator) leakage signals.

[0002] An electronic device can transmit a signal. The electronic device can perform upconversion to transmit the signal. The electronic device can receive a signal. The electronic device can perform downconversion to receive the signal. The electronic device can include a mixer and an oscillator for upconversion or downconversion.

[0003] The above information may be provided as background art to aid in understanding the present disclosure. No claim or determination is made as to whether any of the above is applicable as prior art related to the present disclosure.

[0004] In embodiments of the present disclosure, a radio frequency (RF) transceiver is provided. The RF transceiver may include a transmit processing circuit including a mixer; and a phase locked loop (PLL) circuit. The PLL circuit may include a voltage controlled oscillator (VCO) configured to provide a local oscillator (LO) frequency to the mixer based on a comparison result of a reference clock signal and a feedback signal; and a frequency dividing circuit configured to provide the feedback signal based on a signal from the VCO. The RF transceiver may include an additional frequency dividing circuit; and a control circuit configured to activate the additional frequency dividing circuit based on a control signal from a processor. The feedback signal may be generated from a signal of the VCO using only the frequency dividing circuit among the frequency dividing circuit and the additional frequency dividing circuit before the additional frequency dividing circuit is activated. The above feedback signal can be generated from the signal of the VCO using the frequency dividing circuit and the activated additional frequency dividing circuit after the additional frequency dividing circuit is activated.

[0005] In embodiments of the present disclosure, an electronic device is provided. The electronic device may include a processor; a radio frequency (RF) transceiver; a radio frequency front end (RFFE) circuit connected to the RF transceiver; and an antenna connected to the RFFE circuit. The RF transceiver may include a transmit processing circuit including a mixer, a phase locked loop (PLL) circuit including a voltage controlled oscillator (VCO) configured to provide a local oscillator (LO) frequency to the mixer based on a comparison result of a reference clock signal and a feedback signal, and a frequency dividing circuit configured to provide the feedback signal based on a signal from the VCO; and an additional frequency dividing circuit. The feedback signal may be generated from a signal of the VCO using only the frequency dividing circuit among the frequency dividing circuit and the additional frequency dividing circuit before the additional frequency dividing circuit is activated. The above feedback signal can be generated from the signal of the VCO using the frequency dividing circuit and the activated additional frequency dividing circuit after the additional frequency dividing circuit is activated.

[0006] In embodiments of the present disclosure, an electronic device is provided. The electronic device may include a processor including a processing circuit; a radio frequency (RF) transceiver including a local oscillator (LO) and an LO leakage detection circuit; a radio frequency front end (RFFE) circuit including a coupler and connected to the RF transceiver; and an antenna connected to the RFFE circuit. The RF transceiver may be configured to, in response to a control signal received from the processor, connect the LO leakage detection circuit to a feedback port electrically connected to the coupler of the RFFE circuit, obtain an LO leakage component from a feedback signal from the feedback port through the LO leakage detection circuit, and apply an offset corresponding to the LO leakage component to a digital-to-analog converter (DAC) of the RF transceiver. The control signal may be transmitted when a frequency domain of a transmission signal satisfies a specified condition.

[0007] Figure 1 is a block diagram of an electronic device within a network environment.

[0008] Figure 2 illustrates an example of an electronic device including an RF (radio frequency) transceiver.

[0009] Figure 3 shows an example of an RF transceiver including a local oscillator (LO) leakage detection circuit.

[0010] Figure 4 shows an example of an LO leakage detection circuit.

[0011] Figure 5 shows an example of control of the gain and phase of a transmission signal of an RF transceiver.

[0012] Figure 6 shows an example of functional blocks of a processor for frequency control.

[0013] Figure 7a shows an example of functional blocks of an RF transceiver for frequency control.

[0014] Fig. 7b shows an example of frequency control using an oscillator circuit and an additional frequency divider circuit.

[0015] The terms used in this disclosure are used only to describe specific embodiments and may not be intended to limit the scope of other embodiments. The singular expression may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by those of ordinary skill in the art described in this disclosure. Terms defined in general dictionaries among the terms used in this disclosure may be interpreted as having the same or similar meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined in this disclosure. In some cases, even if a term is defined in this disclosure, it cannot be interpreted to exclude embodiments of the present disclosure.

[0016] The various embodiments of the present disclosure described below illustrate a hardware-based approach as an example. However, since the various embodiments of the present disclosure include techniques utilizing both hardware and software, the various embodiments of the present disclosure do not exclude a software-based approach.

[0017] Terms referring to parts of electronic devices used in the following description (e.g., communication module, wireless communication module, substrate, PCB (printed circuit board), FPCB (flexible PCB), module, antenna, antenna element, circuit, processor, chip, component, device), terms referring to RF-related parts (FEM (front end module0), PAM (power amplifier module), FEMid (FEM including duplexer), PAMid (power amplifier module including duplexer), LPAMid (low noise amplifier PAM including duplexer), RFFE (radio frequency front end)), RFIC (radio frequency integrated circuit)), terms referring to signals (e.g., signal, component, information, data, message), terms referring to data (e.g., information, data, value), terms referring to resources (e.g., symbol, slot, subframe, radio frame, subcarrier, RE (resource element), RB (resource block), BWP (bandwidth part), occasion), terms referring to circuits (e.g., PCB, FPCB, signal line, feeding line, data line, RF signal line, antenna line, signal path, RF path, RF module, RF circuit, splitter, divider, coupler, or combiner, etc. are examples for convenience of explanation. Therefore, the present disclosure is not limited to the terms described below, and other terms having equivalent technical meanings may be used. In addition, '... part', '... device', '... object', or '...The term 'body' may mean at least one geometric structure or a unit that processes a function.

[0018] In addition, in the present disclosure, expressions such as "more than" or "less than" may be used to determine whether a specific condition is satisfied or fulfilled, but this is merely a description for expressing an example and does not exclude descriptions such as "more than" or "less than." A condition described as "more than" may be replaced with "more than," a condition described as "less than" may be replaced with "less than," and a condition described as "more than and less than" may be replaced with "more than and less than." In addition, hereinafter, "A" to "B" mean at least one of elements from A (including A) to B (including B). hereinafter, "C" and / or "D" mean at least one of "C" or "D," that is, including {"C", "D", "C" and "D"}.

[0019] Figure 1 is a block diagram of an electronic device within a network environment.

[0020] Referring to FIG. 1, in a network environment (100), an electronic device (101) may communicate with an electronic device (102) via a first network (198) (e.g., a short-range wireless communication network), or may communicate with at least one of an electronic device (104) or a server (108) via a second network (199) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (101) may communicate with the electronic device (104) via the server (108). According to one embodiment, the electronic device (101) may include a processor (120), a memory (130), an input module (150), an audio output module (155), a display module (160), an audio module (170), a sensor module (176), an interface (177), a connection terminal (178), a haptic module (179), a camera module (180), a power management module (188), a battery (189), a communication module (190), a subscriber identification module (196), or an antenna module (197). In some embodiments, the electronic device (101) may omit at least one of these components (e.g., the connection terminal (178)), or may have one or more other components added. In some embodiments, some of these components (e.g., the sensor module (176), the camera module (180), or the antenna module (197)) may be integrated into one component (e.g., the display module (160)).

[0021] The processor (120) may, for example, execute software (e.g., a program (140)) to control at least one other component (e.g., a hardware or software component) of the electronic device (101) connected to the processor (120) and perform various data processing or calculations. According to one embodiment, as at least a part of the data processing or calculation, the processor (120) may store a command or data received from another component (e.g., a sensor module (176) or a communication module (190)) in a volatile memory (132), process the command or data stored in the volatile memory (132), and store the resulting data in a non-volatile memory (134). According to one embodiment, the processor (120) may include a main processor (121) (e.g., a central processing unit or an application processor) or a secondary processor (123) (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor)) that can operate independently or together therewith. For example, if the electronic device (101) includes a main processor (121) and a secondary processor (123), the secondary processor (123) may be configured to use less power than the main processor (121) or to be specialized for a specified function. The secondary processor (123) may be implemented separately from the main processor (121) or as a part thereof.

[0022] The auxiliary processor (123) may control at least a portion of functions or states associated with at least one component (e.g., a display module (160), a sensor module (176), or a communication module (190)) of the electronic device (101), for example, on behalf of the main processor (121) while the main processor (121) is in an inactive (e.g., sleep) state, or together with the main processor (121) while the main processor (121) is in an active (e.g., application execution) state. In one embodiment, the auxiliary processor (123) (e.g., an image signal processor or a communication processor) may be implemented as a part of another functionally related component (e.g., a camera module (180) or a communication module (190)). In one embodiment, the auxiliary processor (123) (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. The artificial intelligence models may be generated through machine learning. This learning can be performed, for example, on the electronic device (101) itself where the artificial intelligence model is executed, or can be performed through a separate server (e.g., server (108)). The learning algorithm can include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model can include multiple artificial neural network layers.The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to, or alternatively to, a hardware structure, an artificial intelligence model may include a software structure.

[0023] The memory (130) can store various data used by at least one component (e.g., processor (120) or sensor module (176)) of the electronic device (101). The data can include, for example, software (e.g., program (140)) and input data or output data for commands related thereto. The memory (130) can include volatile memory (132) or non-volatile memory (134).

[0024] The program (140) may be stored as software in the memory (130) and may include, for example, an operating system (142), middleware (144), or an application (146).

[0025] The input module (150) can receive commands or data to be used in a component of the electronic device (101) (e.g., a processor (120)) from an external source (e.g., a user) of the electronic device (101). The input module (150) can include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0026] The audio output module (155) can output audio signals to the outside of the electronic device (101). The audio output module (155) can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. In one embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0027] The display module (160) can visually provide information to an external party (e.g., a user) of the electronic device (101). The display module (160) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling the device. In one embodiment, the display module (160) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of a force generated by the touch.

[0028] The audio module (170) can convert sound into an electrical signal, or vice versa, convert an electrical signal into sound. According to one embodiment, the audio module (170) can acquire sound through the input module (150), output sound through the sound output module (155), or an external electronic device (e.g., electronic device (102)) (e.g., speaker or headphone) directly or wirelessly connected to the electronic device (101).

[0029] The sensor module (176) can detect the operating status (e.g., power or temperature) of the electronic device (101) or the external environmental status (e.g., user status) and generate an electrical signal or data value corresponding to the detected status. According to one embodiment, the sensor module (176) can include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0030] The interface (177) may support one or more designated protocols that may be used to directly or wirelessly connect the electronic device (101) with an external electronic device (e.g., the electronic device (102)). In one embodiment, the interface (177) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0031] The connection terminal (178) may include a connector through which the electronic device (101) may be physically connected to an external electronic device (e.g., electronic device (102)). According to one embodiment, the connection terminal (178) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0032] A haptic module (179) can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that a user can perceive through tactile or kinesthetic sensations. In one embodiment, the haptic module (179) can include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

[0033] The camera module (180) can capture still images and videos. According to one embodiment, the camera module (180) may include one or more lenses, image sensors, image signal processors, or flashes.

[0034] The power management module (188) can manage power supplied to the electronic device (101). According to one embodiment, the power management module (188) can be implemented, for example, as at least a part of a power management integrated circuit (PMIC).

[0035] A battery (189) may power at least one component of the electronic device (101). In one embodiment, the battery (189) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0036] The communication module (190) may support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device (101) and an external electronic device (e.g., electronic device (102), electronic device (104), or server (108)), and the performance of communication through the established communication channel. The communication module (190) may operate independently from the processor (120) (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (190) may include a wireless communication module (192) (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (194) (e.g., a local area network (LAN) communication module, or a power line communication module). Among these communication modules, the corresponding communication module can communicate with an external electronic device (104) via a first network (198) (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network (199) (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules can be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (192) can verify or authenticate the electronic device (101) within a communication network such as the first network (198) or the second network (199) by using subscriber information (e.g., an international mobile subscriber identity (IMSI)) stored in the subscriber identification module (196).

[0037] The wireless communication module (192) can support 5G networks and next-generation communication technologies following the 4G network, such as NR access technology (new radio access technology). NR access technology can support high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimizing terminal power and connecting multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low-latency communications)). The wireless communication module (192) can support, for example, a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate. The wireless communication module (192) can support various technologies for securing performance in a high-frequency band, such as beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module (192) can support various requirements specified in the electronic device (101), an external electronic device (e.g., the electronic device (104)), or a network system (e.g., the second network (199)). According to one embodiment, the wireless communication module (192) can support a peak data rate (e.g., 20 Gbps or more) for eMBB realization, a loss coverage (e.g., 164 dB or less) for mMTC realization, or a U-plane latency (e.g., 0.5 ms or less for downlink (DL) and uplink (UL), or 1 ms or less for round trip) for URLLC realization.

[0038] The antenna module (197) can transmit or receive signals or power to or from an external device (e.g., an external electronic device). In one embodiment, the antenna module (197) may include an antenna including a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). In one embodiment, the antenna module (197) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as the first network (198) or the second network (199), may be selected from the plurality of antennas by, for example, the communication module (190). A signal or power may be transmitted or received between the communication module (190) and an external electronic device through the selected at least one antenna. In some embodiments, in addition to the radiator, another component (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as a part of the antenna module (197).

[0039] According to various embodiments, the antenna module (197) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent a first side (e.g., a bottom side) of the printed circuit board and capable of supporting a designated high-frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an array antenna) disposed on or adjacent a second side (e.g., a top side or a side side) of the printed circuit board and capable of transmitting or receiving signals in the designated high-frequency band.

[0040] At least some of the above components can be interconnected and exchange signals (e.g., commands or data) with each other via a communication method between peripheral devices (e.g., a bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)).

[0041] According to one embodiment, commands or data may be transmitted or received between the electronic device (101) and an external electronic device (104) via a server (108) connected to a second network (199). Each of the external electronic devices (102 or 104) may be the same or a different type of device as the electronic device (101). According to one embodiment, all or part of the operations executed in the electronic device (101) may be executed in one or more of the external electronic devices (102, 104, or 108). For example, when the electronic device (101) is to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device (101) may, instead of or in addition to executing the function or service itself, request one or more external electronic devices to perform the function or at least a part of the service. One or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device (101). The electronic device (101) may process the result as is or additionally and provide it as at least a portion of a response to the request. For this purpose, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device (101) may provide an ultra-low latency service by using distributed computing or mobile edge computing, for example. In another embodiment, the external electronic device (104) may include an Internet of Things (IoT) device. The server (108) may be an intelligent server using machine learning and / or a neural network. According to one embodiment, the external electronic device (104) or the server (108) may be included in the second network (199).The electronic device (101) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0042] FIG. 2 illustrates an example of an electronic device (e.g., electronic device (101)) including an RF (radio frequency) transceiver.

[0043] Referring to FIG. 2, the electronic device (101) may include a processor (210), an RF transceiver (220) (e.g., RFIC), a radio frequency front end (RFFE) circuit (230), and an antenna (240). The electronic device (101) may include the processor (210). The processor (210) may include a processing circuit. The processor (210) may include, for example, at least one of an application processor (AP) (e.g., the main processor (121) of FIG. 1)) or a communication processor (CP) (e.g., the auxiliary processor (123) of FIG. 1). For example, the processor (210) may include an AP and a CP. For example, the processor may include an AP. For example, the processor (210) may include a CP. The processor (210) can control the RF transceiver (220) via a control interface (211) (e.g., MIPI or SPI). For example, the processor (210) can generate a baseband signal. The processor (210) can control the RF transceiver (220) to process the generated baseband signal. The processor (210) can transmit a signal (213a) (e.g., analog data or digital data). For example, the signal (213a) can be a communication signal to be transmitted to an external electronic device (e.g., a base station, a satellite, a terminal, an electronic device (102), an electronic device (104), or a server (108)). The processor (210) can control the RF transceiver (220) to transmit the signal via an antenna (240). The processor (210) can receive a signal (213b) (e.g., analog data or digital data). For example, the signal (213b) may be a signal received from an external electronic device (e.g., a base station, a satellite, a terminal, an electronic device (102), an electronic device (104), or a server (108)) via an antenna (240).For another example, signal (213b) may include a signal for measuring transmission power (e.g., a feedback signal). Processor (210) may control RF transceiver (220) to receive signal (213b). For example, processor (210) may obtain feedback signal through one port (e.g., feedback receive port (FBRX)) of RF transceiver (220).

[0044] The electronic device (101) may include an RF transceiver (220). For example, the RF transceiver (220) may be implemented as a single chip (e.g., an RFIC chip) or as part of a single package. The RF transceiver (220) may include a digital to analog converter (DAC) for converting a digital signal to an analog signal. The RF transceiver (220) may include a mixer and an oscillator (e.g., a local oscillator (LO)) for up-conversion. The RF transceiver (220) may convert a baseband signal generated by the processor (210) into an RF transmission signal (221). The RF transceiver (220) may provide the RF transmission signal (221) to the RFFE circuit (230). The RF transceiver (220) can receive an RF reception signal (222) from the RFFE circuit (230). The RF transceiver (220) can include an analog to digital converter (ADC) for converting an analog signal into a digital signal. The RF transceiver (220) can include a mixer and an oscillator for down-conversion. The RF transceiver (220) can convert an RF reception signal (222) received from an antenna (240) into a baseband signal so that the RF reception signal (222) can be processed by the processor (210). The RF transceiver (220) can include one or more transmit ports. The RF transceiver (220) can include one or more receive ports. According to embodiments, the RF transceiver (220) may receive a feedback signal provided from a component (e.g., a coupler (235)) of an RFFE circuit (230) that is electrically connected to an antenna (240). For example, the RF transceiver (220) may include a feedback receive port (FBRX) for the feedback signal.The coupler (235) can be electrically connected to the FBRX via a feedback path (251).

[0045] The electronic device (101) may include an RFFE circuit (230). The RFFE circuit (230) may be configured to transmit an RF transmission signal (221) from an RF transceiver (220) to an antenna (240). The RFFE circuit (230) may include a power amplifier (PA) (231), a duplexer (233), and / or a coupler (235) for a transmission path. The coupler (235) may provide a signal (hereinafter, a feedback signal) obtained through coupling with a signal transmitted to the antenna (240) to the RF transceiver (220) through a feedback path (251). The RF transmission signal (221) generated by the RF transceiver (220) may be radiated into the air through the antenna (240) via the transmission path. The RFFE circuit (230) can transmit an RF reception signal (222) from an antenna (240) to the RF transceiver (220). For example, the RFFE circuit (230) can include components for a reception path in addition to components for a transmission path. The RFFE circuit (230) can include a low noise amplifier (LNA) (232) for the reception path. For example, in a frequency division duplex (FDD) frequency band, the transmission path and the reception path can be branched through a duplexer (233) of the RFFE circuit (230). The RF reception signal (222) received through the antenna (240) can be transmitted to the RF transceiver (220). Although the RFFE circuit (230) for processing a transmission signal and a reception signal is illustrated in FIG. 2, embodiments of the present disclosure are not limited thereto. For example, not only an LPAMid that includes both a transmit path and a receive path, but also a PAMid that includes a transmit path can be used as an example of an RFFE circuit.If it is a circuit that processes an RF signal from an RF transceiver (220) or an antenna (240), it can be understood as an RFFE circuit of an electronic device (101) according to an embodiment of the present disclosure. In addition, for example, the RFFE circuit may be implemented as a single module or as a module and components connected to the module, depending on the implementation example.

[0046] The electronic device (101) may include a clock generation circuit (270) (e.g., a clock generator). The clock generation circuit (270) may receive a clock signal from an oscillator (e.g., a thermal sensing uncompensated crystal oscillator (TSX), a temperature compensated crystal oscillator (TCXO), or a crystal oscillator (XO)). The clock generation circuit (270) may generate a reference clock signal based on the received clock signal. The electronic device (101) may provide the reference clock signal of the clock generation circuit (270) to the processor (210) for operations of components in the processor (210). The electronic device (101) may provide the reference clock signal of the clock generation circuit (270) to the RF transceiver (220) for operations of components in the RF transceiver (220). For example, the reference clock signal can be used to generate a frequency of an oscillator circuit of an RF transceiver (220).

[0047] To provide a stable transmission data processing speed, sufficient error vector magnitude (EVM) performance may be required. The average EVM represents the average EVM over a certain period of time, and the peak EVM represents an EVM value that is momentarily high. A high peak EVM indicates poor channel performance at a specific frequency or time period, which may result in reduced throughput. LO leakage may be cited as a cause of the high peak EVM. When upconverting or downconverting a frequency, a mixer and an oscillator (e.g., LO) of the RF transceiver (220) may be utilized. During this signal conversion process, unwanted frequency components may be generated. The unwanted frequency components may be referred to as LO leakage, LO leakage component, LO leakage signal, and / or equivalent technical terms. As the LO leakage component increases, the channel quality (e.g., SNR) of the transmission signal that the electronic device (101) originally intends to transmit may be degraded. Due to the deterioration of the channel quality, the peak EVM may momentarily increase. In addition to the size of the LO leakage component, its frequency variability can also contribute to a high peak EVM. This is because the higher the frequency variability of the LO leakage component, the more difficult it is to analyze the signal in the frequency domain. To address the above-described issues, embodiments of the present disclosure describe techniques for reducing the impact of the LO leakage component.

[0048] As a high reference clock is required, an oscillation circuit (e.g., TSX) with excellent phase noise control performance can be used. The clock generation circuit (270) can perform temperature compensation and then transmit the reference clock signal after the temperature compensation is performed to each component (e.g., the processor (210) or the RF transceiver (220)). However, if the temperature compensation function is not sufficiently implemented in the oscillation circuit (e.g., TSX) or the temperature compensation performance is not sufficient, a reference clock signal that fluctuates depending on the temperature may be provided to each component (e.g., the processor (210) or the RF transceiver (220)). For example, it is assumed that a reference clock signal with a relatively high frequency fluctuation depending on the temperature (e.g., a fluctuation exceeding a threshold value occurs in the frequency domain) is transmitted to the RF transceiver (220). The RF transceiver (220) can generate an RF signal by up-converting a baseband signal. An LO can be used to generate the RF signal. However, if the variability of the reference clock signal is high, a problem may also occur in the frequency supplied to the LO for the above-mentioned upconversion (hereinafter, LO shaking problem). This may result in a deterioration of the peak EVM.

[0049] FIG. 3 illustrates an example of an RF transceiver (e.g., RF transceiver (220)) including a local oscillator (LO) leakage detection circuit. FIG. 3 illustrates a circuit for detecting LO leakage in the RF transceiver (220) of the electronic device (101) of FIG. 2. The same reference numerals may be used for the same description.

[0050] Referring to FIG. 3, the electronic device (101) may include an RF transceiver (220). The RF transceiver (220) may include an LNA (305) and a feedback processing circuit (310). The coupler (235) may be configured to extract at least a portion of a transmission signal (e.g., the transmission signal (221)). A feedback signal (301) extracted by being coupled with the transmission signal in the coupler (235) may be transmitted to the RF transceiver (220) through a feedback path (251). The RF transceiver (220) may obtain the feedback signal (301) through a feedback port (FBRX). The feedback signal (301) may be amplified through the LNA (305). Since the feedback signal (301) is an RF signal, the feedback processing circuit (310) may be used to transmit the RF signal to the processor (210). The feedback processing circuit (310) can convert the amplified feedback signal into a baseband signal (311). The RF transceiver (220) can generate the baseband signal (311) through the LNA (305) and the feedback processing circuit (310). This baseband signal (311) can be used in the processor (210).

[0051] A method of removing the LO leakage component through the baseband signal (311) measured through the feedback processing circuit (310) may be considered, but the above method may cause an LO shaking problem in that it uses the same oscillator as the mixer and transmitter circuit of the feedback processing circuit (310). In addition, since the analysis is performed after the signal reaches the processor (210), there is a problem of consuming a long time. Therefore, in the embodiments of the present disclosure, instead of using the baseband signal (311) measured through the feedback processing circuit (310), the LO leakage detection circuit (320) within the RF transceiver (220) may be used. The LO leakage detection circuit (320) may be configured to detect the LO leakage component of the feedback signal (301) within the RF transceiver (220). An RF transceiver (220) according to embodiments of the present disclosure may include an LO leakage detection circuit (320) and a switching circuit (330) to obtain an LO leakage component. The switching circuit (330) may be connected to an LNA (305). The switching circuit (330) may be configured to selectively connect the LNA (305) to a feedback processing circuit (310) or an LO leakage detection circuit (320). According to one embodiment, the switching circuit (330) may connect the LNA (305) to the LO leakage detection circuit (320). The switching circuit (330) may be controlled to connect the LNA (305) to the LO leakage detection circuit (320) under the control of the processor (210). The LNA (305) may output an amplified feedback signal. The amplified feedback signal may be input to the LO leakage detection circuit (320). The LO leakage detection circuit (320) can perform measurement of the LO leakage component based on the amplified feedback signal. For example, the LO leakage detection circuit (320) can detect the LO leakage component from the amplified feedback signal.The above LO leakage component may represent a frequency component detected at a location spaced a certain distance from the frequency of the transmission signal. The LO leakage detection circuit (320) may obtain the magnitude of the LO leakage component. The LO leakage detection circuit (320) may obtain the location of the LO leakage component in the frequency domain. The specific operations of the LO leakage detection circuit (320) are described in detail through FIG. 4.

[0052] The LO leakage component may indicate an unintended signal that is different from the signal component to be transmitted. The LO leakage component may be detected in a situation where the transmission signal is allocated only to a part (hereinafter, the transmission frequency region) of the frequency domain (e.g., RBs) of the bandwidth to be transmitted (e.g., the system bandwidth of the cell or the activated bandwidth part (BWP)). According to one embodiment, the processor (210) may activate the LO leakage detection circuit (320) based on resource allocation information (e.g., RB position or RB offset). Activation of the LO leakage detection circuit (320) may indicate connection of the LO leakage detection circuit (320) and the LNA (305) instead of the feedback processing circuit (310) via the switching circuit (330). If the transmission signal is transmitted only to a part of the frequency domain of the bandwidth according to the resource allocation information, the processor (210) may transmit a control signal to the RF transceiver (220) to operate the LO leakage detection circuit (320). For example, the control signal may be transmitted to the RF transceiver (220) via a control interface (e.g., MIPI or SPI). The processor (210) may obtain information on the location of the LO leakage component and / or the magnitude of the LO leakage component in the frequency domain from the RF transceiver (220). As a non-limiting example, when the LO leakage component is detected at a location that is spaced apart from the transmission frequency region by a certain distance (or gap) or more in the frequency domain, the processor (210) may periodically activate the LO leakage detection circuit (320). The processor (210) may periodically transmit a control signal for operating the LO leakage detection circuit (320) to the RF transceiver (220).

[0053] When information about the location of the LO leakage component and / or the size of the LO leakage component is obtained, the RF transceiver (220) can compensate for the LO leakage. For example, the RF transceiver (220) can adjust the DAC offset of the transmission processing circuit. The DAC offset may refer to an offset value applied to the DAC of the RF transceiver (220). The DAC can input a digital signal and output an analog signal. The DAC can generate the analog signal according to a value obtained by multiplying a value of the digital signal by a gain and adding an offset to the value. The output of the analog signal may vary according to the offset. The transmission processing circuit in the RF transceiver (220) may include a first transmission processing circuit for an in-phase component (I) and a second transmission processing circuit for a quadrature-phase component (Q). The first transmission processing circuit may include a first DAC (or may be referred to as DAC-I) for the in-phase component. The second transmission processing circuit may include a second DAC (or may be referred to as DAC-Q) for the quadrature-phase component. The RF transceiver (220) may apply a first offset to the first DAC. The first offset may be used to control an output for the in-phase component. The RF transceiver (220) may apply a second offset to the second DAC. The second offset may be used to control an output for the quadrature-phase component. By adjusting the first offset and / or the second offset, the RF transceiver (220) may be configured to control a gain and / or a phase of an RF transmission signal (221) output from the RF transceiver (220). The operation for controlling the gain and / or phase of the RF transmission signal (221) is described in detail through FIG. 5.

[0054] Although FIG. 3 illustrates a circuit structure in which the LNA (305) is connected before the switching circuit (330), embodiments of the present disclosure are not limited thereto. For example, the switching circuit (330) may be connected to the feedback port (FBRX) of the RF transceiver (220), and the LNA (305) may be included as a component in the feedback processing circuit (310). The switching circuit (330) may be configured to selectively connect the feedback port to the feedback processing circuit (310) or the LO leakage detection circuit (320). As another example, the switching circuit (330) may be connected to the feedback port (FBRX) of the RF transceiver (220), and the LNA (305) may be included as a component in the LO leakage detection circuit (320).

[0055] FIG. 4 illustrates an example of an LO leakage detection circuit (e.g., an LO leakage detection circuit (320)). The LO leakage detection circuit (320) according to embodiments of the present disclosure may be implemented within an RF transceiver (220) so as to be operable even while the electronic device (101) transmits a signal. Even while a signal is transmitted through a transmission processing circuit within the RF transceiver (220), components of the LO leakage detection circuit (320) may function to detect an LO leakage component.

[0056] Referring to FIG. 4, the feedback processing circuit (310) may include a mixer (411), a transimpedance amplifier (TIA) (412), a variable gain amplifier (VGA) (413), and an ADC (414). The feedback signal (301) may include a signal component (401) on a transmission frequency range corresponding to a portion of the bandwidth (477) (e.g., a transmission bandwidth, a system bandwidth, or an activated BWP). The feedback signal (301) may include an LO leakage component (402) outside the transmission frequency range within the bandwidth (477). The feedback signal (301) may be amplified through an LNA (305). If the feedback signal (301) is provided to the feedback processing circuit (310), LO leakage may additionally occur due to the mixer (411) of the feedback processing circuit (310). To detect LO leakage, the RF transceiver (220) according to embodiments of the present disclosure can control the switching circuit (330) to connect the LNA (305) and the detection circuit (421) of the LO leakage detection circuit (320) under the control of the processor (210).

[0057] An LO leakage detection circuit (320) according to embodiments of the present disclosure may include a detection circuit (421), a filter circuit (422), and / or a control circuit (423). The detection circuit (421) may be configured to track an envelope of an amplified feedback signal. By tracking the envelope, a signal including a signal component (401) and an LO leakage component (402) located in a different frequency domain may be detected. For example, the detection circuit (421) may perform self-mixing for envelope detection. The frequency position (471) of the LO leakage component (402) may be identified from a signal obtained through the envelope detection. The filter circuit (422) may be configured to block the signal component (401) and pass only the LO leakage component (402). The filter circuit (422) may be configured to pass a signal in a certain region (472) in the frequency domain. Since the frequency of the LO leakage component (402) is located within a certain range (472), only the LO leakage component (402) can be output. The component (403), which is an unintended signal but located in the same frequency range as the signal component (401), can be removed from the amplified feedback signal through the filter circuit (422). For example, the filter circuit (422) can be a high pass filter (HPF). For example, the filter circuit (422) can be a band pass filter (BPF). As a non-limiting example, the LO leakage detection circuit (320) may not include the filter circuit (422). Unlike as illustrated in FIG. 4, the LO leakage detection circuit (320) may include the detection circuit (421) and the control circuit (423) without the filter circuit (422).

[0058] The control circuit (423) can obtain the magnitude of the LO leakage component (402). The control circuit (423) can obtain the position of the LO leakage component (402). For example, the control circuit (423) can be a microcontroller unit (MCU). The control circuit (423) can be configured to perform a time-frequency transform (e.g., a fast Fourier transform (FFT)). Through the FFT, the control circuit (423) can obtain the position of the LO leakage component (402). The position of the LO signal component (402) can be adjusted through the control circuit (423). The control circuit (423) can measure the power of the LO leakage component (402) that has passed through the filter circuit (422). By measuring the power, the control circuit (423) can obtain the magnitude of the LO leakage component (402). Additionally, the control circuit (423) can obtain the position (e.g., frequency position (471)) of the LO leakage component (402) based on the result of envelope detection in the detection circuit (421) and time-frequency conversion.

[0059] FIG. 5 shows an example of control of the gain and phase of a transmission signal (e.g., a first RF transmission signal (221)) of an RF transceiver (e.g., an RF transceiver (220)).

[0060] Referring to FIG. 5, the RF transceiver (220) may include a transmit processing circuit (520). For example, a transmit signal may be input to the transmit processing circuit (520). The transmit signal may include an in-phase component (I) (501) and a quadrature-phase component (Q) (502). The transmit processing circuit may include a first transmit processing circuit (520a) for the in-phase component (501) and a second transmit processing circuit (520b) for the quadrature-phase component (502). The first transmit processing circuit (520a) may include a DAC (521a), a low-pass filter (LPF) (522a), a voltage-to-currents (V2I) circuit (523a), and / or a mixer (524a) for the in-phase component (501). The mixer (524a) may be connected to an LO (e.g., a voltage controlled oscillator (VCO)) within the RF transceiver (220). The second transmission processing circuit (520b) may include a DAC (521b), an LPF (522b), a V2I circuit (523b), and / or a mixer (524b) for the quadrature phase component (502). The mixer (524b) may be connected to an LO within the RF transceiver (220). The outputs of the mixer (524a) and the mixer (524b) may be output as an RF transmission signal (221) through an amplifier circuit (530). The amplifier circuit (530) may output the RF transmission signal (221) by synthesizing a first analog signal corresponding to an in-phase component and a second analog signal corresponding to a quadrature phase component. For example, the amplifier circuit (530) may be an amplifier (e.g., a variable gain amplifier (VGA), It may include a DA (distribution amplifier)), capacitor (532), transformer (533a, 533b), or capacitor (534).

[0061] The RF transceiver (220) according to embodiments of the present disclosure can adjust the DAC offset to reduce the impact of LO leakage. The RF transceiver (220) can adjust a first offset (510a) to be applied to the DAC (521a). The DAC (521a) can output a first analog signal corresponding to the in-phase component (501). The first offset (510a) can be used to control the magnitude (or amplitude) of the first analog signal. The RF transceiver (220) can adjust a second offset (510b) to be applied to the DAC (521b). The DAC (521b) can output a second analog signal corresponding to the quadrature-phase component (502). The second offset (510b) can be used to control the magnitude (or amplitude) of the analog signal corresponding to the quadrature-phase component (502). The first analog signal and the second analog signal can be synthesized in an orthogonal dimension. The gain and / or phase of the RF transmission signal (221) output from the RF transceiver (220) may be dependent on the first analog signal and the second analog signal. By adjusting the first offset (510a) and / or the second offset (510b), the RF transceiver (220) may be configured to control the gain and / or phase of the RF transmission signal (221) output from the RF transceiver (220). The RF transceiver (220) may control the gain and / or phase of the transmission signal output through the transmission processing circuit (e.g., the first transmission processing circuit (520a) or the second transmission processing circuit (520b)) of the RF transceiver (220) based on the position and magnitude of the LO leakage component (402) obtained through the control circuit (423). The gain and / or phase of the output transmission signal can be controlled by adjusting the bias (e.g., DAC offset) of the DAC within the transmission path. The DAC offset can correspond to the position of the LO leakage component (402).

[0062] According to one embodiment, the RF transceiver (220) can transmit information about the magnitude of an LO leakage component (e.g., LO leakage component (402)), the location of the LO leakage component, and the adjusted DAC offset value to the processor (210). A control signal including information about the magnitude of the LO leakage component (402), the location of the LO leakage component (402), and / or the adjusted DAC offset value can be transmitted to the processor (210) via a control interface (e.g., MIPI or SPI). The processor (210) can store the information in a memory (e.g., non-volatile memory (134)). For example, the processor (210) can store information about the magnitude of the LO leakage component and the DAC offset value corresponding to the magnitude together in the memory. The processor (210) can be configured to store the magnitude of the leakage component and the DAC offset value associated with the magnitude in the memory. If the same leakage component size is detected, the processor (210) can provide the DAC offset value from the memory to the RF transceiver (220). The RF transceiver (220) can receive the DAC offset value from the processor (210). By applying the DAC offset value, the RF transceiver (220) can reduce the size of the LO leakage component without a separate switching operation. Thereafter, according to an additional embodiment, when the RF transceiver (220) does not perform signal transmission, the RF transceiver (220) can change the frequency (e.g., PLL frequency) of the LO under the control of the processor (210).

[0063] As a non-limiting example, the RF transceiver (220) may be configured to control the DAC offset not always, but when certain conditions are met. For example, the RF transceiver (220) may determine a DAC offset corresponding to the magnitude of the LO leakage component (402) when the magnitude of the LO leakage component (402) is greater than or equal to a threshold value.

[0064] Figure 6 shows an example of functional blocks of a processor (e.g., processor (210)) for frequency control.

[0065] Referring to FIG. 6, a processor (210) according to one embodiment may include a complex generation circuit (610), a modulation circuit (620), a frequency control circuit (630), and / or a frequency synchronization circuit (640). The complex generation circuit (610) may be configured to generate complex signals (e.g., real component signals and imaginary component signals). The modulation circuit (620) may perform modulation on the complex signals. The frequency control circuit (630) may be configured to perform automatic frequency control (AFC). The frequency control circuit (630) may be configured to monitor the frequency of a signal for frequency stability. The frequency control circuit (630) may be configured to detect how much a configured bandwidth (e.g., bandwidth (477)) is off with respect to a reference frequency. The frequency control circuit (630) may be configured to detect the degree of frequency off based on information received from a network. For example, the frequency control circuit (630) can detect the amount of frequency to be corrected by the amount of deviation in the frequency domain. The amount of frequency to be corrected (hereinafter, frequency amount) can correspond to the deviation value. According to one embodiment, the frequency control circuit (630) can be configured to supply the frequency amount to the RF transceiver (220) instead of automatically adjusting the frequency according to the frequency amount.

[0066] The processor (210) may include a frequency synchronization circuit (640). The frequency synchronization circuit (640) may be connected to a frequency control circuit (630). The frequency synchronization circuit (640) may obtain a frequency amount to be corrected from the frequency control circuit (630). The frequency synchronization circuit (640) may be configured to transmit information (hereinafter, correction information) (641) about the frequency amount to the RF transceiver (220). The processor (210) may transmit the correction information (641) obtained through the frequency synchronization circuit (640) to the RF transceiver (220) through a control interface (e.g., MIPI or SPI). By controlling the RF transceiver (220) to perform frequency correction, LO shaking may be reduced without interruption of the signal transmission even while the electronic device (101) transmits a signal (e.g., transmission of a signal in a frequency division duplex (FDD) band).

[0067] Although FIG. 6 describes that the frequency synchronization circuit (640) acquires a frequency amount and provides the acquired frequency amount (e.g., correction information (641)) to the RF transceiver (220), embodiments of the present disclosure are not limited thereto. The processor (210) may further include a separate frequency calculation circuit (650). The frequency calculation circuit (650) may be connected to the frequency control circuit (630). The frequency calculation circuit (650) may calculate the frequency amount from the frequency control circuit (630). For example, the frequency calculation circuit (650) may detect the frequency amount from the frequency control circuit (630) based on the degree of distortion in the frequency control circuit (630). As another example, the frequency calculation circuit (650) may calculate the frequency amount to be detected by the frequency control circuit (630) based on learning. The relationship between the temperature information stored in the memory of the electronic device (101) (e.g., built-in memory (136) or external memory (138)) and the degree of distortion detected by the frequency control circuit (630) can be learned. The degree of distortion can be related to the frequency amount to be corrected. The frequency calculation circuit (650) can calculate the frequency amount corresponding to the current temperature based on the result of the learning. The frequency calculation circuit (650) can transmit the frequency amount to the frequency synchronization circuit (640). The frequency synchronization circuit (640) can transmit a control signal to the RF transceiver (220) so that the RF transceiver (220) is corrected by the frequency amount.

[0068] Fig. 7a illustrates an example of functional blocks of an RF transceiver (e.g., RF transceiver (220)) for frequency control. Fig. 7a illustrates an example in which the RF transceiver (220) corrects the LO frequency in the oscillator circuit using the correction information (641) of Fig. 6.

[0069] Referring to FIG. 7A, the RF transceiver (220) may include a first transmit processing circuit (720a), a second transmit processing circuit (720b), an amplifier circuit (730), and / or an oscillator circuit (740) (e.g., a phased-locked loop (PLL) circuit). The oscillator circuit (740) may provide an LO frequency (751) for upconversion. The LO frequency (751) may include an LO frequency (751a) for upconversion of an in-phase component (I) and an LO frequency (751b) for upconversion of a quadrature-phase component (Q). The first transmit processing circuit (720a) may include components for signal processing of the in-phase component (I). The first transmit processing circuit (720a) may include a first mixer (724a). The first mixer (724a) may be configured to perform upconversion. The first mixer (724a) can perform upconversion on the signal by adding the LO frequency (751a) of the oscillator circuit (740) to the frequency of the input signal. The second transmission processing circuit (720b) ​​can include components for signal processing of the quadrature phase component (Q). The second transmission processing circuit (720b) ​​can include the second mixer (724b). The second mixer (724b) can be configured to perform upconversion. The second mixer (724b) can perform upconversion on the signal by adding the LO frequency (751b) of the oscillator circuit (740) to the frequency of the input signal. In one embodiment, the oscillator circuit (740) can be a PLL.

[0070] The RF transceiver (220) can obtain correction information (641) from the processor (210). For example, the RF transceiver (220) can receive the correction information (641) through a control interface (e.g., MIPI or SPI). The RF transceiver (220) can perform frequency compensation to reduce the impact of LO leakage. The RF transceiver (220) can control the LO frequency (751) provided to a mixer (e.g., the first mixer (724a) and / or the second mixer (724b)). For example, the RF transceiver (220) can control the LO frequency (751a) provided to the first mixer (724a). For example, the RF transceiver (220) can control the LO frequency (751b) provided to the second mixer (724b). The RF transceiver (220) can adjust the LO frequency (751) of the oscillator circuit (740) based on the correction information (641). Meanwhile, while a signal is being transmitted through the RF transceiver (220), the oscillator circuit (740) (e.g., a PLL circuit) may be providing a frequency in a locked state. In order to adjust the LO frequency (751) of the oscillator circuit (740) without additional changes to the oscillator circuit (740), the RF transceiver (220) may include a control circuit (750) and an additional frequency divider circuit (760).

[0071] The control circuit (750) may activate the additional frequency divider circuit (760). For example, the control circuit (750) may be configured to activate the additional frequency divider circuit (760) in response to receiving the correction information (641) from the processor (210) or in response to a separate control signal. Activation of the additional frequency divider circuit (760) may indicate that additional frequency division is performed in addition to the frequency division in the oscillator circuit (740) by operating the additional frequency divider circuit (760). For example, activation of the additional frequency divider circuit (760) may indicate electrically connecting the additional frequency divider circuit (760) to the oscillator circuit (740). As another example, activation of the additional frequency divider circuit (760) may indicate changing the setting value of the divider from a default value (e.g., 1) to a value for frequency division (e.g., a value according to the correction information (641)).

[0072] The control circuit (750) can control the additional frequency dividing circuit (760) based on the correction information (641). The additional frequency dividing circuit (760) can adjust the frequency. The oscillator circuit (740) can include a frequency divider. The additional frequency dividing circuit (760) can correspond to a frequency divider that is different from the above frequency divider. In the present disclosure, the frequency dividing circuit can refer to a circuit (e.g., an electronic circuit or a digital circuit) that divides an input frequency by a specific ratio to generate an output frequency. For example, the frequency dividing circuit can be configured to count the period of an input signal and generate an output signal. For example, the frequency dividing circuit can be configured to perform frequency division according to a power of 2 using a flip-flop. For another example, the frequency division circuit may be configured to perform division according to a non-integer ratio through an analog circuit (e.g., a ring oscillator). For another example, the frequency division circuit may be configured to perform frequency division according to a division ratio according to an input value. The frequency divider circuit may be configured to divide the frequency of an input signal according to a division ratio. The frequency divider may be configured to output a signal having a divided frequency. The control circuit (750) may control the additional frequency division circuit (760) to perform frequency division by a value (N') corresponding to the correction information (641). The LO frequency (751) may be adjusted through the frequency division circuit (745) of the oscillator circuit (740) and the additional frequency division circuit (760).

[0073] As a non-limiting example, the control circuit (750) may be configured to first check the status of the oscillator circuit (740) before activating the additional frequency divider circuit (760). For example, the control circuit (750) may detect, in response to the correction information (641), whether the oscillator circuit (740) is operating (e.g., whether the PLL circuit is locked). For example, the control circuit (750) may detect, in response to receiving the correction information (641), whether the oscillator circuit (740) is operating. If the oscillator circuit (740) is operating, the control circuit (750) may activate the additional frequency divider circuit (760).

[0074] Figure 7b shows an example of frequency control using an oscillator circuit (e.g., oscillator circuit (740)) and an additional frequency divider circuit (e.g., additional frequency divider circuit (760)).

[0075] Referring to FIG. 7B, the RF transceiver (220) may include an oscillator circuit (740). For example, the oscillator circuit (740) may be a PLL circuit. The PLL circuit (740) may provide a control system for stably providing a desired frequency. The PLL circuit (740) may include a buffer (741), a comparison circuit (742), a conversion circuit (743), a VCO (744), and a frequency divider circuit (745). The buffer (741) may obtain a reference clock signal (701) (e.g., a reference clock signal from a clock generation circuit (270). The comparison circuit (742) may be configured to compare the reference clock signal (701) with a feedback signal (771) from the frequency divider circuit (745). The comparison circuit (742) may be configured to output (e.g., pulse) a phase difference and / or a frequency difference between the reference clock signal (701) and the feedback signal (771) based on the comparison. The output may be provided to the conversion circuit (743). The conversion circuit (743) may provide an output voltage corresponding to the phase difference and / or the frequency difference between the reference clock signal (701) and the feedback signal (771) to the VCO (744). For example, the conversion circuit (743) may include a charge pump and a loop filter. The charge pump may be configured to output a voltage corresponding to an input pulse from the comparison circuit (742). The loop filter may be configured to remove unnecessary noise. The VCO (744) may output an LO frequency (751) corresponding to the voltage from the conversion circuit (743). The LO frequency (751) (e.g., LO frequency (751a), or LO frequency (751b)) can be provided to a mixer (e.g., first mixer (741a), or second mixer (742a)).

[0076] The RF transceiver (220) may include a control circuit (750), an additional frequency divider circuit (760), and an adder (or an adder circuit) (799). Even if the frequency of the VCO (744) fluctuates, the frequency of the VCO (744) may be controlled to be adjusted to a designated frequency (e.g., the frequency of the reference clock signal (701) or a multiple thereof) through the PLL circuit (740). The PLL circuit (740) may be in a locked state while a signal is being transmitted through the RF transceiver (220). The PLL circuit (740) may provide an LO frequency in the locked state. To confirm the locked state of the PLL circuit (740), the control circuit (750) may detect an operation signal (791) from the comparison circuit (742). Based on the pattern of the operation signal (791), the control circuit (750) can determine whether the comparison circuit (742) is operating, i.e., whether the PLL circuit (740) is in a locked state. If the PLL circuit (740) is in a locked state, the control circuit (750) can apply a control signal (752) to activate an additional frequency dividing circuit (760). The additional frequency dividing circuit (760) can be activated according to the control signal (752).

[0077] To adjust the LO frequency without releasing the lock state of the PLL circuit (740), an adder (799) may be placed between the VCO (744) and the frequency divider circuit (745). The adder (799) may be connected to an additional frequency divider circuit (760). Although the adder (799) is illustrated as a separate component in FIG. 7B to logically illustrate the transmission of a signal, such illustration is exemplary and should not be construed as limiting the embodiments of the present disclosure. For example, the adder (799) may be implemented as a component of the additional frequency divider circuit (760). The additional frequency divider circuit (760) may be activated in response to a control signal (752) from the control circuit (750). The additional frequency divider circuit (760) may be configured to divide the signal (774) from the VCO (744). When the additional frequency dividing circuit (760) is activated (or after activation), the feedback signal (771) input to the comparison circuit (742) can be obtained by dividing the signal (774) through the frequency dividing circuit (745) and the additional frequency dividing circuit (760). When the additional frequency dividing circuit (760) is not activated (or before activation), the feedback signal (771) input to the comparison circuit (742) can be obtained by dividing the signal (774) using only the frequency dividing circuit (745). Frequency division can be performed through the division ratio (N, N is an integer) of the frequency dividing circuit (745) as well as the division ratio (N', N' is an integer and can be the same as or different from N) of the additional frequency dividing circuit (760). For example, the first frequency division using the additional frequency dividing circuit (760) can be performed on the signal (774) of the VCO (744). A second frequency division using a frequency division circuit (745) of a PLL circuit (740) can be performed on the result of the first frequency division.In addition to the frequency division operation of the existing PLL circuit, by adjusting the frequency of the feedback signal (774) through additional frequency division, the LO frequency of the VCO (744) can be adjusted even while the PLL circuit (740) is in operation. By adjusting the LO frequency, the influence due to LO fluctuation can be reduced. Through the additional frequency division circuit (760) and adder (799) additionally connected to the PLL circuit (740), the influence due to LO fluctuation can be reduced even while the PLL circuit (740) is in operation.

[0078] An RF transceiver according to embodiments of the present disclosure detects an LO leakage component within the RF transceiver and reduces the influence of the LO leakage component by applying a DAC offset corresponding to the LO leakage component. An electronic device according to embodiments of the present disclosure provides the frequency amount detected by the AFC to the RF transceiver when a specified frequency condition is satisfied and controls the RF transceiver to correct the LO frequency of a PLL circuit of the RF transceiver, thereby reducing the influence of fluctuation of the LO leakage component. By reducing the influence of the LO leakage component, the peak EVM performance can be improved. With the recent development of communication technology, stable communication performance can be provided even in a channel situation where a high-order modulation scheme (e.g., 1024 QAM (quadrature amplitude modulation)) is used.

[0079] The effects that can be obtained from the present disclosure are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by a person having ordinary skill in the art to which the present disclosure pertains from the description below.

[0080] In embodiments, a radio frequency (RF) transceiver (220) is provided. The RF transceiver (220) may include a transmit processing circuit including a mixer; and a phase locked loop (PLL) circuit (740). The PLL circuit (740) may include a voltage controlled oscillator (VCO) (744) configured to provide a local oscillator (LO) frequency to the mixer based on a comparison result of a reference clock signal and a feedback signal; and a frequency dividing circuit (745) configured to provide the feedback signal based on a signal from the VCO (744). The RF transceiver (220) may include an additional frequency dividing circuit (760); and a control circuit (750) configured to activate the additional frequency dividing circuit (760) based on a control signal from a processor (210). The above feedback signal can be generated from the signal of the VCO (744) using only the frequency dividing circuit among the frequency dividing circuit (745) and the additional frequency dividing circuit (760) before the additional frequency dividing circuit (760) is activated. The above feedback signal can be generated from the signal of the VCO (744) using the frequency dividing circuit (745) and the activated additional frequency dividing circuit (760) after the additional frequency dividing circuit (760) is activated.

[0081] For example, the control signal may include information indicating an amount of frequency adjusted for automatic frequency control (AFC) in the processor (210). The additional frequency division circuit (760) may be configured to perform frequency division at a division ratio corresponding to the information.

[0082] For example, the control circuit (750) may be configured to, in response to receiving the control signal, identify whether the PLL circuit (740) is locked, activate the additional frequency dividing circuit (760) based on a determination that the PLL circuit (740) is locked, and maintain the additional frequency dividing circuit (760) in a deactivated state based on a determination that the PLL circuit (740) is not locked.

[0083] For example, the additional frequency dividing circuit (760) may be connected between the VCO (744) and the frequency dividing circuit (745). The PLL circuit (740) may include a comparison circuit (742) configured to output a comparison result between the reference clock signal and the feedback signal, and a conversion circuit (743) configured to provide an output voltage corresponding to the comparison result.

[0084] For example, the additional frequency division circuit (760) may be configured to perform a first frequency division on the signal of the VCO (744). The frequency division circuit (745) may be configured to perform a second frequency division on the result of the first frequency division.

[0085] For example, the frequency band of the signal transmitted based on the LO frequency of the transmission processing circuit and the VCO (744) may correspond to a frequency-division duplex (FDD) band. While the LO frequency is provided to the mixer through the PLL circuit (740), the feedback signal may be generated using the frequency dividing circuit (745) and the activated additional frequency dividing circuit (760).

[0086] For example, the control signal may be obtained through a digital interface for communication between the processor (210) and the RF transceiver (220).

[0087] In embodiments, an electronic device (101) is provided. The electronic device (101) may include a processor (210); an RF (radio frequency) transceiver (220); a radio frequency front end (RFFE) circuit (230) connected to the RF transceiver (220); and an antenna (240) connected to the RFFE circuit (230). The RF transceiver (220) may include a transmission processing circuit including a mixer, a phase locked loop (PLL) circuit (740) including a voltage controlled oscillator (VCO) (744) configured to provide a local oscillator (LO) frequency to the mixer based on a comparison result of a reference clock signal and a feedback signal, and a frequency divider circuit (745) configured to provide the feedback signal based on a signal from the VCO (744); and an additional frequency divider circuit (760). The above feedback signal can be generated from the signal of the VCO (744) using only the frequency dividing circuit (745) among the frequency dividing circuit (745) and the additional frequency dividing circuit (760) before the additional frequency dividing circuit (760) is activated. The above feedback signal can be generated from the signal of the VCO (744) using the frequency dividing circuit (745) and the activated additional frequency dividing circuit (760) after the additional frequency dividing circuit (760) is activated.

[0088] For example, the processor (210) may control the RF transceiver (220) to cause the additional frequency division circuit (760) to perform frequency division at a division ratio corresponding to the frequency amount adjusted for automatic frequency control (AFC).

[0089] For example, the additional frequency divider circuit (760) may be activated while the PLL circuit (740) is in a locked state.

[0090] For example, the additional frequency dividing circuit (760) may be connected between the VCO (744) and the frequency dividing circuit (745). The PLL circuit (740) may include a comparison circuit (742) configured to output a comparison result between the reference clock signal and the feedback signal, and a conversion circuit (743) configured to provide an output voltage corresponding to the comparison result.

[0091] For example, the additional frequency division circuit (760) may be configured to perform a first frequency division on the signal of the VCO (744). The frequency division circuit (745) may be configured to perform a second frequency division on the result of the first frequency division.

[0092] For example, the frequency band of the signal transmitted through the processor (210), the RF transceiver (220), the RFFE circuit, and the antenna may correspond to a frequency-division duplex (FDD) band. While the signal is transmitted, the PLL circuit (740) may be configured to provide the LO frequency to the mixer based on the frequency dividing circuit (745) and the activated additional frequency dividing circuit (760).

[0093] For example, a control signal for activating the additional frequency division circuit (760) may be transmitted to the RF transceiver (220) via a digital interface for communication between the processor (210) and the RF transceiver (220).

[0094] In embodiments, an electronic device (101) is provided. The electronic device (101) may include a processor (210) including a processing circuit; an RF (radio frequency) transceiver (220) including a local oscillator (LO) and an LO leakage detection circuit (320); an RFFE (radio frequency front end) circuit including a coupler and connected to the RF transceiver (220); and an antenna (240) connected to the RFFE circuit (230). The RF transceiver (220) may be configured to connect the LO leakage detection circuit (320) to a feedback port electrically connected to a coupler of the RFFE circuit (230) in response to a control signal received from the processor (210), obtain an LO leakage component from a feedback signal from the feedback port through the LO leakage detection circuit (320), and apply an offset corresponding to the LO leakage component to a DAC (digital-to-analog converter) of the RF transceiver (220). The control signal may be transmitted when a frequency domain of a transmission signal satisfies a specified condition.

[0095] For example, the specified condition may include that the frequency range of the transmission signal corresponds to a portion of a transmission bandwidth configured in the electronic device (101).

[0096] For example, the RF transceiver (220) may include a feedback circuit for providing the feedback signal to the processor (210), the LO leakage detection circuit (320), and a switching circuit (330) configured to selectively connect the LO leakage detection circuit (320) or the feedback processing circuit (310) to the feedback port.

[0097] For example, the LO leakage detection circuit (320) may include an envelope detection circuit (421) configured to obtain a signal including a signal component of the feedback signal and the LO leakage component, a filter circuit (422) configured to pass only the leakage component among the signal component and the LO leakage component, and a control circuit (423) configured to obtain at least one of the size of the LO leakage component or the position of the LO leakage component.

[0098] For example, the location of the LO leakage component can be obtained based on the FFT (fast Fourier transform) of the control circuit.

[0099] For example, the RF transceiver (220) may include a transmit processing circuit for the transmit signal. The transmit processing circuit may include a first transmit processing circuit for an in-phase component and a second transmit processing circuit for a quadrature-phase component. The first transmit processing circuit may include a first DAC (521a) and a first mixer (524a) connected to the LO. The second transmit processing circuit may include a second DAC (521b) and a second mixer (524b) connected to the LO. The offset corresponding to the LO leakage component may include a first offset to be applied to the first DAC (521a) and a second offset to be applied to the second DAC (521b).

[0100] For example, the RF transceiver (220) may be configured to transmit information about the size of the LO leakage component and the offset to the processor (210) via a control interface. The information about the size of the LO leakage component and the offset may be stored in the memory of the electronic device (101) under the control of the processor (210).

[0101] For one or more embodiments, at least one of the components described in one or more of the preceding drawings may be configured to perform one or more operations, techniques, processes, and / or methods as described herein. For example, a processor (e.g., a baseband processor) described herein with respect to one or more of the preceding drawings may be configured to operate according to one or more examples described herein. For another example, circuitry associated with a user equipment (UE), a base station, a network element, and the like, as described above with respect to one or more of the preceding drawings, may be configured to operate according to one or more examples described herein.

[0102] Any of the embodiments described above may be combined with any other embodiment (or combination of embodiments) unless explicitly stated otherwise. The foregoing description of one or more implementations provides examples and descriptions, but is not intended to be exhaustive or limit the scope of the embodiments to the precise forms disclosed. Modifications and variations are possible in light of the above teachings or may be learned from practicing various embodiments.

[0103] Electronic devices according to the various embodiments disclosed in this document may take various forms. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, electronic devices, or home appliances. Electronic devices according to the embodiments of this document are not limited to the aforementioned devices.

[0104] The various embodiments of this document and the terminology used therein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various modifications, equivalents, or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the context clearly indicates otherwise. In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase among those phrases, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used merely to distinguish one component from another, and do not limit the components in any other respect (e.g., importance or order). When a component (e.g., a first component) is referred to as "coupled" or "connected" to another component (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component can be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0105] The term "module" used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be an integral component, or a minimum unit or part of such a component that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0106] Various embodiments of the present document may be implemented as software (e.g., a program (140)) including one or more instructions stored in a storage medium (e.g., an internal memory (136) or an external memory (138)) readable by a machine (e.g., an electronic device (101)). For example, a processor (e.g., a processor (120)) of the machine (e.g., an electronic device (101)) may call at least one instruction among the one or more instructions stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently or temporarily on the storage medium.

[0107] According to one embodiment, the method according to various embodiments disclosed in the present document may be provided as a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store™) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0108] According to various embodiments, each component (e.g., a module or a program) of the above-described components may include one or more entities, and some of the entities may be separated and placed in other components. According to various embodiments, one or more components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to various embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

1. In RF (radio frequency) transmitters and receivers; A transmission processing circuit including a mixer; PLL (phase locked loop) circuit, the PLL circuit: A voltage controlled oscillator (VCO) configured to provide a local oscillator (LO) frequency to the mixer based on the comparison result of a reference clock signal and a feedback signal; and A frequency dividing circuit configured to provide the feedback signal based on a signal from the VCO, additional frequency divider circuit; and A control circuit configured to activate the additional frequency division circuit based on a control signal of the processor, The above feedback signal is: Before the above additional frequency dividing circuit is activated, a signal is generated from the VCO signal using only the frequency dividing circuit among the above frequency dividing circuit and the above additional frequency dividing circuit, After the above additional frequency dividing circuit is activated, a signal is generated from the VCO using the frequency dividing circuit and the activated additional frequency dividing circuit. RF transceiver.

2. In claim 1, The above control signal includes information indicating the amount of frequency adjusted for automatic frequency control (AFC) in the processor, The above additional frequency division circuit is configured to perform frequency division at a division ratio corresponding to the above information. RF transceiver.

3. In claim 1, The above control circuit: In response to receiving the above control signal, identifying whether the PLL circuit is locked, According to the decision that the above PLL circuit is in a locked state, the above additional frequency division circuit is activated, wherein the PLL circuit is configured to maintain the additional frequency divider circuit in a disabled state based on a decision that the PLL circuit is not in a locked state; RF transceiver.

4. In claim 1, The above additional frequency dividing circuit is connected between the VCO and the frequency dividing circuit, The above PLL circuit: A comparison circuit configured to output a comparison result between the reference clock signal and the feedback signal, and A converter circuit configured to provide an output voltage corresponding to the above comparison result, RF transceiver.

5. In claim 4, The above additional frequency division circuit is configured to perform a first frequency division on the signal of the VCO, The above frequency division circuit is configured to perform a second frequency division on the result of the first frequency division. RF transceiver.

6. In claim 1, The frequency band of the signal transmitted based on the LO frequency of the above transmission processing circuit and the VCO corresponds to the FDD (frequency-division duplex) band, While the LO frequency is provided to the mixer through the PLL circuit, the feedback signal is generated using the frequency dividing circuit and the activated additional frequency dividing circuit. RF transceiver.

7. In claim 1, The above control signal is obtained through a digital interface for communication between the processor and the RF transceiver. RF transceiver.

8. In electronic devices, processor; RF(radio frequency) transmitter and receiver; An RFFE (radio frequency front end) circuit connected to the RF transceiver; and Including an antenna connected to the above RFFE circuit, The above RF transceiver: A transmission processing circuit including a mixer, A phase locked loop (PLL) circuit including a voltage controlled oscillator (VCO) configured to provide a local oscillator (LO) frequency to the mixer based on a comparison result of a reference clock signal and a feedback signal, and a frequency divider circuit configured to provide the feedback signal based on a signal from the VCO; and Includes an additional frequency divider circuit, The above feedback signal is, Before the above additional frequency dividing circuit is activated, a signal is generated from the VCO signal using only the frequency dividing circuit among the above frequency dividing circuit and the above additional frequency dividing circuit, After the above additional frequency dividing circuit is activated, a signal is generated from the VCO using the frequency dividing circuit and the activated additional frequency dividing circuit. Electronic devices.

9. In claim 8, The above processor: Controlling the RF transceiver so that the additional frequency division circuit performs frequency division with a division ratio corresponding to the frequency amount adjusted for AFC (automatic frequency control), Electronic devices.

10. In claim 8, The above additional frequency divider circuit is activated while the PLL circuit is in a locked state. Electronic devices.

11. In claim 8, The above additional frequency dividing circuit is connected between the VCO and the frequency dividing circuit, The above PLL circuit: A comparison circuit configured to output a comparison result between the reference clock signal and the feedback signal, and A converter circuit configured to provide an output voltage corresponding to the above comparison result, Electronic devices.

12. In claim 11, The above additional frequency division circuit is configured to perform a first frequency division on the signal of the VCO, The above frequency division circuit is configured to perform a second frequency division on the result of the first frequency division. Electronic devices.

13. In claim 8, The frequency band of the signal transmitted through the processor, the RF transceiver, the RFFE circuit, and the antenna corresponds to the FDD (frequency-division duplex) band, While the signal is being transmitted, the PLL circuit is configured to provide the LO frequency to the mixer based on the frequency dividing circuit and the activated additional frequency dividing circuit. Electronic devices.

14. In claim 8, A control signal for activating the additional frequency division circuit is transmitted to the RF transceiver via a digital interface for communication between the processor and the RF transceiver. Electronic devices.

15. In electronic devices, A processor comprising a processing circuit; An RF (radio frequency) transceiver including a local oscillator (LO) and an LO leakage detection circuit; A radio frequency front end (RFFE) circuit including a coupler and connected to the RF transceiver; and Including an antenna connected to the above RFFE circuit, The above RF transceiver: In response to a control signal received from the processor, the LO leakage detection circuit is connected to a feedback port electrically connected to a coupler of the RFFE circuit, Through the above LO leakage detection circuit, the LO leakage component is obtained from the feedback signal from the feedback port, It is configured to apply an offset corresponding to the LO leakage component to the DAC (digital-to-analog converter) of the RF transceiver, The above control signal is transmitted when the frequency range of the transmission signal satisfies the specified condition. Electronic devices.

Images