Platform-integrable interconnects for contactless coupling of computer modules

Abstract

Disclosed herein are devices, systems, and methods related to platform-integrable waveguide interconnects for contactless coupling of computer modules / device packages. Such interconnects are formed from a first device package that includes a first contactless coupler, a second device package that includes a second contactless coupler, and a waveguide positioned between the first contactless coupler and the second contactless coupler. The waveguide interconnects provide a cost-effective, efficient, and space-saving connection for communicating signals between the first device package and the second device package.

Description

PLATFORM-INTEGRABLE INTERCONNECTS FOR CONTACTLESS COUPLING OF COMPUTER MODULESTechnical Field

[0001] The disclosure relates generally to connections between electronic device packages such as printed circuit board (PCB) interconnects (PCB to PCB) or system-on-chip (SoC) interconnects (PCB to SoC or SoC to SoC), and in particular, to waveguide-based interconnects that may provide for contactless coupling among computing devices.Background

[0002] In recent years, the computing industry has witnessed a growing trend towards modular devices. From smartphones to desktop computers, modular design has been touted as the future of consumer electronics, offering greater customization, longevity, and sustainability. An exciting development in this space is the emergence of modular laptops, which may change the way the industry thinks about portable computing, offering users unprecedented flexibility and upgradeability.

[0003] While modular design may offer benefits, it may also introduce challenges in the design and engineering process. For example, modular designs may introduce complexities of design, engineering, and compatibility between different modules, all of which may contribute to higher costs. In particular, the cables that typically connect one module to another may be introduce such challenges, as may be seen in today’s desktops and laptops that have interconnecting modules. Today’s laptops and desktops may use layout and stacking techniques to pack more devices, PCBs, SoC, etc. into smaller spaces, but many challenges remain, especially when considering modularity. For example, the formfactor may become relatively thick due to stacking of devices such as large SoCs and graphics processing units (GPU) or other modules, manufacturers may provide too much modularity (e.g., “over-kill” modularity that may not balance price with the extent of modularity), or reliance on expensivecables / connectors that provide high-performance, physical contact interconnects between devices.Brief Description of the Drawings

[0004] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the exemplary principles of the disclosure. In the following description, various exemplary aspects of the disclosure are described with reference to the following drawings, in which:FIG. 1 shows an example computing system from a top view of waveguide interconnects that may be used between components of a computing platform;FIG. 2 shows an example computing system from a cross-sectional side view of waveguide interconnects that may be used between components with a D-cover of a computing platform;FIG. 3 illustrates an example of a waveguide interconnect between two contactless couplers;FIG. 4 illustrates a waveguide interconnect that is integrated into a plastic platform cover and runs between two contactless couplers;FIG. 5 shows an example of a layer stack-up of example D-band horizontal contactless coupler chiplet;FIG. 6 shows an example three-dimensional layout view and overall geometry of the example contactless coupler with the layer stack up of FIG. 5;FIG. 7 shows the area layout of the layers from the cross-sectional view of the example contactless coupler of FIG. 6;FIG. 8 depicts a full simulation mode of a platform with an integrated waveguide interconnect between two horizontal contactless coupler chiplets as well as a simplified model;FIG. 9 depicts comparative S-parameter simulation results for the full simulation platform model and simplified model of FIG. 8;FIG. 10 depicts a simplified model of a side-by-side arrangement of two waveguide interconnects and a pitch between two horizontal contactless coupler chiplets;FIG. 11 shows the S-parameter simulation results for the side-by-side arrangement of FIG. 10;FIG. 12 shows an example of a height variation (e.g., bent in the z axis) along a waveguide interconnect with an 80-mm channel length;FIG. 13 shows the S-parameter simulation results for the waveguide interconnect of FIG. 12;FIG. 14 illustrates an example of a height variation and a width variation (e.g., bent in the z axis and the x-y plane) along a waveguide interconnect with an 80-mm channel length;FIG. 15 illustrates the S-parameter simulation results for the waveguide interconnect of FIG. 14;FIG. 16 illustrates comparative results of the group delay for each of three cases of (i) a waveguide channel with 3-side metal wall bent only in the z axis, (ii) a waveguide channel with 3-side metal wall bent in both the z axis and the x-y plane, and (iii) an optimum waveguide channel with 4-side metal wall bent only in the z axis;FIG. 17 depicts the layouts and dimensions of the waveguide interconnect with respect to its contactless coupler, for each of the cases discussed with respect toFIG. 16;FIG. 18 depicts the comparative S-parameter simulation results for each of the three cases discussed with respect to FIG .17;FIG. 19 depicts the group delay simulation results for each of the three cases discussed with respect to FIG .17;FIG. 20 shows an optimum geometry for an example platform-integrable waveguide design with a 2-side (e.g., top and bottom) metal wall as compared with the 3 -side and the 4-side metal wall cases;FIG. 21 shows the S-parameter simulation comparisons for each of the three waveguide designs of FIG. 20;FIG. 22 shows the Group Delay simulation comparisons for each of the three waveguide designs of FIG. 20;FIG. 23 illustrates two example variants of a three-sided waveguide, where one variant is open on the top or bottom (e.g., U-shaped) and another variant is open on the side (E.g., C-shaped);FIG. 24 illustrates the S-parameter comparisons for each of the variants of FIG. 23;FIG. 25 illustrates the Group Delay comparisons for each of the variants of FIG. 23;FIG. 26 depicts an example of a waveguide channel configuration that transit! ons / tapers between a 3 -sided waveguide and a 4-sided waveguide;FIG. 27 depicts the S-parameter comparisons for each portion of the transitional waveguide channel configuration of FIG. 26;FIG. 28 depicts the Group Delay comparisons for each portion of the transitional waveguide channel configuration of FIG. 26;FIG. 29 shows an example of a multidrop waveguide that feeds connections to two devices from a single coupler that utilizes a waveguide splitter / combiner;FIG. 30 shows an example of a vertical link and an orthogonal link for the connection between coupler and waveguide;FIG. 31 shows a three types of memory interface designs: (i) a conventional memory interface with wired links; (ii) a memory where the wired command / address (C / A) bus has been replaced with a wireless link; and (iii) a wireless interface to a bridge chip;FIG. 32 illustrates an architecture consisting of a point-to-point (P2P) heatsink- integrated wireless inpit / output (WIO) waveguide channel for communicating with memories via a transceiver and wired broadcasting channel;FIG. 33 illustrates an architecture consisting of a P2P heatsink-integrated WIO waveguide channel for communicating with memories via a bridge chip and wired broadcasting channel;FIG. 34 illustrates a block diagram of the architecture depicted in FIG. 33 that may leverage a bridge chip;FIG. 35 depicts an example of a dual P2P heatsink-integrated channel that connects to multiple memories;FIG. 36 depicts an example of a dual P2P heatsink-integrated channel that connects to multiple memories, each via a bridge chip;FIG. 37 depicts an example of a stack-up of an example D-band vertical contactless coupler design;FIG. 38 shows an example of the overall geometry and dimensions for the example of the vertical contactless coupler design with the stack up of FIG. 37;FIG. 39 shows the area layout of the layers from the cross-sectional view of the example contactless coupler of FIG. 38;FIG. 40A shows S-parameter simulation results of the magnitude of the reflection coefficient over frequencies for the vertical contactless coupler design of FIG. 38;FIG. 40B shows a simulated realized-gain, three-dimensional radiation pattern for the vertical contactless coupler design of FIG. 38;FIG. 41 illustrates a simulation result of the power-density flow at 140 GHz for the vertical contactless coupler design of FIG. 38;FIG. 42 illustrates the overall structure and geometry of an exemplary heatsink- integrated waveguide channel design between two vertical contactless couplers;FIG. 43 illustrates the S-parameter simulation results of the exemplary heatsink-integrated waveguide of FIG. 42;FIG. 44 depicts an example of a single-layer wired broadcasting channel for N+J ports;FIG. 45 depicts an example of a single-layer wired broadcasting channel for 7 ports;FIG. 46 depicts the S-Parameter simulation results for the 7 port single-layer wired broadcasting channel design of FIG. 45;FIG. 47 shows an example of a single-layer wired broadcasting channel for 7 ports;FIG. 48 shows the S-Parameter simulation results for the 7 port single-layer wired broadcasting channel design of FIG. 47;FIG. 49 shows a flow chart for a broadcast system that leverages the wireless / RF channel to transmit packets containing an indicator, such as an address, that states that the message is intended either a specific memory or sub-grouping of connected memories; andFIG. 50 illustrates how a broadcast capability may be expanded to enhance the capability of Compute-in-Memory (CiM) and Compute-near-Memory (CnM) within random access memory (RAM) modules.Description

[0005] The following detailed description refers to the accompanying drawings that show, by way of illustration, exemplary details and features.

[0006] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs.

[0007] Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures, unless otherwise noted.

[0008] The phrase “at least one” and “one or more” may be understood to include a numerical quantity greater than or equal to one (e.g., one, two, three, four, [...], etc.). The phrase “at least one of’ with regard to a group of elements may be used herein to mean at least one element from the group consisting of the elements. For example, the phrase “at least one of’ with regard to a group of elements may be used herein to mean a selection of: one of the listed elements, a plurality of one of the listed elements, a plurality of individual listed elements, or a plurality of a multiple of individual listed elements.

[0009] The words “plural” and “multiple” in the description and in the claims expressly refer to a quantity greater than one. Accordingly, any phrases explicitly invoking the aforementioned words (e.g., “plural [elements]”, “multiple [elements]”) referring to a quantity of elements expressly refers to more than one of the said elements. For instance, the phrase “a plurality” may be understood to include a numerical quantity greater than or equal to two (e.g., two, three, four, five, [...], etc.).

[0010] The phrases “group (of)”, “set (of)”, “collection (of)”, “series (of)”, “sequence (of)”, “grouping (of)”, etc., in the description and in the claims, if any, refer to a quantity equal to or greater than one, i.e., one or more. The terms “proper subset”, “reduced subset”, and “lesser subset” refer to a subset of a set that is not equal to the set, illustratively, referring to a subset of a set that contains less elements than the set.

[0011] The term “data” as used herein may be understood to include information in any suitable analog or digital form, e.g., provided as a file, a portion of a file, a set of files, a signal or stream, a portion of a signal or stream, a set of signals or streams, and the like. Further, the term “data” may also be used to mean a reference to information, e.g., in the form of a pointer. The term “data”, however, is not limited to the aforementioned examples and may take various forms and represent any information as understood in the art.

[0012] The terms “processor” or “controller” as, for example, used herein may be understood as any kind of technological entity (e.g., hardware, software, and / or a combination of both) that allows handling of data. The data may be handled according to one or more specific functions executed by the processor or controller. Further, a processor or controller as used herein may be understood as any kind of circuit, e.g., any kind of analog or digital circuit. A processor or a controller may thus be or include an analog circuit, digital circuit, mixed-signal circuit, software, firmware, logic circuit, processor, microprocessor, Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural Processing Unit (NPU), Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA), integrated circuit, Application Specific Integrated Circuit (ASIC), etc., or any combination thereof. Any other kind of implementation of the respective functions, which will be described below in further detail, may also be understood as a processor, controller, or logic circuit. It is understood that any two (or more) of the processors, controllers, or logic circuits detailed herein may be realized as a single entity with equivalent functionality or the like, and conversely that any single processor,controller, or logic circuit detailed herein may be realized as two (or more) separate entities with equivalent functionality or the like.

[0013] As used herein, “memory” is understood as a computer-readable medium (e.g., a non-transitory computer-readable medium) in which data or information can be stored for retrieval. References to “memory” included herein may thus be understood as referring to volatile or non-volatile memory, including random access memory (RAM), read-only memory (ROM), flash memory, solid-state storage, magnetic tape, hard disk drive, optical drive, 3D XPoint™, among others, or any combination thereof. Registers, shift registers, processor registers, data buffers, among others, are also embraced herein by the term memory. The term “software” refers to any type of executable instruction, including firmware.

[0014] Unless explicitly specified, the term “transmit” encompasses both direct (point-to- point) and indirect transmission (via one or more intermediary points). Similarly, the term “receive” encompasses both direct and indirect reception. Furthermore, the terms “transmit,” “receive,” “communicate,” and other similar terms encompass both physical transmission (e.g., the transmission of radio signals) and logical transmission (e.g., the transmission of digital data over a logical software-level connection). For example, a processor or controller may transmit or receive data over a software-level connection with another processor or controller in the form of radio signals, where the physical transmission and reception is handled by radio-layer components such as radio frequency (RF) transceivers and antennas, and the logical transmission and reception over the software-level connection is performed by the processors or controllers. The term “communicate” encompasses one or both of transmitting and receiving, i.e., unidirectional or bidirectional communication in one or both of the incoming and outgoing directions. The term “calculate” encompasses both “direct” calculations via a mathematical expression / formula / relationship and ‘indirect’ calculations via lookup or hash tables and other array indexing or searching operations. References to the TX / RX “chain” or “path” refer to the series of processing steps to convert, modulate, amplify, filter, etc. the data signal to betransmitted (along the TX path) from the antenna or to the series of processing steps to convert, modulate, amplify, filter, etc. the desired signal (along the RX path) that is to be recovered from the received signal at the antenna. References to a “desired” signal refer to the predefined signal that is to be received by the communication device at the prescribed time.

[0015] As noted above, interconnects among computing devices are typically provided by physical, contacting interconnects. In a typical laptop, for example, various PCBs, modules, or SoCs may be connected together using physical cables or other types of wired connections. In some cases, modularity is sacrificed for a single-board design, where the computing devices are not modular. This may mean that there is a poor utilization of the panel due the nature of a large single mother board design that may integrate SoC, GPU, input / out (I / O) devices / connectors (e.g., USB, Thunderbolt, HDMI, audio, etc.). A single-board design may also demand an individual design / layout for each unique platform (e.g., a type of laptop / desktop computer offered (e.g., for each different screen size, each different laptop size, each different target user (e.g., gamers, professionals, content creators, students, etc.))), which may lead to high engineering, design cost, and manufacturing costs. There may also be delays in design changes so as to keep up with evolving technology and consumers’ demands.

[0016] In some cases, modular designs may be used with special interposers and / or connectors to support modularity and flexibility. These special interposers, however, often have a relatively thick formfactor due to the stacking SoC and GPU modules, for example, and may be expensive. In addition, each modular aspect may require its own special interposer, and so price becomes the tradeoff for offering modularity by such specially-designed interposers.

[0017] In some cases, wireless interconnects have been used to connect modular computing boards / devices, where the wireless communication is enabled by a beam steerable transmit and receive antennas to direct the wireless communications. However, such wireless antenna approaches tend to occupy large physical areas in order to achieve a sufficiently narrowbeam, may involve complex transceiver architectures, and may consume a high amount power at the wireless transceiver.

[0018] In some cases, omni-directional antennas have been used to provide a broadcasting wireless interconnect to multiple devices. Such an approach, however, may have a limited communication range due to low radiation pattern directivity and may also provide unreliable communication link performance due to multi-path effects. In addition, such a broadcasting antenna approach may be susceptible to potential spurious interference from other circuits / systems.

[0019] Different from the above listed interconnects, disclosed herein is a waveguidebased interconnect that may provide a cost-effective approach for interconnecting computing device. The disclosed waveguide-based interconnect may utilize dielectric-material-loaded waveguide-based channels. These waveguides may be created from and / or integrated into a laptop D-cover (bottom of laptop, feet surface) and / or C-cover (keyboard surface) of modular laptops, or integrated into other compact computing formfactors. The disclosed waveguidebased interconnect may utilize contactless couplers on devices to be interconnected (e.g. on an SoC module, a discrete graphics module, an I / O module, a PCB, etc.), enabling the interconnected modules to communicate through the integrated waveguide channels. The loading material of the waveguide may be a dielectric with a dielectric constant that is lower than that of the contactless couplers so as to relax the maximum allowed misalignment between the waveguide and the contactless couplers, allowing for greater placement tolerance.

[0020] Overall, the disclosed waveguide interconnects may provide for cost-effective modular laptop / computing designs that may be specialized configurations and tailored to specific market segments or user groups, allow for the development of modular components that cater to the unique needs and preferences of a given customers base / target audience (e.g., gamers, professionals, content creators, students, etc.). The waveguide interconnects may provide better utilization of a laptop panel with smaller modular boards (e.g., an SoC board, adiscrete graphic board, an I / O board (e.g., USB, Thunderbolt, HDMI, audio, etc.) that may be more uniformly shaped than the specialized larger boards with unique shapes, such as an “L” shape, an inverted short “T” shape, or a “multi-leg” shape. This also allows the modules to be on the same plane so that component stacking may not be necessary, leading to an ultra-thin profile. The waveguide channels may support high data rates for each channel, where speeds greater than 150 Gbps may be feasible for the D-band channel with 110 - 170 GHz operational bandwidth, and achievable maximum data throughputs may be proportional to bandwidth. So, if the channel and transceiver support the entire G-band, the data throughputs may increase by three times compared to the D-band case. In addition, the platform-integrable waveguide channels may be easily fabricated and assembled. For an example, the waveguide walled structure (e.g., a three sided wall or U-shaped structure) may be created / extruded as part of the metallic D cover of a laptop, and then a thin plastic thread (e.g. a dielectric) may be inserted into the opening formed by the waveguide walls. While any type of dielectric material may be used, two examples of a dielectric filler are Acrylonitrile Butadiene Styrene (ABS) and Polytetrafluoroethylene (PTFE).

[0021] FIG. 1 shows an example system from a top view (along an x-axis and a y-axis) of how the disclosed waveguide interconnects may be used in an example computing platform. Computing platform 100 includes devices such as a GPU 110 (e.g., a package or PCB) that connects to an SoC 120 (e.g., a package or PCB). There SoC 120 may also connect to other input / output boards / packages (e.g., a USB device, an HDMI device, etc.) such as daughter board 130 and daughter board 140. The interconnects between connected devices (interconnects 115, 125, 135) may utilize contactless couplers and platform-integrated waveguides. FIG. 2 shows a cross-sectional side view along the z-axis and x-axis of computing platform 100 so that its perspective within the D-cover housing may be seen.

[0022] An example of a waveguide interconnect 325 is depicted in FIG. 3. The waveguide of the waveguide interconnect 325 may be formed from at least three walls (e.g., side wall 301,bottom wall 302, and side wall 303 that form a U-shaped structure) that run the distance of separation (e.g., along the x-axis of FIG. 3) between a first device package (e.g., the SoC module) and a second device package (e.g., the GPU module). Each of the device packages may include a contactless coupler (e.g., contactless couplers 331, 332 that is used to feed signals into the waveguide from one device package (e.g., contactless coupler 332 of the SoC module) and to read signals from the waveguide into the other device package (e.g., contactless coupler 331 of the GPU module) or vice-versa, providing for communications among the two device packages over the waveguide. Any of the walls of the waveguide interconnect 325 may be integrated into a metal platform (e.g., a housing / cover of the laptop or computing device in which the electronics are housed).

[0023] The three walls of the waveguide may form a hollow opening that may be filled with a dielectric material as discussed above, or a fourth wall may enclose the waveguide to form a transmission pipe between couplers. As noted above, the dielectric material within the waveguide may be ABS or PTFE or any other dielectric. The dielectric material of the contactless couplers may be higher than the dielectric material of the waveguide, such as glass, which may enable hybrid bonding with a transceiver (TCVR) chip. As noted, at least three walls of the waveguide may be metalized (e.g., leaving an opening in the wall of the waveguide like a U shaped structure), which may be preferable over a fully enclosed waveguide (e.g., with four walls or an enclosed rectangle). This is because a dielectric-loaded four-sided waveguide may have a fundamental TEio mode of which electric fields need to be perpendicular to the direction of power flow. By contrast, a platform-integrated waveguide with three metallic walls that leaves an opening in the waveguide may excite a hybrid mode, meaning that neither the electric fields nor the magnetic fields need to be exactly perpendicular to the direction of the power flow inside the platform-integrated waveguide. This means that the mechanical alignment requirements may be relaxed as between the waveguide and the contactless coupler, and it may also simplify the broadband contactless coupler design.

[0024] As should be understood, while a rectangular profile (e.g., the waveguide has a rectangular cross-section, where in a three-walled form it is open like a U-shape and in a fourwalled form it is enclosed) is shown as an example throughout this disclosure, the waveguide may have any number of walls that form any cross-sectional shape (e.g., circle, oval, square, triangular, trapezoid, rhombus, etc.) that enclose the waveguide or leave it open any number of sides / walls.

[0025] In other cases, when the platform is not metallic or when a four-sided (enclosed) waveguide is desired, the waveguide may be formed with a top wall (e.g., enclosing the U- shape so that it becomes an enclosed rectangle). One such example is shown in FIG. 4, which depicts an example of a waveguide interconnect 425 that is integrated into a plastic platform cover. In this case, a side wall 401, a top wall 402, and a side wall 403 form a three-sided waveguide, which may be integrated into the platform cover using a offset 404 (e.g., a dielectric / plastic (e.g., integrated into the platform cover)) that are coated with metal to form the side wall 401, top wall 402, and side wall 403 of the waveguide. This means that the “opening” in the waveguide may be filled with a dielectric material of the offset 404. As should be understood, the height of the offset 404 and or an additional “leg” or “pillar” may be sized so as to align the waveguide with the contactless couplers 431, 432.

[0026] FIG. 5 shows an example of a layer stack-up of example D-band (110 - 170 GHz) horizontal (end-fire) contactless coupler design. Although the design example is based on a glass core with panel-level fabrication design rules (e.g., Intel™ Laurentide design rules), other cores, such as silicon and organic substrates, may be used to implement the coupler architecture. The stack-up in FIG. 5 shows two redistribution layers (RDLs) on both the bottom and on the top of the glass core, but as should be appreciated, these may be asymmetric (e.g., a different number of layers above the core as is below the core). The substrate thickness of RDLs may be ranged from a few microns to -200 pm, depending on the fabrication process type (e.g., wafer-level fabrication, panel-level fabrication, PoP (package on a package) with BGA / CSP,etc. As should be understood, the layer thicknesses (including the RDLs) shown in FIG. 5 are merely exemplary. In addition, the metal thickness may be thicker than the skin depth at the lowest operational frequency of the coupler. FIG. 6 shows a three-dimensional layout view and overall geometry of the example D-band horizontal contactless coupler design with the layer stack-up of FIG. 6. FIG. 7 shows the area layout of the layers from the cross-sectional view of FIG. 6. LI and L4 are ground layers. The circles in the other layers indicate locations of vias that penetrate through the layer (either as a blind via or as a through-hole via, where there is a a single BGV in the middle of TGV that is larger than the other through-hole vias). As can be seen in L3, a feed line (in the middle of L3) and surrounded by ground (e.g., forming a coplaner waveguide) may excite a blind via, as discussed below.

[0027] With reference to FIGs. 5, 6, and 7, the horizontal contactless coupler architecture includes a pattern of through-glass vias (TGVs), blind glass vias (blind GV or BGV), and ground (GND) metal layers with voids. TGVs may used to create a tapered reflector structure for enabling ultra-wideband impedance match and a GND fence of vias for directing energies toward the open-end of the coupler. The blind glass via may be fed by a planar transmission line (or any other type of feed such as a microstrip line, a stripline, a co-planar waveguide (CPW) feed, etc.). The CPW may excite the three-dimensional energy-coupling aperture outlined by the TGVs and GND planes. This coupler may be referred to as glass-based contactless coupler chiplet and, as discussed in more detail below, may be horizontal or vertically oriented.

[0028] A glass-based horizontal contactless coupler chiplet may be integrated with a TCVR chip by using hybrid bonding, direct bonding, or other bonding methods. The glassbased contactless coupler chiplet may be located on the package of an SoC, GPU, and / or directly on a PCB to couple to a corresponding platform -integrated waveguide.

[0029] The waveguide may be formed as a straight channel, bent channel, curved channel, or any other type of shape or combination of shapes. A 4 mm straight channel, platformintegrated waveguide interconnect was simulated to show a proof of concept, where the waveguide interconnect was integrated into a metallic platform with a PCB / package below horizontal contactless couplers, as shown in simulated platform 800 of FIG. 8. Given that the full model of the simulated platform 800 may require extensive computing resources due to the electrical size of the model at sub-THz band, a simplified model 801, as shown in FIG. 8, was also considered.

[0030] The comparison simulation results are shown in FIG. 9, which indicates that the magnitude of the reflection coefficient at the contactless coupler feed and the channel loss between the full model of simulated platform 800 and the simplified model 801 are close to each other. The results indicate not only that the simulation resource reduction with the simplified model 801, but the results also show that a platform-integrated waveguide along with horizontal contactless couplers is resilient to boundary conditions (e.g. distance from plastic or metallic platform) and proximity environment variations, such as package / PCB shape, size, and material properties. This resilient capability is strongly referred characteristics to support various modular-platform application scenarios with minimum number of platform-specific designs configurations (e.g., stock-keeping-unit numbers or SKUs).

[0031] A D-band (110 - 170 GHz) transceiver may support > 150 Gbps for each cannel with 60-GHz bandwidth and < 25-dB insertion loss (channel loss). The platform-integrable channel may not only offer >60-GHz bandwidth, but it may also support data aggregation by placing platform-integrable channels side by side as an array form as the crosstalk between two adjacent channels may be below 35 dB. See FIG. 11, which shows simulated S-parameters for the side by side arrangement shown in FIG. 10.

[0032] As illustrated in FIG. 2, the VO modules may be located at higher z location than an SoC module in a laptop D cover because I / O ports are often located around half of the D cover height. To describe potential performance degradation due to the height variation (bent in z axis) over the platform-integrable channel, an 80-mm channel length example as shown inFIG. 12. FIG. 13 shows simulation results for the example of FIG. 12, which shows that the channel loss for an 80-mm platform-integrated channel including horizontal contactless couplers may be less than 13.25 dB (>10-dB margin to support 150 Gbps throughputs with D- band transceiver). Reflection bandwidth is approximately 80 GHz (100 - 180 GHz).

[0033] An additional example is shown in FIG. 14 for a platform-integrable 80-mm bent channel in both z-axis and x-y plane with horizontal contactless couplers. This example supports the platform integrable channel for the communication between SoC and VO modules which are not only at the same z location on the D cover than the location of the SoC module, but there are also offset distances between I / O modules and SoC module in x and y directions. Simulation results for FIG. 14 are shown in FIG. 15, which shows that the channel loss for an 80-mm platform -integrated channel including contactless couplers may be less than 13.25 dB (>10-dB margin to support 150 Gbps throughputs with D-band transceiver). Reflection bandwidth is approximately 80 GHz (100 - 180 GHz). These results are very similar to the case with channel bent only in the z axis. Group-delay comparison for different types of 80- mm bent channels is also made for the following cases to understand the overall channel quality. Case l is a waveguide channel with 3-side metal wall bent in z axis only; Case 2 is a waveguide channel with 3-side metal wall bent both z axis and x-y plane; Case 3 is an optimum waveguide channel with 4-side metal wall bent in z axis only. The layouts for each of these cases are illustrated in FIG. 17, while FIG. 16 depicts the comparative results of the group delay for each case.

[0034] As sown FIG. 16, the group delay slope over frequencies for Cases 1 and 2 (3 -side metal wall supporting hybrid mode) are lower than that of Case 3 (4-side metal wall supporting TE10 mode). In fact, it is observed that the group delay curve of the Cases 1 and 2 over D band range (110 - 170 GHz) varies in quasi-linear fashion. This is because the cut-off frequency of the hybrid mode with 3-side metal wall may be more than 10 times lower than that of the TE10 mode with 4-side metal wall. These results not only indicate that the proposed platform-integrable channel support various channel bending scenarios, but also implies that the proposed channel can be resilient to manufacturing and assembly variations in a high volume manufacturing (HVM) process. This benefit may also be preferred for modular laptop applications in terms of cost reduction because mechanical design tolerance and assembly tolerance may be relaxed.

[0035] It may be desirable to make the dielectric constant of the loading material in the platform-integrated waveguide lower than that of the contactless coupler’s substrate material. For example, consider the sr(relative permittivity) of the contactless coupler substrate is lower than the srof the dielectric material filling the platform-integrated waveguide. In this way, the cross-section area of the platform-integrated waveguide is larger than aperture area of the contactless coupler. Thus, coupling loss between the contactless coupler and the platform- integrated waveguide almost remains same when the aperture area of the contactless coupler moves within the cross-section area of the platform-integrated waveguide. This feature may be preferred for modular platforms because this feature offers enhanced mechanical and coupling tolerance for misalignment between the contactless coupler and the platform-integrable waveguide.

[0036] In addition, optimum cross-section area dimension of a platform-integrated waveguide with 3-side metal wall (hybrid mode) may be larger than that of a waveguide with 4-sided metal walls (rectangular TE10 mode) due to imposed boundary condition differences. Therefore, misalignment tolerance range of a platform-integrated waveguide with 3-side metal wall may be higher than that of a waveguide with 4-side metal wall.

[0037] The three cases discussed above are depicted in FIG. 17, and each of these cases is considered below. Case 1 represents an optimum geometry of a platform-integrable waveguide with 3-side metal wall. The contactless coupler is located at 439-pm offset distance from the center of the waveguide. Case 2 represents an optimum geometry of platform-integrable waveguide with 4-side metal wall. Its overall dimension is smaller than that of Case 1, meaningthat it has an approximately 19.4% aperture area reduction. The contactless coupler is located at 198-pm offset distance from the center of the waveguide. Case 3 represents an enclosed waveguide covering all 4 sides of the Case 1 waveguide with metal. The corresponding offset distance is the same as the Case 1 distance, i.e. 439-pm.

[0038] The comparison simulation results for 80-mm channel length are shown in FIGs. 18-19, which show that reflection bandwidth of all 3 cases is approximately 80 GHz (110 - 180 GHz). However, the operational bandwidth of Case 3 is practically limited to ~ 30 GHz due to the fluctuating channel magnitude above 130 GHz while Cases 1 and 2 support more than 60 GHz operational bandwidth. In fact, Case 1 (3 -side metal wall supporting hybrid mode) can support > 60 GHz due to the relaxed bound conditions and a lower (e.g., ten times lower) cut-off frequency, compared to Case 2. The maximum misalignment range for the Case 1 is approximately + / - 400 pm while that of Case 2 is approximately + / - 200 pm.

[0039] The simulated group delay comparison in FIG. 19 supports the observations made from the S-parameter simulation comparison. In particular, the group delay variation over frequencies of Case 3 is dispersive out of the ~ 30 GHz operational bandwidth (100 - 130 GHz), meaning that effective operational bandwidth (or corresponding data throughputs) of the Case 3 may be significantly impacted by the offset distance. Although offset distance comparison is demonstrated only in channel width, it can be shown that similar observations can be made with offset distance variation in channel height. On the other hand, the lowest operating frequency of the Case 1 may be further lowered because the group delay below the lowest frequency of reflection bandwidth (approximately 100 GHz) varies smoothly.

[0040] FIG. 20 shows an optimum geometry of example platform-integrable waveguide design with a 2-side (e.g., top and bottom) metal wall as compared with the 3-side and the 4- side metal wall cases. As number of metallic walls decreases, channel loss slightly increases while misalignment impact decreases, i.e. channel loss and misalignment impacts are in tradeoff relationship. In addition, dominant mode of the 2-side metallic waveguide is quasi-TEM,which would impose further alignment constrains in Z-axis dimension because both electric and magnetic fields need to be orthogonal to the direction of power flow inside the waveguide. There is almost zero margin to the left in the z-axis direction for misalignment along the z-axis, as may be seen in FIG. 20. Of the three cases, it is the most vulnerable to misalignment impact.

[0041] In terms of vertical contactless coupler perspective, the 2-side metallic waveguide may face difficulties to get coupled from the vertical contactless coupler. In addition, the 2- side metallic waveguide case may be exposed to various challenges in terms of high volume manufacturing (HVM), assembly, and communication reliability perspectives. Nevertheless, the waveguide with a 2-side metal wall may have the smallest formfactor and superior performance (e.g., lowest channel loss and flat group delay over entire D band due to the nature of quasi-TEM mode excitation), as shown in FIG. 21 (S-parameter comparison) and FIG. 22 (group delay comparison). Although resilience to misalignment and channel performance / aperture size may have a trade-off relationship, the platform-integrable channel with 3-side metal wall may be the optimum configuration for modular laptop applications.

[0042] A platform-integrable channel with 3 -side metal wall may have at least two variants, one where the top is open and one where the side is open, as is shown in FIG. 23 with each variant’s overall geometry and dimensions. In a sense, the side-open platform-integrable channel with 3-side metal wall may have similar z-axis-related constrains that waveguide channel with 2-side metal wall may have, as noted above. In addition, the side-opening type may also have additional constrains due to the added vertical metal wall and asymmetrical boundary conditions. However, the side-open channel may have applications were the unique configuration and boundary conditions may be leveraged. Simulated S-parameters and group delay are shown in FIGs. 24-25, respectively.

[0043] In the variant where the top side of the platform-integrable waveguide channel with3-side metal wall is open, the channel performance may be impacted when a metal structure or component is too close to the open wall side. To prevent loss of channel performance, theadvantages of both a 3-sided channel (advantage: hybrid mode, strong resilient to misalignment) and a 4-sided channel (advantage: TEw mode, best link performance with relatively flat group delay over entire D band) may be realized by connecting both types through a transition section (e.g., transition section 1 and transition section 2). Thus, the open area size of the channel may be minimized. The overall geometry and dimension of an example channel waveguide configuration that transitions between a 3 -sided waveguide and 4-sided waveguide are shown in FIG. 26. Corresponding, simulated S-parameter and group delay results are shown in FIG. 27 and FIG. 28, respectively.

[0044] FIG. 29 and FIG. 30 each show additional examples of the connections between waveguide and coupler, where FIG. 29 shows a multidrop waveguide that feeds connections to two devices from a single coupler that utilizes a waveguide splitter / combiner. FIG. 30 shows an example of a vertical link and an orthogonal link for the connection between coupler and waveguide.

[0045] Considering applications of the disclosed platform integrated waveguide and couplers discussed above, memory devices may have particular interest. The demand for higher bandwidth per shoreline (BW / mm) memory interface has been increasing due to the need for high bandwidth to integrate more cores, graphic processors, and memory chiplets through a heterogeneous three-dimensional integrated circuit (3D-IC). Increasing the bandwidth per shoreline of the memory interfaces, such as in a low power double-data rate (LPDDR) memory, a double data rate (DDR) memory, and / or a high bandwidth memory (HBM), may have significant technical challenges due to the current 3D-IC designs. Reducing the memory interface shoreline may enable the use of a smaller die with a higher yield and lower cost. For example, current state-of-the-art Al accelerators heavily relies on expensive HBMs. It may be advantageous, then, to replace the HBMs with lower-cost LPDDRs. However, the limited bandwidth of LPDDRs (or limited available SoC shoreline) may be one of the key challengesin such a replacement because many LPDDR channels may need to be added in order to match the HBM bandwidth.

[0046] Employing a wireless interface between SoC and LPDDR may offer a potential solution for increasing bandwidth and meeting the system’s bandwidth requirement by creating a dedicated wireless channel for memory command / address (C / A) signals, as illustrated in FIG. 31, which shows: a conventional memory interface with wired links, containing full- duplex high-speed buses (DQ’s) and one-way command / address (C / A) buses; a memory where the wired C / A bus has been replaced with a wireless link to reduce pin count; and a memory where a bridge chip has been used to provide Joint Electron Device Engineering Council (JEDEC) standard compatibility, where the bridge chip may locally convert wireless C / A signals to wired C / A bus to each LPDDR module to reduce the congested PCB routing. Approximately 20% shoreline reduction may be possible with a wireless approach. Unfortunately, in real-world scenarios, the wireless link channel may not only suffer from narrow operational bandwidth, but the channel may also become dispersive due to scatterings (and reflections) from edges (and boundaries) of SoCs, packages, and LPDDRs. In addition, the wireless channel characteristics may noticeably change based on the floor plan or layout on the platform PCB, which may demand robust wireless communication capability support.

[0047] Existing solutions to such issues may be insufficient. Current wired HBM / DDR / LPDDR memory interfaces may not be able to increase the bandwidth per shoreline of the memory interfaces involves due to the conventional 3D-IC designs. This would require larger die area with high yield and lower cost, which may not be feasible. In wireless broadcasting approaches, an antenna may broadcast memory C / A signals to all LPDDRs on the same PCB side where SoC is located and may achieve ~10 GHz impedance bandwidth. However, wireless broadcasting channel may be dispersive due to scatterings (and reflections) from edges (and boundaries) of SoCs, Pkg, and LPDDRs. In a heterogenous approach using a point-to-point (P2P) wireless “domino” channel (e.g., where the directive beam may mimic a pencil-beam) 1and a wired broadcasting channel, the P2P may provide up to 100 mm in D band (110 - 170 GHz), have a multi-drop range < 100 mm, depending on the number of “drops,” have a relatively narrow operational bandwidth (<45 GHz), and not have flushed channel.

[0048] Another option may be a contactless extended multidrop / broadcast channel, which involves a near-field (NF) antenna, a gap, an NF antenna, a transmission line, an NF antenna, a gap, and an NF antenna. The multidrop / broadcast channel may have a demonstrated data rate of 3 Gbps with 64 quadrature amplitude modulation (QAM), a demonstrated coupler reflection bandwidth of up to 260 MHz, and may be particularly useful for an operational frequency below 30 GHz. However, these may be potentially vulnerable to signal dispersion and distortion due to severe reflections, scatterings, and cavity resonances when PCB and channel are enclosed by heatsink.

[0049] Another option may be a heterogeneous network-on-chip (NoC) technique, where the intra-NoC may have a hybrid switching (e.g., circuit plus packet) between caches and memory controllers in an on-chip mesh network. The inter-NoC may have a wireless network accessing off-chip memory through the same-frequency channel using 60-GHz omnidirectional loop antennas (e.g., a 25 GHz bandwidth and 5 ns of worst-case dispersion). These have been demonstrated to operate at 195.36 Gbps with orthogonal frequency-division multiplexing (OFDM) scheme and 64-QAM. Implementing a hybrid switching mechanism and integrating off-chip wireless links may, however, introduce additional complexity to the system design and ensuring seamless coordination between different switching modes and managing wireless communication may also be challenging. In addition, the inclusion of wireless components and specialized switching mechanisms may increase the overall cost of the system. Designing and manufacturing such components may also be expensive. Moreover, this technique may be vulnerable to signal distortion due to severe reflections, scatterings, and cavity resonances when the system with omni-directional antennas is enclosed by a heatsink.

[0050] As discussed in more detail below, the disclosed contactless coupler with an integrated waveguide interconnect (e.g., a contactless vertical coupler, heatsink-integrated channel, and a wired or wireless broadcasting channel) may address some of the above- mentioned real-world challenges in employing a wireless channel between SoC and memory, enabling a cost-effective LPDDR-based Al accelerator. The design may consist of a P2P heatsink-integrated wireless input / output (WIO) waveguide channel, a “bridge” chip (e.g., for optional JEDEC support), and an optional wired (or wireless) broadcasting channel to the memories. The P2P heatsink-integrated WIO channel may leverage glass-based vertical (e.g., broadside) contactless couplers. The “bridge” chip may recover the received signals from P2P heatsink-integrated WIO channel in terms of strength and quality, and then retransmit the signals to each LPDDR modules through the wired broadcasting channel so that they may be compatible with a standard such as JEDEC. Approximately 20% shoreline reduction may be possible by replacing memory command / address bus with a cost-effective heterogeneous chip- to-chip channel.

[0051] The disclosed contactless coupler with an integrated waveguide interconnect may provide for a cost-effective LPDDR-based Al accelerator. It may also increase system bandwidth by 20% and overcome shoreline / PCB routing limitation by replacing the memory command / address (C / A) bus with heterogeneous contactless communication links over integrated waveguides. It may also reduce the loading effect of memory C / A bus and may run faster and independent of the number of memory banks. It may also reduce package pinout / routing and PCB routing. In may also support a broadcast mode so that it may communicate memory bus status and any SoC message, such as wakeup signal, may be very fast. The broadcast mode for command / address signals may be used for distributed additional compute-in-memory (CIM) command, such as sort and find. In addition, support memory or CIM-initiated transmit, return, write, and interrupt may be possible with bidirectional interconnects. It may implement a more robust instruction set, including CIM instructions. Itmay address challenges in minimizing delay differences between traces within the congested routing area (e.g., a single platform-integrable channel may effectively be equivalent to many signal traces).

[0052] The disclosed contactless coupler with an integrated waveguide interconnect may have an architecture consisting of a P2P heatsink-integrated WIO waveguide channel for communicating with memories via a transceiver and wired broadcasting channel (e.g., FIG. 32) or via a “bridge” chip connected to a wired broadcasting channel (e.g., FIG. 33). The P2P heatsink-integrated WIO waveguide channel may leverage a glass-based vertical (e.g., broadside) contactless coupler (e.g., a chiplet). The glass-based contactless coupler chiplet may be integrated with an SoC, memory module, and / or “bridge” chip (e.g., a non-monolithic die complex, using hybrid bonding, direct bonding, or other bonding methods).

[0053] The signals from the P2P heatsink-integrated WIO channel may be coupled to a vertical contactless coupler on memory module (as shown in the example of FIG. 32) or a vertical contactless coupler on “bridge” chip (as shown in the example of FIG. 33). The transceiver on memory module or “bridge” chip amplifies the received signals from the P2P heatsink-integrated WIO channel, converts the received RF signals to baseband signals, and broadcasts the converted baseband signals to each memory module through the wired broadcasting channel. The signal path through “bridge” chip may provide compatibility with the JEDEC standard or other wired protocols. A block diagram of the architecture that may leverage a “bridge” chip is depicted in FIG. 34.

[0054] The architectures using a single P2P heatsink-integrated channel may be easily extended to support dual P2P heatsink-integrated channel case without loss of generality. The signals from the vertical contactless coupler may be coupled to two P2P heatsink-integrated channels simultaneously, examples of which are shown in FIGs. 35 and 36. In such a manner, the SoC may reach to memory modules located at both ends of PCB. In addition, the JEDEC-compatible one-way communication of C / A signals between SoC and memory modules may be expanded with bi-directional communication support.

[0055] The stack-up and overall geometry of an example D-band vertical (e.g., broadside) contactless coupler design is shown in FIGs. 37 and 38. Although the design example is based on glass core with wafer-level fabrication design rules, other cores, such as silicon and organic substrates, may be used to implement the proposed coupler architecture. The vertical contactless coupler of the example shown in FIGs. 37 and 38 contain two separated “E”-shaped metal polygons at the surface metal layer (LI). Each “E”-shaped metal polygon is electrically shorted to the GND metal layer (L2) through two thru vias. These thru vias on top and bottom connect to the prongs of the E on the top and bottom, but not the middle prong. A gap exists between the two separated “E”-shaped metal polygons that face each other, and the gap together with the spacing between prongs of the E’s acts as a zig-zag slot and it is excited from an “H”- shaped slot (void) at the L2 GND layer. The “H”-shaped slot is excited from a feed transmission line with a stub at the below metal layer (L3). A detailed layout of the exemplary D-band vertical contactless coupler design is depicted in FIG. 39.

[0056] A simulation of the magnitude of the reflection coefficient over frequencies is shown in FIG. 40A, where the example design supports 72-GHz operational bandwidth (or 53.6% fractional bandwidth). As should be understood, the operational bandwidth may increase as the antenna / coupler substrate height increases. However, the overall electrical height of the example design may be approximately 1 / 8 or 0.125 guided- wavelength at the lowest end of the operational frequency range (103.6 GHz), which may provide for an extremely low profile, compared to 0.25 guided- wavelength of electrical height of conventional slot antennas. The simulated realized-gain 3-D radiation pattern for this example is shown in FIG. 40B, where there is a peak of 4.48 dBi, which indicates that the example vertical coupler design for D band may be efficient in terms of coupling and / or radiation. FIG. 41 shows a simulation of power-density flow at 140 GHz, which indicates that dominant radiation occursfrom edges of the slot (gap) between the two “E”-shaped, facing polygons, mirrored around x- axis. Thus, the example D-band vertical coupler design may have quite different radiation patters from that of conventional E-path antenna and variants. This example D-band vertical coupler design may accommodate wafer-level fabrication rules, and thus may be able to provide the efficient coupling and ultra-wideband operation, which allows non-monolithic die complex integration.

[0057] An overall structure and geometry of an exemplary heatsink-integrated channel design with the D-band vertical contactless couplers are illustrated in FIG. 42, where a view 4220 of one of the vertical contactless couplers is zoomed-in in view 4220z. Cost-effective ABS material, PTFE material, or other dielectric material may be inserted between metallic rails and serve as dielectric loading material. Together with the metal plane of the heatsink, the ABS thread between the metal rails forms a dielectric-loaded waveguide having 3-side metal wall, similar to those discussed above. The rectangular proximity area surrounding the channel may be voided (cut out) to minimize channel insertion loss. Alternatively, the void area may be filled with a perforated dielectric (e.g., a perforated ABS material) to lower the dielectric constant (e.g., close to that of air at 1.0) and the resulting channel design may be flush, meaning that the integrated channel may be in the same plane as the adjacent surface of the heatsink. Thus, the channel may be protected from potential damage. In this case, the dielectric-loading ABS (e.g., the original dielectric constant) and perforated ABS (e.g., the lower dielectric constant for more efficient coupling between the contactless coupler and the channel) materials may be formed a single body / unit, which may make the assembly process easy and cost- effective.

[0058] Simulated S-parameters of an example of a 50-mm heatsink-integrated channel with vertical contactless couplers is shown in FIG. 43, indicating that the channel supports the entire D-band (110 - 170 GHz, 60-GHz channel bandwidth) with < 21.25-dB insertion loss. When a formfactor such as a peripheral component interconnect express (PCIe) type of PCB isconsidered, a 50-mm channel length may be the maximum P2P channel length, due to PCIe constraints. If used in a D-band radio, it may be able to support > 150 Gbps data throughput for < 25 dB channel loss.

[0059] The wired broadcasting channels, such as the conventional D-band design having a generally circular shape may be used to support the proposed heterogeneous chip-chip interconnect architecture. A single-layer wired broadcasting channel, an example of which is shown in FIG. 44, may be an alternative to conventional designs. The example structure may be further optimized (e.g., used as a seed structure and then optimized) to suit the particular application, the particular number of ports, the desired frequency band, etc. Examples of such resulting designs, optimized for DC - 170 GHz bandwidth, are shown in FIG. 45 and FIG. 47.

[0060] Considering signal routing congestion challenges between SoC and memory modules, broadcasting output ports, Port 2 - Port N+l, would be located toward edge of PCB to avoid the congestion. Especially ports closest to the PCB edge would get connected to memory modules on the backside of PCB while ports close to the perpendicular direction of input port (Port 1) would be routed to memory modules on the frontside of the PCB. Thus, the overall shape of the single-layer wired broadcasting channel in FIG. 44 may offer a simple and area-efficient broadcasting signal routing layout.

[0061] The single-layer wired broadcasting channel may have one bigger elliptical hole (void, cut-out) aligned with input (Port 1) and multiple smaller elliptical holes angled and aligned with outputs (Port 2 - Port N+l). Basically, one smaller elliptical hole is located between output port pairs. Because an analytic design solution does not exist, the elliptic hole sizes and the offset locations may be determined through global optimization approaches, such as genetic algorithm (GA), particle swarm optimizations (PSO), and / or covariance Matrix adaptation (CMA) evolutionary strategy through electromagnetic simulations.

[0062] Geometry of an example single-layer wired broadcasting channel design for broadcasting ports N = 6 (total number of ports = N + 1 = 7) is shown in FIG. 45. Notice thatthe smaller elliptical holes are combined. S-Parameter simulation results are shown in FIG. 46 for the 7 port single-layer wired broadcasting channel design of FIG. 45 and indicate that the example design may support DC to 170 GHz of the extremely broad operational frequency range. Notice that theoretical insertion loss (= — 10 * log10[l / 7V]) of 6-port broadcasting channel is about 7.78 dB for loss-free transmission line. The result suggests that the insertion loss of the output ports (Port 2 - Port 7) from DC to 40 GHz is observed as about 8.44 dB, which is very close to the theoretical loss. On the other hand, insertion loss for D band varies within maximum 1.5 dB from the insertion loss of DC to 40 GHz range, which is also an excellent result. Thus, practical operational bandwidth of the example single-layer wired broadcasting channel may be considered as DC to 170 GHz. If desired, the relatively-flat insertion loss response may be obtained for band-limited cases (e.g., in the D band from about 110 to 170 GHz).

[0063] A further example of another geometry is shown in FIG. 47. Unlike the previous example, all elliptical holes are merged, and a single large polygon open aperture (hole) is created inside the channel design. Notice that angles between Ports 2 and Port N are significantly reduced as compared to the previous example. Simulation results for this design are shown in FIG. 48, which show that the insertion loss of the output ports (Port 2 - Port 7) from DC to 40 GHz is about 8.34 dB, which is slightly lower than the previous example and even closer to the theoretical loss. In addition, D-band channel loss only varies within maximum 0.5 dB. Therefore, overall channel insertion loss of this additional example over DC to 170 GHz may be quite flat. As a potential disadvantage if the entire operational frequency range (DC to 170+ GHz) is used, the example of FIG. 47 may demand more routing area. This is because a curved signal routing transmission line may require a signal trace with a larger radius for mmW / sub-THz frequencies. In addition, the example of FIG. 44 already accounted for the angles needed for the curved signal trace. Thus, no noticeable extra routing area in that cases is needed, but it comes with an extra 1-dB channel loss at D band. The overall footprintof the single-layer wired broadcasting channel, including curved signal traces, as compared to channel loss exhibit a tradeoff relationship.

[0064] The architectures described heretofore may be implemented in many different ways using die-to-die links in larger package form factors, off-package links between two packages, PCB to PCB links, or a combination thereof. Off-package links between two packages may provide short package to package links, enable package disaggregation (e.g., breaking a large package into two more smaller packages and leveraging top side contact to augment bottom side wired package to package links). Off-package links between two packages may also provide longer package to package links so as to alleviate the PCB congestion problem by using the chassis as part of the channel, passing the PCB. An example of a PCB (module) to PCB (module) link, for example, may be direct attachment of a radio frequency integrated circuit (RFIC) and coupler die on the PCB to provide a cableless channel between two PCBs. An example of a combination of techniques is a die in the middle of the package to RFIC / coupler on a PCB: a link, for example, between an SoC package and a horizontally-placed memory module (e.g. a DIMM). In addition, the channel may be integrated not only into the housing / chassis, but also to the heatsink, cooling pipes, etc. to become part of the whole thermal solution.

[0065] When contactless coupler waveguide links are used to support an SoC -memory architecture, which contains a point-to-point wireless link between an SoC and a bridge Chip that utilizes wired memory interfaces such as those interfaces according to the standards provided by JEDEC, a broadcasting capability may still be possible. The broadcasting capability may leverage the wireless / RF channel to transmit packets containing an indicator, such as an address, that states that the message is intended either a specific LPDDR memory or to be broadcast to all or a sub-grouping of the connected LPDDR memories. FIG. 49 shows a flow chart of how such a broadcast may operate.

[0066] Given that Artificial Intelligence (Al) and Machine Learning (ML) applications tend to be inherently data-intensive, with compute and memory requirements growing significantly year over year, parameter sizes may easily exceed hundreds of billions of parameters. As a result, memory and input / output (VO) bandwidth have struggled to keep pace with compute and memory requirements, leading to bottlenecks that may significantly hamper performance. Compute-in-Memory (CiM) and Compute-near-Memory (CnM) have become typical hardware candidates for accelerating the execution and training of ML models because it allows sidestepping this bottleneck. Recently, the Memory Industry has proposed adding custom instruction extensions to HBM DRAM to enable CiM and CnM functionality within RAM modules.

[0067] Building upon the broadcast capability, as shown in FIG. 50, the broadcast capability may be expanded to enhance the capability of the CiM and CnM functionality within RAM modules. For memory with wired links (on the leftmost side of FIG. 50), the SoC cannot issue CiM / CnM commands to multiple memory modules in parallel. With a direct wireless connection (in the middle of FIG. 50) on the C / A bus, this may enable highly parallelizable commands to be executed simultaneously across multiple chips, which may significantly increase the throughput for most Al workloads. Similarly, employing a dedicated bridge chip (on the rightmost side of FIG. 50) may allow for broadcast behavior while maintaining compatibility with the JEDEC standard or other wired memory standards. Another benefit of adding broadcast behavior to CiM / CnM enabled RAM modules is that by moving the processing from the SoC to the memory module, there may be a significant reduction in the total required memory bandwidth (e.g., the CiM / CnM linear algebra operations comprise 80- 90% of the compute in a typical Al or neural network application), allowing a further reduction in the required number of DQ lines.

[0068] In the following, various examples are provided that may include one or more features of the contactless coupler and waveguide interconnect discussed above. It may beintended that aspects described in relation to the devices may apply also to the described method(s), and vice versa.

[0069] Example 1 is a device including a first device package including a first coupler; a second device package including a second coupler; and a waveguide positioned between the first coupler and the second coupler to communicate signals between the first device package and the second device package.

[0070] Example 2 is the device of example 1, wherein the first device package or the second device package includes a printed circuit board (PCB) or a semiconductor chip package.

[0071] Example 3 is the device of example 2, wherein the waveguide includes a three sided structure that forms an opening along the waveguide.

[0072] Example 4 is the device of example 3, wherein the opening extends along the waveguide from the first device package to the second device package.

[0073] Example 5 is the device of any one of examples 1 to 4, wherein the waveguide includes an enclosed structure.

[0074] Example 6 is the device of any one of examples 1 to 5, wherein the waveguide has a rectangular cross-sectional profile.

[0075] Example 7 is the device of any one of examples 1 to 6, wherein an interior of the waveguide is filled with a dielectric material.

[0076] Example 8 is the device of any one of examples 1 to 7, wherein the waveguide is spaced apart from the first coupler at a first distance and the waveguide is spaced apart from the second coupler at a second distance.

[0077] Example 9 is the device of any one of examples 1 to 8, wherein the waveguide is metallic (e.g., includes a metallic wall, is a metallic block, or is formed with a metallic coating).

[0078] Example 10 is the device of any one of examples 1 to 9, wherein the first coupler or the second coupler includes a horizontal contactless coupler chiplet.

[0079] Example 11 is the device of any one of examples 1 to 10, wherein the horizontal contactless coupler chiplet includes a core and a horizontal layer stack.

[0080] Example 12 is the device of example 11, wherein the core includes a material with a relative permittivity value in a range from about 2 to 200 (e.g., silicon, alumina, glass, LTCC (low temperature co-fired ceramic), or HTCC (high temperature co-fired ceramic), etc.) and a thickness in a range from about one-twelfth of a guided wavelength of the waveguide to about equal the guided wavelength.

[0081] Example 13 is the device of any one of examples 11 to 12, wherein the horizontal layer stack includes a first layer stack that is stacked above the core and a second layer stack that is stacked below the core.

[0082] Example 14 is the device of any one of examples 11 to 13, wherein the horizontal layer stack includes alternating layers of a substrate layer and a metal layer.

[0083] Example 15 is the device of example 14, wherein the substrate layer includes one or more voids therein.

[0084] Example 16 is the device of and one of examples 14 to 15, wherein each layer of the horizontal layer stack has a thickness of about 4 micrometers.

[0085] Example 17 is the device of and one of examples 14 to 16, wherein each layer of the horizontal layer stack has a thickness of about 15 micrometers.

[0086] Example 18 is the device of and one of examples 13 to 17, wherein one layer of the first layer stack and one layer of the second layer stack each are about 25 micrometers thick, wherein other layers of the first layer stack and other layers of the second layer stack each are about 15 micrometers thick.

[0087] Example 19 is the device of any one of examples 11 to 18, wherein the horizontal contactless coupler chiplet further includes: a blind via within the core fed by a planar transmission-line (e.g., a microstrip line, a stripline, a co-planar waveguide feed port, etc.); and through-hole vias that penetrate through the core.

[0088] Example 20 is the device of example 19, wherein the planar transmission line is configured to excite an energy coupling aperture outlined by the through-hole vias.

[0089] Example 21 is the device of any one of examples 11 to 20, wherein the core has a relative permittivity that is greater than a relative permittivity of a dielectric material in the waveguide.

[0090] Example 22 is the device of any one of examples 1 to 21, wherein the waveguide includes a three-sided structure on one side of the waveguide that tapers to a four-sided structure toward an other side of the waveguide, wherein the four-sided structure expands to a three- sided structure on the other side.

[0091] Example 23 is the device of any one of examples 1 to 22, wherein the waveguide includes a splitter configured to communicate the signals between the first device package and a third device package.

[0092] Example 24 is the device of any one of examples 1 to 23, wherein the first coupler or second coupler includes a vertically-oriented coupler that is fed vertically with respect to the waveguide.

[0093] Example 25 is the device of any one of examples 1 to 24, wherein the first coupler or second coupler includes a horizontally-oriented coupler that is fed horizontally with respect to the waveguide.

[0094] Example 26 is the device of any one of examples 1 to 25, wherein the first device package includes a processing chip and the second device package includes a memory module of the processing chip.

[0095] Example 27 is the device of example 26, wherein the processing chip includes a transceiver, wherein the memory module includes a memory transceiver, wherein the signals include radio frequency (RF) signals, wherein the transceiver and the memory transceiver are configured to modulate and demodulate baseband memory signals into radio frequency signalsthat are communicated through the waveguide between the processing chip and the memory module.

[0096] Example 28 is the device of example 27, wherein the memory module includes a plurality of memory chips connected to the memory module via a wired broadcasting channel.

[0097] Example 29 is the device of example 28, wherein the wired broadcasting channel includes a first port that feeds a planar layer to supply a plurality of broadcast ports, wherein a first elliptical void is in the planar layer and positioned between the first port and the plurality of broadcast ports.

[0098] Example 30 is the device of example 29, wherein a plurality of second elliptical voids in the planar layer are positioned between adjacent ones of the plurality of broadcast ports, wherein each of the plurality of second elliptical voids is smaller than the first elliptical void.

[0099] Example 31 is the device of any one of examples 1 to 30, wherein the first device package includes a processing chip and the second device package includes a bridge chip that connects to a memory module of the processing chip.

[0100] Example 32 is the device of example 31, wherein the bridge chip is configured to provide memory communications to the processing chip according to a memory standard.

[0101] Example 33 is the device of example 32, wherein the memory standard includes a Joint Electron Device Engineering Council (JEDEC) memory standard.

[0102] Example 34 is the device of any one of examples 1 to 33, the device further including a heatsink, wherein the waveguide is integrated into the heatsink.

[0103] Example 35 is the device of any one of examples 1 to 34, wherein the horizontal contactless coupler chiplet includes an upper layer stack that is stacked on a core, wherein the core is stacked on a lower layer stack, wherein a surface layer of the upper layer stack includes a planar metal layer including: a first E-shaped polygon; a second E-shaped polygon that mirrors the first E-shaped polygon along an axis; and a void that separates the first E-shaped polygon from the second E-shaped polygon along the axis.

[0104] Example 36 is the device of example 35, wherein the first E-shaped polygon and the second E-shaped polygon of the planar metal layer are connected to a metal layer of the lower layer stack, wherein through-hole vias connect the first E-shaped polygon and the second E-shaped polygon to the metal layer through the core.

[0105] Example 37 is the device of example 36, wherein the first E-shaped polygon includes a stem portion connected to two outer prong portions and a middle prong portion, wherein each of the through-hole vias that connect the first E-shaped polygon to the metal layer are located on the two outer prong portions.

[0106] Example 38 is the device of any one of examples 36 to 37, wherein the metal layer has an H-shaped void, wherein the H-shaped void is fed by a feed transmission line that connects to the H-shaped void via a stub through a substrate layer below the metal layer to a second metal layer below the substrate layer.

[0107] While the disclosure has been particularly shown and described with reference to specific aspects, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims. The scope of the disclosure is thus indicated by the appended claims and all changes, which come within the meaning and range of equivalency of the claims, are therefore intended to be embraced.

Claims

CLAIMSClaimed is:

1. A device comprising: a first device package comprising a first coupler; a second device package comprising a second coupler; and a waveguide positioned between the first coupler and the second coupler to communicate signals between the first device package and the second device package.

2. The device of claim 1, wherein the first device package or the second device package comprises a printed circuit board (PCB) or a semiconductor chip package.

3. The device of claim 2, wherein the waveguide comprises a U-shaped structure that forms an opening along the waveguide between the first device package to the second device package.

4. The device of any one of claims 1 to 3, wherein an interior of the waveguide is filled with a dielectric material.

5. The device of any one of claims 1 to 4, wherein the first coupler or the second coupler comprises a horizontal-oriented coupler that is fed horizontally with respect to the waveguide or a vertically-oriented coupler that is fed vertically with respect to the waveguide.

6. The device of any one of claims 1 to 5, wherein the waveguide is spaced apart from the first coupler at a first distance and the waveguide is spaced apart from the second coupler at a second distance.

7. The device of any one of claims 1 to 6, wherein the first coupler or the second coupler comprises a contactless coupler chiplet comprising a core and a layer stack, wherein the contactless coupler chiplet further comprises:a blind via within the core fed by a planar transmission line; and through-hole vias that penetrate through the core.

8. The device of claim 7, wherein the planar transmission line is configured to excite an energy coupling aperture outlined by the through-hole vias.

9. The device of any one of claims 1 to 8, wherein the waveguide comprises a first three- sided structure on one side of the waveguide that tapers to a four-sided enclosed structure toward an other side of the waveguide, wherein the four-sided enclosed structure expands to a second three-sided structure on the other side.

10. The device of any one of claims 1 to 9, wherein the waveguide comprises a splitter configured to communicate the signals between the first device package and a third device package.

11. The device of any one of claims 1 to 10, wherein the first device package comprises a processing chip and the second device package comprises a memory module of the processing chip, wherein the processing chip includes a transceiver, wherein the memory module includes a memory transceiver, wherein the signals comprise radio frequency (RF) signals, wherein the transceiver and the memory transceiver are configured to modulate and demodulate baseband memory signals into radio frequency signals that are communicated through the waveguide between the processing chip and the memory module.

12. The device of claim 11, wherein the memory module comprises a plurality of memory chips connected to the memory module via a wired broadcasting channel or via a wireless broadcasting channel.

13. The device of claim 12, wherein the wired broadcasting channel comprises a first port that feeds a planar layer to supply a plurality of broadcast ports, wherein a first elliptical void is in the planar layer and positioned between the first port and the plurality of broadcast ports.

14. The device of claim 13, wherein a plurality of second elliptical voids in the planar layer are positioned between adjacent ones of the plurality of broadcast ports, wherein each of the plurality of second elliptical voids is smaller than the first elliptical void.

15. The device of any one of claims 1 to 14, wherein the first device package comprises a processing chip and the second device package comprises a bridge chip that connects to a memory module of the processing chip, wherein the bridge chip is configured to provide memory communications to the processing chip according to a wired memory standard.

16. The device of any one of claims 1 to 15, the device further comprising a heatsink, wherein the waveguide is integrated into the heatsink.

17. A computing system comprising: a waveguide positioned between a first coupler of a first electronic component and a second coupler of a second electronic component, wherein the waveguide, first coupler, and second coupler are configured to communicate signals between one another via the waveguide, wherein each of the first coupler and the second coupler comprise an upper layer stack that is stacked on a core, wherein the core is stacked on a lower layer stack, wherein a surface layer of the upper layer stack comprises a planar metal layer comprising: a first E-shaped polygon; a second E-shaped polygon that mirrors the first E-shaped polygon along an axis; and a void that separates the first E-shaped polygon from the second E-shaped polygon along the axis.

18. The computing system of claim 17, wherein the first E-shaped polygon and the second E- shaped polygon of the planar metal layer are connected to a metal layer of the lower layer stack, wherein through-hole vias connect the first E-shaped polygon and the second E-shaped polygon to the metal layer through the core.

19. The computing of claim 18, wherein the first E-shaped polygon comprises a stem portion connected to two outer prong portions and a middle prong portion, wherein each of the through-hole vias that connect the first E-shaped polygon to the metal layer are located on the two outer prong portions.

20. The computing system of any one of claims 18 to 19, wherein the metal layer has an IT- shaped void, wherein the H-shaped void is fed by a feed transmission line that connects to the H-shaped void via a stub through a substrate layer below the metal layer to a second metal layer below the substrate layer.

Images