Temperature independent, low switching energy quantum switch for nonvolatile memories

Abstract

A temperature independent, low switching energy nonvolatile switching device capable of high-temperature static storage is described. The device is useful as deep nanoscale structures such as nanowires and nanosheets. The device body, sandwiched between conducting electrodes and having a surface not covered by the conducting electrodes, is fabricated using carbon-doped transition metal oxides or carbon-doped post transition metal oxides, with a neutral, non-switching, surface passivation protective oxide covering at least a portion of the surface, whereby, quantum-based metal-insulator phase transitions are produced. Transverse and longitudinal configurations have enhanced switching endurance with low fatigue. Memory arrays using these switchable resistance devices are described.

Description

TEMPERATURE INDEPENDENT, LOW SWITCHING ENERGY QUANTUM SWITCH FOR NONVOLATILE MEMORIESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of United States Provisional Patent Application Number 63 / 665,117 for “Temperature Independent, Low Switching Energy Quantum Switch for Nonvolatile Memories” by Carlos A. Paz de Araujo, which was filed on June 27, 2024, the entire content of which application is hereby specifically incorporated by reference herein for all that it discloses and teaches.BACKGROUND

[0002] For more than fifty years, the metal-oxide semiconductor field-effect transistor, or MOSFET, has been the dominant switch in integrated circuits. The use of nanosheets (2D) and nanowires (1 D) with effective channel lengths below 2 nm, have permitted an increase in the density of transistors by stacking layers of 1D and 2D form factor devices, theoretically enhancing a MOSFET’s speed, as an example. However, the electrostatic integrity and conduction mechanisms in the transistors remain limited by band bending near the surface of the semiconductor, and it is not possible to avoid potential wells that localize electrons in the oxide / semiconductor interface. Thermal fluctuations can cause deleterious hopping between these potential well ‘traps’, which create significant heating from Mott variable range hopping’. This noise and heating limit device performance and reliability. Thus, the improvement in device speed provided by scaling is compromised by these effects.

[0003] Therefore, switching mechanisms outside band-bending field effect in transistors have been sought.

[0004] Quantum phase transitions occurring in transition metal oxides such as NiO due to incomplete shells (a ‘3d’ shell short of two filled orbitals), which could switch between a conductive and an insulating state by modulation of screening densities, are known as ‘Mott Insulators’. However, devices based on this principle have high band gaps (> 4 eV), which requires high gate voltages (> 4 V) as opposed to < 0.8 V for today’s technology.

[0005] Naturally occurring potential switches are found in materials having hysteresis such as magnetic materials and ferroelectric materials. Although the switching mechanisms for ferroelectrics (atomic dipole polarization), and magnetic materials (spin polarization), cannot be scaled in area because polarization is not scalable; that is, magnetic flux diminishes with area, and the sensing current vanishes for ferroelectrics as the area becomes smaller. Therefore, there has been no effort to scale these devices into the nanoscale dimensions, the domain of nanosheets, since the materials and manufacturing processes are incompatible and too expensive.

[0006] ‘Flash’ memory devices (‘trapped charge’ semiconductor memory) add charge trapping layers in the gate stack of MOSFETs, and when the power is off, as area is decreased below about 900 nm2, the charge sheet in the gate has insufficient electron density to store a state from the space charge region induced in the silicon surface.

[0007] Recent efforts to create a ‘switching resistor’ for memory applications and artificial synapses for artificial intelligence arrays have rarely achieved a pure Mott transition. For the oxide, NiO, a known Mott insulator, the higher voltages and currents applied during the electroforming process (preparation step, which creates conductive filaments that grow between contacts), and the large intrinsic defects (vacancies, dislocations, and grain boundaries), hinder a stable and reliable quantum phase transition. Such procedures shrink the thickness of the resistor, thereby creating a region near the contacts that the local electron density can be modulated. The randomness of these soft dielectric breakdown paths make every potential ‘bit’ a unique device having inconsistent characteristics.SUMMARY

[0008] In accordance with the purposes of the present invention, as embodied and broadly described herein, an embodiment of the quantum switch, hereof, includes: a carbon-doped, transition metal oxide or a carbon-doped post-transition metal oxide sandwiched between a first conducting electrode and a second conducting electrode and in electrical contact therewith, forming a switchable resistor having a surface portion not in contact with the first conducting electrode and the second conducting electrode; and a non-carbon-dopedprotective oxide coating the surface portion; whereby, a protective oxide coated switchable resistor is formed.

[0009] In another aspect of the present invention, in accordance with the purposes thereof, as embodied and broadly described herein, an embodiment of the quantum switch, hereof, includes: a carbon-doped, transition metal oxide or a carbon-doped post-transition metal oxide sandwiched between a first conducting electrode and a second conducting electrode and in electrical contact therewith, forming a switchable resistor having a surface portion not in contact with said first conducting electrode and said second conducting electrode; and a non-carbon-doped protective oxide coating part of the surface portion; whereby, a protective oxide coated switchable resistor is formed.

[0010] Benefits and advantages of embodiments of the present invention include, but are not limited to, providing a temperature independent, low switching energy nonvolatile switching device capable of high-temperature static storage useful as deep nanoscale structures such as nanowires and nanosheets. The device body, sandwiched between conducting electrodes, and fabricated using carbon-doped transition metal oxides or carbon-doped post transition metal oxides, and having a neutral, non-switching protective oxide surface passivation, is capable of quantum-based metal-insulator phase transitions.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and form a part of the specification, illustrate the embodiments of the present invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0012] FIGURE 1 is a schematic representation of a front perspective view of a transverse carbon-doped switchable oxide resistor illustrating the carbon-doped switchable oxide material having protective oxide covering the carbon-doped switchable oxide material (OAA; oxide all around), except for the opposing metal electrical contacts.

[0013] FIGURE 2 is a schematic representation of a front cutaway view of a longitudinal carbon-doped switchable oxide resistor illustrating the opposing electrical contacts being attached to the small ends of the carbon-doped switchable oxide material, and having protective oxide covering the carbon-doped switchable oxide material, except for the metal electrical contacts.

[0014] FIGURE 3 is a schematic representation of a front perspective view of the longitudinal carbon-doped switchable oxide resistor having protective oxide covering the top and bottom areas of the carbon-doped switchable oxide material, except for the metal electrodes, and forming a channel for the electrodes.

[0015] FIGURES 4A-4C illustrate implementations of longitudinal resistors in 2D, 1D and 0D form factors, with FIG. 4A being a schematic representation of a top perspective view of a 3D stack of nanosheets as a 2D switch; FIG. 4B being a schematic representation of a side perspective view of a 3D stack of nanowires as a 1 D switch, and FIG. 4C being a schematic representation of a quantum dot as a 0D switch.

[0016] FIGURE 5A is a graph of the current versus applied voltage for carbon-doped CeRAM (Strongly Correlated Random Access Memory), compared with ReRAM (Resistive Random Access Memory) where the NiO does not have carbon doping; and FIG. 4B is a graph of the resistance (Ohms) of the switchable resistor as a function of applied voltage, illustrating the resistive hysteresis of the switchable resistor.

[0017] FIGURE 6A is a graph of the current versus applied voltage for a switchable resistor for high carbon doping (solid circles), and for low carbon doping (solid squares), illustrating that conductor-to-insulator switching (solid lines) occurs at lower voltages for high carbon doping than for low carbon doping, compared with the insulator-to-conductor transition (dotted lines); FIG. 6B is a graph of current versus applied voltage for a carbon- doped switchable resistor illustrating that both critical voltage and current must be met for the resistor to transition from an insulating-to-conducting state; and FIG. 6C is a graph of current versus applied voltage for a carbon-doped switchable resistor illustrating that both critical voltage and current must be met for the resistor to transition from a conducting-to- insulating state.

[0018] FIGURE 7 is a graph illustrating the high-speed characteristics of the carbon- doped switchable resistors.

[0019] FIGURE 8 is a schematic representation of a memory array using either longitudinal or transverse carbon-doped, transition or post transition metal oxides.

[0020] FIGURE 9A is a graph illustrating the l-V characteristics of carbon-doped HfO2 at 1.5 K, while FIG. 9B is a graph of the l-V characteristics of carbon-doped HfOa at 423 K, showing stable switching over a wide temperature range.DETAILED DESCRIPTION

[0021] In “Universal Non-Polar Switching in Carbon-Doped Transition Metal Oxides (TMOs)” by C.A. Paz de Araujo et al., APL Mater. 10, 040904 (2022), the contents of which are hereby incorporated by reference herein for all that it describes and teaches, reduced bandgaps were achieved for transition metal oxides and some non-transition metal oxides (post-transition metal oxide). A reduction in NiO (and other oxides) bandgap from 4.1 eV to 0.9 eV was unambiguously shown by photo-conductivity measurements.

[0022] In an embodiment of a switchable ‘transverse resistor’ having a metal-oxide- metal form factor of the present invention, to be discussed in detail below, electrical measurements show the bandgap to be about 0.75 eV, taking into consideration the screening effect of the metal contacts. Additional investigation, by the present inventor has shown that the sidewalls of the transverse resistor, created by etching and delineating the device, generate defects that had sufficient variable range hopping to heat the device, thereby causing electrical shorting, and causing the device endurance to be too short for broad use of the technology. For example, for NiO the endurance was less than one thousand cycles.

[0023] Sidewall and other surface passivation by layers, for example, HfOz, that surround and bind to the switchable oxide, for example, HfO2:C, thereby passivating defects, has been found to raise the endurance to seventeen thousand cycles without further optimization. Since area scaling (for example, from 25 M nm2down to 2,500 nm2) is common for these carbon-doped devices, the only physical dimension of interest is their deep nanoscale lengths between 110 nm and 10s of nm, and are termed switchable ‘longitudinal resistors’. To be noted is that this length becomes the thickness for switchable ‘transverse resistors’. These switchable longitudinal resistors, in the form of nanosheets and nanowires, together with their protective, non-switching oxides, have significant relevance to current integrated circuit technologies, as will be discussed in detail below.

[0024] Briefly, embodiments of the present invention include the addition of a nonswitching oxide between the top electrode and the bottom electrode of a switchable transverse resistor in the form of ‘oxide-all-around’ (OAA), and the addition of top and bottom oxide layers on longitudinal resistors, including OAA, the non-switching oxidebeing of similar stoichiometry to the switching oxide, or having a different stoichiometry thereto, where the neutrality of the protective oxide derives from the lack of carbon doping. Embodiments further include the insertion of such longitudinal or transverse resistors into passive structures for multi-layering nanosheets, nanowires, and quantum dots, and use of such structures and individual longitudinal and transverse resistors in non-volatile memory arrays.

[0025] Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. In the Figures, similar structures will be identified using identical reference characters. It will be understood that the FIGURES are presented for the purpose of describing particular embodiments of the invention and are not intended to limit the invention thereto.

[0026] A. Carbon-Doped Metal-Oxide Switchable Resistor Devices:

[0027] FIGURE 1 is a schematic representation of a front perspective view of a transverse carbon-doped, metal oxide switchable resistor, 10, illustrating the carbon- doped switchable oxide material, 12, having protective oxide, 14, covering the carbon- doped switchable oxide material (OAA; oxide all around) 12, except for the opposing metal electrical contacts, 16, and 18, which cover an area from < 45 nm x 45 nm to 100 nm x 100 nm, and are between 10 nm and 100 nm apart.

[0028] FIGURE 2 is a schematic representation of a front cutaway view of a longitudinal carbon-doped switchable oxide resistor, 20, illustrating the opposing electrical contacts 16 and 18 being attached to the small ends, 22, and 24, of carbon-doped switchable oxide material (HfO2:C, as an example) 12 between 1 nm and 50 nm apart, and having protective oxide (HfC , as an example) 14 covering the carbon-doped switchable oxide material 12, except for metal electrical contacts 16 and 18.

[0029] FIGURE 3 is a schematic representation of a front perspective view of the longitudinal carbon-doped switchable oxide resistor, 26, having protective oxide, HfO2, as an example, 14a, and 14b, covering the top, 28, and bottom, 30, areas of the carbon- doped switchable oxide material 12, forming channels, 32, and 34, for metal contacts 16 and 18, respectively.

[0030] FIGURES 4A-4C illustrate implementations of longitudinal resistors in 2D, 1 D and 0D form factors, with FIG. 4A being a schematic representation of a top perspective view of a 3D stack, 36, of nanosheets, 38a - 38c, as a 2D switch, supported by insulating material, 40, and resting on insulator, 42.

[0031] FIGURE 4B is a schematic representation of a side perspective view of a 3D stack, 44 of nanowires, 46a, and 46b, as a 1D switch resting on insulating material, 50, and FIG. 4C is a schematic representation of quantum dot, 52, as a 0D switch.

[0032] FIGURE 5A is a graph of the current versus applied voltage for carbon-doped NiO CeRAM (Correlated Electron Random Access Memory) having about 1 % of carbon doping, compared with ReRAM (Resistive Random Access Memory) where the NiO does not have carbon doping. This graph is completely symmetrical for negative applied voltages. The CeRAM device of embodiments of the present invention switches from conducting to semiconducting by simultaneously applying unique values of lonmax and VReset as identified by reference character, 60, and dependent on the doping, and from insulating to conducting as identified by reference character, 62, again dependent on the doping. With voltage as the input and current being read as the output, operations are performed in the direction of increasing voltage. The initial conduction is indicative of a metal-like phase (low resistance) that is “born-on, ” and there is no forming required. The low resistance state of the device switches to a semi-insulating high resistance state around VReset. If VReset is not applied, the non-volatile metal-like state does not change. Once transitioned to a high resistance state, the CeRAM stays in a non-volatile state and only changes to a metal-like state when Vset is applied, which is a drastic change. This sharp, first-order quantum phase transition is temperature independent from about 1 .5 K to approximately 473 K (200 °C), as may be observed in FIGS. 9A and 9B below, and is effectively an adiabatic switch requiring about 1.3 x 10’18Joules for switching (1 attojoule).

[0033] An external current compliance source (not shown in FIG. 5A) is applied at reference character 62 to avoid device burn-out from too-high current flow, and the current flowing through the carbon-doped switching resistor is a function of (compliance, such that lonmax < (compliance. The relatively constant current plateau between VReset and Vset represents the reference semi-insulating phase of the CeRAM.

[0034] As can be observed, there is no such switching for the undoped NiO.

[0035] FIGURE 5B is a graph of the resistance (Ohms) of the switchable resistor as a function of applied voltage, illustrating the resistive hysteresis thereof (R = I — J ). Typical values for HfO2:C include ROff / on between 100 and 1000 with 1 % carbon doping, Vres = 0,8 V, Vset = 1.6 V, and VREAD < 0.2 V (1 E12 cycles), which is much less than Vres. That Vset = 2 Vres is a characteristic of the quantum (bulk) switching physics.

[0036] Applying VREAD, two resistance values are present: an insulator (semiconductor) phase having low output current, which can be defined as logic T, and a conducting phase having higher output current, as logic ‘O’.

[0037] Other carbon-doped metal oxides (transition metal oxides and post transition metal oxides) having similar switching l-V (reset and set) to NiO include PbNiOs, HfOz, YTiOs, ZrO2, HfxZn-xO2, Bi2O3, and mixtures thereof, having about 1% carbon doping. Carbon doping between about 0.5 % and about 5 % may be employed. In addition to NiO, other protective oxides may be chosen from: PbNiOs, HfO2, YTiOs, ZrO2, HfxZn-xO2, Bi20s, and other transition metal oxides and post transition metal oxides, undoped with carbon, and mixtures thereof. Mixtures thereof, may also be included. Silicon (Si). Silicon dioxide (S1O2), or S13N4 may also be used as protective oxides.

[0038] FIGURE 6A is a graph of the current versus applied voltage for a switchable resistor for high carbon doping (solid circles), and for low carbon doping (solid squares), illustrating that conductor-to-insulator switching (solid lines) occurs at lower voltages for high carbon doping than for low carbon doping. The dotted lines represent the insulator- to-conductor transition.

[0039] FIGURE 6B is a graph of the SET current versus applied voltage for a carbon- doped switchable resistor illustrating that both critical voltage and current must be met for the resistor to transition from an insulating-to-conducting state. A 1T1 R circuit is used to drive the series-connected switchable resistor. With the transistor gate voltage (Vg) equal to 0.9 V, an external current compliance (not shown in FIG. 6B) is set to 2 mA (to avoid device burn-out from too-high current flow), which increases to 5 mA when Vgis increased to 0.95 V. Since the reset current for these resistors is greater than 2 mA, the switchable resistor will only reset (callout 60 in FIG. 5A) when Vgis 0.95 V and the compliance current is 5 mA. The SET (callout 62 in FIG. 5A) gate voltages for FIG. 6B are 0.7 V for (a), 0.75V for (b), 0.8 V for (c), 0.85 V for (d), 0.9 V for (e), and 0.95 for (f), with corresponding curves for FIG. 6C

[0040] FIGURE 6C is a graph of RESET current versus applied voltage for a carbon- doped switchable resistor illustrating that both critical voltage and current must be met for the resistor to transition from a conducting-to-insulating state (callout 60 in FIG. 5A).

[0041] FIGURE 7 is a graph illustrating the read current at 0.3 V after switching (SET and RESET) for different precharge pulse widths comparing 2 ns and 5 ns switching pulses of the switchable resistor. The transistor gate described FIGS. 6B and 6C is switched on to precharge the switchable resistor and then again switched on after a delay by application of the switching voltage to the 1T1 R.

[0042] Referring to FIG. 8, below, “pre-charge" means that the transistor addressing a selected bit has an intrinsic delay. This delay varies from transistor to transistor, but the data from FIG. 7 is for a pass-gate transistor for every bit ("1T / 1 R" cells). However, for a configuration having only 1 R bits (A, for example), as in memory array, 70, for precharging transistors, specifically, the column decoder circuits, a "buffer" circuit is used for pre-charging. That is, decoder, 72, contains logic circuits driving output buffers for precharging the switchable resistors of "Mott-type."

[0043] B. Nonvolatile Memory Arrays Using Carbon-Doped, Metal Oxide Switchable Resistors:

[0044] FIGURE 8 is a schematic representation of memory array, 70, using carbon- doped oxides, with HfO2:C and HfOs as the protective oxide as examples. Read / Write controller or decoder, 72, controls transistor voltage supply, 74, for Vnc, Vi2c, ... , transistor gate voltage supply, 76, for Tm , Tc2, ... , and transistor gate voltage supply, 78, for TRI , TR2, . .. . The row transistor gate voltages for row access transistors TRI , 80, T 2, 82, T S, 84, and TR4, 86, ..., are VG , and VGC are the column transistor gate voltages for column access transistors Tm, 88, Tc2, 90, and Tcs, 92, ... , for writing a bit into memory 70 with positive biasing (1stQuadrant in FIG. 5A), where a voltage pulse for Vijc> 0, and VkiR= 0. Note that writing can be achieved using positive voltages, and reading using negative voltages (3rdQuadrant in FIG. 5A, not shown), and vice-versa.

[0045] As an example, selecting protective oxide-coated, 93, nonvolatile memory carbon-doped resistor “A”, 94, a positive writing procedure requires TR2 on (VGR > 0), Tci on (VGC > 0), and V21R= 0 (Vnc(VReset or Vset) > 0).

[0046] Because a change in state requires both unique values of lonmax and VReset (critical current and critical voltage), memory array 70 does not require a pass-gate transistor, a MOSFET switch that either passes or blocks a signal. With Tci on, the entire column is receiving the applied voltage at Vnc> 0. Although every column bit is disturbed, there will not be an unanticipated ‘write’, since the VkiRs of the non-selected bits can be made equal to jcs (in magnitude and polarity). For example, if VReset ~ 0.7 V at jcwith i = 1 , j = 1 for jc, and k = 2, I = 1 for VkiR, the address for bit A, and the same voltage that is applied to Vncis applied to all VkiR, for k 2 and I 1 (the non-addressed bits).

[0047] More generally, VkiR= jc= VaPP(VReset or Vset), and TR(k) is on for k 2.

[0048] Alternatively, as shown in FIG. 8, all VkiRare set equal to zero including the selected bit, with all transistors TiR, TsR, ... with the exception of T2R, the selected bit in this discussion, being off. Thus, although Ticis on, disturbing column 1 , the TRs are off for the non-selected bit, and cross-talk is eliminated. Note that when VkiRare not equal to zero, an additional transistor voltage supply, not shown in FIG. 8, and controlled by read / Write controller or decoder, 72 is required.

[0049] As stated, in the write step, there are two options for the row biasing. First, the row transistor may be turned on for the selected bit and a voltage other than zero is applied to the source. For the non-selected bits, both the gate voltage (of row transistors) and the gate voltage for the column transistor are set at zero, and for both row and column transistors, the source bias is zero.

[0050] Variations, where a selected transistor does not have to be switched until desired, include setting the column transistors of the selected bit to gate voltages below the threshold (critical current in the variable resistor), which may be identified as the "low threshold switching bias of the variable resistor bit. This places the bit in stand-by mode, which will not delay the overall access when the device needs to identify a bit logic value. This allows for speeding up or delaying the output bits in accordance with the system's needs in the memory to processor (whether Central Processing Unit, CPU, or Graphic Processing Unit, GPU±used in Al). The memory delay is called the "Memory Latency",which is a major problem for Al. For the present devices, a short latency period is expected, but as arrays grow to huge numbers of elements, latency can be managed as described with "Low stand-by" biasing for critical current values by adjusting the gate voltage of the column (also possible with row transistors or a combination of both).

[0051] C. Device Fabrication:

[0052] (1) Carbon-Doped Hafnium Dioxide Thin Films:

[0053] Pt / Ti electrodes were formed on a SiC / Si substrate using ion beam deposition. A 20 nm thick carbon-doped HfO2 film was deposited by the fine channel mist chemical vapor deposition (CVD) method at a temperature of 400 °C. Tetrakis(acetylacetonate) hafnium (IV) dissolved in methanol was used to mist CVD forming a microcrystalline film. An upper Pt thin film electrode was formed by sputtering. As may be observed in FIGS. 9A and 9B, the l-V characteristics of the film, including switching from high resistance to low resistance, show no temperature dependence between room temperature and 473 K (200 °C).

[0054] Carbon-doped NiO and carbon-doped Hf films were also prepared using the same chemistry with spin-on-glass, SOG, coating technique, as well as using sputtering, and Liquid-Source Based Chemical Vapor Deposition, LSCVD.

[0055] (2) Protective Coating:

[0056] Carbon-doped HfCh and carbon-doped NiO were coated with protective films of undoped HfO2 and undoped NiO, respectively, using well-known procedures coating procedures.

[0057] FIGURE 9A is a graph illustrating the l-V characteristics of carbon-doped HfO2 at 1.5 K, while FIG. 9B is a graph of the l-V characteristics of carbon-doped HfO2 at 423 K, showing stable switching over a wide temperature range. More recent investigations by the present inventor show stable switching at 473 K (200 °C).

[0058] The foregoing description of the invention has been presented for purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application to thereby enableothers skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims

[0059] WHAT IS CLAIMED IS:1 . A quantum switch, comprising: a carbon-doped, transition metal oxide or a carbon-doped post-transition metal oxide sandwiched between a first conducting electrode and a second conducting electrode and in electrical contact therewith, forming a switchable resistor having a surface portion not in contact with said first conducting electrode and said second conducting electrode; and a non-carbon-doped protective oxide coating the surface portion; whereby, a protective oxide coated switchable resistor is formed.

2. The protective oxide coated switchable resistor of claim 1 , wherein said first conducting electrode and said second conducting electrode comprise metal electrodes.

3. The protective oxide coated switchable resistor of claim 1 , wherein said protective oxide coated switchable resistor has a current versus voltage that is temperature independent between about 1 .5 K and 473 K.

4. The protective oxide coated switchable resistor of claim 1 , wherein said carbon- doped transition metal oxide or said carbon-doped post-transition metal oxide are chosen from: NiO, PbNiOs, HfO , YTiCh, ZrOz, HfxZn-xCh, BisOe, and mixtures thereof, having between about 0.5 % and about 5 % carbon doping.

5. The protective oxide coated switchable resistor of claim 1 , wherein said non- carbon-doped protective oxide is chosen from: NiO, PbNiCh, HfO2, YTiOa, ZrO2, HfxZn-xO , Bi2O3, and other transition metal oxides and post transition metal oxides undoped with carbon, and mixtures thereof.

6. The protective oxide coated switchable resistor of claim 1 , wherein said protective oxide coated switchable resistor comprises a longitudinal or a transverse protective oxide coated switchable resistor.

7. The protective oxide coated switchable resistor of claim 6, wherein said longitudinal protective oxide coated switchable resistor comprises a nanosheet or a nanowire.

8. The protective oxide coated switchable resistor of claim 1 , wherein both a critical voltage and critical current are applied to the first conducting electrode and the second conducting electrode of the protective oxide coated switchable resistor for the protective oxide coated switchable resistor to transition from a conducting to an insulating state.

9. The protective oxide coated switchable resistor of claim 1 , wherein at least one protective oxide coated switchable resistor is used as a bit in a nonvolatile memory array.

10. The protective oxide coated switchable resistor of claim 9, wherein either the first conducting electrode or the second conducting electrode is grounded.

11. The protective oxide coated switchable resistor of claim 1 , wherein said non- carbon-doped protective oxide is chosen from Si, SiO2, and Si3N4.

12. The protective oxide coated switchable resistor of claim 4, wherein said carbon- doped transition metal oxide or said carbon-doped post-transition metal oxide are chosen from: NiO, PbNiCh, HfCh, YTiOs, ZrC , HfxZn-xO2, Bi2Os, and mixtures thereof, having about 1% carbon doping.

13. A quantum switch, comprising: a carbon-doped, transition metal oxide or a carbon-doped post-transition metal oxide sandwiched between a first conducting electrode and a second conducting electrode and in electrical contact therewith, forming a switchable resistor having a surface portion not in contact with said first conducting electrode and said second conducting electrode; and a non-carbon-doped protective oxide coating part of the surface portion; whereby, a protective oxide coated switchable resistor is formed.

14. The protective oxide coated switchable resistor of claim 13, wherein said first conducting electrode and said second conducting electrode comprise metal electrodes.

15. The protective oxide coated switchable resistor of claim 13, wherein said protective oxide coated switchable resistor has a current versus voltage that is temperature independent between about 1 .5 K and 473 K.

16. The protective oxide coated switchable resistor of claim 13, wherein said carbon- doped transition metal oxide or said carbon-doped post-transition metal oxide are chosen from: NiO, PbNiCh, HfC , YTiOs, ZrO2, HfxZn-xO2, Bi2Os, and mixtures thereof, having between about 0.5 % and about 5 % carbon doping.

17. The protective oxide coated switchable resistor of claim 13, wherein said non- carbon-doped protective oxide is chosen from: NiO, PbNiOs, HfO2, YTiOs, ZrO2, HfxZn-xO2, Bi2O3, and other transition metal oxides and post transition metal oxides undoped with carbon, and mixtures thereof.

18. The protective oxide coated switchable resistor of claim 13, wherein said protective oxide coated switchable resistor comprises a longitudinal or a transverse protective oxide coated switchable resistor.

19. The protective oxide coated switchable resistor of claim 18, wherein said longitudinal protective oxide coated switchable resistor comprises a nanosheet or a nanowire.

20. The protective oxide coated switchable resistor of claim 13, wherein both a critical voltage and critical current are applied to the first conducting electrode and the second conducting electrode of the protective oxide coated switchable resistor for the protective oxide coated switchable resistor to transition from a conducting to an insulating state.

21. The protective oxide coated switchable resistor of claim 13, wherein at least one protective oxide coated switchable resistor is used as a bit in a nonvolatile memory array.

22. The protective oxide coated switchable resistor of claim 21 , wherein either the first conducting electrode or the second conducting electrode is grounded.

23. The protective oxide coated switchable resistor of claim 13, wherein said non- carbon-doped protective oxide is chosen from Si, SiO2, and SisN4.

24. The protective oxide coated switchable resistor of claim 16, wherein said carbon- doped transition metal oxide or said carbon-doped post-transition metal oxide are chosen from: NiO, PbNiOs, HfO2, YTiOs, ZrO2, HfxZn-xO2, Bi20s, and mixtures thereof, having about 1% carbon doping.

5. The protective oxide coated switchable resistor of claim 18, wherein said longitudinal protective oxide coated switchable resistor comprises a top surface and a bottom surface disposed between said first conducting electrode and said second conducting electrode, and a first non-carbon-doped protective oxide covering the top surface and a second non-carbon-doped protective oxide covering the bottom surface thereof.

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