Basic arithmetic unit, arithmetic apparatus and method, and computer-readable storage medium

Abstract

A basic arithmetic unit, an arithmetic apparatus and method, and a computer-readable storage medium. The basic arithmetic unit comprises a plurality of modular arithmetic basic addition units, a plurality of selection units and a plurality of concatenation units, the modular arithmetic basic addition units comprising a first modular arithmetic basic addition unit and a second modular arithmetic basic addition unit, wherein the first modular arithmetic basic addition unit is configured to perform an operation on lower bits of an operand to obtain a plurality of lower-bit operation results; the second modular arithmetic basic addition unit is configured to perform an operation on higher bits of the operand to obtain a plurality of higher-bit operation results, the higher-bit operation results including with-carry results and without-carry results; the plurality of selection units are configured to select corresponding with-carry results or without-carry results on the basis of whether carries from the lower-bit operation results to the higher bits occur, and output the with-carry results or without-carry results to the concatenation units; an operation result is determined on the basis of the highest bits of concatenation results; and the plurality of concatenation units are configured to concatenate the higher-bit operation results with the lower-bit operation results to obtain concatenation results.

Description

Base operation unit, operation device and method, and computer readable storage medium TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to, but are not limited to, the technical field of Zero-knowledge Proofs (ZKP), and particularly relate to a base operation unit, an operation device and method, and a computer readable storage medium. BACKGROUND

[0002] Zero-knowledge proof is a method of proving the validity of a statement without exposing the statement itself, where the "prover" is the party trying to prove the statement, and the "verifier" is responsible for verifying the statement. Zero-Knowledge Succinct Non-Interactive Argument of Knowledge (ZK-SNARK) and Zero-Knowledge Scalable Transparent Argument of Knowledge (ZK-STARK) are two zero-knowledge proof systems. In high-performance ZK-SNARKs / ZK-STARKs protocols such as Plonky2 (a recursive zero-knowledge proof scheme), the Fast Reed-Solomen Interactive Oracle Proofs of Proximity (FRI) protocol based on the Goldilocks field is used for polynomial commitment, where the Goldilocks field is defined as: P = 2 64 -2 32 +1 = 0xffffffff00000001. When each algorithm is based on finite field calculation of the Goldilocks field, multiple modulo addition or subtraction calculations of 64-bit unsigned numbers are required.

[0003] When the current base operation unit and standard computer instructions are used to implement the Goldilocks field modulo addition or subtraction calculation, multiple instruction operations such as addition, subtraction, comparison, judgment, jump, etc. are required, and each operation can only calculate a group of 64-bit unsigned numbers, which is low in operation efficiency.

[0004] SUMMARY

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The embodiment of the present disclosure provides a basic operation unit, a plurality of modular operation basic addition units, a plurality of selection units and a plurality of splicing units, the modular operation basic addition units include a first modular operation basic addition unit and a second modular operation basic addition unit, the selection units include a first selection unit and a second selection unit, wherein: the first modular operation basic addition unit is configured to operate low bits of to-be-operated numbers to obtain a plurality of low-bit operation results; the second modular operation basic addition unit is configured to operate high bits of the to-be-operated numbers to obtain a plurality of high-bit operation results, the high-bit operation results include a carry result and a non-carry result, the carry result is a high-bit operation result of the to-be-operated numbers when the low-bit operation results are carried to high bits, and the non-carry result is a high-bit operation result of the to-be-operated numbers when the low-bit operation results are not carried to high bits; the first selection unit is configured to select a corresponding carry result or non-carry result according to whether the low-bit operation results are carried to high bits, and output to the splicing unit; the second selection unit is configured to determine an operation result according to the highest bit of the splicing result; and the splicing unit is configured to splice the high-bit operation results and the low-bit operation results to obtain a splicing result.

[0007] The embodiment of the present disclosure also provides an operation device, including the basic operation unit in any embodiment of the present disclosure, and further including a configuration unit and a storage unit, the storage unit includes a first storage unit, a second storage unit and a third storage unit, wherein: the configuration unit is configured to receive a modular operation instruction, the modular operation instruction includes an operation type, an address of the first storage unit, an address of the second storage unit and an address of the third storage unit; read an unsigned number A from the first storage unit, read an unsigned number B from the second storage unit, and set input values of the modular operation basic addition units in the basic operation unit according to the operation type, the unsigned number A and the unsigned number B; obtain an operation result of the basic operation unit and write the operation result into the third storage unit.

[0008] The embodiment of the present disclosure also provides an operation method based on the basic operation unit in any embodiment of the present disclosure, including: receiving a modular operation instruction, the modular operation instruction including an operation type, an address of a first storage unit, an address of a second storage unit and an address of a third storage unit; reading an unsigned number A from the first storage unit and reading an unsigned number B from the second storage unit; setting input values of modular operation basic addition units in the basic operation unit according to the operation type and values of A and B; obtaining an operation result of the basic operation unit and writing the operation result into the third storage unit.

[0009] The embodiment of the present disclosure further provides an operation device, comprising a memory and a processor connected to the memory, the memory is used for storing instructions, and the processor is configured to execute the steps of the operation method according to any one of the embodiments of the present disclosure based on the instructions stored in the memory.

[0010] The embodiment of the present disclosure further provides a computer readable storage medium, which stores a computer program, and the program is executed by a processor to implement the operation method according to any one of the embodiments of the present disclosure.

[0011] The basic operation unit, the operation device and the method, and the computer readable storage medium provided by the embodiment of the present disclosure can realize the modulo addition or the modulo subtraction operation without performing the subtraction, the comparison, the judgment, the jump and the like, so that the overall operation time of the modulo addition or the modulo subtraction operation is greatly reduced (the time of a single group of modulo addition or modulo subtraction operation can be reduced to about 1 / 10 of the time of the general instruction), and the efficiency of the zero-knowledge proof process such as the polynomial commitment algorithm is improved.

[0012] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the technical scheme of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical scheme of the present disclosure, and do not constitute a limitation on the technical scheme of the present disclosure.

[0014] Fig. 1 is a structural schematic diagram of a basic operation unit according to an exemplary embodiment of the present disclosure;

[0015] Fig. 2 is a structural schematic diagram of a modulo operation basic addition unit according to an exemplary embodiment of the present disclosure;

[0016] Fig. 3 is a structural schematic diagram of a basic operation unit for performing modulo addition operation according to an exemplary embodiment of the present disclosure;

[0017] Fig. 4 is a structural schematic diagram of a basic operation unit for performing modulo subtraction operation according to an exemplary embodiment of the present disclosure;

[0018] Fig. 5 is a flow schematic diagram of implementing the modulo addition operation using standard computer instructions;

[0019] Fig. 6 is a flow schematic diagram of implementing the modulo subtraction operation using standard computer instructions;

[0020] Fig. 7 is a structural schematic diagram of an operation device according to an exemplary embodiment of the present disclosure;

[0021] Fig. 8 is a structural schematic diagram of another operation device according to an exemplary embodiment of the present disclosure;

[0022] Figure 9 is a flowchart illustrating the implementation of modular addition using computer instructions in an exemplary embodiment of this disclosure;

[0023] Figure 10 is a flowchart illustrating the implementation of modular subtraction using computer instructions in an exemplary embodiment of the present disclosure;

[0024] Figure 11 is a flowchart illustrating an exemplary embodiment of the present disclosure of a calculation method;

[0025] Figure 12 is a schematic diagram of the structure of a computing device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0026] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features described herein can be combined arbitrarily.

[0027] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, but do not exclude other elements or objects.

[0028] As shown in Figure 1, this embodiment of the present disclosure provides a basic arithmetic unit, including multiple modular arithmetic basic addition units 101, multiple selection units 102, and multiple splicing units 103. The modular arithmetic basic addition units 101 include a first modular arithmetic basic addition unit 1011 and a second modular arithmetic basic addition unit 1012. The selection units 102 include a first selection unit 1021, 1022 and a second selection unit 1023, wherein:

[0029] The first modular arithmetic basic addition unit 1011 is configured to perform operations on the lower bits of the operands to obtain multiple lower bit operation results;

[0030] The second modular arithmetic basic addition unit 1012 is configured to perform operations on the high-order bits of the operands to obtain multiple high-order bit operation results. The high-order bit operation results include results with carry and results without carry. The result with carry is the high-order bit operation result of the operands when the low-order bit operation result carries to the high-order bit. The result without carry is the high-order bit operation result of the operands when the low-order bit operation result does not carry to the high-order bit.

[0031] The first selection units 1021 and 1022 are configured to select the corresponding result with or without carry based on whether the result of the low-order operation is carried over to the high-order bit, and output it to the splicing unit 103.

[0032] The second selection unit 1023 is configured to determine the operation result according to the highest bit of the splicing result.

[0033] The splicing unit 103 is configured to splice the high-bit operation result and the low-bit operation result to obtain a splicing result.

[0034] The basic operation unit of the embodiment of the present disclosure, by setting a plurality of modulo operation basic addition units 101, a plurality of selection units 102 and a plurality of splicing units 103, can realize modulo addition or modulo subtraction operation without performing subtraction, comparison, judgment, jump and other operations (only need to perform addition, selection and splicing operation), thereby greatly reducing the overall operation time of modulo addition or modulo subtraction operation (the single group of modulo addition or modulo subtraction operation time can be reduced to about 1 / 10 of the general instruction time), and improving the efficiency of the polynomial commitment algorithm and other zero-knowledge proof processes.

[0035] In some example embodiments, the basic operation unit is configured to perform modulo addition or modulo subtraction operation on the unsigned number A and the unsigned number B, the modulus is P, and the to-be-operated numbers include the unsigned number A and the unsigned number B, or include the unsigned number A, the unsigned number B and the modulus P.

[0036] In the embodiment of the present disclosure, the high bit of the to-be-operated number and the low bit of the to-be-operated number are defined in the following way: after the to-be-operated number is converted into a binary number, it is divided into left and right two parts, all bit numbers in the left part are high bits of the to-be-operated number, and all bit numbers in the right part are low bits of the to-be-operated number.

[0037] In the embodiment of the present disclosure, the selection unit 102 includes the first selection unit 1021, 1022 and the second selection unit 1023, wherein the first selection unit 1021, 1022 selects the corresponding carry result or non-carry result according to whether the low-bit operation result carries to the high bit, and outputs to the splicing unit 103; the second selection unit 1023 selects one splicing result as the final operation result according to the highest bit of the splicing result output by the splicing unit 103.

[0038] In the embodiment of the present disclosure, the splicing result includes the first splicing result and the second splicing result, wherein the first splicing result is the result of operation on the unsigned number A and the unsigned number B, and the second splicing result is the result of operation on the unsigned number A, the unsigned number B and the modulus P. The second selection unit 1023 determines the operation result according to the highest bit of the splicing result output by the splicing unit 103, specifically, selects the first splicing result or the second splicing result as the final operation result according to the highest bit of the first splicing result or the second splicing result.

[0039] For example, when the base operation unit is configured to perform a modulo addition operation on the unsigned number A and the unsigned number B, the first splicing result is the sum of the unsigned number A and the unsigned number B (A+B), and the second splicing result is the difference between the sum of the unsigned number A and the unsigned number B and the modulus P (A+B-P). The second selection unit 1023 selects the first splicing result (A+B) or the second splicing result (A+B-P) as the final operation result according to the highest bit of the second splicing result (A+B-P). Specifically, when the highest bit of the second splicing result (A+B-P) is 1, the second selection unit 1023 selects the first splicing result (A+B) as the final operation result; and when the highest bit of the second splicing result (A+B-P) is 0, the second selection unit 1023 selects the second splicing result (A+B-P) as the final operation result.

[0040] When the base operation unit is configured to perform a modulo subtraction operation on the unsigned number A and the unsigned number B, the first splicing result is the difference between the unsigned number A and the unsigned number B (A-B), and the second splicing result is the sum of the difference between the unsigned number A and the unsigned number B and the modulus P (A-B+P). The second selection unit 1023 selects the first splicing result (A-B) or the second splicing result (A-B+P) as the final operation result according to the highest bit of the first splicing result (A-B). Specifically, when the highest bit of the first splicing result (A-B) is 1, the second selection unit 1023 selects the second splicing result (A-B+P) as the final operation result; and when the highest bit of the first splicing result (A-B) is 0, the second selection unit 1023 selects the first splicing result (A-B) as the final operation result.

[0041] The core component of the base operation unit is a modulo operation base addition unit (BAU). In some example embodiments, as shown in FIG. 2, each modulo operation base addition unit is configured to receive four input values a, b, p, and c, and perform an addition operation on the four input values, and output out, i.e., out=a+b+p+c. Among the four input values, one input value (input value a) is set according to the high bit or the low bit of A, one input value (input value b) is set according to the high bit or the low bit of B, one input value (input value p) is set according to the high bit or the low bit of P or set to 0, and one input value (input value c) is set to 0 or 1.

[0042] In some example embodiments, A, B, and P are all (N1+N2)-bit binary numbers, N1 and N2 are both natural numbers greater than or equal to 1, in the first modulo operation base addition unit 1011, one input value is the value of the low N2 bits of A, one input value is the value of the low N2 bits of B or the value of the low N2 bits of the complement of B, and one input value is the value of the low N2 bits of P, the value of the low N2 bits of the complement of P, or 0.

[0043] In the second modulo operation base addition unit 1012, one input value is the high N1-bit value of A, the high N1-bit value of B or the high N1-bit value of the inverse code of B, one input value is the high N1-bit value of P, the high N1-bit value of the inverse code of P or 0.

[0044] In the embodiments of the present disclosure, the low bit number of the operand operated by the first modulo operation base addition unit 1011 and the high bit number of the operand operated by the second modulo operation base addition unit 1012 can be equal (i.e. N1=N2=N, N is a natural number greater than or equal to 1) or not equal (i.e. N1≠N2). When the low bit number of the operand operated by the first modulo operation base addition unit 1011 and the high bit number of the operand operated by the second modulo operation base addition unit 1012 are equal, the structures of the plurality of adders in the first modulo operation base addition unit 1011 and the second modulo operation base addition unit 1012 can be set to be completely the same structure (only the input values are different), so that the overall structure is simpler and the operation efficiency is higher. Hereinafter, an example is taken to illustrate that the unsigned number A, the unsigned number B and the modulus P are all 2N-bit binary numbers, the first modulo operation base addition unit 1011 operates on the low N bits of the operand, and the second modulo operation base addition unit 1011 operates on the high N bits of the operand.

[0045] The base operation unit in the embodiments of the present disclosure performs polynomial commitment based on the FRI protocol of the Goldilocks field, and therefore P=0xffffffff00000001. When the base operation unit operates based on different fields, the value of P can be a fixed value set for the field.

[0046] In some example embodiments, N=32. However, the embodiments of the present disclosure do not limit this, and the value of N can be set as needed.

[0047] As shown in FIG. 3, when the base operation unit performs modulo addition operation on the unsigned number A and the unsigned number B, the plurality of modulo operation base addition units can include a first adder BAU_C0, a second adder BAU_C1, a third adder BAU_0, a fourth adder BAU_P_C0, a fifth adder BAU_P_C1, and a sixth adder BAU_P_0, the plurality of selection units can include a first selector S1 (i.e. the first selection unit 1021), a second selector S2 (i.e. the first selection unit 1022) and a third selector S3 (i.e. the second selection unit 1023), and the plurality of splicing units can include a first splicer 1031 and a second splicer 1032.

[0048] In the embodiments of the present disclosure, the entire basic operation unit can be divided into two operation branches: a first operation branch and a second operation branch. The first operation branch (i.e., all the modular operation basic addition units, selection units and splicing units on the branch connected with the first input end of the third selector S3 in FIG. 3) is configured to calculate the sum of the two unsigned numbers A and B, obtaining (A+B), which is a (2N+1)-bit binary number. The second operation branch (i.e., all the modular operation basic addition units, selection units and splicing units on the branch connected with the second input end of the third selector S3 in FIG. 3) is configured to calculate the sum of the two unsigned numbers A and B, the inverse code of the modulus P and 1, obtaining which is a (2N+1)-bit binary number, denotes the NOT operation on the modulus P; the third selector S3 selects (A+B) or according to the value of the highest bit of The low 2N bits of

[0049] In the embodiments of the present disclosure, when the value of the highest bit of is 1, the third selector S3 selects the low 2N bits of (A+B) as the modular addition result of the two unsigned numbers A and B; when the value of the highest bit of is 0, the third selector S3 selects as the modular addition result of the two unsigned numbers A and B.

[0050] In some example embodiments, the first operation branch includes a first adder BAU_C0, a second adder BAU_C1, a third adder BAU_0, a first selector S1 and a first splicer 1031, wherein:

[0051] The first adder BAU_C0 is configured to calculate the sum of the high N bits A[2N-1:N] of the unsigned number A and the high N bits B[2N-1:N] of the unsigned number B, obtaining the value out_c0[N:0] of (A2+B2), which is an (N+1)-bit binary number (in the figure, N=32 is taken as an example), and inputting the value out_c0[N:0] of (A2+B2) into the first input end of the first selector S1, A2 representing the high N bits of A and B2 representing the high N bits of B;

[0052] The second adder BAU_C1 is configured to calculate the sum of the high N bits A[2N-1:N] of the unsigned number A, the high N bits B[2N-1:N] of the unsigned number B and 1, to obtain the value out_c1[N:0] of (A2+B2+1), (A2+B2+1) being an (N+1)-bit binary number, and input the value out_c1[N:0] of (A2+B2+1) to the second input terminal of the first selector S1;

[0053] The third adder BAU_0 is configured to calculate the sum of the low N bits A[N-1:0] of the unsigned number A and the low N bits B[N-1:0] of the unsigned number B, to obtain the value out_0[N:0] of (A1+B1), (A1+B1) being an (N+1)-bit binary number, input the value out_0[N] of the highest bit of (A1+B1) to the control terminal of the first selector S1, and input the value out_0[N-1:0] of the low N bits of (A1+B1) to the first input terminal of the first splicer 1031, A1 representing the low N bits of A, and B1 representing the low N bits of B.

[0054] The first selector S1 is configured to select the value out_c0[N:0] of (A2+B2) or the value out_c1[N:0] of (A2+B2+1) input to the second input terminal of the first splicer 1031 according to the value out_0[N] of the highest bit of (A1+B1).

[0055] The first splicer 1031 is configured to splice the value out_0[N-1:0] input by the third adder BAU_0 and the value out_c[N:0] input by the first selector S1, to obtain the value out[2N:0] of (A+B), and input the value out[2N-1:0] of the low 2N bits of (A+B) to the first input terminal of the third selector S3.

[0056] In the embodiments of the present disclosure, when the value out_0[N] of the highest bit of (A1+B1) is 1, the first selector S1 selects the value out_c1[N:0] of (A2+B2+1) to be input to the second input terminal of the first splicer 1031; and when the value out_0[N] of the highest bit of (A1+B1) is 0, the first selector S1 selects the value out_c0[N:0] of (A2+B2) to be input to the second input terminal of the first splicer 1031.

[0057] In some example embodiments, the second operation branch includes a fourth adder BAU_P_C0, a fifth adder BAU_P_C1, a sixth adder BAU_P_0, a second selector S2 and a second splicer 1032, wherein:

[0058] The fourth adder, BAU_P_C0, is configured to calculate the sum of the high N bits A[2N-1:N] of the unsigned number A, the high N bits B[2N-1:N] of the unsigned number B, and the high N bits ~P[2N-1:N] of the one's complement of the modulus P, to obtain... The value of out_p_c0[N:0], For an (N+1) bit binary number, The value out_p_c0[N:0] is input to the first input terminal of the second selector S2, where A2 represents the high N bits of A and B2 represents the high N bits of B. The high N bits represent the one's complement of the modulus P;

[0059] The fifth adder, BAU_P_C1, is configured to calculate the sum of the high N bits A[2N-1:N] of the unsigned number A, the high N bits B[2N-1:N] of the unsigned number B, and the high N bits ~P[2N-1:N] of the one's complement of the modulus P, plus 1, to obtain... The value of out_p_c1[N:0], For an (N+1) bit binary number, The value out_p_c1[N:0] is input to the second input terminal of the second selector S2;

[0060] The sixth adder, BAU_P_0, is configured to calculate the sum of the lower N bits A[N-1:0] of the unsigned number A, the lower N bits B[N-1:0] of the unsigned number B, the lower N bits ~P[N-1:0] of the one's complement of the modulus P, and 1, to obtain... The value of out_p_0[N:0] is... For an (N+1) bit binary number, The highest bit value, out_p_0[N], is input to the control terminal of the second selector S2. The lower N bits of the value, out_p_0[N-1:0], are input to the first input of the second splicer. A1 represents the lower N bits of A, and B1 represents the lower N bits of B. The lower N bits represent the one's complement of the modulus P;

[0061] The second selector S2 is configured to, according to The highest bit value out_p_0[N] is selected. The value of out_p_c0[N:0] or The value out_p_c1[N:0] is input to the second input terminal of the second splicer 1032;

[0062] The second splicer 1032 is configured to splice the value out_p_0[N-1:0] input by the sixth adder BAU_P_0 and the value out_p_c[N:0] input by the second selector S2 to obtain the value out_p[2N:0] of , and input the value out_p[2N-1:0] of the highest bit of to the control end of the third selector S3, and input the value out_p[2N-1:0] of the low 2N bits of to the second input end of the third selector S3.

[0063] In the embodiment of the present disclosure, when the value out_p_0[N] of the highest bit of is 1, the second selector S2 selects the value out_p_c1[N:0] of to input the second input end of the second splicer 1032; when the value out_p_0[N] of the highest bit of is 0, the second selector S2 selects the value out_p_c0[N:0] of to input the second input end of the second splicer 1032.

[0064] As shown in FIG. 4, when the basic operation unit performs the modulo subtraction operation on the unsigned number A and the unsigned number B, the plurality of modulo operation basic adders can include a seventh adder BAU_C0', an eighth adder BAU_C1', a ninth adder BAU_0', a tenth adder BAU_P_C0', an eleventh adder BAU_P_C1', and a twelfth adder BAU_P_0', the plurality of selection units can include a fourth selector S4 (i.e., the first selection unit 1021), a fifth selector S5 (i.e., the first selection unit 1022), and a sixth selector S6 (i.e., the second selection unit 1023), and the plurality of splicing units can include a third splicer 1031' and a fourth splicer 1032'.

[0065] In the embodiment of the present disclosure, the entire basic operation unit can still be divided into two operation branches: a first operation branch and a second operation branch, wherein the first operation branch (i.e., all the modulo operation basic adders, selection units, and splicing units on the branch connected with the first input end of the sixth selector S6 in FIG. 4) is configured to calculate the sum of the complement of the unsigned number A, the unsigned number B, and 1 to obtain as a (2N+1)-bit binary number; and the second operation branch (i.e., all the modulo operation basic adders, selection units, and splicing units on the branch connected with the second input end of the sixth selector S6 in FIG. 4) is configured to calculate the sum of the complement of the unsigned number A, the unsigned number B, and the modulus P to obtain as a (2N+1)-bit binary number, denotes a NOT operation on the unsigned number B; the sixth selector S6 selects the value of the lower 2N bits of or or as the modulo subtraction result of the two unsigned numbers A and B.

[0066] In the embodiments of the present disclosure, when the value of the most significant bit of is 1, the sixth selector S6 selects the value of the lower 2N bits of as the modulo subtraction result of the two unsigned numbers A and B; when the value of the most significant bit of is 0, the sixth selector S6 selects the value of the lower 2N bits of as the modulo subtraction result of the two unsigned numbers A and B.

[0067] In some example embodiments, the first operation branch includes a seventh adder BAU_C0', an eighth adder BAU_C1', a ninth adder BAU_0', a fourth selector S4 and a third splicer 1031', wherein:

[0068] The seventh adder BAU_C0' is configured to calculate the sum of the high N bits A[2N-1:N] of the unsigned number A and the high N bits ~B[2N-1:N] of the complement of the unsigned number B, to obtain the value out_c0'[N:0] of is a (N+1)-bit binary number, and the value out_c0'[N:0] of is input to the first input end of the fourth selector S4, A2 represents the high N bits of A, represents the high N bits of the complement of B;

[0069] The eighth adder BAU_C1' is configured to calculate the sum of the high N bits A[2N-1:N] of the unsigned number A, the high N bits ~B[2N-1:N] of the complement of the unsigned number B and 1, to obtain the value out_c1'[N:0] of

[0070] is a (N+1)-bit binary number, and the value out_c1'[N:0] of is input to the second input end of the fourth selector S4;

[0071] The ninth adder BAU_0' is configured to calculate the sum of the low N bits A[N-1:0] of the unsigned number A, the low N bits ~B[N-1:0] of the complement of the unsigned number B and 1, to obtain the value out_0'[N:0] of is a (N+1)-bit binary number, and the value out_0'[N:0] of ​​​the value out_0'[N] of the highest bit of the value out_0' of A is input to the control end of the fourth selector S4, and the value out_0' of A is input to the first input end of the third splicer 1031'. the value out_0' of A, the value out_0' of A is input to the first input end of the third splicer 1031', A1 represents the low N bits of A, the low N bits of the complement of B;

[0072] The fourth selector S4 is configured to select, according to the value out_0'[N] of the highest bit of the value out_0' of A, the value out_c0'[N:0] of the value out_c0' of A or the value out_c1'[N:0] of the value out_c1' of A is input to the second input end of the third splicer 1031'.

[0073] The third splicer 1031' is configured to splice the value out_0'[N-1:0] input by the ninth adder BAU_0' and the value out_c'[N:0] input by the fourth selector S4 to obtain the value out'[2N:0] of the value out' of A, and input the value out'[2N] of the highest bit of the value out' of A to the control end of the sixth selector S6, and input the value out'[2N-1:0] of the low 2N bits of the value out' of A to the first input end of the sixth selector S6.

[0074] In the embodiments of the present disclosure, when the value out_0'[N] of the highest bit of the value out_0' of A is 1, the fourth selector S4 selects the value out_c1'[N:0] of the value out_c1' of A to be input to the second input end of the third splicer 1031'; when the value out_0'[N] of the highest bit of the value out_0' of A is 0, the fourth selector S4 selects the value out_c0'[N:0] of the value out_c0' of A to be input to the second input end of the third splicer 1031'.

[0075] In some example embodiments, the second operation branch includes a tenth adder BAU_P_C0', an eleventh adder BAU_P_C1', a twelfth adder BAU_P_0', a fifth selector S5 and a fourth splicer 1032', wherein:

[0076] The tenth adder BAU_P_C0' is configured to calculate the sum of the high N bits A[2N-1:N] of the unsigned number A, the high N bits ~B[2N-1:N] of the complement of the unsigned number B and the high N bits P[2N-1:N] of the modulus P to obtain the value out_p_c0'[N:0] of the value out_p_c0' of A, is a (N+1)-bit binary number, and ​​​​​​​​​​The value out_p_c0'[N:0] of the first selector S1 is input into the first input end of the fifth selector S5, A2 represents the high N bits of A, P2 represents the high N bits of the modulus P;

[0077] The eleventh adder BAU_P_C1' is configured to calculate the sum of the high N bits A[2N-1:N] of the unsigned number A, the high N bits ~B[2N-1:N] of the one's complement of the unsigned number B, the high N bits P[2N-1:N] of the modulus P, and 1, to obtain The value out_p_c1'[N:0] of the eleventh adder BAU_P_C1', The value out_p_c1'[N:0] of the eleventh adder BAU_P_C1' is input into the second input end of the fifth selector S5.

[0078] The twelfth adder BAU_P_0' is configured to calculate the sum of the low N bits A[N-1:0] of the unsigned number A, the low N bits B[N-1:0] of the one's complement of the unsigned number B, the low N bits P[N-1:0] of the modulus P, and 1, to obtain The value out_p_0'[N:0] of the twelfth adder BAU_P_0', The highest bit of the value out_p_0'[N] of the twelfth adder BAU_P_0' is input into the control end of the fifth selector S5, and the low N bits of the value out_p_0'[N-1:0] of the twelfth adder BAU_P_0' are input into the first input end of the fourth splicer 1032'. P1 represents the low N bits of the modulus P;

[0079] The fifth selector S5 is configured to select The value out_p_c0'[N:0] of the first selector S1 or the value out_p_c1'[N:0] of the eleventh adder BAU_P_C1' according to the highest bit of the value out_p_0'[N] of the twelfth adder BAU_P_0', The value out_p_c0'[N:0] of the first selector S1 or the value out_p_c1'[N:0] of the eleventh adder BAU_P_C1' according to the highest bit of the value out_p_0'[N] of the twelfth adder BAU_P_0' is input into the second input end of the fourth splicer 1032'.

[0080] The fourth splicer 1032' is configured to splice the value out_p_0'[N-1:0] input by the twelfth adder BAU_P_0' and the value out_p_c'[N:0] input by the fifth selector S5, to obtain The value out_p'[2N:0] of the fourth splicer 1032', and The low 2N bits of the value out_p'[2N-1:0] of the fourth splicer 1032' are input into the second input end of the sixth selector S6.

[0081] In the embodiments of the present disclosure, when ​​​​When the value of the most significant bit of out_p_0' [N] is 1, the fifth selector S5 selects When the value of the most significant bit of out_p_0' [N] is 1, the fifth selector S5 selects When the value of the most significant bit of out_p_0' [N] is 1, the fifth selector S5 selects When the value of the most significant bit of out_p_0' [N] is 1, the fifth selector S5 selects

[0082] In the embodiments of the present disclosure, the first adder BAU_C0, the second adder BAU_C1, the third adder BAU_0, the fourth adder BAU_P_C0, the fifth adder BAU_P_C1, the sixth adder BAU_P_0, the seventh adder BAU_C0', the eighth adder BAU_C1', the ninth adder BAU_0', the tenth adder BAU_P_C0', the eleventh adder BAU_P_C1' and the twelfth adder BAU_P_0' can be implemented by a modulo operation basic adder unit, each modulo operation basic adder unit includes four inputs a, b, p and c, and an output out, and the operation performed inside the modulo operation basic adder unit is: out = a + b + p + c.

[0083] As shown in FIG. 3 and FIG. 4, taking N = 32 bits as an example, the input of each modulo operation basic adder unit includes 32-bit a, 32-bit b, 32-bit p and 1-bit c, wherein the 32-bit a and the 32-bit b of the input are the high 32 bits or the low 32 bits of the 64-bit unsigned number A and the 64-bit unsigned number B (or the inverse code thereof) for modulo addition or modulo subtraction, the 32-bit p of the input is the high 32 bits or the low 32 bits of the Goldilocks domain P (or the inverse code thereof) or 0, and the 1-bit c of the input is the carry bit or the set bit (1 or 0). The output of the modulo operation basic adder unit is 33-bit out, which is the result after operation. Since a carry is generated in the calculation process, the out is 33 bits.

[0084] Each modulo operation unit includes 6 modulo operation basic adder units, and only the input values of the modulo operation basic adder units need to be changed when calculating modulo addition and modulo subtraction.

[0085] As shown in FIG. 3, when performing modulo addition operation, the following calculations are respectively performed in each modulo operation basic adder unit:

[0086] BAU_0: A low 32 bits plus B low 32 bits, output is 33-bit out_0;

[0087] BAU_C0: A high 32 bits plus B high 32 bits, output is 33-bit out_c0;

[0088] BAU_C1: A's high 32 bits plus B's high 32 bits plus carry-in c = 1, output is 33 bits out cl;

[0089] BAU_P_0: A's low 32 bits plus B's low 32 bits plus P's low 32 bits taken as complement, plus carry-in c = 1 (adding complement of P plus one is equivalent to subtracting P), output is 33 bits out p_0;

[0090] BAU_P_C0: A's high 32 bits plus B's high 32 bits plus P's high 32 bits taken as complement, output is 33 bits out p_c0;

[0091] BAU_P_C1: A's high 32 bits plus B's high 32 bits plus P's high 32 bits taken as complement, plus carry-in c = 1, output is 33 bits out p_cl;

[0092] If the 33rd bit of out_0 is 1, indicating that the result of A's low 32 bits plus B's low 32 bits requires carry-in, then out cl is selected as the high 33 bits, concatenated with the low 32 bits of out_0 to obtain 65-bit out; otherwise, out c0 is selected as the high 33 bits, concatenated with the low 32 bits of out_0 to obtain 65-bit out;

[0093] If the 33rd bit of out p_0 is 1, indicating that the result of A's low 32 bits plus B's low 32 bits plus P's low 32 bits taken as complement, plus carry-in c = 1 requires carry-in, then out p_cl is selected as the high 33 bits, concatenated with the low 32 bits of out p_0 to obtain 65-bit out p; otherwise, out p_c0 is selected as the high 33 bits, concatenated with the low 32 bits of out p_0 to obtain 65-bit out p;

[0094] If the 65th bit of out p is 1, indicating that the value of A + B - P is negative, then the low 64 bits of out are selected as the final output C; otherwise, the low 64 bits of out p are selected as the final output C.

[0095] As shown in FIG. 4, when performing the modulo subtraction operation, the following calculations are respectively performed in each modulo operation basis addition unit:

[0096] BAU_0': A's low 32 bits plus B's low 32 bits taken as complement, plus carry-in c = 1 (adding complement of B plus one is equivalent to subtracting B), output is 33 bits out_0';

[0097] BAU_C0': A's high 32 bits plus B's high 32 bits taken as complement, output is 33 bits out c0';

[0098] BAU_C1': the high 32 bits of A plus the high 32 bits of B taken complement, plus carry-in c = 1, output as 33 bits out_c1';

[0099] BAU_P_0': the low 32 bits of A plus the low 32 bits of B taken complement, plus the low 32 bits of P, plus 1, output as 33 bits out_p_0';

[0100] BAU_P_C0': the high 32 bits of A plus the high 32 bits of B taken complement, plus the high 32 bits of P, output as 33 bits out_p_c0';

[0101] BAU_P_C1': the high 32 bits of A plus the high 32 bits of B taken complement, plus the high 32 bits of P, plus carry-in c = 1, output as 33 bits out_p_c1';

[0102] If the 33rd bit of out_0' is 1, indicating that the result of the low 32 bits of A plus the low 32 bits of B taken complement, plus the set bit 1 needs carry, then select out_c1' as the high 33 bits, concatenated with the low 32 bits of out_0', to obtain 65 bits of out'; otherwise, select out_c0' as the high 33 bits, concatenated with the low 32 bits of out_0', to obtain 65 bits of out';

[0103] If the 33rd bit of out_p_0' is 1, indicating that the result of the low 32 bits of A plus the low 32 bits of B taken complement, plus the low 32 bits of P, plus the set bit c = 1 needs carry, then select out_p_c1' as the high 33 bits, concatenated with the low 32 bits of out_p_0', to obtain 65 bits of out_p'; otherwise, select out_p_c0' as the high 33 bits, concatenated with the low 32 bits of out_p_0', to obtain 65 bits of out_p';

[0104] If the 65th bit of out' is 1, indicating that the value of A-B is negative, P needs to be added, then select the low 64 bits of out_p' as the final output C, otherwise select the low 64 bits of out' as the final output C.

[0105] In FIG. 3 and FIG. 4, [31:0] represents the 0th bit to the 31st bit, i.e., the low 32 bits; [63:32] represents the 32nd bit to the 63rd bit, i.e., the high 32 bits; [64:0] represents the 0th bit to the 64th bit; [63:0] represents the 0th bit to the 63rd bit; [32:0] represents the 0th bit to the 32nd bit;

[0032] represents the 32nd bit;

[0064] represents the 64th bit.

[0106] As shown in FIG. 5, when implementing the modulo addition operation of the 64-bit unsigned number A and the unsigned number B in the Goldilocks field using standard computer instructions, the following instructions need to be executed: executing the instruction "LD reg1, A" to load A into register 1, executing the instruction "LD reg2, B" to load B into register 2; executing the instruction "ADD reg3, reg1, reg2" to add the values of register 1 and register 2, and store the result in register 3; executing the instruction "BLT reg3, reg1" to compare whether the value of register 3 is less than the value of register 1, that is, to determine whether overflow occurs; when the value of register 3 is less than the value of register 1, executing the instruction "ADD reg3, reg3, reg7" to add the values of register 3 and register 7, and store the result in register 3, the value of register 7 is previously set to 0xffffffff; when the value of register 3 is greater than or equal to the value of register 1, executing the instruction "BLT reg3, reg8" to compare whether the value of register 3 is less than the value of the Goldilocks field P, the value of register 8 is previously set to the value of the Goldilocks field P; when the value of register 3 is less than the value of the Goldilocks field P, executing the instruction "SD reg3, SmodP" to store the value in register 3 as the final result; when the value of register 3 is greater than or equal to the value of the Goldilocks field P, executing the instruction "SUB reg3, reg3, reg8" to subtract the value of the Goldilocks field P from the value of register 3, and store the result in register 3, and then executing the instruction "SD reg3, SmodP" to store the value in register 3 as the final result.

[0107] As can be seen, when performing the modulo addition operation of the 64-bit unsigned number A and the number B in the Goldilocks field using standard computer instructions once, in addition to the loading and storage operations, the following operations need to be performed:

[0108] At most: 1 addition, 2 comparison jumps, 2 subtractions;

[0109] At least: 1 addition, 2 comparison jumps.

[0110] When performing the modulo addition operation of the 64-bit unsigned number A and the number B in the Goldilocks field using the basic operation unit of the embodiment of the present disclosure once, in addition to the loading and storage operations, the following operations need to be performed: 6 additions, 3 selections, and 2 splices. The 6 addition operations can be performed simultaneously, and the selection and splice operations do not occupy too much time compared with the comparison jump operation.

[0111] The computer execution of the jump instruction involves instruction jump prediction, instruction loading, prediction result correction, instruction clearing, and other processes, which are time-consuming (in some embodiments, 10-20 clock cycles are consumed for evaluation); while the time required for the execution of the modulo addition operation of the present disclosure is equal to or only slightly more than the time for the execution of the addition operation (in some embodiments, using the improved functional unit, the time for the execution of the modulo addition operation can be equal to the time for the execution of the addition operation, which is 2 clock cycles; in other embodiments, using the general functional unit, the time for the execution of the modulo addition operation can be 2 clock cycles more than the time for the execution of the addition operation, which is 4 clock cycles). Therefore, the time for the execution of the Goldilocks field 64-bit unsigned number modulo addition operation by the basic operation unit using the embodiments of the present disclosure is greatly reduced, which can be about 1 / 10 of the time for the general instruction.

[0112] As shown in FIG. 6, when the modulo subtraction operation of the Goldilocks field 64-bit unsigned number A and the unsigned number B is implemented using standard computer instructions, the following instructions need to be executed: the instruction "LD reg1, A" is executed to load A into register 1, the instruction "LD reg2, B" is executed to load B into register 2; the instruction "BLT reg1, reg2" is executed to compare whether the value of register 1 is less than the value of register 2; when the value of register 1 is less than the value of register 2, the instruction "SUB reg3, reg8, reg2" is executed to subtract the value of register 2 from the value of register 8, and the result is stored in register 3, and the value of register 8 is previously set as the value of the Goldilocks field P, then the instruction "ADD reg3, reg1, reg3" is executed to add the values of register 1 and register 3, and the result is stored in register 3, then the instruction "SD reg3, DmodP" is executed to store the value in register 3 as the final result; when the value of register 1 is greater than or equal to the value of register 2, the instruction "SUB reg3, reg1, reg2" is executed to subtract the value of register 2 from the value of register 1, and the result is stored in register 3, then the instruction "SD reg3, DmodP" is executed to store the value in register 3 as the final result.

[0113] As can be seen, in addition to the loading and storage operations, the following operations are required for the execution of the modulo subtraction operation of the Goldilocks field 64-bit unsigned number A and number B using standard computer instructions once:

[0114] At most: 1 comparison jump, 1 subtraction, 1 addition;

[0115] At least: 1 comparison jump, 1 subtraction.

[0116] The basic operation unit of the embodiment of the present disclosure is used to perform the modulus subtraction operation of the 64-bit unsigned number A and the number B in the Goldilocks field once, and in addition to the loading and storage operations, 6 additions, 3 selections, and 2 splices are required. The 6 addition operations can be performed simultaneously, and the selection and splice operations do not occupy too much time compared with the relatively jump operation.

[0117] The computer execution jump instruction involves instruction jump prediction, instruction loading, prediction result correction, instruction clearing, and other processes, which is time-consuming (in some embodiments, it takes 10-20 clock cycles to evaluate); and the time required for the modulus subtraction operation of the present disclosure is equal to or slightly more than the time required for the addition operation (in some embodiments, the improved functional unit can be used to achieve the same time as the addition operation, which is 2 clock cycles, and in other embodiments, the general functional unit can be used to achieve 2 clock cycles more than the addition operation, which is 4 clock cycles). Therefore, the time required for the modulus subtraction operation of the 64-bit unsigned number in the finite field of the Goldilocks field using the basic operation unit of the embodiment of the present disclosure is greatly reduced, which can be reduced to about 1 / 10 of the general instruction time.

[0118] As shown in FIGS. 7 and 8, the embodiment of the present disclosure also provides an operation device, which comprises the basic operation unit 701 as described in any embodiment of the present disclosure, and further comprises a configuration unit 702 and a storage unit 703, the storage unit 703 comprises a first storage unit 7031, a second storage unit 7032, and a third storage unit 7033, wherein:

[0119] The configuration unit 702 is configured to receive a modulus operation instruction, the modulus operation instruction comprising an operation type, an address of the first storage unit 7031, an address of the second storage unit 7032, and an address of the third storage unit 7033; read the unsigned number A from the first storage unit 7031, read the unsigned number B from the second storage unit 7032, and set the input values of the modulus operation basic addition unit in the basic operation unit 701 according to the operation type, the unsigned number A, and the unsigned number B; obtain the operation result of the basic operation unit 701, and write the operation result into the third storage unit 7033.

[0120] In the embodiment of the present disclosure, the storage unit 703 can be realized by a register, however, the embodiment of the present disclosure does not limit this.

[0121] In some example embodiments, N1=N2=N, as shown in FIG. 8, the storage width of the first storage unit 7031 is X*2N bits, the storage width of the second storage unit 7032 is X*2N bits, the operation device comprises X basic operation units 701, the X basic operation units 701 are arranged in parallel, and X is a natural number greater than or equal to 1.

[0122] X unsigned numbers A are stored in the first storage unit 7031 after splicing, X unsigned numbers B are stored in the second storage unit 7032 after splicing, and the operation results of the X basic operation units 701 are stored in the third storage unit 7033 after splicing;

[0123] The configuration unit 702 is further configured to split the unsigned number A read from the first storage unit 7031 into X unsigned numbers A0 to A(X-1), split the unsigned number B read from the second storage unit 7032 into X unsigned numbers B0 to B(X-1), and splice the operation results C0 to C(X-1) output by the X basic operation units 701 into an unsigned number C and store the unsigned number C in the third storage unit 7033.

[0124] The configuration unit 702 reads the unsigned number A from the first storage unit 7031, splits it into X unsigned numbers A0, A1, A2, A3, …, takes Ai as one of the operation numbers of the i-th basic operation unit 701, i is a natural number greater than or equal to 0, reads the unsigned number B from the second storage unit 7032, splits it into X unsigned numbers B0, B1, B2, B3, …, takes Bi as the other operation number of the i-th basic operation unit 701, sets the input values of the modulo operation and addition unit in each basic operation unit 701 according to the operation type and the corresponding operation numbers Ai and Bi of each basic operation unit 701, executes the operation by each basic operation unit 701, outputs the operation result Ci, and the configuration unit 702 splices the operation results C0 to C(X-1) and stores them in the third storage unit 7033.

[0125] The operation device of the embodiments of the present disclosure can simultaneously calculate the modulo addition or subtraction operation of X groups of unsigned numbers Ai and unsigned numbers Bi. For example, assuming that X = 4, the total calculation time can be reduced to about 1 / 40 of the general instruction time.

[0126] In some exemplary embodiments, the format of the modulo operation instruction can be: "instruction destination register, source register 1, source register 2", wherein the instruction can be a batch modulo addition or batch modulo subtraction instruction, the modulo operation instruction directly calculates the results of the modulo addition or subtraction of the X 64-bit unsigned numbers stored side by side in the source register 1 with the X 64-bit unsigned numbers stored side by side in the source register 2 in the Goldilocks domain, and stores the results side by side in the destination register, X is a natural number greater than or equal to 1.

[0127] As shown in FIG. 9, when the operation device of the embodiments of the present disclosure is used to implement the modulo addition operation of the 64-bit unsigned numbers A and the unsigned numbers B in the Goldilocks domain, the following instructions can be executed:

[0128] GADDMP dst,src1,src2

[0129] Upon receiving the instruction, the operation device calls the basic operation unit to perform the following operations: the X 64-bit unsigned numbers stored side by side in the src1 register are taken as the input Ai of each basic operation unit, the X 64-bit unsigned numbers stored side by side in the src2 register are taken as the input Bi of each basic operation unit, the modulo addition result of Ai and Bi is calculated by each basic operation unit, after each basic operation unit is run, Ci is obtained, and the output Ci of the basic operation unit is stored side by side in the dst register, X≥1.

[0130] As shown in FIG. 10, when the operation device using the embodiment of the present disclosure implements the modulo subtraction operation of the 64-bit unsigned number A and the unsigned number B in the Goldilocks domain, the following instruction can be executed:

[0131] GSUBMP dst,src1,src2

[0132] Upon receiving the instruction, the operation device calls the basic operation unit to perform the following operations: the X 64-bit unsigned numbers stored side by side in the src1 register are taken as the input Ai of each basic operation unit, the X 64-bit unsigned numbers stored side by side in the src2 register are taken as the input Bi of each basic operation unit, the modulo subtraction result of Ai and Bi is calculated by each basic operation unit, after each basic operation unit is run, Ci is obtained, and the output Ci of the basic operation unit is stored side by side in the dst register, X≥1.

[0133] By using the computer instruction matched with the embodiment of the present disclosure, when the basic operation unit is called to calculate the Goldilocks domain modulo addition and modulo subtraction, multiple groups of 64-bit unsigned numbers can be calculated at the same time, which greatly speeds up the calculation, simplifies the program logic, reduces the number of instructions, and improves the program running efficiency.

[0134] As shown in FIG. 11, the embodiment of the present disclosure also provides an operation method based on the basic operation unit described in any embodiment of the present disclosure, which comprises:

[0135] Step 1101, receiving a modulo operation instruction, the modulo operation instruction comprising an operation type, an address of a first storage unit, an address of a second storage unit, and an address of a third storage unit;

[0136] Step 1102, reading an unsigned number A from the first storage unit and reading an unsigned number B from the second storage unit;

[0137] Step 1103, setting the input value of the modulo operation basic addition unit in the basic operation unit according to the operation type and the values of A and B.

[0138] obtaining an operation result of the basic operation unit, and writing the operation result into the third storage unit.

[0139] In some example embodiments, the storage width of the first storage unit is X*2N bits, the storage width of the second storage unit is X*2N bits, the number of the basic operation units is X, and the X basic operation units are arranged in parallel; the X unsigned numbers A are stored in the first storage unit after being spliced, the X unsigned numbers B are stored in the second storage unit after being spliced, and the operation results of the X basic operation units are stored in the third storage unit after being spliced, where X is a natural number greater than or equal to 1, and N is a natural number greater than or equal to 1.

[0140] The operation method further includes splitting the unsigned numbers A read from the first storage unit, splitting the unsigned numbers B read from the second storage unit, and splicing the operation results of the X basic operation units.

[0141] The embodiments of the present disclosure further provide an operation apparatus, including a memory and a processor connected to the memory, the memory is configured to store instructions, and the processor is configured to execute the steps of the operation method according to any of the embodiments of the present disclosure based on the instructions stored in the memory.

[0142] As shown in FIG. 12, in one example, the operation apparatus can include a processor 1210, a memory 1220, a bus system 1230, and a transceiver 1240, wherein the processor 1210, the memory 1220, and the transceiver 1240 are connected through the bus system 1230, the memory 1220 is configured to store instructions, and the processor 1210 is configured to execute the instructions stored in the memory 1220 to control the transceiver 1240 to transceive signals. Specifically, the transceiver 1240 can receive a modulo operation instruction under the control of the processor 1210, the modulo operation instruction including an operation type, an address of a first storage unit, an address of a second storage unit, and an address of a third storage unit, the processor 1210 reads unsigned numbers A from the first storage unit and unsigned numbers B from the second storage unit; according to the operation type and the values of A and B, the input values of the modulo operation basis addition units in the basic operation units are set; an operation result of the basic operation unit is obtained, and the operation result is written into the third storage unit.

[0143] It should be understood that the processor 1210 can be a central processing unit (CPU), and the processor 1210 can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), programmable logic devices (PLD), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0144] The memory 1220 can include a read-only memory and a random access memory, and provide instructions and data for the processor 1210. A part of the memory 1220 can also include a non-volatile random access memory. For example, the memory 1220 can also store device type information.

[0145] The bus system 1230 can include a data bus, a power bus, a control bus, a status signal bus, etc. in addition to the data bus. However, for the purpose of clarity, all the buses are marked as the bus system 1230 in FIG. 12.

[0146] In the implementation process, the processing performed by the processing device can be completed by the integrated logic circuit of the hardware in the processor 1210 or the instructions in the form of software. That is, the method steps of the embodiments of the present disclosure can be embodied as being completed by a hardware processor or being completed by a combination of hardware and software modules in the processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, or the like storage medium. The storage medium is located in the memory 1220, and the processor 1210 reads the information in the memory 1220 and completes the steps of the above method in combination with the hardware. To avoid repetition, it will not be described in detail here.

[0147] The embodiments of the present disclosure also provide a computer readable storage medium, which stores a computer program, and the program is executed by a processor to implement the operation method according to any of the embodiments of the present disclosure.

[0148] In some possible implementation manners, various aspects of the operation method provided by the present disclosure can also be implemented in the form of a program product, which includes program codes for causing a computer device to perform the steps in the operation method according to various exemplary embodiments of the present disclosure described above in the specification, for example, the computer device can execute the operation method recorded in the embodiments of the present disclosure.

[0149] The program product can employ any combination of one or more computer-readable media. The computer-readable media can be a computer-readable storage medium or a computer-readable signal medium. Computer-readable storage media can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0150] Those of ordinary skill in the art will appreciate that all or certain steps in the methods disclosed above, functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units referred to in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Certain components or all components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile discs (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, it should be appreciated by those skilled in the art that computer readable media generally include computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

[0151] It should be noted that the above-described embodiments or implementations are merely exemplary, but not limiting. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, and omissions can be made to the specific embodiments without departing from the scope of the disclosure.

Claims

1. A base operation unit, comprising a plurality of modulo operation base adder units, a plurality of selection units and a plurality of concatenation units, the modulo operation base adder units comprising a first modulo operation base adder unit and a second modulo operation base adder unit, the selection units comprising a first selection unit and a second selection unit, wherein: the first modulo operation base adder unit is configured to operate on low bits of operands to obtain a plurality of low bit operation results; the second modulo operation base adder unit is configured to operate on high bits of the operands to obtain a plurality of high bit operation results, the high bit operation results comprising a carry result and a non-carry result, the carry result being a high bit operation result of the operands when the low bit operation results carry to the high bits, the non-carry result being a high bit operation result of the operands when the low bit operation results do not carry to the high bits; the first selection unit is configured to select the corresponding carry result or non-carry result according to whether the low bit operation results carry to the high bits, and output to the concatenation unit; the concatenation unit is configured to concatenate the high bit operation results and the low bit operation results to obtain a concatenation result; and the second selection unit is configured to determine an operation result according to the highest bit of the concatenation result. The base operation unit is configured to perform modulo addition or subtraction operation on unsigned number A and unsigned number B, modulus P, the operands comprising the unsigned number A and the unsigned number B, or the unsigned number A, the unsigned number B and the modulus P. Each of the modulo operation base adder units is configured to receive four input values and perform addition operation on the four input values, one of the four input values being set according to the high bits or low bits of the unsigned number A, one of the four input values being set according to the high bits or low bits of the unsigned number B, one of the four input values being set according to the high bits or low bits of the modulus P or being set as 0, and one of the four input values being set as 0 or 1. The unsigned number A, the unsigned number B and the modulus P are all (N1+N2) bit binary numbers, N1 and N2 are both natural numbers greater than or equal to 1, in the first modulo operation base adder unit, one of the input values is the value of the low N2 bits of the unsigned number A, one of the input values is the value of the low N2 bits of the unsigned number B or the value of the low N2 bits of the complement of the unsigned number B, and one of the input values is the value of the low N2 bits of the modulus P, the value of the low N2 bits of the complement of the modulus P or 0; in the second modulo operation base adder unit, one of the input values is the value of the high N1 bits of the unsigned number A, one of the input values is the value of the high N1 bits of the unsigned number B or the value of the high N1 bits of the complement of the unsigned number B, and one of the input values is the value of the high N1 bits of the modulus P, the value of the high N1 bits of the complement of the modulus P or 0. The base operation unit comprises a first operation branch and a second operation branch connected to the second selection unit. ​ ​ ​ ​ ​ 2. The base arithmetic unit of claim 1, wherein, ​ 3. The base arithmetic unit of claim 2, wherein, ​ 4. The base arithmetic unit of claim 3, wherein, ​ ​ 5. The base arithmetic unit of claim 2, wherein, ​ When the basic operation unit performs modulo addition operation on the unsigned number A and the unsigned number B, the first operation branch calculates the sum of A and B, and inputs the value of the highest bit of the calculation result of itself to the control end of the second selection unit; When the basic operation unit performs modulo subtraction operation on the unsigned number A and the unsigned number B, the first operation branch calculates the difference between A and B, and inputs the value of the highest bit of the calculation result of itself to the control end of the second selection unit; The second operation branch calculates the difference between A and B plus P; The second selection unit is configured to select the calculation result of the first operation branch or the second operation branch to output according to the value received by the control end of itself.

6. The base arithmetic unit of claim 5, wherein, When the basic operation unit performs modulo addition operation on the unsigned number A and the unsigned number B, the first operation branch includes a first adder, a second adder, a third adder, a first selector and a first splicer; The first adder is configured to calculate the sum of the high N1 bits of A and the high N1 bits of B, and input the calculated value to the first input end of the first selector; The second adder is configured to calculate the sum of the high N1 bits of A, the high N1 bits of B and 1, and input the calculated value to the second input end of the first selector; The third adder is configured to calculate the sum of the low N2 bits of A and the low N2 bits of B, input the highest bit of the calculated value to the control end of the first selector, and input the low N2 bits of the calculated value to the first input end of the first splicer; The first selector is configured to select the value received by the first input end or the second input end to input to the second input end of the first splicer according to the value received by the control end of itself; The first splicer is configured to splice the input of the third adder and the input of the first selector, and input the spliced value to the first input end of the second selection unit.

7. The base arithmetic unit of claim 5, wherein, When the basic operation unit performs modulo addition operation on the unsigned number A and the unsigned number B, the second operation branch includes a fourth adder, a fifth adder, a sixth adder, a second selector and a second splicer; The fourth adder is configured to calculate the sum of the high N1 bits of A, the high N1 bits of B and the high N1 bits of the complement of P, and input the calculated value to the first input end of the second selector; The fifth adder is configured to calculate the sum of the high N1 bits of A, the high N1 bits of B and the high N1 bits of the complement of P and 1, and input the calculated value to the second input end of the second selector; The sixth adder is configured to calculate the sum of the low N2 bits of A, the low N2 bits of B, the low N2 bits of the complement of P and 1, input the highest bit of the calculated value to the control end of the second selector, and input the low N2 bits of the calculated value to the first input end of the second splicer; The second selector is configured to select the value received by the first input or the second input according to the value received by the control input, and input the selected value into the second input of the second splicer; The second splicer is configured to splice the input of the sixth adder and the input of the second selector, input the most significant bit of the spliced value into the control input of the second selection unit, and input the spliced value into the second input of the second selection unit.

8. The base arithmetic unit of claim 5, wherein, When the basic operation unit performs the modulo subtraction operation on the unsigned number A and the unsigned number B, the first operation branch includes a seventh adder, an eighth adder, a ninth adder, a fourth selector and a third splicer; The seventh adder is configured to calculate the sum of the high N1 bits of A and the high N1 bits of the inverse code of B, and input the calculated value into the first input of the fourth selector; The eighth adder is configured to calculate the sum of the high N1 bits of A, the high N1 bits of the inverse code of B and 1, and input the calculated value into the second input of the fourth selector; The ninth adder is configured to calculate the sum of the low N2 bits of A, the low N2 bits of the inverse code of B and 1, input the most significant bit of the calculated value into the control input of the fourth selector, and input the low N2 bits of the calculated value into the first input of the third splicer; The fourth selector is configured to select the value received by the first input or the second input according to the value received by the control input, and input the selected value into the second input of the third splicer; The third splicer is configured to splice the input of the ninth adder and the input of the fourth selector, and input the most significant bit of the spliced value into the control input of the second selection unit, and input the spliced value into the first input of the second selection unit.

9. The base arithmetic unit of claim 5, wherein, When the basic operation unit performs the modulo subtraction operation on the unsigned number A and the unsigned number B, the first operation branch includes a seventh adder, an eighth adder, a ninth adder, a fourth selector and a third splicer; The tenth adder is configured to calculate the sum of the high N1 bits of A, the high N1 bits of the inverse code of B and the high N1 bits of P, and input the calculated value into the first input of the fifth selector; The eleventh adder is configured to calculate the sum of the high N1 bits of A, the high N1 bits of the inverse code of B, the high N1 bits of P and 1, and input the calculated value into the second input of the fifth selector; The twelfth adder is configured to calculate the sum of the low N2 bits of A, the low N2 bits of the inverse code of B, the low N2 bits of P and 1, input the most significant bit of the calculated value into the control input of the fifth selector, and input the low N2 bits of the calculated value into the first input of the fourth splicer; The fifth selector is configured to select the value received by the first input or the second input according to the value received by the control input, and input the selected value into the second input of the fourth splicer; The fourth splicer is configured to splice the input of the twelfth adder and the input of the fifth selector, and input the spliced value into the second input of the second selection unit.

10. An operation device comprising the base operation unit of any one of claims 1 to 9, further comprising a configuration unit and a storage unit, the storage unit comprising a first storage unit, a second storage unit and a third storage unit, wherein: the configuration unit is configured to receive a modulo operation instruction, the modulo operation instruction comprising an operation type, an address of the first storage unit, an address of the second storage unit and an address of the third storage unit; read an unsigned number A from the first storage unit, read an unsigned number B from the second storage unit, and set input values of the modulo operation base addition units in the base operation unit according to the operation type, the unsigned number A and the unsigned number B; obtain an operation result of the base operation unit, and write the operation result into the third storage unit. N1=N2=N, a storage width of the first storage unit is X*2N bits, a storage width of the second storage unit is X*2N bits, a number of the base operation units is X, X base operation units are arranged in parallel; X unsigned numbers A are stored in the first storage unit after being spliced, X unsigned numbers B are stored in the second storage unit after being spliced, operation results of X base operation units are stored in the third storage unit after being spliced, X is a natural number greater than or equal to 1, N is a natural number greater than or equal to 1; 11. The operation device according to claim 10, wherein the configuration unit is further configured to split the unsigned number A read from the first storage unit, split the unsigned number B read from the second storage unit, and splice operation results of X base operation units.

12. An operation method based on the base operation unit of any one of claims 1 to 9, comprising: receiving a modulo operation instruction, the modulo operation instruction comprising an operation type, an address of a first storage unit, an address of a second storage unit and an address of a third storage unit; reading an unsigned number A from the first storage unit, reading an unsigned number B from the second storage unit; setting input values of modulo operation base addition units in the base operation unit according to the operation type and values of A and B; obtaining an operation result of the base operation unit, and writing the operation result into the third storage unit.

13. An operation device comprising a memory and a processor connected to the memory, the memory being used to store instructions, and the processor being configured to execute steps of the operation method of claim 12 based on the instructions stored in the memory.

14. A computer readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the operation method of claim 12. ​ ​ ​ ​ ​

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